drivers/pinctrl/pinctrl-single.c

   1 /*
   2  * Generic device tree based pinctrl driver for one register per pin
   3  * type pinmux controllers
   4  *
   5  * Copyright (C) 2012 Texas Instruments, Inc.
   6  *
   7  * This file is licensed under the terms of the GNU General Public
   8  * License version 2. This program is licensed "as is" without any
   9  * warranty of any kind, whether express or implied.
  10  */
  11
  12 #include <linux/init.h>
  13 #include <linux/module.h>
  14 #include <linux/io.h>
  15 #include <linux/slab.h>
  16 #include <linux/err.h>
  17 #include <linux/list.h>
  18 #include <linux/interrupt.h>
  19
  20 #include <linux/irqchip/chained_irq.h>
  21
  22 #include <linux/of.h>
  23 #include <linux/of_device.h>
  24 #include <linux/of_address.h>
  25 #include <linux/of_irq.h>
  26
  27 #include <linux/pinctrl/pinctrl.h>
  28 #include <linux/pinctrl/pinmux.h>
  29 #include <linux/pinctrl/pinconf-generic.h>
  30
  31 #include <linux/platform_data/pinctrl-single.h>
  32
  33 #include "core.h"
  34 #include "pinconf.h"
  35
  36 #define DRIVER_NAME                     "pinctrl-single"
  37 #define PCS_MUX_PINS_NAME               "pinctrl-single,pins"
  38 #define PCS_MUX_BITS_NAME               "pinctrl-single,bits"
  39 #define PCS_REG_NAME_LEN                ((sizeof(unsigned long) * 2) + 3)
  40 #define PCS_OFF_DISABLED                ~0U
  41
  42 /**
  43  * struct pcs_pingroup - pingroups for a function
  44  * @np:         pingroup device node pointer
  45  * @name:       pingroup name
  46  * @gpins:      array of the pins in the group
  47  * @ngpins:     number of pins in the group
  48  * @node:       list node
  49  */
  50 struct pcs_pingroup {
  51         struct device_node *np;
  52         const char *name;
  53         int *gpins;
  54         int ngpins;
  55         struct list_head node;
  56 };
  57
  58 /**
  59  * struct pcs_func_vals - mux function register offset and value pair
  60  * @reg:        register virtual address
  61  * @val:        register value
  62  */
  63 struct pcs_func_vals {
  64         void __iomem *reg;
  65         unsigned val;
  66         unsigned mask;
  67 };
  68
  69 /**
  70  * struct pcs_conf_vals - pinconf parameter, pinconf register offset
  71  * and value, enable, disable, mask
  72  * @param:      config parameter
  73  * @val:        user input bits in the pinconf register
  74  * @enable:     enable bits in the pinconf register
  75  * @disable:    disable bits in the pinconf register
  76  * @mask:       mask bits in the register value
  77  */
  78 struct pcs_conf_vals {
  79         enum pin_config_param param;
  80         unsigned val;
  81         unsigned enable;
  82         unsigned disable;
  83         unsigned mask;
  84 };
  85
  86 /**
  87  * struct pcs_conf_type - pinconf property name, pinconf param pair
  88  * @name:       property name in DTS file
  89  * @param:      config parameter
  90  */
  91 struct pcs_conf_type {
  92         const char *name;
  93         enum pin_config_param param;
  94 };
  95
  96 /**
  97  * struct pcs_function - pinctrl function
  98  * @name:       pinctrl function name
  99  * @vals:       register and vals array
 100  * @nvals:      number of entries in vals array
 101  * @pgnames:    array of pingroup names the function uses
 102  * @npgnames:   number of pingroup names the function uses
 103  * @node:       list node
 104  */
 105 struct pcs_function {
 106         const char *name;
 107         struct pcs_func_vals *vals;
 108         unsigned nvals;
 109         const char **pgnames;
 110         int npgnames;
 111         struct pcs_conf_vals *conf;
 112         int nconfs;
 113         struct list_head node;
 114 };
 115
 116 /**
 117  * struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function
 118  * @offset:     offset base of pins
 119  * @npins:      number pins with the same mux value of gpio function
 120  * @gpiofunc:   mux value of gpio function
 121  * @node:       list node
 122  */
 123 struct pcs_gpiofunc_range {
 124         unsigned offset;
 125         unsigned npins;
 126         unsigned gpiofunc;
 127         struct list_head node;
 128 };
 129
 130 /**
 131  * struct pcs_data - wrapper for data needed by pinctrl framework
 132  * @pa:         pindesc array
 133  * @cur:        index to current element
 134  *
 135  * REVISIT: We should be able to drop this eventually by adding
 136  * support for registering pins individually in the pinctrl
 137  * framework for those drivers that don't need a static array.
 138  */
 139 struct pcs_data {
 140         struct pinctrl_pin_desc *pa;
 141         int cur;
 142 };
 143
 144 /**
 145  * struct pcs_name - register name for a pin
 146  * @name:       name of the pinctrl register
 147  *
 148  * REVISIT: We may want to make names optional in the pinctrl
 149  * framework as some drivers may not care about pin names to
 150  * avoid kernel bloat. The pin names can be deciphered by user
 151  * space tools using debugfs based on the register address and
 152  * SoC packaging information.
 153  */
 154 struct pcs_name {
 155         char name[PCS_REG_NAME_LEN];
 156 };
 157
 158 /**
 159  * struct pcs_soc_data - SoC specific settings
 160  * @flags:      initial SoC specific PCS_FEAT_xxx values
 161  * @irq:        optional interrupt for the controller
 162  * @irq_enable_mask:    optional SoC specific interrupt enable mask
 163  * @irq_status_mask:    optional SoC specific interrupt status mask
 164  * @rearm:      optional SoC specific wake-up rearm function
 165  */
 166 struct pcs_soc_data {
 167         unsigned flags;
 168         int irq;
 169         unsigned irq_enable_mask;
 170         unsigned irq_status_mask;
 171         void (*rearm)(void);
 172 };
 173
 174 /**
 175  * struct pcs_device - pinctrl device instance
 176  * @res:        resources
 177  * @base:       virtual address of the controller
 178  * @size:       size of the ioremapped area
 179  * @dev:        device entry
 180  * @pctl:       pin controller device
 181  * @flags:      mask of PCS_FEAT_xxx values
 182  * @lock:       spinlock for register access
 183  * @mutex:      mutex protecting the lists
 184  * @width:      bits per mux register
 185  * @fmask:      function register mask
 186  * @fshift:     function register shift
 187  * @foff:       value to turn mux off
 188  * @fmax:       max number of functions in fmask
 189  * @bits_per_pin:number of bits per pin
 190  * @names:      array of register names for pins
 191  * @pins:       physical pins on the SoC
 192  * @pgtree:     pingroup index radix tree
 193  * @ftree:      function index radix tree
 194  * @pingroups:  list of pingroups
 195  * @functions:  list of functions
 196  * @gpiofuncs:  list of gpio functions
 197  * @irqs:       list of interrupt registers
 198  * @chip:       chip container for this instance
 199  * @domain:     IRQ domain for this instance
 200  * @ngroups:    number of pingroups
 201  * @nfuncs:     number of functions
 202  * @desc:       pin controller descriptor
 203  * @read:       register read function to use
 204  * @write:      register write function to use
 205  */
 206 struct pcs_device {
 207         struct resource *res;
 208         void __iomem *base;
 209         unsigned size;
 210         struct device *dev;
 211         struct pinctrl_dev *pctl;
 212         unsigned flags;
 213 #define PCS_QUIRK_SHARED_IRQ    (1 << 2)
 214 #define PCS_FEAT_IRQ            (1 << 1)
 215 #define PCS_FEAT_PINCONF        (1 << 0)
 216         struct pcs_soc_data socdata;
 217         raw_spinlock_t lock;
 218         struct mutex mutex;
 219         unsigned width;
 220         unsigned fmask;
 221         unsigned fshift;
 222         unsigned foff;
 223         unsigned fmax;
 224         bool bits_per_mux;
 225         unsigned bits_per_pin;
 226         struct pcs_name *names;
 227         struct pcs_data pins;
 228         struct radix_tree_root pgtree;
 229         struct radix_tree_root ftree;
 230         struct list_head pingroups;
 231         struct list_head functions;
 232         struct list_head gpiofuncs;
 233         struct list_head irqs;
 234         struct irq_chip chip;
 235         struct irq_domain *domain;
 236         unsigned ngroups;
 237         unsigned nfuncs;
 238         struct pinctrl_desc desc;
 239         unsigned (*read)(void __iomem *reg);
 240         void (*write)(unsigned val, void __iomem *reg);
 241 };
 242
 243 #define PCS_QUIRK_HAS_SHARED_IRQ        (pcs->flags & PCS_QUIRK_SHARED_IRQ)
 244 #define PCS_HAS_IRQ             (pcs->flags & PCS_FEAT_IRQ)
 245 #define PCS_HAS_PINCONF         (pcs->flags & PCS_FEAT_PINCONF)
 246
 247 static int pcs_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
 248                            unsigned long *config);
 249 static int pcs_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
 250                            unsigned long *configs, unsigned num_configs);
 251
 252 static enum pin_config_param pcs_bias[] = {
 253         PIN_CONFIG_BIAS_PULL_DOWN,
 254         PIN_CONFIG_BIAS_PULL_UP,
 255 };
 256
 257 /*
 258  * REVISIT: Reads and writes could eventually use regmap or something
 259  * generic. But at least on omaps, some mux registers are performance
 260  * critical as they may need to be remuxed every time before and after
 261  * idle. Adding tests for register access width for every read and
 262  * write like regmap is doing is not desired, and caching the registers
 263  * does not help in this case.
 264  */
 265
 266 static unsigned __maybe_unused pcs_readb(void __iomem *reg)
 267 {
 268         return readb(reg);
 269 }
 270
 271 static unsigned __maybe_unused pcs_readw(void __iomem *reg)
 272 {
 273         return readw(reg);
 274 }
 275
 276 static unsigned __maybe_unused pcs_readl(void __iomem *reg)
 277 {
 278         return readl(reg);
 279 }
 280
 281 static void __maybe_unused pcs_writeb(unsigned val, void __iomem *reg)
 282 {
 283         writeb(val, reg);
 284 }
 285
 286 static void __maybe_unused pcs_writew(unsigned val, void __iomem *reg)
 287 {
 288         writew(val, reg);
 289 }
 290
 291 static void __maybe_unused pcs_writel(unsigned val, void __iomem *reg)
 292 {
 293         writel(val, reg);
 294 }
 295
 296 static int pcs_get_groups_count(struct pinctrl_dev *pctldev)
 297 {
 298         struct pcs_device *pcs;
 299
 300         pcs = pinctrl_dev_get_drvdata(pctldev);
 301
 302         return pcs->ngroups;
 303 }
 304
 305 static const char *pcs_get_group_name(struct pinctrl_dev *pctldev,
 306                                         unsigned gselector)
 307 {
 308         struct pcs_device *pcs;
 309         struct pcs_pingroup *group;
 310
 311         pcs = pinctrl_dev_get_drvdata(pctldev);
 312         group = radix_tree_lookup(&pcs->pgtree, gselector);
 313         if (!group) {
 314                 dev_err(pcs->dev, "%s could not find pingroup%i\n",
 315                         __func__, gselector);
 316                 return NULL;
 317         }
 318
 319         return group->name;
 320 }
 321
 322 static int pcs_get_group_pins(struct pinctrl_dev *pctldev,
 323                                         unsigned gselector,
 324                                         const unsigned **pins,
 325                                         unsigned *npins)
 326 {
 327         struct pcs_device *pcs;
 328         struct pcs_pingroup *group;
 329
 330         pcs = pinctrl_dev_get_drvdata(pctldev);
 331         group = radix_tree_lookup(&pcs->pgtree, gselector);
 332         if (!group) {
 333                 dev_err(pcs->dev, "%s could not find pingroup%i\n",
 334                         __func__, gselector);
 335                 return -EINVAL;
 336         }
 337
 338         *pins = group->gpins;
 339         *npins = group->ngpins;
 340
 341         return 0;
 342 }
 343
 344 static void pcs_pin_dbg_show(struct pinctrl_dev *pctldev,
 345                                         struct seq_file *s,
 346                                         unsigned pin)
 347 {
 348         struct pcs_device *pcs;
 349         unsigned val, mux_bytes;
 350
 351         pcs = pinctrl_dev_get_drvdata(pctldev);
 352
 353         mux_bytes = pcs->width / BITS_PER_BYTE;
 354         val = pcs->read(pcs->base + pin * mux_bytes);
 355
 356         seq_printf(s, "%08x %s " , val, DRIVER_NAME);
 357 }
 358
 359 static void pcs_dt_free_map(struct pinctrl_dev *pctldev,
 360                                 struct pinctrl_map *map, unsigned num_maps)
 361 {
 362         struct pcs_device *pcs;
 363
 364         pcs = pinctrl_dev_get_drvdata(pctldev);
 365         devm_kfree(pcs->dev, map);
 366 }
 367
 368 static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
 369                                 struct device_node *np_config,
 370                                 struct pinctrl_map **map, unsigned *num_maps);
 371
 372 static const struct pinctrl_ops pcs_pinctrl_ops = {
 373         .get_groups_count = pcs_get_groups_count,
 374         .get_group_name = pcs_get_group_name,
 375         .get_group_pins = pcs_get_group_pins,
 376         .pin_dbg_show = pcs_pin_dbg_show,
 377         .dt_node_to_map = pcs_dt_node_to_map,
 378         .dt_free_map = pcs_dt_free_map,
 379 };
 380
 381 static int pcs_get_functions_count(struct pinctrl_dev *pctldev)
 382 {
 383         struct pcs_device *pcs;
 384
 385         pcs = pinctrl_dev_get_drvdata(pctldev);
 386
 387         return pcs->nfuncs;
 388 }
 389
 390 static const char *pcs_get_function_name(struct pinctrl_dev *pctldev,
 391                                                 unsigned fselector)
 392 {
 393         struct pcs_device *pcs;
 394         struct pcs_function *func;
 395
 396         pcs = pinctrl_dev_get_drvdata(pctldev);
 397         func = radix_tree_lookup(&pcs->ftree, fselector);
 398         if (!func) {
 399                 dev_err(pcs->dev, "%s could not find function%i\n",
 400                         __func__, fselector);
 401                 return NULL;
 402         }
 403
 404         return func->name;
 405 }
 406
 407 static int pcs_get_function_groups(struct pinctrl_dev *pctldev,
 408                                         unsigned fselector,
 409                                         const char * const **groups,
 410                                         unsigned * const ngroups)
 411 {
 412         struct pcs_device *pcs;
 413         struct pcs_function *func;
 414
 415         pcs = pinctrl_dev_get_drvdata(pctldev);
 416         func = radix_tree_lookup(&pcs->ftree, fselector);
 417         if (!func) {
 418                 dev_err(pcs->dev, "%s could not find function%i\n",
 419                         __func__, fselector);
 420                 return -EINVAL;
 421         }
 422         *groups = func->pgnames;
 423         *ngroups = func->npgnames;
 424
 425         return 0;
 426 }
 427
 428 static int pcs_get_function(struct pinctrl_dev *pctldev, unsigned pin,
 429                             struct pcs_function **func)
 430 {
 431         struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
 432         struct pin_desc *pdesc = pin_desc_get(pctldev, pin);
 433         const struct pinctrl_setting_mux *setting;
 434         unsigned fselector;
 435
 436         /* If pin is not described in DTS & enabled, mux_setting is NULL. */
 437         setting = pdesc->mux_setting;
 438         if (!setting)
 439                 return -ENOTSUPP;
 440         fselector = setting->func;
 441         *func = radix_tree_lookup(&pcs->ftree, fselector);
 442         if (!(*func)) {
 443                 dev_err(pcs->dev, "%s could not find function%i\n",
 444                         __func__, fselector);
 445                 return -ENOTSUPP;
 446         }
 447         return 0;
 448 }
 449
 450 static int pcs_enable(struct pinctrl_dev *pctldev, unsigned fselector,
 451         unsigned group)
 452 {
 453         struct pcs_device *pcs;
 454         struct pcs_function *func;
 455         int i;
 456
 457         pcs = pinctrl_dev_get_drvdata(pctldev);
 458         /* If function mask is null, needn't enable it. */
 459         if (!pcs->fmask)
 460                 return 0;
 461         func = radix_tree_lookup(&pcs->ftree, fselector);
 462         if (!func)
 463                 return -EINVAL;
 464
 465         dev_dbg(pcs->dev, "enabling %s function%i\n",
 466                 func->name, fselector);
 467
 468         for (i = 0; i < func->nvals; i++) {
 469                 struct pcs_func_vals *vals;
 470                 unsigned long flags;
 471                 unsigned val, mask;
 472
 473                 vals = &func->vals[i];
 474                 raw_spin_lock_irqsave(&pcs->lock, flags);
 475                 val = pcs->read(vals->reg);
 476
 477                 if (pcs->bits_per_mux)
 478                         mask = vals->mask;
 479                 else
 480                         mask = pcs->fmask;
 481
 482                 val &= ~mask;
 483                 val |= (vals->val & mask);
 484                 pcs->write(val, vals->reg);
 485                 raw_spin_unlock_irqrestore(&pcs->lock, flags);
 486         }
 487
 488         return 0;
 489 }
 490
 491 static void pcs_disable(struct pinctrl_dev *pctldev, unsigned fselector,
 492                                         unsigned group)
 493 {
 494         struct pcs_device *pcs;
 495         struct pcs_function *func;
 496         int i;
 497
 498         pcs = pinctrl_dev_get_drvdata(pctldev);
 499         /* If function mask is null, needn't disable it. */
 500         if (!pcs->fmask)
 501                 return;
 502
 503         func = radix_tree_lookup(&pcs->ftree, fselector);
 504         if (!func) {
 505                 dev_err(pcs->dev, "%s could not find function%i\n",
 506                         __func__, fselector);
 507                 return;
 508         }
 509
 510         /*
 511          * Ignore disable if function-off is not specified. Some hardware
 512          * does not have clearly defined disable function. For pin specific
 513          * off modes, you can use alternate named states as described in
 514          * pinctrl-bindings.txt.
 515          */
 516         if (pcs->foff == PCS_OFF_DISABLED) {
 517                 dev_dbg(pcs->dev, "ignoring disable for %s function%i\n",
 518                         func->name, fselector);
 519                 return;
 520         }
 521
 522         dev_dbg(pcs->dev, "disabling function%i %s\n",
 523                 fselector, func->name);
 524
 525         for (i = 0; i < func->nvals; i++) {
 526                 struct pcs_func_vals *vals;
 527                 unsigned long flags;
 528                 unsigned val, mask;
 529
 530                 vals = &func->vals[i];
 531                 raw_spin_lock_irqsave(&pcs->lock, flags);
 532                 val = pcs->read(vals->reg);
 533
 534                 if (pcs->bits_per_mux)
 535                         mask = vals->mask;
 536                 else
 537                         mask = pcs->fmask;
 538
 539                 val &= ~mask;
 540                 val |= pcs->foff << pcs->fshift;
 541                 pcs->write(val, vals->reg);
 542                 raw_spin_unlock_irqrestore(&pcs->lock, flags);
 543         }
 544 }
 545
 546 static int pcs_request_gpio(struct pinctrl_dev *pctldev,
 547                             struct pinctrl_gpio_range *range, unsigned pin)
 548 {
 549         struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
 550         struct pcs_gpiofunc_range *frange = NULL;
 551         struct list_head *pos, *tmp;
 552         int mux_bytes = 0;
 553         unsigned data;
 554
 555         /* If function mask is null, return directly. */
 556         if (!pcs->fmask)
 557                 return -ENOTSUPP;
 558
 559         list_for_each_safe(pos, tmp, &pcs->gpiofuncs) {
 560                 frange = list_entry(pos, struct pcs_gpiofunc_range, node);
 561                 if (pin >= frange->offset + frange->npins
 562                         || pin < frange->offset)
 563                         continue;
 564                 mux_bytes = pcs->width / BITS_PER_BYTE;
 565                 data = pcs->read(pcs->base + pin * mux_bytes) & ~pcs->fmask;
 566                 data |= frange->gpiofunc;
 567                 pcs->write(data, pcs->base + pin * mux_bytes);
 568                 break;
 569         }
 570         return 0;
 571 }
 572
 573 static const struct pinmux_ops pcs_pinmux_ops = {
 574         .get_functions_count = pcs_get_functions_count,
 575         .get_function_name = pcs_get_function_name,
 576         .get_function_groups = pcs_get_function_groups,
 577         .enable = pcs_enable,
 578         .disable = pcs_disable,
 579         .gpio_request_enable = pcs_request_gpio,
 580 };
 581
 582 /* Clear BIAS value */
 583 static void pcs_pinconf_clear_bias(struct pinctrl_dev *pctldev, unsigned pin)
 584 {
 585         unsigned long config;
 586         int i;
 587         for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
 588                 config = pinconf_to_config_packed(pcs_bias[i], 0);
 589                 pcs_pinconf_set(pctldev, pin, &config, 1);
 590         }
 591 }
 592
 593 /*
 594  * Check whether PIN_CONFIG_BIAS_DISABLE is valid.
 595  * It's depend on that PULL_DOWN & PULL_UP configs are all invalid.
 596  */
 597 static bool pcs_pinconf_bias_disable(struct pinctrl_dev *pctldev, unsigned pin)
 598 {
 599         unsigned long config;
 600         int i;
 601
 602         for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
 603                 config = pinconf_to_config_packed(pcs_bias[i], 0);
 604                 if (!pcs_pinconf_get(pctldev, pin, &config))
 605                         goto out;
 606         }
 607         return true;
 608 out:
 609         return false;
 610 }
 611
 612 static int pcs_pinconf_get(struct pinctrl_dev *pctldev,
 613                                 unsigned pin, unsigned long *config)
 614 {
 615         struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
 616         struct pcs_function *func;
 617         enum pin_config_param param;
 618         unsigned offset = 0, data = 0, i, j, ret;
 619
 620         ret = pcs_get_function(pctldev, pin, &func);
 621         if (ret)
 622                 return ret;
 623
 624         for (i = 0; i < func->nconfs; i++) {
 625                 param = pinconf_to_config_param(*config);
 626                 if (param == PIN_CONFIG_BIAS_DISABLE) {
 627                         if (pcs_pinconf_bias_disable(pctldev, pin)) {
 628                                 *config = 0;
 629                                 return 0;
 630                         } else {
 631                                 return -ENOTSUPP;
 632                         }
 633                 } else if (param != func->conf[i].param) {
 634                         continue;
 635                 }
 636
 637                 offset = pin * (pcs->width / BITS_PER_BYTE);
 638                 data = pcs->read(pcs->base + offset) & func->conf[i].mask;
 639                 switch (func->conf[i].param) {
 640                 /* 4 parameters */
 641                 case PIN_CONFIG_BIAS_PULL_DOWN:
 642                 case PIN_CONFIG_BIAS_PULL_UP:
 643                 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 644                         if ((data != func->conf[i].enable) ||
 645                             (data == func->conf[i].disable))
 646                                 return -ENOTSUPP;
 647                         *config = 0;
 648                         break;
 649                 /* 2 parameters */
 650                 case PIN_CONFIG_INPUT_SCHMITT:
 651                         for (j = 0; j < func->nconfs; j++) {
 652                                 switch (func->conf[j].param) {
 653                                 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 654                                         if (data != func->conf[j].enable)
 655                                                 return -ENOTSUPP;
 656                                         break;
 657                                 default:
 658                                         break;
 659                                 }
 660                         }
 661                         *config = data;
 662                         break;
 663                 case PIN_CONFIG_DRIVE_STRENGTH:
 664                 case PIN_CONFIG_SLEW_RATE:
 665                 case PIN_CONFIG_LOW_POWER_MODE:
 666                 default:
 667                         *config = data;
 668                         break;
 669                 }
 670                 return 0;
 671         }
 672         return -ENOTSUPP;
 673 }
 674
 675 static int pcs_pinconf_set(struct pinctrl_dev *pctldev,
 676                                 unsigned pin, unsigned long *configs,
 677                                 unsigned num_configs)
 678 {
 679         struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
 680         struct pcs_function *func;
 681         unsigned offset = 0, shift = 0, i, data, ret;
 682         u16 arg;
 683         int j;
 684
 685         ret = pcs_get_function(pctldev, pin, &func);
 686         if (ret)
 687                 return ret;
 688
 689         for (j = 0; j < num_configs; j++) {
 690                 for (i = 0; i < func->nconfs; i++) {
 691                         if (pinconf_to_config_param(configs[j])
 692                                 != func->conf[i].param)
 693                                 continue;
 694
 695                         offset = pin * (pcs->width / BITS_PER_BYTE);
 696                         data = pcs->read(pcs->base + offset);
 697                         arg = pinconf_to_config_argument(configs[j]);
 698                         switch (func->conf[i].param) {
 699                         /* 2 parameters */
 700                         case PIN_CONFIG_INPUT_SCHMITT:
 701                         case PIN_CONFIG_DRIVE_STRENGTH:
 702                         case PIN_CONFIG_SLEW_RATE:
 703                         case PIN_CONFIG_LOW_POWER_MODE:
 704                                 shift = ffs(func->conf[i].mask) - 1;
 705                                 data &= ~func->conf[i].mask;
 706                                 data |= (arg << shift) & func->conf[i].mask;
 707                                 break;
 708                         /* 4 parameters */
 709                         case PIN_CONFIG_BIAS_DISABLE:
 710                                 pcs_pinconf_clear_bias(pctldev, pin);
 711                                 break;
 712                         case PIN_CONFIG_BIAS_PULL_DOWN:
 713                         case PIN_CONFIG_BIAS_PULL_UP:
 714                                 if (arg)
 715                                         pcs_pinconf_clear_bias(pctldev, pin);
 716                                 /* fall through */
 717                         case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 718                                 data &= ~func->conf[i].mask;
 719                                 if (arg)
 720                                         data |= func->conf[i].enable;
 721                                 else
 722                                         data |= func->conf[i].disable;
 723                                 break;
 724                         default:
 725                                 return -ENOTSUPP;
 726                         }
 727                         pcs->write(data, pcs->base + offset);
 728
 729                         break;
 730                 }
 731                 if (i >= func->nconfs)
 732                         return -ENOTSUPP;
 733         } /* for each config */
 734
 735         return 0;
 736 }
 737
 738 static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev,
 739                                 unsigned group, unsigned long *config)
 740 {
 741         const unsigned *pins;
 742         unsigned npins, old = 0;
 743         int i, ret;
 744
 745         ret = pcs_get_group_pins(pctldev, group, &pins, &npins);
 746         if (ret)
 747                 return ret;
 748         for (i = 0; i < npins; i++) {
 749                 if (pcs_pinconf_get(pctldev, pins[i], config))
 750                         return -ENOTSUPP;
 751                 /* configs do not match between two pins */
 752                 if (i && (old != *config))
 753                         return -ENOTSUPP;
 754                 old = *config;
 755         }
 756         return 0;
 757 }
 758
 759 static int pcs_pinconf_group_set(struct pinctrl_dev *pctldev,
 760                                 unsigned group, unsigned long *configs,
 761                                 unsigned num_configs)
 762 {
 763         const unsigned *pins;
 764         unsigned npins;
 765         int i, ret;
 766
 767         ret = pcs_get_group_pins(pctldev, group, &pins, &npins);
 768         if (ret)
 769                 return ret;
 770         for (i = 0; i < npins; i++) {
 771                 if (pcs_pinconf_set(pctldev, pins[i], configs, num_configs))
 772                         return -ENOTSUPP;
 773         }
 774         return 0;
 775 }
 776
 777 static void pcs_pinconf_dbg_show(struct pinctrl_dev *pctldev,
 778                                 struct seq_file *s, unsigned pin)
 779 {
 780 }
 781
 782 static void pcs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
 783                                 struct seq_file *s, unsigned selector)
 784 {
 785 }
 786
 787 static void pcs_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
 788                                         struct seq_file *s,
 789                                         unsigned long config)
 790 {
 791         pinconf_generic_dump_config(pctldev, s, config);
 792 }
 793
 794 static const struct pinconf_ops pcs_pinconf_ops = {
 795         .pin_config_get = pcs_pinconf_get,
 796         .pin_config_set = pcs_pinconf_set,
 797         .pin_config_group_get = pcs_pinconf_group_get,
 798         .pin_config_group_set = pcs_pinconf_group_set,
 799         .pin_config_dbg_show = pcs_pinconf_dbg_show,
 800         .pin_config_group_dbg_show = pcs_pinconf_group_dbg_show,
 801         .pin_config_config_dbg_show = pcs_pinconf_config_dbg_show,
 802         .is_generic = true,
 803 };
 804
 805 /**
 806  * pcs_add_pin() - add a pin to the static per controller pin array
 807  * @pcs: pcs driver instance
 808  * @offset: register offset from base
 809  */
 810 static int pcs_add_pin(struct pcs_device *pcs, unsigned offset,
 811                 unsigned pin_pos)
 812 {
 813         struct pcs_soc_data *pcs_soc = &pcs->socdata;
 814         struct pinctrl_pin_desc *pin;
 815         struct pcs_name *pn;
 816         int i;
 817
 818         i = pcs->pins.cur;
 819         if (i >= pcs->desc.npins) {
 820                 dev_err(pcs->dev, "too many pins, max %i\n",
 821                         pcs->desc.npins);
 822                 return -ENOMEM;
 823         }
 824
 825         if (pcs_soc->irq_enable_mask) {
 826                 unsigned val;
 827
 828                 val = pcs->read(pcs->base + offset);
 829                 if (val & pcs_soc->irq_enable_mask) {
 830                         dev_dbg(pcs->dev, "irq enabled at boot for pin at %lx (%x), clearing\n",
 831                                 (unsigned long)pcs->res->start + offset, val);
 832                         val &= ~pcs_soc->irq_enable_mask;
 833                         pcs->write(val, pcs->base + offset);
 834                 }
 835         }
 836
 837         pin = &pcs->pins.pa[i];
 838         pn = &pcs->names[i];
 839         sprintf(pn->name, "%lx.%d",
 840                 (unsigned long)pcs->res->start + offset, pin_pos);
 841         pin->name = pn->name;
 842         pin->number = i;
 843         pcs->pins.cur++;
 844
 845         return i;
 846 }
 847
 848 /**
 849  * pcs_allocate_pin_table() - adds all the pins for the pinctrl driver
 850  * @pcs: pcs driver instance
 851  *
 852  * In case of errors, resources are freed in pcs_free_resources.
 853  *
 854  * If your hardware needs holes in the address space, then just set
 855  * up multiple driver instances.
 856  */
 857 static int pcs_allocate_pin_table(struct pcs_device *pcs)
 858 {
 859         int mux_bytes, nr_pins, i;
 860         int num_pins_in_register = 0;
 861
 862         mux_bytes = pcs->width / BITS_PER_BYTE;
 863
 864         if (pcs->bits_per_mux) {
 865                 pcs->bits_per_pin = fls(pcs->fmask);
 866                 nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin;
 867                 num_pins_in_register = pcs->width / pcs->bits_per_pin;
 868         } else {
 869                 nr_pins = pcs->size / mux_bytes;
 870         }
 871
 872         dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins);
 873         pcs->pins.pa = devm_kzalloc(pcs->dev,
 874                                 sizeof(*pcs->pins.pa) * nr_pins,
 875                                 GFP_KERNEL);
 876         if (!pcs->pins.pa)
 877                 return -ENOMEM;
 878
 879         pcs->names = devm_kzalloc(pcs->dev,
 880                                 sizeof(struct pcs_name) * nr_pins,
 881                                 GFP_KERNEL);
 882         if (!pcs->names)
 883                 return -ENOMEM;
 884
 885         pcs->desc.pins = pcs->pins.pa;
 886         pcs->desc.npins = nr_pins;
 887
 888         for (i = 0; i < pcs->desc.npins; i++) {
 889                 unsigned offset;
 890                 int res;
 891                 int byte_num;
 892                 int pin_pos = 0;
 893
 894                 if (pcs->bits_per_mux) {
 895                         byte_num = (pcs->bits_per_pin * i) / BITS_PER_BYTE;
 896                         offset = (byte_num / mux_bytes) * mux_bytes;
 897                         pin_pos = i % num_pins_in_register;
 898                 } else {
 899                         offset = i * mux_bytes;
 900                 }
 901                 res = pcs_add_pin(pcs, offset, pin_pos);
 902                 if (res < 0) {
 903                         dev_err(pcs->dev, "error adding pins: %i\n", res);
 904                         return res;
 905                 }
 906         }
 907
 908         return 0;
 909 }
 910
 911 /**
 912  * pcs_add_function() - adds a new function to the function list
 913  * @pcs: pcs driver instance
 914  * @np: device node of the mux entry
 915  * @name: name of the function
 916  * @vals: array of mux register value pairs used by the function
 917  * @nvals: number of mux register value pairs
 918  * @pgnames: array of pingroup names for the function
 919  * @npgnames: number of pingroup names
 920  */
 921 static struct pcs_function *pcs_add_function(struct pcs_device *pcs,
 922                                         struct device_node *np,
 923                                         const char *name,
 924                                         struct pcs_func_vals *vals,
 925                                         unsigned nvals,
 926                                         const char **pgnames,
 927                                         unsigned npgnames)
 928 {
 929         struct pcs_function *function;
 930
 931         function = devm_kzalloc(pcs->dev, sizeof(*function), GFP_KERNEL);
 932         if (!function)
 933                 return NULL;
 934
 935         function->name = name;
 936         function->vals = vals;
 937         function->nvals = nvals;
 938         function->pgnames = pgnames;
 939         function->npgnames = npgnames;
 940
 941         mutex_lock(&pcs->mutex);
 942         list_add_tail(&function->node, &pcs->functions);
 943         radix_tree_insert(&pcs->ftree, pcs->nfuncs, function);
 944         pcs->nfuncs++;
 945         mutex_unlock(&pcs->mutex);
 946
 947         return function;
 948 }
 949
 950 static void pcs_remove_function(struct pcs_device *pcs,
 951                                 struct pcs_function *function)
 952 {
 953         int i;
 954
 955         mutex_lock(&pcs->mutex);
 956         for (i = 0; i < pcs->nfuncs; i++) {
 957                 struct pcs_function *found;
 958
 959                 found = radix_tree_lookup(&pcs->ftree, i);
 960                 if (found == function)
 961                         radix_tree_delete(&pcs->ftree, i);
 962         }
 963         list_del(&function->node);
 964         mutex_unlock(&pcs->mutex);
 965 }
 966
 967 /**
 968  * pcs_add_pingroup() - add a pingroup to the pingroup list
 969  * @pcs: pcs driver instance
 970  * @np: device node of the mux entry
 971  * @name: name of the pingroup
 972  * @gpins: array of the pins that belong to the group
 973  * @ngpins: number of pins in the group
 974  */
 975 static int pcs_add_pingroup(struct pcs_device *pcs,
 976                                         struct device_node *np,
 977                                         const char *name,
 978                                         int *gpins,
 979                                         int ngpins)
 980 {
 981         struct pcs_pingroup *pingroup;
 982
 983         pingroup = devm_kzalloc(pcs->dev, sizeof(*pingroup), GFP_KERNEL);
 984         if (!pingroup)
 985                 return -ENOMEM;
 986
 987         pingroup->name = name;
 988         pingroup->np = np;
 989         pingroup->gpins = gpins;
 990         pingroup->ngpins = ngpins;
 991
 992         mutex_lock(&pcs->mutex);
 993         list_add_tail(&pingroup->node, &pcs->pingroups);
 994         radix_tree_insert(&pcs->pgtree, pcs->ngroups, pingroup);
 995         pcs->ngroups++;
 996         mutex_unlock(&pcs->mutex);
 997
 998         return 0;
 999 }
1000
1001 /**
1002  * pcs_get_pin_by_offset() - get a pin index based on the register offset
1003  * @pcs: pcs driver instance
1004  * @offset: register offset from the base
1005  *
1006  * Note that this is OK as long as the pins are in a static array.
1007  */
1008 static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset)
1009 {
1010         unsigned index;
1011
1012         if (offset >= pcs->size) {
1013                 dev_err(pcs->dev, "mux offset out of range: 0x%x (0x%x)\n",
1014                         offset, pcs->size);
1015                 return -EINVAL;
1016         }
1017
1018         if (pcs->bits_per_mux)
1019                 index = (offset * BITS_PER_BYTE) / pcs->bits_per_pin;
1020         else
1021                 index = offset / (pcs->width / BITS_PER_BYTE);
1022
1023         return index;
1024 }
1025
1026 /*
1027  * check whether data matches enable bits or disable bits
1028  * Return value: 1 for matching enable bits, 0 for matching disable bits,
1029  *               and negative value for matching failure.
1030  */
1031 static int pcs_config_match(unsigned data, unsigned enable, unsigned disable)
1032 {
1033         int ret = -EINVAL;
1034
1035         if (data == enable)
1036                 ret = 1;
1037         else if (data == disable)
1038                 ret = 0;
1039         return ret;
1040 }
1041
1042 static void add_config(struct pcs_conf_vals **conf, enum pin_config_param param,
1043                        unsigned value, unsigned enable, unsigned disable,
1044                        unsigned mask)
1045 {
1046         (*conf)->param = param;
1047         (*conf)->val = value;
1048         (*conf)->enable = enable;
1049         (*conf)->disable = disable;
1050         (*conf)->mask = mask;
1051         (*conf)++;
1052 }
1053
1054 static void add_setting(unsigned long **setting, enum pin_config_param param,
1055                         unsigned arg)
1056 {
1057         **setting = pinconf_to_config_packed(param, arg);
1058         (*setting)++;
1059 }
1060
1061 /* add pinconf setting with 2 parameters */
1062 static void pcs_add_conf2(struct pcs_device *pcs, struct device_node *np,
1063                           const char *name, enum pin_config_param param,
1064                           struct pcs_conf_vals **conf, unsigned long **settings)
1065 {
1066         unsigned value[2], shift;
1067         int ret;
1068
1069         ret = of_property_read_u32_array(np, name, value, 2);
1070         if (ret)
1071                 return;
1072         /* set value & mask */
1073         value[0] &= value[1];
1074         shift = ffs(value[1]) - 1;
1075         /* skip enable & disable */
1076         add_config(conf, param, value[0], 0, 0, value[1]);
1077         add_setting(settings, param, value[0] >> shift);
1078 }
1079
1080 /* add pinconf setting with 4 parameters */
1081 static void pcs_add_conf4(struct pcs_device *pcs, struct device_node *np,
1082                           const char *name, enum pin_config_param param,
1083                           struct pcs_conf_vals **conf, unsigned long **settings)
1084 {
1085         unsigned value[4];
1086         int ret;
1087
1088         /* value to set, enable, disable, mask */
1089         ret = of_property_read_u32_array(np, name, value, 4);
1090         if (ret)
1091                 return;
1092         if (!value[3]) {
1093                 dev_err(pcs->dev, "mask field of the property can't be 0\n");
1094                 return;
1095         }
1096         value[0] &= value[3];
1097         value[1] &= value[3];
1098         value[2] &= value[3];
1099         ret = pcs_config_match(value[0], value[1], value[2]);
1100         if (ret < 0)
1101                 dev_dbg(pcs->dev, "failed to match enable or disable bits\n");
1102         add_config(conf, param, value[0], value[1], value[2], value[3]);
1103         add_setting(settings, param, ret);
1104 }
1105
1106 static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np,
1107                              struct pcs_function *func,
1108                              struct pinctrl_map **map)
1109
1110 {
1111         struct pinctrl_map *m = *map;
1112         int i = 0, nconfs = 0;
1113         unsigned long *settings = NULL, *s = NULL;
1114         struct pcs_conf_vals *conf = NULL;
1115         struct pcs_conf_type prop2[] = {
1116                 { "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, },
1117                 { "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, },
1118                 { "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, },
1119                 { "pinctrl-single,low-power-mode", PIN_CONFIG_LOW_POWER_MODE, },
1120         };
1121         struct pcs_conf_type prop4[] = {
1122                 { "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, },
1123                 { "pinctrl-single,bias-pulldown", PIN_CONFIG_BIAS_PULL_DOWN, },
1124                 { "pinctrl-single,input-schmitt-enable",
1125                         PIN_CONFIG_INPUT_SCHMITT_ENABLE, },
1126         };
1127
1128         /* If pinconf isn't supported, don't parse properties in below. */
1129         if (!PCS_HAS_PINCONF)
1130                 return 0;
1131
1132         /* cacluate how much properties are supported in current node */
1133         for (i = 0; i < ARRAY_SIZE(prop2); i++) {
1134                 if (of_find_property(np, prop2[i].name, NULL))
1135                         nconfs++;
1136         }
1137         for (i = 0; i < ARRAY_SIZE(prop4); i++) {
1138                 if (of_find_property(np, prop4[i].name, NULL))
1139                         nconfs++;
1140         }
1141         if (!nconfs)
1142                 return 0;
1143
1144         func->conf = devm_kzalloc(pcs->dev,
1145                                   sizeof(struct pcs_conf_vals) * nconfs,
1146                                   GFP_KERNEL);
1147         if (!func->conf)
1148                 return -ENOMEM;
1149         func->nconfs = nconfs;
1150         conf = &(func->conf[0]);
1151         m++;
1152         settings = devm_kzalloc(pcs->dev, sizeof(unsigned long) * nconfs,
1153                                 GFP_KERNEL);
1154         if (!settings)
1155                 return -ENOMEM;
1156         s = &settings[0];
1157
1158         for (i = 0; i < ARRAY_SIZE(prop2); i++)
1159                 pcs_add_conf2(pcs, np, prop2[i].name, prop2[i].param,
1160                               &conf, &s);
1161         for (i = 0; i < ARRAY_SIZE(prop4); i++)
1162                 pcs_add_conf4(pcs, np, prop4[i].name, prop4[i].param,
1163                               &conf, &s);
1164         m->type = PIN_MAP_TYPE_CONFIGS_GROUP;
1165         m->data.configs.group_or_pin = np->name;
1166         m->data.configs.configs = settings;
1167         m->data.configs.num_configs = nconfs;
1168         return 0;
1169 }
1170
1171 static void pcs_free_pingroups(struct pcs_device *pcs);
1172
1173 /**
1174  * smux_parse_one_pinctrl_entry() - parses a device tree mux entry
1175  * @pcs: pinctrl driver instance
1176  * @np: device node of the mux entry
1177  * @map: map entry
1178  * @num_maps: number of map
1179  * @pgnames: pingroup names
1180  *
1181  * Note that this binding currently supports only sets of one register + value.
1182  *
1183  * Also note that this driver tries to avoid understanding pin and function
1184  * names because of the extra bloat they would cause especially in the case of
1185  * a large number of pins. This driver just sets what is specified for the board
1186  * in the .dts file. Further user space debugging tools can be developed to
1187  * decipher the pin and function names using debugfs.
1188  *
1189  * If you are concerned about the boot time, set up the static pins in
1190  * the bootloader, and only set up selected pins as device tree entries.
1191  */
1192 static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
1193                                                 struct device_node *np,
1194                                                 struct pinctrl_map **map,
1195                                                 unsigned *num_maps,
1196                                                 const char **pgnames)
1197 {
1198         struct pcs_func_vals *vals;
1199         const __be32 *mux;
1200         int size, rows, *pins, index = 0, found = 0, res = -ENOMEM;
1201         struct pcs_function *function;
1202
1203         mux = of_get_property(np, PCS_MUX_PINS_NAME, &size);
1204         if ((!mux) || (size < sizeof(*mux) * 2)) {
1205                 dev_err(pcs->dev, "bad data for mux %s\n",
1206                         np->name);
1207                 return -EINVAL;
1208         }
1209
1210         size /= sizeof(*mux);   /* Number of elements in array */
1211         rows = size / 2;
1212
1213         vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows, GFP_KERNEL);
1214         if (!vals)
1215                 return -ENOMEM;
1216
1217         pins = devm_kzalloc(pcs->dev, sizeof(*pins) * rows, GFP_KERNEL);
1218         if (!pins)
1219                 goto free_vals;
1220
1221         while (index < size) {
1222                 unsigned offset, val;
1223                 int pin;
1224
1225                 offset = be32_to_cpup(mux + index++);
1226                 val = be32_to_cpup(mux + index++);
1227                 vals[found].reg = pcs->base + offset;
1228                 vals[found].val = val;
1229
1230                 pin = pcs_get_pin_by_offset(pcs, offset);
1231                 if (pin < 0) {
1232                         dev_err(pcs->dev,
1233                                 "could not add functions for %s %ux\n",
1234                                 np->name, offset);
1235                         break;
1236                 }
1237                 pins[found++] = pin;
1238         }
1239
1240         pgnames[0] = np->name;
1241         function = pcs_add_function(pcs, np, np->name, vals, found, pgnames, 1);
1242         if (!function)
1243                 goto free_pins;
1244
1245         res = pcs_add_pingroup(pcs, np, np->name, pins, found);
1246         if (res < 0)
1247                 goto free_function;
1248
1249         (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1250         (*map)->data.mux.group = np->name;
1251         (*map)->data.mux.function = np->name;
1252
1253         if (PCS_HAS_PINCONF) {
1254                 res = pcs_parse_pinconf(pcs, np, function, map);
1255                 if (res)
1256                         goto free_pingroups;
1257                 *num_maps = 2;
1258         } else {
1259                 *num_maps = 1;
1260         }
1261         return 0;
1262
1263 free_pingroups:
1264         pcs_free_pingroups(pcs);
1265         *num_maps = 1;
1266 free_function:
1267         pcs_remove_function(pcs, function);
1268
1269 free_pins:
1270         devm_kfree(pcs->dev, pins);
1271
1272 free_vals:
1273         devm_kfree(pcs->dev, vals);
1274
1275         return res;
1276 }
1277
1278 #define PARAMS_FOR_BITS_PER_MUX 3
1279
1280 static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs,
1281                                                 struct device_node *np,
1282                                                 struct pinctrl_map **map,
1283                                                 unsigned *num_maps,
1284                                                 const char **pgnames)
1285 {
1286         struct pcs_func_vals *vals;
1287         const __be32 *mux;
1288         int size, rows, *pins, index = 0, found = 0, res = -ENOMEM;
1289         int npins_in_row;
1290         struct pcs_function *function;
1291
1292         mux = of_get_property(np, PCS_MUX_BITS_NAME, &size);
1293
1294         if (!mux) {
1295                 dev_err(pcs->dev, "no valid property for %s\n", np->name);
1296                 return -EINVAL;
1297         }
1298
1299         if (size < (sizeof(*mux) * PARAMS_FOR_BITS_PER_MUX)) {
1300                 dev_err(pcs->dev, "bad data for %s\n", np->name);
1301                 return -EINVAL;
1302         }
1303
1304         /* Number of elements in array */
1305         size /= sizeof(*mux);
1306
1307         rows = size / PARAMS_FOR_BITS_PER_MUX;
1308         npins_in_row = pcs->width / pcs->bits_per_pin;
1309
1310         vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows * npins_in_row,
1311                         GFP_KERNEL);
1312         if (!vals)
1313                 return -ENOMEM;
1314
1315         pins = devm_kzalloc(pcs->dev, sizeof(*pins) * rows * npins_in_row,
1316                         GFP_KERNEL);
1317         if (!pins)
1318                 goto free_vals;
1319
1320         while (index < size) {
1321                 unsigned offset, val;
1322                 unsigned mask, bit_pos, val_pos, mask_pos, submask;
1323                 unsigned pin_num_from_lsb;
1324                 int pin;
1325
1326                 offset = be32_to_cpup(mux + index++);
1327                 val = be32_to_cpup(mux + index++);
1328                 mask = be32_to_cpup(mux + index++);
1329
1330                 /* Parse pins in each row from LSB */
1331                 while (mask) {
1332                         bit_pos = ffs(mask);
1333                         pin_num_from_lsb = bit_pos / pcs->bits_per_pin;
1334                         mask_pos = ((pcs->fmask) << (bit_pos - 1));
1335                         val_pos = val & mask_pos;
1336                         submask = mask & mask_pos;
1337
1338                         if ((mask & mask_pos) == 0) {
1339                                 dev_err(pcs->dev,
1340                                         "Invalid mask for %s at 0x%x\n",
1341                                         np->name, offset);
1342                                 break;
1343                         }
1344
1345                         mask &= ~mask_pos;
1346
1347                         if (submask != mask_pos) {
1348                                 dev_warn(pcs->dev,
1349                                                 "Invalid submask 0x%x for %s at 0x%x\n",
1350                                                 submask, np->name, offset);
1351                                 continue;
1352                         }
1353
1354                         vals[found].mask = submask;
1355                         vals[found].reg = pcs->base + offset;
1356                         vals[found].val = val_pos;
1357
1358                         pin = pcs_get_pin_by_offset(pcs, offset);
1359                         if (pin < 0) {
1360                                 dev_err(pcs->dev,
1361                                         "could not add functions for %s %ux\n",
1362                                         np->name, offset);
1363                                 break;
1364                         }
1365                         pins[found++] = pin + pin_num_from_lsb;
1366                 }
1367         }
1368
1369         pgnames[0] = np->name;
1370         function = pcs_add_function(pcs, np, np->name, vals, found, pgnames, 1);
1371         if (!function)
1372                 goto free_pins;
1373
1374         res = pcs_add_pingroup(pcs, np, np->name, pins, found);
1375         if (res < 0)
1376                 goto free_function;
1377
1378         (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1379         (*map)->data.mux.group = np->name;
1380         (*map)->data.mux.function = np->name;
1381
1382         if (PCS_HAS_PINCONF) {
1383                 dev_err(pcs->dev, "pinconf not supported\n");
1384                 goto free_pingroups;
1385         }
1386
1387         *num_maps = 1;
1388         return 0;
1389
1390 free_pingroups:
1391         pcs_free_pingroups(pcs);
1392         *num_maps = 1;
1393 free_function:
1394         pcs_remove_function(pcs, function);
1395
1396 free_pins:
1397         devm_kfree(pcs->dev, pins);
1398
1399 free_vals:
1400         devm_kfree(pcs->dev, vals);
1401
1402         return res;
1403 }
1404 /**
1405  * pcs_dt_node_to_map() - allocates and parses pinctrl maps
1406  * @pctldev: pinctrl instance
1407  * @np_config: device tree pinmux entry
1408  * @map: array of map entries
1409  * @num_maps: number of maps
1410  */
1411 static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
1412                                 struct device_node *np_config,
1413                                 struct pinctrl_map **map, unsigned *num_maps)
1414 {
1415         struct pcs_device *pcs;
1416         const char **pgnames;
1417         int ret;
1418
1419         pcs = pinctrl_dev_get_drvdata(pctldev);
1420
1421         /* create 2 maps. One is for pinmux, and the other is for pinconf. */
1422         *map = devm_kzalloc(pcs->dev, sizeof(**map) * 2, GFP_KERNEL);
1423         if (!*map)
1424                 return -ENOMEM;
1425
1426         *num_maps = 0;
1427
1428         pgnames = devm_kzalloc(pcs->dev, sizeof(*pgnames), GFP_KERNEL);
1429         if (!pgnames) {
1430                 ret = -ENOMEM;
1431                 goto free_map;
1432         }
1433
1434         if (pcs->bits_per_mux) {
1435                 ret = pcs_parse_bits_in_pinctrl_entry(pcs, np_config, map,
1436                                 num_maps, pgnames);
1437                 if (ret < 0) {
1438                         dev_err(pcs->dev, "no pins entries for %s\n",
1439                                 np_config->name);
1440                         goto free_pgnames;
1441                 }
1442         } else {
1443                 ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map,
1444                                 num_maps, pgnames);
1445                 if (ret < 0) {
1446                         dev_err(pcs->dev, "no pins entries for %s\n",
1447                                 np_config->name);
1448                         goto free_pgnames;
1449                 }
1450         }
1451
1452         return 0;
1453
1454 free_pgnames:
1455         devm_kfree(pcs->dev, pgnames);
1456 free_map:
1457         devm_kfree(pcs->dev, *map);
1458
1459         return ret;
1460 }
1461
1462 /**
1463  * pcs_free_funcs() - free memory used by functions
1464  * @pcs: pcs driver instance
1465  */
1466 static void pcs_free_funcs(struct pcs_device *pcs)
1467 {
1468         struct list_head *pos, *tmp;
1469         int i;
1470
1471         mutex_lock(&pcs->mutex);
1472         for (i = 0; i < pcs->nfuncs; i++) {
1473                 struct pcs_function *func;
1474
1475                 func = radix_tree_lookup(&pcs->ftree, i);
1476                 if (!func)
1477                         continue;
1478                 radix_tree_delete(&pcs->ftree, i);
1479         }
1480         list_for_each_safe(pos, tmp, &pcs->functions) {
1481                 struct pcs_function *function;
1482
1483                 function = list_entry(pos, struct pcs_function, node);
1484                 list_del(&function->node);
1485         }
1486         mutex_unlock(&pcs->mutex);
1487 }
1488
1489 /**
1490  * pcs_free_pingroups() - free memory used by pingroups
1491  * @pcs: pcs driver instance
1492  */
1493 static void pcs_free_pingroups(struct pcs_device *pcs)
1494 {
1495         struct list_head *pos, *tmp;
1496         int i;
1497
1498         mutex_lock(&pcs->mutex);
1499         for (i = 0; i < pcs->ngroups; i++) {
1500                 struct pcs_pingroup *pingroup;
1501
1502                 pingroup = radix_tree_lookup(&pcs->pgtree, i);
1503                 if (!pingroup)
1504                         continue;
1505                 radix_tree_delete(&pcs->pgtree, i);
1506         }
1507         list_for_each_safe(pos, tmp, &pcs->pingroups) {
1508                 struct pcs_pingroup *pingroup;
1509
1510                 pingroup = list_entry(pos, struct pcs_pingroup, node);
1511                 list_del(&pingroup->node);
1512         }
1513         mutex_unlock(&pcs->mutex);
1514 }
1515
1516 /**
1517  * pcs_irq_free() - free interrupt
1518  * @pcs: pcs driver instance
1519  */
1520 static void pcs_irq_free(struct pcs_device *pcs)
1521 {
1522         struct pcs_soc_data *pcs_soc = &pcs->socdata;
1523
1524         if (pcs_soc->irq < 0)
1525                 return;
1526
1527         if (pcs->domain)
1528                 irq_domain_remove(pcs->domain);
1529
1530         if (PCS_QUIRK_HAS_SHARED_IRQ)
1531                 free_irq(pcs_soc->irq, pcs_soc);
1532         else
1533                 irq_set_chained_handler(pcs_soc->irq, NULL);
1534 }
1535
1536 /**
1537  * pcs_free_resources() - free memory used by this driver
1538  * @pcs: pcs driver instance
1539  */
1540 static void pcs_free_resources(struct pcs_device *pcs)
1541 {
1542         pcs_irq_free(pcs);
1543
1544         if (pcs->pctl)
1545                 pinctrl_unregister(pcs->pctl);
1546
1547         pcs_free_funcs(pcs);
1548         pcs_free_pingroups(pcs);
1549 }
1550
1551 #define PCS_GET_PROP_U32(name, reg, err)                                \
1552         do {                                                            \
1553                 ret = of_property_read_u32(np, name, reg);              \
1554                 if (ret) {                                              \
1555                         dev_err(pcs->dev, err);                         \
1556                         return ret;                                     \
1557                 }                                                       \
1558         } while (0);
1559
1560 static struct of_device_id pcs_of_match[];
1561
1562 static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs)
1563 {
1564         const char *propname = "pinctrl-single,gpio-range";
1565         const char *cellname = "#pinctrl-single,gpio-range-cells";
1566         struct of_phandle_args gpiospec;
1567         struct pcs_gpiofunc_range *range;
1568         int ret, i;
1569
1570         for (i = 0; ; i++) {
1571                 ret = of_parse_phandle_with_args(node, propname, cellname,
1572                                                  i, &gpiospec);
1573                 /* Do not treat it as error. Only treat it as end condition. */
1574                 if (ret) {
1575                         ret = 0;
1576                         break;
1577                 }
1578                 range = devm_kzalloc(pcs->dev, sizeof(*range), GFP_KERNEL);
1579                 if (!range) {
1580                         ret = -ENOMEM;
1581                         break;
1582                 }
1583                 range->offset = gpiospec.args[0];
1584                 range->npins = gpiospec.args[1];
1585                 range->gpiofunc = gpiospec.args[2];
1586                 mutex_lock(&pcs->mutex);
1587                 list_add_tail(&range->node, &pcs->gpiofuncs);
1588                 mutex_unlock(&pcs->mutex);
1589         }
1590         return ret;
1591 }
1592 /**
1593  * @reg:        virtual address of interrupt register
1594  * @hwirq:      hardware irq number
1595  * @irq:        virtual irq number
1596  * @node:       list node
1597  */
1598 struct pcs_interrupt {
1599         void __iomem *reg;
1600         irq_hw_number_t hwirq;
1601         unsigned int irq;
1602         struct list_head node;
1603 };
1604
1605 /**
1606  * pcs_irq_set() - enables or disables an interrupt
1607  *
1608  * Note that this currently assumes one interrupt per pinctrl
1609  * register that is typically used for wake-up events.
1610  */
1611 static inline void pcs_irq_set(struct pcs_soc_data *pcs_soc,
1612                                int irq, const bool enable)
1613 {
1614         struct pcs_device *pcs;
1615         struct list_head *pos;
1616         unsigned mask;
1617
1618         pcs = container_of(pcs_soc, struct pcs_device, socdata);
1619         list_for_each(pos, &pcs->irqs) {
1620                 struct pcs_interrupt *pcswi;
1621                 unsigned soc_mask;
1622
1623                 pcswi = list_entry(pos, struct pcs_interrupt, node);
1624                 if (irq != pcswi->irq)
1625                         continue;
1626
1627                 soc_mask = pcs_soc->irq_enable_mask;
1628                 raw_spin_lock(&pcs->lock);
1629                 mask = pcs->read(pcswi->reg);
1630                 if (enable)
1631                         mask |= soc_mask;
1632                 else
1633                         mask &= ~soc_mask;
1634                 pcs->write(mask, pcswi->reg);
1635                 raw_spin_unlock(&pcs->lock);
1636         }
1637
1638         if (pcs_soc->rearm)
1639                 pcs_soc->rearm();
1640 }
1641
1642 /**
1643  * pcs_irq_mask() - mask pinctrl interrupt
1644  * @d: interrupt data
1645  */
1646 static void pcs_irq_mask(struct irq_data *d)
1647 {
1648         struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
1649
1650         pcs_irq_set(pcs_soc, d->irq, false);
1651 }
1652
1653 /**
1654  * pcs_irq_unmask() - unmask pinctrl interrupt
1655  * @d: interrupt data
1656  */
1657 static void pcs_irq_unmask(struct irq_data *d)
1658 {
1659         struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
1660
1661         pcs_irq_set(pcs_soc, d->irq, true);
1662 }
1663
1664 /**
1665  * pcs_irq_set_wake() - toggle the suspend and resume wake up
1666  * @d: interrupt data
1667  * @state: wake-up state
1668  *
1669  * Note that this should be called only for suspend and resume.
1670  * For runtime PM, the wake-up events should be enabled by default.
1671  */
1672 static int pcs_irq_set_wake(struct irq_data *d, unsigned int state)
1673 {
1674         if (state)
1675                 pcs_irq_unmask(d);
1676         else
1677                 pcs_irq_mask(d);
1678
1679         return 0;
1680 }
1681
1682 /**
1683  * pcs_irq_handle() - common interrupt handler
1684  * @pcs_irq: interrupt data
1685  *
1686  * Note that this currently assumes we have one interrupt bit per
1687  * mux register. This interrupt is typically used for wake-up events.
1688  * For more complex interrupts different handlers can be specified.
1689  */
1690 static int pcs_irq_handle(struct pcs_soc_data *pcs_soc)
1691 {
1692         struct pcs_device *pcs;
1693         struct list_head *pos;
1694         int count = 0;
1695
1696         pcs = container_of(pcs_soc, struct pcs_device, socdata);
1697         list_for_each(pos, &pcs->irqs) {
1698                 struct pcs_interrupt *pcswi;
1699                 unsigned mask;
1700
1701                 pcswi = list_entry(pos, struct pcs_interrupt, node);
1702                 raw_spin_lock(&pcs->lock);
1703                 mask = pcs->read(pcswi->reg);
1704                 raw_spin_unlock(&pcs->lock);
1705                 if (mask & pcs_soc->irq_status_mask) {
1706                         generic_handle_irq(irq_find_mapping(pcs->domain,
1707                                                             pcswi->hwirq));
1708                         count++;
1709                 }
1710         }
1711
1712         return count;
1713 }
1714
1715 /**
1716  * pcs_irq_handler() - handler for the shared interrupt case
1717  * @irq: interrupt
1718  * @d: data
1719  *
1720  * Use this for cases where multiple instances of
1721  * pinctrl-single share a single interrupt like on omaps.
1722  */
1723 static irqreturn_t pcs_irq_handler(int irq, void *d)
1724 {
1725         struct pcs_soc_data *pcs_soc = d;
1726
1727         return pcs_irq_handle(pcs_soc) ? IRQ_HANDLED : IRQ_NONE;
1728 }
1729
1730 /**
1731  * pcs_irq_handle() - handler for the dedicated chained interrupt case
1732  * @irq: interrupt
1733  * @desc: interrupt descriptor
1734  *
1735  * Use this if you have a separate interrupt for each
1736  * pinctrl-single instance.
1737  */
1738 static void pcs_irq_chain_handler(unsigned int irq, struct irq_desc *desc)
1739 {
1740         struct pcs_soc_data *pcs_soc = irq_desc_get_handler_data(desc);
1741         struct irq_chip *chip;
1742         int res;
1743
1744         chip = irq_get_chip(irq);
1745         chained_irq_enter(chip, desc);
1746         res = pcs_irq_handle(pcs_soc);
1747         /* REVISIT: export and add handle_bad_irq(irq, desc)? */
1748         chained_irq_exit(chip, desc);
1749
1750         return;
1751 }
1752
1753 static int pcs_irqdomain_map(struct irq_domain *d, unsigned int irq,
1754                              irq_hw_number_t hwirq)
1755 {
1756         struct pcs_soc_data *pcs_soc = d->host_data;
1757         struct pcs_device *pcs;
1758         struct pcs_interrupt *pcswi;
1759
1760         pcs = container_of(pcs_soc, struct pcs_device, socdata);
1761         pcswi = devm_kzalloc(pcs->dev, sizeof(*pcswi), GFP_KERNEL);
1762         if (!pcswi)
1763                 return -ENOMEM;
1764
1765         pcswi->reg = pcs->base + hwirq;
1766         pcswi->hwirq = hwirq;
1767         pcswi->irq = irq;
1768
1769         mutex_lock(&pcs->mutex);
1770         list_add_tail(&pcswi->node, &pcs->irqs);
1771         mutex_unlock(&pcs->mutex);
1772
1773         irq_set_chip_data(irq, pcs_soc);
1774         irq_set_chip_and_handler(irq, &pcs->chip,
1775                                  handle_level_irq);
1776
1777 #ifdef CONFIG_ARM
1778         set_irq_flags(irq, IRQF_VALID);
1779 #else
1780         irq_set_noprobe(irq);
1781 #endif
1782
1783         return 0;
1784 }
1785
1786 static struct irq_domain_ops pcs_irqdomain_ops = {
1787         .map = pcs_irqdomain_map,
1788         .xlate = irq_domain_xlate_onecell,
1789 };
1790
1791 /**
1792  * pcs_irq_init_chained_handler() - set up a chained interrupt handler
1793  * @pcs: pcs driver instance
1794  * @np: device node pointer
1795  */
1796 static int pcs_irq_init_chained_handler(struct pcs_device *pcs,
1797                                         struct device_node *np)
1798 {
1799         struct pcs_soc_data *pcs_soc = &pcs->socdata;
1800         const char *name = "pinctrl";
1801         int num_irqs;
1802
1803         if (!pcs_soc->irq_enable_mask ||
1804             !pcs_soc->irq_status_mask) {
1805                 pcs_soc->irq = -1;
1806                 return -EINVAL;
1807         }
1808
1809         INIT_LIST_HEAD(&pcs->irqs);
1810         pcs->chip.name = name;
1811         pcs->chip.irq_ack = pcs_irq_mask;
1812         pcs->chip.irq_mask = pcs_irq_mask;
1813         pcs->chip.irq_unmask = pcs_irq_unmask;
1814         pcs->chip.irq_set_wake = pcs_irq_set_wake;
1815
1816         if (PCS_QUIRK_HAS_SHARED_IRQ) {
1817                 int res;
1818
1819                 res = request_irq(pcs_soc->irq, pcs_irq_handler,
1820                                   IRQF_SHARED | IRQF_NO_SUSPEND,
1821                                   name, pcs_soc);
1822                 if (res) {
1823                         pcs_soc->irq = -1;
1824                         return res;
1825                 }
1826         } else {
1827                 irq_set_handler_data(pcs_soc->irq, pcs_soc);
1828                 irq_set_chained_handler(pcs_soc->irq,
1829                                         pcs_irq_chain_handler);
1830         }
1831
1832         /*
1833          * We can use the register offset as the hardirq
1834          * number as irq_domain_add_simple maps them lazily.
1835          * This way we can easily support more than one
1836          * interrupt per function if needed.
1837          */
1838         num_irqs = pcs->size;
1839
1840         pcs->domain = irq_domain_add_simple(np, num_irqs, 0,
1841                                             &pcs_irqdomain_ops,
1842                                             pcs_soc);
1843         if (!pcs->domain) {
1844                 irq_set_chained_handler(pcs_soc->irq, NULL);
1845                 return -EINVAL;
1846         }
1847
1848         return 0;
1849 }
1850
1851 #ifdef CONFIG_PM
1852 static int pinctrl_single_suspend(struct platform_device *pdev,
1853                                         pm_message_t state)
1854 {
1855         struct pcs_device *pcs;
1856
1857         pcs = platform_get_drvdata(pdev);
1858         if (!pcs)
1859                 return -EINVAL;
1860
1861         return pinctrl_force_sleep(pcs->pctl);
1862 }
1863
1864 static int pinctrl_single_resume(struct platform_device *pdev)
1865 {
1866         struct pcs_device *pcs;
1867
1868         pcs = platform_get_drvdata(pdev);
1869         if (!pcs)
1870                 return -EINVAL;
1871
1872         return pinctrl_force_default(pcs->pctl);
1873 }
1874 #endif
1875
1876 static int pcs_probe(struct platform_device *pdev)
1877 {
1878         struct device_node *np = pdev->dev.of_node;
1879         const struct of_device_id *match;
1880         struct pcs_pdata *pdata;
1881         struct resource *res;
1882         struct pcs_device *pcs;
1883         const struct pcs_soc_data *soc;
1884         int ret;
1885
1886         match = of_match_device(pcs_of_match, &pdev->dev);
1887         if (!match)
1888                 return -EINVAL;
1889
1890         pcs = devm_kzalloc(&pdev->dev, sizeof(*pcs), GFP_KERNEL);
1891         if (!pcs) {
1892                 dev_err(&pdev->dev, "could not allocate\n");
1893                 return -ENOMEM;
1894         }
1895         pcs->dev = &pdev->dev;
1896         raw_spin_lock_init(&pcs->lock);
1897         mutex_init(&pcs->mutex);
1898         INIT_LIST_HEAD(&pcs->pingroups);
1899         INIT_LIST_HEAD(&pcs->functions);
1900         INIT_LIST_HEAD(&pcs->gpiofuncs);
1901         soc = match->data;
1902         pcs->flags = soc->flags;
1903         memcpy(&pcs->socdata, soc, sizeof(*soc));
1904
1905         PCS_GET_PROP_U32("pinctrl-single,register-width", &pcs->width,
1906                          "register width not specified\n");
1907
1908         ret = of_property_read_u32(np, "pinctrl-single,function-mask",
1909                                    &pcs->fmask);
1910         if (!ret) {
1911                 pcs->fshift = ffs(pcs->fmask) - 1;
1912                 pcs->fmax = pcs->fmask >> pcs->fshift;
1913         } else {
1914                 /* If mask property doesn't exist, function mux is invalid. */
1915                 pcs->fmask = 0;
1916                 pcs->fshift = 0;
1917                 pcs->fmax = 0;
1918         }
1919
1920         ret = of_property_read_u32(np, "pinctrl-single,function-off",
1921                                         &pcs->foff);
1922         if (ret)
1923                 pcs->foff = PCS_OFF_DISABLED;
1924
1925         pcs->bits_per_mux = of_property_read_bool(np,
1926                                                   "pinctrl-single,bit-per-mux");
1927
1928         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1929         if (!res) {
1930                 dev_err(pcs->dev, "could not get resource\n");
1931                 return -ENODEV;
1932         }
1933
1934         pcs->res = devm_request_mem_region(pcs->dev, res->start,
1935                         resource_size(res), DRIVER_NAME);
1936         if (!pcs->res) {
1937                 dev_err(pcs->dev, "could not get mem_region\n");
1938                 return -EBUSY;
1939         }
1940
1941         pcs->size = resource_size(pcs->res);
1942         pcs->base = devm_ioremap(pcs->dev, pcs->res->start, pcs->size);
1943         if (!pcs->base) {
1944                 dev_err(pcs->dev, "could not ioremap\n");
1945                 return -ENODEV;
1946         }
1947
1948         INIT_RADIX_TREE(&pcs->pgtree, GFP_KERNEL);
1949         INIT_RADIX_TREE(&pcs->ftree, GFP_KERNEL);
1950         platform_set_drvdata(pdev, pcs);
1951
1952         switch (pcs->width) {
1953         case 8:
1954                 pcs->read = pcs_readb;
1955                 pcs->write = pcs_writeb;
1956                 break;
1957         case 16:
1958                 pcs->read = pcs_readw;
1959                 pcs->write = pcs_writew;
1960                 break;
1961         case 32:
1962                 pcs->read = pcs_readl;
1963                 pcs->write = pcs_writel;
1964                 break;
1965         default:
1966                 break;
1967         }
1968
1969         pcs->desc.name = DRIVER_NAME;
1970         pcs->desc.pctlops = &pcs_pinctrl_ops;
1971         pcs->desc.pmxops = &pcs_pinmux_ops;
1972         if (PCS_HAS_PINCONF)
1973                 pcs->desc.confops = &pcs_pinconf_ops;
1974         pcs->desc.owner = THIS_MODULE;
1975
1976         ret = pcs_allocate_pin_table(pcs);
1977         if (ret < 0)
1978                 goto free;
1979
1980         pcs->pctl = pinctrl_register(&pcs->desc, pcs->dev, pcs);
1981         if (!pcs->pctl) {
1982                 dev_err(pcs->dev, "could not register single pinctrl driver\n");
1983                 ret = -EINVAL;
1984                 goto free;
1985         }
1986
1987         ret = pcs_add_gpio_func(np, pcs);
1988         if (ret < 0)
1989                 goto free;
1990
1991         pcs->socdata.irq = irq_of_parse_and_map(np, 0);
1992         if (pcs->socdata.irq)
1993                 pcs->flags |= PCS_FEAT_IRQ;
1994
1995         /* We still need auxdata for some omaps for PRM interrupts */
1996         pdata = dev_get_platdata(&pdev->dev);
1997         if (pdata) {
1998                 if (pdata->rearm)
1999                         pcs->socdata.rearm = pdata->rearm;
2000                 if (pdata->irq) {
2001                         pcs->socdata.irq = pdata->irq;
2002                         pcs->flags |= PCS_FEAT_IRQ;
2003                 }
2004         }
2005
2006         if (PCS_HAS_IRQ) {
2007                 ret = pcs_irq_init_chained_handler(pcs, np);
2008                 if (ret < 0)
2009                         dev_warn(pcs->dev, "initialized with no interrupts\n");
2010         }
2011
2012         dev_info(pcs->dev, "%i pins at pa %p size %u\n",
2013                  pcs->desc.npins, pcs->base, pcs->size);
2014
2015         return 0;
2016
2017 free:
2018         pcs_free_resources(pcs);
2019
2020         return ret;
2021 }
2022
2023 static int pcs_remove(struct platform_device *pdev)
2024 {
2025         struct pcs_device *pcs = platform_get_drvdata(pdev);
2026
2027         if (!pcs)
2028                 return 0;
2029
2030         pcs_free_resources(pcs);
2031
2032         return 0;
2033 }
2034
2035 static const struct pcs_soc_data pinctrl_single_omap_wkup = {
2036         .flags = PCS_QUIRK_SHARED_IRQ,
2037         .irq_enable_mask = (1 << 14),   /* OMAP_WAKEUP_EN */
2038         .irq_status_mask = (1 << 15),   /* OMAP_WAKEUP_EVENT */
2039 };
2040
2041 static const struct pcs_soc_data pinctrl_single = {
2042 };
2043
2044 static const struct pcs_soc_data pinconf_single = {
2045         .flags = PCS_FEAT_PINCONF,
2046 };
2047
2048 static struct of_device_id pcs_of_match[] = {
2049         { .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup },
2050         { .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup },
2051         { .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup },
2052         { .compatible = "pinctrl-single", .data = &pinctrl_single },
2053         { .compatible = "pinconf-single", .data = &pinconf_single },
2054         { },
2055 };
2056 MODULE_DEVICE_TABLE(of, pcs_of_match);
2057
2058 static struct platform_driver pcs_driver = {
2059         .probe          = pcs_probe,
2060         .remove         = pcs_remove,
2061         .driver = {
2062                 .owner          = THIS_MODULE,
2063                 .name           = DRIVER_NAME,
2064                 .of_match_table = pcs_of_match,
2065         },
2066 #ifdef CONFIG_PM
2067         .suspend = pinctrl_single_suspend,
2068         .resume = pinctrl_single_resume,
2069 #endif
2070 };
2071
2072 module_platform_driver(pcs_driver);
2073
2074 MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>");
2075 MODULE_DESCRIPTION("One-register-per-pin type device tree based pinctrl driver");
2076 MODULE_LICENSE("GPL v2");