4 * Copyright (C) 2007-2012 ST-Ericsson AB
5 * License terms: GNU General Public License (GPL) version 2
6 * COH 901 571/3 - Used in DB3210 (U365 2.0) and DB3350 (U335 1.0)
7 * Author: Linus Walleij <linus.walleij@linaro.org>
8 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
10 #include <linux/module.h>
11 #include <linux/irq.h>
12 #include <linux/interrupt.h>
13 #include <linux/delay.h>
14 #include <linux/errno.h>
16 #include <linux/clk.h>
17 #include <linux/err.h>
18 #include <linux/platform_device.h>
19 #include <linux/gpio.h>
20 #include <linux/list.h>
21 #include <linux/slab.h>
22 #include <linux/pinctrl/consumer.h>
23 #include <linux/pinctrl/pinconf-generic.h>
24 #include <linux/platform_data/pinctrl-coh901.h>
25 #include "pinctrl-coh901.h"
27 #define U300_GPIO_PORT_STRIDE (0x30)
29 * Control Register 32bit (R/W)
30 * bit 15-9 (mask 0x0000FE00) contains the number of cores. 8*cores
31 * gives the number of GPIO pins.
32 * bit 8-2 (mask 0x000001FC) contains the core version ID.
34 #define U300_GPIO_CR (0x00)
35 #define U300_GPIO_CR_SYNC_SEL_ENABLE (0x00000002UL)
36 #define U300_GPIO_CR_BLOCK_CLKRQ_ENABLE (0x00000001UL)
37 #define U300_GPIO_PXPDIR (0x04)
38 #define U300_GPIO_PXPDOR (0x08)
39 #define U300_GPIO_PXPCR (0x0C)
40 #define U300_GPIO_PXPCR_ALL_PINS_MODE_MASK (0x0000FFFFUL)
41 #define U300_GPIO_PXPCR_PIN_MODE_MASK (0x00000003UL)
42 #define U300_GPIO_PXPCR_PIN_MODE_SHIFT (0x00000002UL)
43 #define U300_GPIO_PXPCR_PIN_MODE_INPUT (0x00000000UL)
44 #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL (0x00000001UL)
45 #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN (0x00000002UL)
46 #define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE (0x00000003UL)
47 #define U300_GPIO_PXPER (0x10)
48 #define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK (0x000000FFUL)
49 #define U300_GPIO_PXPER_PULL_UP_DISABLE (0x00000001UL)
50 #define U300_GPIO_PXIEV (0x14)
51 #define U300_GPIO_PXIEN (0x18)
52 #define U300_GPIO_PXIFR (0x1C)
53 #define U300_GPIO_PXICR (0x20)
54 #define U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK (0x000000FFUL)
55 #define U300_GPIO_PXICR_IRQ_CONFIG_MASK (0x00000001UL)
56 #define U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE (0x00000000UL)
57 #define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE (0x00000001UL)
59 /* 8 bits per port, no version has more than 7 ports */
60 #define U300_GPIO_PINS_PER_PORT 8
61 #define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * 7)
64 struct gpio_chip chip;
65 struct list_head port_list;
67 struct resource *memres;
72 /* Register offsets */
82 struct u300_gpio_port {
83 struct list_head node;
84 struct u300_gpio *gpio;
92 * Macro to expand to read a specific register found in the "gpio"
93 * struct. It requires the struct u300_gpio *gpio variable to exist in
94 * its context. It calculates the port offset from the given pin
95 * offset, muliplies by the port stride and adds the register offset
96 * so it provides a pointer to the desired register.
98 #define U300_PIN_REG(pin, reg) \
99 (gpio->base + (pin >> 3) * gpio->stride + gpio->reg)
102 * Provides a bitmask for a specific gpio pin inside an 8-bit GPIO
105 #define U300_PIN_BIT(pin) \
108 struct u300_gpio_confdata {
114 /* BS335 has seven ports of 8 bits each = GPIO pins 0..55 */
115 #define BS335_GPIO_NUM_PORTS 7
117 #define U300_FLOATING_INPUT { \
118 .bias_mode = PIN_CONFIG_BIAS_HIGH_IMPEDANCE, \
122 #define U300_PULL_UP_INPUT { \
123 .bias_mode = PIN_CONFIG_BIAS_PULL_UP, \
127 #define U300_OUTPUT_LOW { \
132 #define U300_OUTPUT_HIGH { \
137 /* Initial configuration */
138 static const struct __initconst u300_gpio_confdata
139 bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
140 /* Port 0, pins 0-7 */
151 /* Port 1, pins 0-7 */
162 /* Port 2, pins 0-7 */
173 /* Port 3, pins 0-7 */
184 /* Port 4, pins 0-7 */
195 /* Port 5, pins 0-7 */
206 /* Port 6, pind 0-7 */
220 * to_u300_gpio() - get the pointer to u300_gpio
221 * @chip: the gpio chip member of the structure u300_gpio
223 static inline struct u300_gpio *to_u300_gpio(struct gpio_chip *chip)
225 return container_of(chip, struct u300_gpio, chip);
228 static int u300_gpio_request(struct gpio_chip *chip, unsigned offset)
231 * Map back to global GPIO space and request muxing, the direction
232 * parameter does not matter for this controller.
234 int gpio = chip->base + offset;
236 return pinctrl_request_gpio(gpio);
239 static void u300_gpio_free(struct gpio_chip *chip, unsigned offset)
241 int gpio = chip->base + offset;
243 pinctrl_free_gpio(gpio);
246 static int u300_gpio_get(struct gpio_chip *chip, unsigned offset)
248 struct u300_gpio *gpio = to_u300_gpio(chip);
250 return readl(U300_PIN_REG(offset, dir)) & U300_PIN_BIT(offset);
253 static void u300_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
255 struct u300_gpio *gpio = to_u300_gpio(chip);
259 local_irq_save(flags);
261 val = readl(U300_PIN_REG(offset, dor));
263 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, dor));
265 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, dor));
267 local_irq_restore(flags);
270 static int u300_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
272 struct u300_gpio *gpio = to_u300_gpio(chip);
276 local_irq_save(flags);
277 val = readl(U300_PIN_REG(offset, pcr));
278 /* Mask out this pin, note 2 bits per setting */
279 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1));
280 writel(val, U300_PIN_REG(offset, pcr));
281 local_irq_restore(flags);
285 static int u300_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
288 struct u300_gpio *gpio = to_u300_gpio(chip);
293 local_irq_save(flags);
294 val = readl(U300_PIN_REG(offset, pcr));
296 * Drive mode must be set by the special mode set function, set
297 * push/pull mode by default if no mode has been selected.
299 oldmode = val & (U300_GPIO_PXPCR_PIN_MODE_MASK <<
300 ((offset & 0x07) << 1));
301 /* mode = 0 means input, else some mode is already set */
303 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK <<
304 ((offset & 0x07) << 1));
305 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL
306 << ((offset & 0x07) << 1));
307 writel(val, U300_PIN_REG(offset, pcr));
309 u300_gpio_set(chip, offset, value);
310 local_irq_restore(flags);
314 static int u300_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
316 struct u300_gpio *gpio = to_u300_gpio(chip);
317 int retirq = gpio->irq_base + offset;
319 dev_dbg(gpio->dev, "request IRQ for GPIO %d, return %d\n", offset,
324 /* Returning -EINVAL means "supported but not available" */
325 int u300_gpio_config_get(struct gpio_chip *chip,
327 unsigned long *config)
329 struct u300_gpio *gpio = to_u300_gpio(chip);
330 enum pin_config_param param = (enum pin_config_param) *config;
334 /* One bit per pin, clamp to bool range */
335 biasmode = !!(readl(U300_PIN_REG(offset, per)) & U300_PIN_BIT(offset));
337 /* Mask out the two bits for this pin and shift to bits 0,1 */
338 drmode = readl(U300_PIN_REG(offset, pcr));
339 drmode &= (U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1));
340 drmode >>= ((offset & 0x07) << 1);
343 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
350 case PIN_CONFIG_BIAS_PULL_UP:
357 case PIN_CONFIG_DRIVE_PUSH_PULL:
359 if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL)
364 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
366 if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN)
371 case PIN_CONFIG_DRIVE_OPEN_SOURCE:
373 if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE)
384 int u300_gpio_config_set(struct gpio_chip *chip, unsigned offset,
385 enum pin_config_param param)
387 struct u300_gpio *gpio = to_u300_gpio(chip);
391 local_irq_save(flags);
393 case PIN_CONFIG_BIAS_DISABLE:
394 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
395 val = readl(U300_PIN_REG(offset, per));
396 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, per));
398 case PIN_CONFIG_BIAS_PULL_UP:
399 val = readl(U300_PIN_REG(offset, per));
400 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, per));
402 case PIN_CONFIG_DRIVE_PUSH_PULL:
403 val = readl(U300_PIN_REG(offset, pcr));
404 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
405 << ((offset & 0x07) << 1));
406 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL
407 << ((offset & 0x07) << 1));
408 writel(val, U300_PIN_REG(offset, pcr));
410 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
411 val = readl(U300_PIN_REG(offset, pcr));
412 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
413 << ((offset & 0x07) << 1));
414 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN
415 << ((offset & 0x07) << 1));
416 writel(val, U300_PIN_REG(offset, pcr));
418 case PIN_CONFIG_DRIVE_OPEN_SOURCE:
419 val = readl(U300_PIN_REG(offset, pcr));
420 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
421 << ((offset & 0x07) << 1));
422 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE
423 << ((offset & 0x07) << 1));
424 writel(val, U300_PIN_REG(offset, pcr));
427 local_irq_restore(flags);
428 dev_err(gpio->dev, "illegal configuration requested\n");
431 local_irq_restore(flags);
435 static struct gpio_chip u300_gpio_chip = {
436 .label = "u300-gpio-chip",
437 .owner = THIS_MODULE,
438 .request = u300_gpio_request,
439 .free = u300_gpio_free,
440 .get = u300_gpio_get,
441 .set = u300_gpio_set,
442 .direction_input = u300_gpio_direction_input,
443 .direction_output = u300_gpio_direction_output,
444 .to_irq = u300_gpio_to_irq,
447 static void u300_toggle_trigger(struct u300_gpio *gpio, unsigned offset)
451 val = readl(U300_PIN_REG(offset, icr));
452 /* Set mode depending on state */
453 if (u300_gpio_get(&gpio->chip, offset)) {
454 /* High now, let's trigger on falling edge next then */
455 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
456 dev_dbg(gpio->dev, "next IRQ on falling edge on pin %d\n",
459 /* Low now, let's trigger on rising edge next then */
460 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
461 dev_dbg(gpio->dev, "next IRQ on rising edge on pin %d\n",
466 static int u300_gpio_irq_type(struct irq_data *d, unsigned trigger)
468 struct u300_gpio_port *port = irq_data_get_irq_chip_data(d);
469 struct u300_gpio *gpio = port->gpio;
470 int offset = d->irq - gpio->irq_base;
473 if ((trigger & IRQF_TRIGGER_RISING) &&
474 (trigger & IRQF_TRIGGER_FALLING)) {
476 * The GPIO block can only trigger on falling OR rising edges,
477 * not both. So we need to toggle the mode whenever the pin
478 * goes from one state to the other with a special state flag
481 "trigger on both rising and falling edge on pin %d\n",
483 port->toggle_edge_mode |= U300_PIN_BIT(offset);
484 u300_toggle_trigger(gpio, offset);
485 } else if (trigger & IRQF_TRIGGER_RISING) {
486 dev_dbg(gpio->dev, "trigger on rising edge on pin %d\n",
488 val = readl(U300_PIN_REG(offset, icr));
489 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
490 port->toggle_edge_mode &= ~U300_PIN_BIT(offset);
491 } else if (trigger & IRQF_TRIGGER_FALLING) {
492 dev_dbg(gpio->dev, "trigger on falling edge on pin %d\n",
494 val = readl(U300_PIN_REG(offset, icr));
495 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
496 port->toggle_edge_mode &= ~U300_PIN_BIT(offset);
502 static void u300_gpio_irq_enable(struct irq_data *d)
504 struct u300_gpio_port *port = irq_data_get_irq_chip_data(d);
505 struct u300_gpio *gpio = port->gpio;
506 int offset = d->irq - gpio->irq_base;
510 local_irq_save(flags);
511 val = readl(U300_PIN_REG(offset, ien));
512 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, ien));
513 local_irq_restore(flags);
516 static void u300_gpio_irq_disable(struct irq_data *d)
518 struct u300_gpio_port *port = irq_data_get_irq_chip_data(d);
519 struct u300_gpio *gpio = port->gpio;
520 int offset = d->irq - gpio->irq_base;
524 local_irq_save(flags);
525 val = readl(U300_PIN_REG(offset, ien));
526 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, ien));
527 local_irq_restore(flags);
530 static struct irq_chip u300_gpio_irqchip = {
531 .name = "u300-gpio-irqchip",
532 .irq_enable = u300_gpio_irq_enable,
533 .irq_disable = u300_gpio_irq_disable,
534 .irq_set_type = u300_gpio_irq_type,
538 static void u300_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
540 struct u300_gpio_port *port = irq_get_handler_data(irq);
541 struct u300_gpio *gpio = port->gpio;
542 int pinoffset = port->number << 3; /* get the right stride */
545 desc->irq_data.chip->irq_ack(&desc->irq_data);
546 /* Read event register */
547 val = readl(U300_PIN_REG(pinoffset, iev));
548 /* Mask relevant bits */
549 val &= 0xFFU; /* 8 bits per port */
550 /* ACK IRQ (clear event) */
551 writel(val, U300_PIN_REG(pinoffset, iev));
553 /* Call IRQ handler */
557 for_each_set_bit(irqoffset, &val, U300_GPIO_PINS_PER_PORT) {
558 int pin_irq = gpio->irq_base + (port->number << 3)
560 int offset = pinoffset + irqoffset;
562 dev_dbg(gpio->dev, "GPIO IRQ %d on pin %d\n",
564 generic_handle_irq(pin_irq);
566 * Triggering IRQ on both rising and falling edge
569 if (port->toggle_edge_mode & U300_PIN_BIT(offset))
570 u300_toggle_trigger(gpio, offset);
574 desc->irq_data.chip->irq_unmask(&desc->irq_data);
577 static void __init u300_gpio_init_pin(struct u300_gpio *gpio,
579 const struct u300_gpio_confdata *conf)
581 /* Set mode: input or output */
583 u300_gpio_direction_output(&gpio->chip, offset, conf->outval);
585 /* Deactivate bias mode for output */
586 u300_gpio_config_set(&gpio->chip, offset,
587 PIN_CONFIG_BIAS_HIGH_IMPEDANCE);
589 /* Set drive mode for output */
590 u300_gpio_config_set(&gpio->chip, offset,
591 PIN_CONFIG_DRIVE_PUSH_PULL);
593 dev_dbg(gpio->dev, "set up pin %d as output, value: %d\n",
594 offset, conf->outval);
596 u300_gpio_direction_input(&gpio->chip, offset);
598 /* Always set output low on input pins */
599 u300_gpio_set(&gpio->chip, offset, 0);
601 /* Set bias mode for input */
602 u300_gpio_config_set(&gpio->chip, offset, conf->bias_mode);
604 dev_dbg(gpio->dev, "set up pin %d as input, bias: %04x\n",
605 offset, conf->bias_mode);
609 static void __init u300_gpio_init_coh901571(struct u300_gpio *gpio,
610 struct u300_gpio_platform *plat)
614 /* Write default config and values to all pins */
615 for (i = 0; i < plat->ports; i++) {
616 for (j = 0; j < 8; j++) {
617 const struct u300_gpio_confdata *conf;
618 int offset = (i*8) + j;
620 conf = &bs335_gpio_config[i][j];
621 u300_gpio_init_pin(gpio, offset, conf);
626 static inline void u300_gpio_free_ports(struct u300_gpio *gpio)
628 struct u300_gpio_port *port;
629 struct list_head *p, *n;
631 list_for_each_safe(p, n, &gpio->port_list) {
632 port = list_entry(p, struct u300_gpio_port, node);
633 list_del(&port->node);
638 static int __init u300_gpio_probe(struct platform_device *pdev)
640 struct u300_gpio_platform *plat = dev_get_platdata(&pdev->dev);
641 struct u300_gpio *gpio;
648 gpio = kzalloc(sizeof(struct u300_gpio), GFP_KERNEL);
650 dev_err(&pdev->dev, "failed to allocate memory\n");
654 gpio->chip = u300_gpio_chip;
655 gpio->chip.ngpio = plat->ports * U300_GPIO_PINS_PER_PORT;
656 gpio->irq_base = plat->gpio_irq_base;
657 gpio->chip.dev = &pdev->dev;
658 gpio->chip.base = plat->gpio_base;
659 gpio->dev = &pdev->dev;
662 gpio->clk = clk_get(gpio->dev, NULL);
663 if (IS_ERR(gpio->clk)) {
664 err = PTR_ERR(gpio->clk);
665 dev_err(gpio->dev, "could not get GPIO clock\n");
668 err = clk_prepare_enable(gpio->clk);
670 dev_err(gpio->dev, "could not enable GPIO clock\n");
671 goto err_no_clk_enable;
674 gpio->memres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
676 dev_err(gpio->dev, "could not get GPIO memory resource\n");
678 goto err_no_resource;
681 if (!request_mem_region(gpio->memres->start,
682 resource_size(gpio->memres),
683 "GPIO Controller")) {
685 goto err_no_ioregion;
688 gpio->base = ioremap(gpio->memres->start, resource_size(gpio->memres));
695 "initializing GPIO Controller COH 901 571/3\n");
696 gpio->stride = U300_GPIO_PORT_STRIDE;
697 gpio->pcr = U300_GPIO_PXPCR;
698 gpio->dor = U300_GPIO_PXPDOR;
699 gpio->dir = U300_GPIO_PXPDIR;
700 gpio->per = U300_GPIO_PXPER;
701 gpio->icr = U300_GPIO_PXICR;
702 gpio->ien = U300_GPIO_PXIEN;
703 gpio->iev = U300_GPIO_PXIEV;
704 ifr = U300_GPIO_PXIFR;
706 val = readl(gpio->base + U300_GPIO_CR);
707 dev_info(gpio->dev, "COH901571/3 block version: %d, " \
708 "number of cores: %d totalling %d pins\n",
709 ((val & 0x000001FC) >> 2),
710 ((val & 0x0000FE00) >> 9),
711 ((val & 0x0000FE00) >> 9) * 8);
712 writel(U300_GPIO_CR_BLOCK_CLKRQ_ENABLE,
713 gpio->base + U300_GPIO_CR);
714 u300_gpio_init_coh901571(gpio, plat);
716 /* Add each port with its IRQ separately */
717 INIT_LIST_HEAD(&gpio->port_list);
718 for (portno = 0 ; portno < plat->ports; portno++) {
719 struct u300_gpio_port *port =
720 kmalloc(sizeof(struct u300_gpio_port), GFP_KERNEL);
723 dev_err(gpio->dev, "out of memory\n");
728 snprintf(port->name, 8, "gpio%d", portno);
729 port->number = portno;
732 port->irq = platform_get_irq_byname(pdev,
735 dev_dbg(gpio->dev, "register IRQ %d for %s\n", port->irq,
738 irq_set_chained_handler(port->irq, u300_gpio_irq_handler);
739 irq_set_handler_data(port->irq, port);
741 /* For each GPIO pin set the unique IRQ handler */
742 for (i = 0; i < U300_GPIO_PINS_PER_PORT; i++) {
743 int irqno = gpio->irq_base + (portno << 3) + i;
745 dev_dbg(gpio->dev, "handler for IRQ %d on %s\n",
747 irq_set_chip_and_handler(irqno, &u300_gpio_irqchip,
749 set_irq_flags(irqno, IRQF_VALID);
750 irq_set_chip_data(irqno, port);
753 /* Turns off irq force (test register) for this port */
754 writel(0x0, gpio->base + portno * gpio->stride + ifr);
756 list_add_tail(&port->node, &gpio->port_list);
758 dev_dbg(gpio->dev, "initialized %d GPIO ports\n", portno);
760 err = gpiochip_add(&gpio->chip);
762 dev_err(gpio->dev, "unable to add gpiochip: %d\n", err);
766 /* Spawn pin controller device as child of the GPIO, pass gpio chip */
767 plat->pinctrl_device->dev.platform_data = &gpio->chip;
768 err = platform_device_register(plat->pinctrl_device);
772 platform_set_drvdata(pdev, gpio);
777 err = gpiochip_remove(&gpio->chip);
780 u300_gpio_free_ports(gpio);
783 release_mem_region(gpio->memres->start, resource_size(gpio->memres));
786 clk_disable_unprepare(gpio->clk);
791 dev_info(&pdev->dev, "module ERROR:%d\n", err);
795 static int __exit u300_gpio_remove(struct platform_device *pdev)
797 struct u300_gpio *gpio = platform_get_drvdata(pdev);
800 /* Turn off the GPIO block */
801 writel(0x00000000U, gpio->base + U300_GPIO_CR);
803 err = gpiochip_remove(&gpio->chip);
805 dev_err(gpio->dev, "unable to remove gpiochip: %d\n", err);
808 u300_gpio_free_ports(gpio);
810 release_mem_region(gpio->memres->start,
811 resource_size(gpio->memres));
812 clk_disable_unprepare(gpio->clk);
814 platform_set_drvdata(pdev, NULL);
819 static struct platform_driver u300_gpio_driver = {
823 .remove = __exit_p(u300_gpio_remove),
826 static int __init u300_gpio_init(void)
828 return platform_driver_probe(&u300_gpio_driver, u300_gpio_probe);
831 static void __exit u300_gpio_exit(void)
833 platform_driver_unregister(&u300_gpio_driver);
836 arch_initcall(u300_gpio_init);
837 module_exit(u300_gpio_exit);
839 MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
840 MODULE_DESCRIPTION("ST-Ericsson AB COH 901 335/COH 901 571/3 GPIO driver");
841 MODULE_LICENSE("GPL");