1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2015 - 2019 MediaTek Inc.
4 * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
5 * Ryder Lee <ryder.lee@mediatek.com>
11 #include <generic-phy.h>
15 #include <dm/device_compat.h>
16 #include <dm/devres.h>
17 #include <linux/delay.h>
19 #include <dt-bindings/phy/phy.h>
21 /* version V1 sub-banks offset base address */
22 /* banks shared by multiple phys */
23 #define SSUSB_SIFSLV_V1_SPLLC 0x000 /* shared by u3 phys */
24 #define SSUSB_SIFSLV_V1_U2FREQ 0x100 /* shared by u2 phys */
25 #define SSUSB_SIFSLV_V1_CHIP 0x300 /* shared by u3 phys */
27 #define SSUSB_SIFSLV_V1_U2PHY_COM 0x000
28 /* u3/pcie/sata phy banks */
29 #define SSUSB_SIFSLV_V1_U3PHYD 0x000
30 #define SSUSB_SIFSLV_V1_U3PHYA 0x200
32 /* version V2 sub-banks offset base address */
34 #define SSUSB_SIFSLV_V2_MISC 0x000
35 #define SSUSB_SIFSLV_V2_U2FREQ 0x100
36 #define SSUSB_SIFSLV_V2_U2PHY_COM 0x300
37 /* u3/pcie/sata phy banks */
38 #define SSUSB_SIFSLV_V2_SPLLC 0x000
39 #define SSUSB_SIFSLV_V2_CHIP 0x100
40 #define SSUSB_SIFSLV_V2_U3PHYD 0x200
41 #define SSUSB_SIFSLV_V2_U3PHYA 0x400
43 #define U3P_USBPHYACR0 0x000
44 #define PA0_RG_U2PLL_FORCE_ON BIT(15)
45 #define PA0_RG_USB20_INTR_EN BIT(5)
47 #define U3P_USBPHYACR5 0x014
48 #define PA5_RG_U2_HSTX_SRCAL_EN BIT(15)
49 #define PA5_RG_U2_HSTX_SRCTRL GENMASK(14, 12)
50 #define PA5_RG_U2_HSTX_SRCTRL_VAL(x) ((0x7 & (x)) << 12)
51 #define PA5_RG_U2_HS_100U_U3_EN BIT(11)
53 #define U3P_USBPHYACR6 0x018
54 #define PA6_RG_U2_BC11_SW_EN BIT(23)
55 #define PA6_RG_U2_OTG_VBUSCMP_EN BIT(20)
56 #define PA6_RG_U2_SQTH GENMASK(3, 0)
57 #define PA6_RG_U2_SQTH_VAL(x) (0xf & (x))
59 #define U3P_U2PHYACR4 0x020
60 #define P2C_RG_USB20_GPIO_CTL BIT(9)
61 #define P2C_USB20_GPIO_MODE BIT(8)
62 #define P2C_U2_GPIO_CTR_MSK \
63 (P2C_RG_USB20_GPIO_CTL | P2C_USB20_GPIO_MODE)
65 #define U3P_U2PHYDTM0 0x068
66 #define P2C_FORCE_UART_EN BIT(26)
67 #define P2C_FORCE_DATAIN BIT(23)
68 #define P2C_FORCE_DM_PULLDOWN BIT(21)
69 #define P2C_FORCE_DP_PULLDOWN BIT(20)
70 #define P2C_FORCE_XCVRSEL BIT(19)
71 #define P2C_FORCE_SUSPENDM BIT(18)
72 #define P2C_FORCE_TERMSEL BIT(17)
73 #define P2C_RG_DATAIN GENMASK(13, 10)
74 #define P2C_RG_DATAIN_VAL(x) ((0xf & (x)) << 10)
75 #define P2C_RG_DMPULLDOWN BIT(7)
76 #define P2C_RG_DPPULLDOWN BIT(6)
77 #define P2C_RG_XCVRSEL GENMASK(5, 4)
78 #define P2C_RG_XCVRSEL_VAL(x) ((0x3 & (x)) << 4)
79 #define P2C_RG_SUSPENDM BIT(3)
80 #define P2C_RG_TERMSEL BIT(2)
81 #define P2C_DTM0_PART_MASK \
82 (P2C_FORCE_DATAIN | P2C_FORCE_DM_PULLDOWN | \
83 P2C_FORCE_DP_PULLDOWN | P2C_FORCE_XCVRSEL | \
84 P2C_FORCE_TERMSEL | P2C_RG_DMPULLDOWN | \
85 P2C_RG_DPPULLDOWN | P2C_RG_TERMSEL)
87 #define U3P_U2PHYDTM1 0x06C
88 #define P2C_RG_UART_EN BIT(16)
89 #define P2C_FORCE_IDDIG BIT(9)
90 #define P2C_RG_VBUSVALID BIT(5)
91 #define P2C_RG_SESSEND BIT(4)
92 #define P2C_RG_AVALID BIT(2)
93 #define P2C_RG_IDDIG BIT(1)
95 #define U3P_U3_CHIP_GPIO_CTLD 0x0c
96 #define P3C_REG_IP_SW_RST BIT(31)
97 #define P3C_MCU_BUS_CK_GATE_EN BIT(30)
98 #define P3C_FORCE_IP_SW_RST BIT(29)
100 #define U3P_U3_CHIP_GPIO_CTLE 0x10
101 #define P3C_RG_SWRST_U3_PHYD BIT(25)
102 #define P3C_RG_SWRST_U3_PHYD_FORCE_EN BIT(24)
104 #define U3P_U3_PHYA_REG0 0x000
105 #define P3A_RG_CLKDRV_OFF GENMASK(3, 2)
106 #define P3A_RG_CLKDRV_OFF_VAL(x) ((0x3 & (x)) << 2)
108 #define U3P_U3_PHYA_REG1 0x004
109 #define P3A_RG_CLKDRV_AMP GENMASK(31, 29)
110 #define P3A_RG_CLKDRV_AMP_VAL(x) ((0x7 & (x)) << 29)
112 #define U3P_U3_PHYA_REG6 0x018
113 #define P3A_RG_TX_EIDLE_CM GENMASK(31, 28)
114 #define P3A_RG_TX_EIDLE_CM_VAL(x) ((0xf & (x)) << 28)
116 #define U3P_U3_PHYA_REG9 0x024
117 #define P3A_RG_RX_DAC_MUX GENMASK(5, 1)
118 #define P3A_RG_RX_DAC_MUX_VAL(x) ((0x1f & (x)) << 1)
120 #define U3P_U3_PHYA_DA_REG0 0x100
121 #define P3A_RG_XTAL_EXT_PE2H GENMASK(17, 16)
122 #define P3A_RG_XTAL_EXT_PE2H_VAL(x) ((0x3 & (x)) << 16)
123 #define P3A_RG_XTAL_EXT_PE1H GENMASK(13, 12)
124 #define P3A_RG_XTAL_EXT_PE1H_VAL(x) ((0x3 & (x)) << 12)
125 #define P3A_RG_XTAL_EXT_EN_U3 GENMASK(11, 10)
126 #define P3A_RG_XTAL_EXT_EN_U3_VAL(x) ((0x3 & (x)) << 10)
128 #define U3P_U3_PHYA_DA_REG4 0x108
129 #define P3A_RG_PLL_DIVEN_PE2H GENMASK(21, 19)
130 #define P3A_RG_PLL_BC_PE2H GENMASK(7, 6)
131 #define P3A_RG_PLL_BC_PE2H_VAL(x) ((0x3 & (x)) << 6)
133 #define U3P_U3_PHYA_DA_REG5 0x10c
134 #define P3A_RG_PLL_BR_PE2H GENMASK(29, 28)
135 #define P3A_RG_PLL_BR_PE2H_VAL(x) ((0x3 & (x)) << 28)
136 #define P3A_RG_PLL_IC_PE2H GENMASK(15, 12)
137 #define P3A_RG_PLL_IC_PE2H_VAL(x) ((0xf & (x)) << 12)
139 #define U3P_U3_PHYA_DA_REG6 0x110
140 #define P3A_RG_PLL_IR_PE2H GENMASK(19, 16)
141 #define P3A_RG_PLL_IR_PE2H_VAL(x) ((0xf & (x)) << 16)
143 #define U3P_U3_PHYA_DA_REG7 0x114
144 #define P3A_RG_PLL_BP_PE2H GENMASK(19, 16)
145 #define P3A_RG_PLL_BP_PE2H_VAL(x) ((0xf & (x)) << 16)
147 #define U3P_U3_PHYA_DA_REG20 0x13c
148 #define P3A_RG_PLL_DELTA1_PE2H GENMASK(31, 16)
149 #define P3A_RG_PLL_DELTA1_PE2H_VAL(x) ((0xffff & (x)) << 16)
151 #define U3P_U3_PHYA_DA_REG25 0x148
152 #define P3A_RG_PLL_DELTA_PE2H GENMASK(15, 0)
153 #define P3A_RG_PLL_DELTA_PE2H_VAL(x) (0xffff & (x))
155 #define U3P_U3_PHYD_LFPS1 0x00c
156 #define P3D_RG_FWAKE_TH GENMASK(21, 16)
157 #define P3D_RG_FWAKE_TH_VAL(x) ((0x3f & (x)) << 16)
159 #define U3P_U3_PHYD_CDR1 0x05c
160 #define P3D_RG_CDR_BIR_LTD1 GENMASK(28, 24)
161 #define P3D_RG_CDR_BIR_LTD1_VAL(x) ((0x1f & (x)) << 24)
162 #define P3D_RG_CDR_BIR_LTD0 GENMASK(12, 8)
163 #define P3D_RG_CDR_BIR_LTD0_VAL(x) ((0x1f & (x)) << 8)
165 #define U3P_U3_PHYD_RXDET1 0x128
166 #define P3D_RG_RXDET_STB2_SET GENMASK(17, 9)
167 #define P3D_RG_RXDET_STB2_SET_VAL(x) ((0x1ff & (x)) << 9)
169 #define U3P_U3_PHYD_RXDET2 0x12c
170 #define P3D_RG_RXDET_STB2_SET_P3 GENMASK(8, 0)
171 #define P3D_RG_RXDET_STB2_SET_P3_VAL(x) (0x1ff & (x))
173 #define U3P_SPLLC_XTALCTL3 0x018
174 #define XC3_RG_U3_XTAL_RX_PWD BIT(9)
175 #define XC3_RG_U3_FRC_XTAL_RX_PWD BIT(8)
177 enum mtk_phy_version {
191 void __iomem *phyd; /* include u3phyd_bank2 */
192 void __iomem *phya; /* include u3phya_da */
195 struct mtk_phy_instance {
196 void __iomem *port_base;
197 const struct device_node *np;
199 struct u2phy_banks u2_banks;
200 struct u3phy_banks u3_banks;
203 struct clk ref_clk; /* reference clock of (digital) phy */
204 struct clk da_ref_clk; /* reference clock of analog phy */
211 void __iomem *sif_base;
212 enum mtk_phy_version version;
213 struct mtk_phy_instance **phys;
217 static void u2_phy_instance_init(struct mtk_tphy *tphy,
218 struct mtk_phy_instance *instance)
220 struct u2phy_banks *u2_banks = &instance->u2_banks;
222 /* switch to USB function, and enable usb pll */
223 clrsetbits_le32(u2_banks->com + U3P_U2PHYDTM0,
224 P2C_FORCE_UART_EN | P2C_FORCE_SUSPENDM,
225 P2C_RG_XCVRSEL_VAL(1) | P2C_RG_DATAIN_VAL(0));
227 clrbits_le32(u2_banks->com + U3P_U2PHYDTM1, P2C_RG_UART_EN);
228 setbits_le32(u2_banks->com + U3P_USBPHYACR0, PA0_RG_USB20_INTR_EN);
230 /* disable switch 100uA current to SSUSB */
231 clrbits_le32(u2_banks->com + U3P_USBPHYACR5, PA5_RG_U2_HS_100U_U3_EN);
233 clrbits_le32(u2_banks->com + U3P_U2PHYACR4, P2C_U2_GPIO_CTR_MSK);
235 /* DP/DM BC1.1 path Disable */
236 clrsetbits_le32(u2_banks->com + U3P_USBPHYACR6,
237 PA6_RG_U2_BC11_SW_EN | PA6_RG_U2_SQTH,
238 PA6_RG_U2_SQTH_VAL(2));
240 /* set HS slew rate */
241 clrsetbits_le32(u2_banks->com + U3P_USBPHYACR5,
242 PA5_RG_U2_HSTX_SRCTRL, PA5_RG_U2_HSTX_SRCTRL_VAL(4));
244 dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
247 static void u2_phy_instance_power_on(struct mtk_tphy *tphy,
248 struct mtk_phy_instance *instance)
250 struct u2phy_banks *u2_banks = &instance->u2_banks;
252 clrbits_le32(u2_banks->com + U3P_U2PHYDTM0,
253 P2C_RG_XCVRSEL | P2C_RG_DATAIN | P2C_DTM0_PART_MASK);
256 setbits_le32(u2_banks->com + U3P_USBPHYACR6,
257 PA6_RG_U2_OTG_VBUSCMP_EN);
259 clrsetbits_le32(u2_banks->com + U3P_U2PHYDTM1,
260 P2C_RG_SESSEND, P2C_RG_VBUSVALID | P2C_RG_AVALID);
262 dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
265 static void u2_phy_instance_power_off(struct mtk_tphy *tphy,
266 struct mtk_phy_instance *instance)
268 struct u2phy_banks *u2_banks = &instance->u2_banks;
270 clrbits_le32(u2_banks->com + U3P_U2PHYDTM0,
271 P2C_RG_XCVRSEL | P2C_RG_DATAIN);
274 clrbits_le32(u2_banks->com + U3P_USBPHYACR6,
275 PA6_RG_U2_OTG_VBUSCMP_EN);
277 clrsetbits_le32(u2_banks->com + U3P_U2PHYDTM1,
278 P2C_RG_VBUSVALID | P2C_RG_AVALID, P2C_RG_SESSEND);
280 dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
283 static void u3_phy_instance_init(struct mtk_tphy *tphy,
284 struct mtk_phy_instance *instance)
286 struct u3phy_banks *u3_banks = &instance->u3_banks;
288 /* gating PCIe Analog XTAL clock */
289 setbits_le32(u3_banks->spllc + U3P_SPLLC_XTALCTL3,
290 XC3_RG_U3_XTAL_RX_PWD | XC3_RG_U3_FRC_XTAL_RX_PWD);
293 clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG0,
294 P3A_RG_XTAL_EXT_EN_U3, P3A_RG_XTAL_EXT_EN_U3_VAL(2));
296 clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG9,
297 P3A_RG_RX_DAC_MUX, P3A_RG_RX_DAC_MUX_VAL(4));
299 clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG6,
300 P3A_RG_TX_EIDLE_CM, P3A_RG_TX_EIDLE_CM_VAL(0xe));
302 clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_CDR1,
303 P3D_RG_CDR_BIR_LTD0 | P3D_RG_CDR_BIR_LTD1,
304 P3D_RG_CDR_BIR_LTD0_VAL(0xc) |
305 P3D_RG_CDR_BIR_LTD1_VAL(0x3));
307 clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_LFPS1,
308 P3D_RG_FWAKE_TH, P3D_RG_FWAKE_TH_VAL(0x34));
310 clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET1,
311 P3D_RG_RXDET_STB2_SET, P3D_RG_RXDET_STB2_SET_VAL(0x10));
313 clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET2,
314 P3D_RG_RXDET_STB2_SET_P3,
315 P3D_RG_RXDET_STB2_SET_P3_VAL(0x10));
317 dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
320 static void pcie_phy_instance_init(struct mtk_tphy *tphy,
321 struct mtk_phy_instance *instance)
323 struct u3phy_banks *u3_banks = &instance->u3_banks;
325 if (tphy->version != MTK_TPHY_V1)
328 clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG0,
329 P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H,
330 P3A_RG_XTAL_EXT_PE1H_VAL(0x2) |
331 P3A_RG_XTAL_EXT_PE2H_VAL(0x2));
334 clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG1, P3A_RG_CLKDRV_AMP,
335 P3A_RG_CLKDRV_AMP_VAL(0x4));
336 clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG0, P3A_RG_CLKDRV_OFF,
337 P3A_RG_CLKDRV_OFF_VAL(0x1));
339 /* SSC delta -5000ppm */
340 clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG20,
341 P3A_RG_PLL_DELTA1_PE2H,
342 P3A_RG_PLL_DELTA1_PE2H_VAL(0x3c));
344 clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG25,
345 P3A_RG_PLL_DELTA_PE2H,
346 P3A_RG_PLL_DELTA_PE2H_VAL(0x36));
348 /* change pll BW 0.6M */
349 clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG5,
350 P3A_RG_PLL_BR_PE2H | P3A_RG_PLL_IC_PE2H,
351 P3A_RG_PLL_BR_PE2H_VAL(0x1) |
352 P3A_RG_PLL_IC_PE2H_VAL(0x1));
353 clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG4,
354 P3A_RG_PLL_DIVEN_PE2H | P3A_RG_PLL_BC_PE2H,
355 P3A_RG_PLL_BC_PE2H_VAL(0x3));
357 clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG6,
358 P3A_RG_PLL_IR_PE2H, P3A_RG_PLL_IR_PE2H_VAL(0x2));
359 clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG7,
360 P3A_RG_PLL_BP_PE2H, P3A_RG_PLL_BP_PE2H_VAL(0xa));
362 /* Tx Detect Rx Timing: 10us -> 5us */
363 clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET1,
364 P3D_RG_RXDET_STB2_SET,
365 P3D_RG_RXDET_STB2_SET_VAL(0x10));
366 clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET2,
367 P3D_RG_RXDET_STB2_SET_P3,
368 P3D_RG_RXDET_STB2_SET_P3_VAL(0x10));
370 /* wait for PCIe subsys register to active */
374 static void pcie_phy_instance_power_on(struct mtk_tphy *tphy,
375 struct mtk_phy_instance *instance)
377 struct u3phy_banks *bank = &instance->u3_banks;
379 clrbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLD,
380 P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST);
381 clrbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLE,
382 P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD);
385 static void pcie_phy_instance_power_off(struct mtk_tphy *tphy,
386 struct mtk_phy_instance *instance)
389 struct u3phy_banks *bank = &instance->u3_banks;
391 setbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLD,
392 P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST);
393 setbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLE,
394 P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD);
397 static void phy_v1_banks_init(struct mtk_tphy *tphy,
398 struct mtk_phy_instance *instance)
400 struct u2phy_banks *u2_banks = &instance->u2_banks;
401 struct u3phy_banks *u3_banks = &instance->u3_banks;
403 switch (instance->type) {
405 u2_banks->misc = NULL;
406 u2_banks->fmreg = tphy->sif_base + SSUSB_SIFSLV_V1_U2FREQ;
407 u2_banks->com = instance->port_base + SSUSB_SIFSLV_V1_U2PHY_COM;
411 u3_banks->spllc = tphy->sif_base + SSUSB_SIFSLV_V1_SPLLC;
412 u3_banks->chip = tphy->sif_base + SSUSB_SIFSLV_V1_CHIP;
413 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;
414 u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA;
417 dev_err(tphy->dev, "incompatible PHY type\n");
422 static void phy_v2_banks_init(struct mtk_tphy *tphy,
423 struct mtk_phy_instance *instance)
425 struct u2phy_banks *u2_banks = &instance->u2_banks;
426 struct u3phy_banks *u3_banks = &instance->u3_banks;
428 switch (instance->type) {
430 u2_banks->misc = instance->port_base + SSUSB_SIFSLV_V2_MISC;
431 u2_banks->fmreg = instance->port_base + SSUSB_SIFSLV_V2_U2FREQ;
432 u2_banks->com = instance->port_base + SSUSB_SIFSLV_V2_U2PHY_COM;
436 u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V2_SPLLC;
437 u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V2_CHIP;
438 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V2_U3PHYD;
439 u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V2_U3PHYA;
442 dev_err(tphy->dev, "incompatible PHY type\n");
447 static int mtk_phy_init(struct phy *phy)
449 struct mtk_tphy *tphy = dev_get_priv(phy->dev);
450 struct mtk_phy_instance *instance = tphy->phys[phy->id];
453 ret = clk_enable(&instance->ref_clk);
455 dev_err(tphy->dev, "failed to enable ref_clk\n");
459 ret = clk_enable(&instance->da_ref_clk);
461 dev_err(tphy->dev, "failed to enable da_ref_clk %d\n", ret);
462 clk_disable(&instance->ref_clk);
466 switch (instance->type) {
468 u2_phy_instance_init(tphy, instance);
471 u3_phy_instance_init(tphy, instance);
474 pcie_phy_instance_init(tphy, instance);
477 dev_err(tphy->dev, "incompatible PHY type\n");
484 static int mtk_phy_power_on(struct phy *phy)
486 struct mtk_tphy *tphy = dev_get_priv(phy->dev);
487 struct mtk_phy_instance *instance = tphy->phys[phy->id];
489 if (instance->type == PHY_TYPE_USB2)
490 u2_phy_instance_power_on(tphy, instance);
491 else if (instance->type == PHY_TYPE_PCIE)
492 pcie_phy_instance_power_on(tphy, instance);
497 static int mtk_phy_power_off(struct phy *phy)
499 struct mtk_tphy *tphy = dev_get_priv(phy->dev);
500 struct mtk_phy_instance *instance = tphy->phys[phy->id];
502 if (instance->type == PHY_TYPE_USB2)
503 u2_phy_instance_power_off(tphy, instance);
504 else if (instance->type == PHY_TYPE_PCIE)
505 pcie_phy_instance_power_off(tphy, instance);
510 static int mtk_phy_exit(struct phy *phy)
512 struct mtk_tphy *tphy = dev_get_priv(phy->dev);
513 struct mtk_phy_instance *instance = tphy->phys[phy->id];
515 clk_disable(&instance->da_ref_clk);
516 clk_disable(&instance->ref_clk);
521 static int mtk_phy_xlate(struct phy *phy,
522 struct ofnode_phandle_args *args)
524 struct mtk_tphy *tphy = dev_get_priv(phy->dev);
525 struct mtk_phy_instance *instance = NULL;
526 const struct device_node *phy_np = ofnode_to_np(args->node);
530 dev_err(phy->dev, "null pointer phy node\n");
534 if (args->args_count < 1) {
535 dev_err(phy->dev, "invalid number of cells in 'phy' property\n");
539 for (index = 0; index < tphy->nphys; index++)
540 if (phy_np == tphy->phys[index]->np) {
541 instance = tphy->phys[index];
546 dev_err(phy->dev, "failed to find appropriate phy\n");
551 instance->type = args->args[1];
552 if (!(instance->type == PHY_TYPE_USB2 ||
553 instance->type == PHY_TYPE_USB3 ||
554 instance->type == PHY_TYPE_PCIE)) {
555 dev_err(phy->dev, "unsupported device type\n");
559 if (tphy->version == MTK_TPHY_V1) {
560 phy_v1_banks_init(tphy, instance);
561 } else if (tphy->version == MTK_TPHY_V2) {
562 phy_v2_banks_init(tphy, instance);
564 dev_err(phy->dev, "phy version is not supported\n");
571 static const struct phy_ops mtk_tphy_ops = {
572 .init = mtk_phy_init,
573 .exit = mtk_phy_exit,
574 .power_on = mtk_phy_power_on,
575 .power_off = mtk_phy_power_off,
576 .of_xlate = mtk_phy_xlate,
579 static int mtk_tphy_probe(struct udevice *dev)
581 struct mtk_tphy *tphy = dev_get_priv(dev);
585 tphy->nphys = dev_get_child_count(dev);
587 tphy->phys = devm_kcalloc(dev, tphy->nphys, sizeof(*tphy->phys),
593 tphy->version = dev_get_driver_data(dev);
595 /* v1 has shared banks */
596 if (tphy->version == MTK_TPHY_V1) {
597 tphy->sif_base = dev_read_addr_ptr(dev);
602 dev_for_each_subnode(subnode, dev) {
603 struct mtk_phy_instance *instance;
607 instance = devm_kzalloc(dev, sizeof(*instance), GFP_KERNEL);
611 addr = ofnode_get_addr(subnode);
612 if (addr == FDT_ADDR_T_NONE)
615 instance->port_base = map_sysmem(addr, 0);
616 instance->index = index;
617 instance->np = ofnode_to_np(subnode);
618 tphy->phys[index] = instance;
621 err = clk_get_optional_nodev(subnode, "ref",
626 err = clk_get_optional_nodev(subnode, "da_ref",
627 &instance->da_ref_clk);
635 static const struct udevice_id mtk_tphy_id_table[] = {
636 { .compatible = "mediatek,generic-tphy-v1", .data = MTK_TPHY_V1, },
637 { .compatible = "mediatek,generic-tphy-v2", .data = MTK_TPHY_V2, },
641 U_BOOT_DRIVER(mtk_tphy) = {
644 .of_match = mtk_tphy_id_table,
645 .ops = &mtk_tphy_ops,
646 .probe = mtk_tphy_probe,
647 .priv_auto_alloc_size = sizeof(struct mtk_tphy),