2 * m8xx_pcmcia.c - Linux PCMCIA socket driver for the mpc8xx series.
4 * (C) 1999-2000 Magnus Damm <damm@bitsmart.com>
5 * (C) 2001-2002 Montavista Software, Inc.
8 * Support for two slots by Cyclades Corporation
9 * <oliver.kurth@cyclades.de>
10 * Further fixes, v2.6 kernel port
11 * <marcelo.tosatti@cyclades.com>
13 * Some fixes, additions (C) 2005-2007 Montavista Software, Inc.
14 * <vbordug@ru.mvista.com>
16 * "The ExCA standard specifies that socket controllers should provide
17 * two IO and five memory windows per socket, which can be independently
18 * configured and positioned in the host address space and mapped to
19 * arbitrary segments of card address space. " - David A Hinds. 1999
21 * This controller does _not_ meet the ExCA standard.
23 * m8xx pcmcia controller brief info:
24 * + 8 windows (attrib, mem, i/o)
25 * + up to two slots (SLOT_A and SLOT_B)
26 * + inputpins, outputpins, event and mask registers.
27 * - no offset register. sigh.
29 * Because of the lacking offset register we must map the whole card.
30 * We assign each memory window PCMCIA_MEM_WIN_SIZE address space.
31 * Make sure there is (PCMCIA_MEM_WIN_SIZE * PCMCIA_MEM_WIN_NO
32 * * PCMCIA_SOCKETS_NO) bytes at PCMCIA_MEM_WIN_BASE.
33 * The i/o windows are dynamically allocated at PCMCIA_IO_WIN_BASE.
34 * They are maximum 64KByte each...
37 #include <linux/module.h>
38 #include <linux/init.h>
39 #include <linux/types.h>
40 #include <linux/fcntl.h>
41 #include <linux/string.h>
43 #include <linux/kernel.h>
44 #include <linux/errno.h>
45 #include <linux/slab.h>
46 #include <linux/timer.h>
47 #include <linux/ioport.h>
48 #include <linux/delay.h>
49 #include <linux/interrupt.h>
50 #include <linux/fsl_devices.h>
53 #include <asm/bitops.h>
54 #include <asm/system.h>
56 #include <asm/mpc8xx.h>
57 #include <asm/8xx_immap.h>
59 #include <asm/fs_pd.h>
60 #include <asm/of_device.h>
61 #include <asm/of_platform.h>
63 #include <pcmcia/version.h>
64 #include <pcmcia/cs_types.h>
65 #include <pcmcia/cs.h>
66 #include <pcmcia/ss.h>
69 static int pc_debug = PCMCIA_DEBUG;
70 module_param(pc_debug, int, 0);
71 #define dprintk(args...) printk(KERN_DEBUG "m8xx_pcmcia: " args);
73 #define dprintk(args...)
76 #define pcmcia_info(args...) printk(KERN_INFO "m8xx_pcmcia: "args)
77 #define pcmcia_error(args...) printk(KERN_ERR "m8xx_pcmcia: "args)
79 static const char *version = "Version 0.06, Aug 2005";
80 MODULE_LICENSE("Dual MPL/GPL");
82 #if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)
84 /* The RPX series use SLOT_B */
85 #if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE)
86 #define CONFIG_PCMCIA_SLOT_B
87 #define CONFIG_BD_IS_MHZ
90 /* The ADS board use SLOT_A */
92 #define CONFIG_PCMCIA_SLOT_A
93 #define CONFIG_BD_IS_MHZ
96 /* The FADS series are a mess */
98 #if defined(CONFIG_MPC860T) || defined(CONFIG_MPC860) || defined(CONFIG_MPC821)
99 #define CONFIG_PCMCIA_SLOT_A
101 #define CONFIG_PCMCIA_SLOT_B
105 #if defined(CONFIG_MPC885ADS)
106 #define CONFIG_PCMCIA_SLOT_A
107 #define PCMCIA_GLITCHY_CD
110 /* Cyclades ACS uses both slots */
112 #define CONFIG_PCMCIA_SLOT_A
113 #define CONFIG_PCMCIA_SLOT_B
116 #endif /* !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) */
118 #if defined(CONFIG_PCMCIA_SLOT_A) && defined(CONFIG_PCMCIA_SLOT_B)
120 #define PCMCIA_SOCKETS_NO 2
121 /* We have only 8 windows, dualsocket support will be limited. */
122 #define PCMCIA_MEM_WIN_NO 2
123 #define PCMCIA_IO_WIN_NO 2
124 #define PCMCIA_SLOT_MSG "SLOT_A and SLOT_B"
126 #elif defined(CONFIG_PCMCIA_SLOT_A) || defined(CONFIG_PCMCIA_SLOT_B)
128 #define PCMCIA_SOCKETS_NO 1
129 /* full support for one slot */
130 #define PCMCIA_MEM_WIN_NO 5
131 #define PCMCIA_IO_WIN_NO 2
133 /* define _slot_ to be able to optimize macros */
135 #ifdef CONFIG_PCMCIA_SLOT_A
137 #define PCMCIA_SLOT_MSG "SLOT_A"
140 #define PCMCIA_SLOT_MSG "SLOT_B"
144 #error m8xx_pcmcia: Bad configuration!
147 /* ------------------------------------------------------------------------- */
149 #define PCMCIA_MEM_WIN_BASE 0xe0000000 /* base address for memory window 0 */
150 #define PCMCIA_MEM_WIN_SIZE 0x04000000 /* each memory window is 64 MByte */
151 #define PCMCIA_IO_WIN_BASE _IO_BASE /* base address for io window 0 */
152 /* ------------------------------------------------------------------------- */
154 static int pcmcia_schlvl;
156 static DEFINE_SPINLOCK(events_lock);
158 #define PCMCIA_SOCKET_KEY_5V 1
159 #define PCMCIA_SOCKET_KEY_LV 2
161 /* look up table for pgcrx registers */
162 static u32 *m8xx_pgcrx[2];
165 * This structure is used to address each window in the PCMCIA controller.
167 * Keep in mind that we assume that pcmcia_win[n+1] is mapped directly
168 * after pcmcia_win[n]...
177 * For some reason the hardware guys decided to make both slots share
180 * Could someone invent object oriented hardware ?
182 * The macros are used to get the right bit from the registers.
187 #define M8XX_PCMCIA_VS1(slot) (0x80000000 >> (slot << 4))
188 #define M8XX_PCMCIA_VS2(slot) (0x40000000 >> (slot << 4))
189 #define M8XX_PCMCIA_VS_MASK(slot) (0xc0000000 >> (slot << 4))
190 #define M8XX_PCMCIA_VS_SHIFT(slot) (30 - (slot << 4))
192 #define M8XX_PCMCIA_WP(slot) (0x20000000 >> (slot << 4))
193 #define M8XX_PCMCIA_CD2(slot) (0x10000000 >> (slot << 4))
194 #define M8XX_PCMCIA_CD1(slot) (0x08000000 >> (slot << 4))
195 #define M8XX_PCMCIA_BVD2(slot) (0x04000000 >> (slot << 4))
196 #define M8XX_PCMCIA_BVD1(slot) (0x02000000 >> (slot << 4))
197 #define M8XX_PCMCIA_RDY(slot) (0x01000000 >> (slot << 4))
198 #define M8XX_PCMCIA_RDY_L(slot) (0x00800000 >> (slot << 4))
199 #define M8XX_PCMCIA_RDY_H(slot) (0x00400000 >> (slot << 4))
200 #define M8XX_PCMCIA_RDY_R(slot) (0x00200000 >> (slot << 4))
201 #define M8XX_PCMCIA_RDY_F(slot) (0x00100000 >> (slot << 4))
202 #define M8XX_PCMCIA_MASK(slot) (0xFFFF0000 >> (slot << 4))
204 #define M8XX_PCMCIA_POR_VALID 0x00000001
205 #define M8XX_PCMCIA_POR_WRPROT 0x00000002
206 #define M8XX_PCMCIA_POR_ATTRMEM 0x00000010
207 #define M8XX_PCMCIA_POR_IO 0x00000018
208 #define M8XX_PCMCIA_POR_16BIT 0x00000040
210 #define M8XX_PGCRX(slot) m8xx_pgcrx[slot]
212 #define M8XX_PGCRX_CXOE 0x00000080
213 #define M8XX_PGCRX_CXRESET 0x00000040
215 /* we keep one lookup table per socket to check flags */
217 #define PCMCIA_EVENTS_MAX 5 /* 4 max at a time + termination */
224 static const char driver_name[] = "m8xx-pcmcia";
227 void (*handler)(void *info, u32 events);
231 pcmconf8xx_t *pcmcia;
235 socket_state_t state;
236 struct pccard_mem_map mem_win[PCMCIA_MEM_WIN_NO];
237 struct pccard_io_map io_win[PCMCIA_IO_WIN_NO];
238 struct event_table events[PCMCIA_EVENTS_MAX];
239 struct pcmcia_socket socket;
242 static struct socket_info socket[PCMCIA_SOCKETS_NO];
245 * Search this table to see if the windowsize is
249 #define M8XX_SIZES_NO 32
251 static const u32 m8xx_size_to_gray[M8XX_SIZES_NO] =
253 0x00000001, 0x00000002, 0x00000008, 0x00000004,
254 0x00000080, 0x00000040, 0x00000010, 0x00000020,
255 0x00008000, 0x00004000, 0x00001000, 0x00002000,
256 0x00000100, 0x00000200, 0x00000800, 0x00000400,
258 0x0fffffff, 0xffffffff, 0xffffffff, 0xffffffff,
259 0x01000000, 0x02000000, 0xffffffff, 0x04000000,
260 0x00010000, 0x00020000, 0x00080000, 0x00040000,
261 0x00800000, 0x00400000, 0x00100000, 0x00200000
264 /* ------------------------------------------------------------------------- */
266 static irqreturn_t m8xx_interrupt(int irq, void *dev);
268 #define PCMCIA_BMT_LIMIT (15*4) /* Bus Monitor Timeout value */
270 /* ------------------------------------------------------------------------- */
271 /* board specific stuff: */
272 /* voltage_set(), hardware_enable() and hardware_disable() */
273 /* ------------------------------------------------------------------------- */
274 /* RPX Boards from Embedded Planet */
276 #if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE)
278 /* The RPX boards seems to have it's bus monitor timeout set to 6*8 clocks.
279 * SYPCR is write once only, therefore must the slowest memory be faster
280 * than the bus monitor or we will get a machine check due to the bus timeout.
283 #define PCMCIA_BOARD_MSG "RPX CLASSIC or RPX LITE"
285 #undef PCMCIA_BMT_LIMIT
286 #define PCMCIA_BMT_LIMIT (6*8)
288 static int voltage_set(int slot, int vcc, int vpp)
295 reg |= BCSR1_PCVCTL4;
298 reg |= BCSR1_PCVCTL5;
309 reg |= BCSR1_PCVCTL6;
314 reg |= BCSR1_PCVCTL7;
319 if(!((vcc == 50) || (vcc == 0)))
322 /* first, turn off all power */
324 out_be32(((u32 *)RPX_CSR_ADDR), in_be32(((u32 *)RPX_CSR_ADDR)) & ~(BCSR1_PCVCTL4 | BCSR1_PCVCTL5 | BCSR1_PCVCTL6 | BCSR1_PCVCTL7));
326 /* enable new powersettings */
328 out_be32(((u32 *)RPX_CSR_ADDR), in_be32(((u32 *)RPX_CSR_ADDR)) | reg);
333 #define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
334 #define hardware_enable(_slot_) /* No hardware to enable */
335 #define hardware_disable(_slot_) /* No hardware to disable */
337 #endif /* CONFIG_RPXCLASSIC */
339 /* FADS Boards from Motorola */
341 #if defined(CONFIG_FADS)
343 #define PCMCIA_BOARD_MSG "FADS"
345 static int voltage_set(int slot, int vcc, int vpp)
353 reg |= BCSR1_PCCVCC0;
356 reg |= BCSR1_PCCVCC1;
368 reg |= BCSR1_PCCVPP1;
373 if ((vcc == 33) || (vcc == 50))
374 reg |= BCSR1_PCCVPP0;
381 /* first, turn off all power */
382 out_be32((u32 *)BCSR1, in_be32((u32 *)BCSR1) & ~(BCSR1_PCCVCC_MASK | BCSR1_PCCVPP_MASK));
384 /* enable new powersettings */
385 out_be32((u32 *)BCSR1, in_be32((u32 *)BCSR1) | reg);
390 #define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
392 static void hardware_enable(int slot)
394 out_be32((u32 *)BCSR1, in_be32((u32 *)BCSR1) & ~BCSR1_PCCEN);
397 static void hardware_disable(int slot)
399 out_be32((u32 *)BCSR1, in_be32((u32 *)BCSR1) | BCSR1_PCCEN);
404 /* MPC885ADS Boards */
406 #if defined(CONFIG_MPC885ADS)
408 #define PCMCIA_BOARD_MSG "MPC885ADS"
409 #define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
411 static inline void hardware_enable(int slot)
413 m8xx_pcmcia_ops.hw_ctrl(slot, 1);
416 static inline void hardware_disable(int slot)
418 m8xx_pcmcia_ops.hw_ctrl(slot, 0);
421 static inline int voltage_set(int slot, int vcc, int vpp)
423 return m8xx_pcmcia_ops.voltage_set(slot, vcc, vpp);
428 /* ------------------------------------------------------------------------- */
429 /* Motorola MBX860 */
431 #if defined(CONFIG_MBX)
433 #define PCMCIA_BOARD_MSG "MBX"
435 static int voltage_set(int slot, int vcc, int vpp)
463 if ((vcc == 33) || (vcc == 50))
471 /* first, turn off all power */
472 out_8((u8 *)MBX_CSR2_ADDR, in_8((u8 *)MBX_CSR2_ADDR) & ~(CSR2_VCC_MASK | CSR2_VPP_MASK));
474 /* enable new powersettings */
475 out_8((u8 *)MBX_CSR2_ADDR, in_8((u8 *)MBX_CSR2_ADDR) | reg);
480 #define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V
481 #define hardware_enable(_slot_) /* No hardware to enable */
482 #define hardware_disable(_slot_) /* No hardware to disable */
484 #endif /* CONFIG_MBX */
486 #if defined(CONFIG_PRxK)
487 #include <asm/cpld.h>
488 extern volatile fpga_pc_regs *fpga_pc;
490 #define PCMCIA_BOARD_MSG "MPC855T"
492 static int voltage_set(int slot, int vcc, int vpp)
496 cpld_regs *ccpld = get_cpld();
502 reg |= PCMCIA_VCC_33;
505 reg |= PCMCIA_VCC_50;
517 reg |= PCMCIA_VPP_VCC;
522 if ((vcc == 33) || (vcc == 50))
523 reg |= PCMCIA_VPP_12;
530 reg = reg >> (slot << 2);
531 regread = in_8(&ccpld->fpga_pc_ctl);
532 if (reg != (regread & ((PCMCIA_VCC_MASK | PCMCIA_VPP_MASK) >> (slot << 2)))) {
533 /* enable new powersettings */
534 regread = regread & ~((PCMCIA_VCC_MASK | PCMCIA_VPP_MASK) >> (slot << 2));
535 out_8(&ccpld->fpga_pc_ctl, reg | regread);
542 #define socket_get(_slot_) PCMCIA_SOCKET_KEY_LV
543 #define hardware_enable(_slot_) /* No hardware to enable */
544 #define hardware_disable(_slot_) /* No hardware to disable */
546 #endif /* CONFIG_PRxK */
548 static u32 pending_events[PCMCIA_SOCKETS_NO];
549 static DEFINE_SPINLOCK(pending_event_lock);
551 static irqreturn_t m8xx_interrupt(int irq, void *dev)
553 struct socket_info *s;
554 struct event_table *e;
555 unsigned int i, events, pscr, pipr, per;
556 pcmconf8xx_t *pcmcia = socket[0].pcmcia;
558 dprintk("Interrupt!\n");
559 /* get interrupt sources */
561 pscr = in_be32(&pcmcia->pcmc_pscr);
562 pipr = in_be32(&pcmcia->pcmc_pipr);
563 per = in_be32(&pcmcia->pcmc_per);
565 for(i = 0; i < PCMCIA_SOCKETS_NO; i++) {
572 events |= e->eventbit;
578 * report only if both card detect signals are the same
580 * we depend on that CD2 is the bit to the left of CD1...
582 if(events & SS_DETECT)
583 if(((pipr & M8XX_PCMCIA_CD2(i)) >> 1) ^
584 (pipr & M8XX_PCMCIA_CD1(i)))
586 events &= ~SS_DETECT;
589 #ifdef PCMCIA_GLITCHY_CD
591 * I've experienced CD problems with my ADS board.
592 * We make an extra check to see if there was a
593 * real change of Card detection.
596 if((events & SS_DETECT) &&
598 (M8XX_PCMCIA_CD2(i) | M8XX_PCMCIA_CD1(i))) == 0) &&
599 (s->state.Vcc | s->state.Vpp)) {
600 events &= ~SS_DETECT;
601 /*printk( "CD glitch workaround - CD = 0x%08x!\n",
602 (pipr & (M8XX_PCMCIA_CD2(i)
603 | M8XX_PCMCIA_CD1(i))));*/
607 /* call the handler */
609 dprintk("slot %u: events = 0x%02x, pscr = 0x%08x, "
611 i, events, pscr, pipr);
614 spin_lock(&pending_event_lock);
615 pending_events[i] |= events;
616 spin_unlock(&pending_event_lock);
618 * Turn off RDY_L bits in the PER mask on
619 * CD interrupt receival.
621 * They can generate bad interrupts on the
622 * ACS4,8,16,32. - marcelo
624 per &= ~M8XX_PCMCIA_RDY_L(0);
625 per &= ~M8XX_PCMCIA_RDY_L(1);
627 out_be32(&pcmcia->pcmc_per, per);
630 pcmcia_parse_events(&socket[i].socket, events);
634 /* clear the interrupt sources */
635 out_be32(&pcmcia->pcmc_pscr, pscr);
637 dprintk("Interrupt done.\n");
642 static u32 m8xx_get_graycode(u32 size)
646 for(k = 0; k < M8XX_SIZES_NO; k++)
647 if(m8xx_size_to_gray[k] == size)
650 if((k == M8XX_SIZES_NO) || (m8xx_size_to_gray[k] == -1))
656 static u32 m8xx_get_speed(u32 ns, u32 is_io, u32 bus_freq)
658 u32 reg, clocks, psst, psl, psht;
663 * We get called with IO maps setup to 0ns
664 * if not specified by the user.
665 * They should be 255ns.
671 ns = 100; /* fast memory if 0 */
675 * In PSST, PSL, PSHT fields we tell the controller
676 * timing parameters in CLKOUT clock cycles.
677 * CLKOUT is the same as GCLK2_50.
680 /* how we want to adjust the timing - in percent */
682 #define ADJ 180 /* 80 % longer accesstime - to be sure */
684 clocks = ((bus_freq / 1000) * ns) / 1000;
685 clocks = (clocks * ADJ) / (100*1000);
686 if(clocks >= PCMCIA_BMT_LIMIT) {
687 printk( "Max access time limit reached\n");
688 clocks = PCMCIA_BMT_LIMIT-1;
691 psst = clocks / 7; /* setup time */
692 psht = clocks / 7; /* hold time */
693 psl = (clocks * 5) / 7; /* strobe length */
695 psst += clocks - (psst + psht + psl);
704 static int m8xx_get_status(struct pcmcia_socket *sock, unsigned int *value)
706 int lsock = container_of(sock, struct socket_info, socket)->slot;
707 struct socket_info *s = &socket[lsock];
708 unsigned int pipr, reg;
709 pcmconf8xx_t *pcmcia = s->pcmcia;
711 pipr = in_be32(&pcmcia->pcmc_pipr);
713 *value = ((pipr & (M8XX_PCMCIA_CD1(lsock)
714 | M8XX_PCMCIA_CD2(lsock))) == 0) ? SS_DETECT : 0;
715 *value |= (pipr & M8XX_PCMCIA_WP(lsock)) ? SS_WRPROT : 0;
717 if (s->state.flags & SS_IOCARD)
718 *value |= (pipr & M8XX_PCMCIA_BVD1(lsock)) ? SS_STSCHG : 0;
720 *value |= (pipr & M8XX_PCMCIA_RDY(lsock)) ? SS_READY : 0;
721 *value |= (pipr & M8XX_PCMCIA_BVD1(lsock)) ? SS_BATDEAD : 0;
722 *value |= (pipr & M8XX_PCMCIA_BVD2(lsock)) ? SS_BATWARN : 0;
725 if (s->state.Vcc | s->state.Vpp)
726 *value |= SS_POWERON;
730 * This driver only supports 16-Bit pc-cards.
731 * Cardbus is not handled here.
733 * To determine what voltage to use we must read the VS1 and VS2 pin.
734 * Depending on what socket type is present,
735 * different combinations mean different things.
737 * Card Key Socket Key VS1 VS2 Card Vcc for CIS parse
739 * 5V 5V, LV* NC NC 5V only 5V (if available)
741 * 5V 5V, LV* GND NC 5 or 3.3V as low as possible
743 * 5V 5V, LV* GND GND 5, 3.3, x.xV as low as possible
745 * LV* 5V - - shall not fit into socket
747 * LV* LV* GND NC 3.3V only 3.3V
749 * LV* LV* NC GND x.xV x.xV (if avail.)
751 * LV* LV* GND GND 3.3 or x.xV as low as possible
753 * *LV means Low Voltage
756 * That gives us the following table:
758 * Socket VS1 VS2 Voltage
761 * 5V NC GND none (should not be possible)
765 * LV NC NC 5V (if available)
766 * LV NC GND x.xV (if available)
770 * So, how do I determine if I have a 5V or a LV
771 * socket on my board? Look at the socket!
774 * Socket with 5V key:
775 * ++--------------------------------------------+
780 * +---------------------------------------------+
782 * Socket with LV key:
783 * ++--------------------------------------------+
788 * +---------------------------------------------+
791 * With other words - LV only cards does not fit
792 * into the 5V socket!
795 /* read out VS1 and VS2 */
797 reg = (pipr & M8XX_PCMCIA_VS_MASK(lsock))
798 >> M8XX_PCMCIA_VS_SHIFT(lsock);
800 if(socket_get(lsock) == PCMCIA_SOCKET_KEY_LV) {
804 break; /* GND, NC - 3.3V only */
807 break; /* NC. GND - x.xV only */
811 dprintk("GetStatus(%d) = %#2.2x\n", lsock, *value);
815 static int m8xx_set_socket(struct pcmcia_socket *sock, socket_state_t *state)
817 int lsock = container_of(sock, struct socket_info, socket)->slot;
818 struct socket_info *s = &socket[lsock];
819 struct event_table *e;
822 pcmconf8xx_t *pcmcia = socket[0].pcmcia;
824 dprintk( "SetSocket(%d, flags %#3.3x, Vcc %d, Vpp %d, "
825 "io_irq %d, csc_mask %#2.2x)\n", lsock, state->flags,
826 state->Vcc, state->Vpp, state->io_irq, state->csc_mask);
828 /* First, set voltage - bail out if invalid */
829 if(voltage_set(lsock, state->Vcc, state->Vpp))
833 /* Take care of reset... */
834 if(state->flags & SS_RESET)
835 out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) | M8XX_PGCRX_CXRESET); /* active high */
837 out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) & ~M8XX_PGCRX_CXRESET);
839 /* ... and output enable. */
841 /* The CxOE signal is connected to a 74541 on the ADS.
842 I guess most other boards used the ADS as a reference.
843 I tried to control the CxOE signal with SS_OUTPUT_ENA,
844 but the reset signal seems connected via the 541.
845 If the CxOE is left high are some signals tristated and
846 no pullups are present -> the cards act wierd.
847 So right now the buffers are enabled if the power is on. */
849 if(state->Vcc || state->Vpp)
850 out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) & ~M8XX_PGCRX_CXOE); /* active low */
852 out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) | M8XX_PGCRX_CXOE);
855 * We'd better turn off interrupts before
856 * we mess with the events-table..
859 spin_lock_irqsave(&events_lock, flags);
862 * Play around with the interrupt mask to be able to
863 * give the events the generic pcmcia driver wants us to.
869 if(state->csc_mask & SS_DETECT) {
870 e->eventbit = SS_DETECT;
871 reg |= e->regbit = (M8XX_PCMCIA_CD2(lsock)
872 | M8XX_PCMCIA_CD1(lsock));
875 if(state->flags & SS_IOCARD) {
879 if(state->csc_mask & SS_STSCHG) {
880 e->eventbit = SS_STSCHG;
881 reg |= e->regbit = M8XX_PCMCIA_BVD1(lsock);
885 * If io_irq is non-zero we should enable irq.
888 out_be32(M8XX_PGCRX(lsock),
889 in_be32(M8XX_PGCRX(lsock)) | mk_int_int_mask(s->hwirq) << 24);
891 * Strange thing here:
892 * The manual does not tell us which interrupt
893 * the sources generate.
894 * Anyhow, I found out that RDY_L generates IREQLVL.
896 * We use level triggerd interrupts, and they don't
897 * have to be cleared in PSCR in the interrupt handler.
899 reg |= M8XX_PCMCIA_RDY_L(lsock);
902 out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) & 0x00ffffff);
908 if(state->csc_mask & SS_BATDEAD) {
909 e->eventbit = SS_BATDEAD;
910 reg |= e->regbit = M8XX_PCMCIA_BVD1(lsock);
913 if(state->csc_mask & SS_BATWARN) {
914 e->eventbit = SS_BATWARN;
915 reg |= e->regbit = M8XX_PCMCIA_BVD2(lsock);
918 /* What should I trigger on - low/high,raise,fall? */
919 if(state->csc_mask & SS_READY) {
920 e->eventbit = SS_READY;
921 reg |= e->regbit = 0; //??
926 e->regbit = 0; /* terminate list */
929 * Clear the status changed .
930 * Port A and Port B share the same port.
931 * Writing ones will clear the bits.
934 out_be32(&pcmcia->pcmc_pscr, reg);
938 * Port A and Port B share the same port.
939 * Need for read-modify-write.
940 * Ones will enable the interrupt.
943 reg |= in_be32(&pcmcia->pcmc_per) & (M8XX_PCMCIA_MASK(0) | M8XX_PCMCIA_MASK(1));
944 out_be32(&pcmcia->pcmc_per, reg);
946 spin_unlock_irqrestore(&events_lock, flags);
948 /* copy the struct and modify the copy */
955 static int m8xx_set_io_map(struct pcmcia_socket *sock, struct pccard_io_map *io)
957 int lsock = container_of(sock, struct socket_info, socket)->slot;
959 struct socket_info *s = &socket[lsock];
960 struct pcmcia_win *w;
961 unsigned int reg, winnr;
962 pcmconf8xx_t *pcmcia = s->pcmcia;
965 #define M8XX_SIZE (io->stop - io->start + 1)
966 #define M8XX_BASE (PCMCIA_IO_WIN_BASE + io->start)
968 dprintk( "SetIOMap(%d, %d, %#2.2x, %d ns, "
969 "%#4.4x-%#4.4x)\n", lsock, io->map, io->flags,
970 io->speed, io->start, io->stop);
972 if ((io->map >= PCMCIA_IO_WIN_NO) || (io->start > 0xffff)
973 || (io->stop > 0xffff) || (io->stop < io->start))
976 if((reg = m8xx_get_graycode(M8XX_SIZE)) == -1)
979 if(io->flags & MAP_ACTIVE) {
981 dprintk( "io->flags & MAP_ACTIVE\n");
983 winnr = (PCMCIA_MEM_WIN_NO * PCMCIA_SOCKETS_NO)
984 + (lsock * PCMCIA_IO_WIN_NO) + io->map;
986 /* setup registers */
988 w = (void *) &pcmcia->pcmc_pbr0;
991 out_be32(&w->or, 0); /* turn off window first */
992 out_be32(&w->br, M8XX_BASE);
995 reg |= M8XX_PCMCIA_POR_IO |(lsock << 2);
997 reg |= m8xx_get_speed(io->speed, 1, s->bus_freq);
999 if(io->flags & MAP_WRPROT)
1000 reg |= M8XX_PCMCIA_POR_WRPROT;
1002 /*if(io->flags & (MAP_16BIT | MAP_AUTOSZ))*/
1003 if(io->flags & MAP_16BIT)
1004 reg |= M8XX_PCMCIA_POR_16BIT;
1006 if(io->flags & MAP_ACTIVE)
1007 reg |= M8XX_PCMCIA_POR_VALID;
1009 out_be32(&w->or, reg);
1011 dprintk("Socket %u: Mapped io window %u at %#8.8x, "
1012 "OR = %#8.8x.\n", lsock, io->map, w->br, w->or);
1014 /* shutdown IO window */
1015 winnr = (PCMCIA_MEM_WIN_NO * PCMCIA_SOCKETS_NO)
1016 + (lsock * PCMCIA_IO_WIN_NO) + io->map;
1018 /* setup registers */
1020 w = (void *) &pcmcia->pcmc_pbr0;
1023 out_be32(&w->or, 0); /* turn off window */
1024 out_be32(&w->br, 0); /* turn off base address */
1026 dprintk("Socket %u: Unmapped io window %u at %#8.8x, "
1027 "OR = %#8.8x.\n", lsock, io->map, w->br, w->or);
1030 /* copy the struct and modify the copy */
1031 s->io_win[io->map] = *io;
1032 s->io_win[io->map].flags &= (MAP_WRPROT
1035 dprintk("SetIOMap exit\n");
1040 static int m8xx_set_mem_map(struct pcmcia_socket *sock, struct pccard_mem_map *mem)
1042 int lsock = container_of(sock, struct socket_info, socket)->slot;
1043 struct socket_info *s = &socket[lsock];
1044 struct pcmcia_win *w;
1045 struct pccard_mem_map *old;
1046 unsigned int reg, winnr;
1047 pcmconf8xx_t *pcmcia = s->pcmcia;
1049 dprintk( "SetMemMap(%d, %d, %#2.2x, %d ns, "
1050 "%#5.5lx, %#5.5x)\n", lsock, mem->map, mem->flags,
1051 mem->speed, mem->static_start, mem->card_start);
1053 if ((mem->map >= PCMCIA_MEM_WIN_NO)
1054 // || ((mem->s) >= PCMCIA_MEM_WIN_SIZE)
1055 || (mem->card_start >= 0x04000000)
1056 || (mem->static_start & 0xfff) /* 4KByte resolution */
1057 || (mem->card_start & 0xfff))
1060 if((reg = m8xx_get_graycode(PCMCIA_MEM_WIN_SIZE)) == -1) {
1061 printk( "Cannot set size to 0x%08x.\n", PCMCIA_MEM_WIN_SIZE);
1066 winnr = (lsock * PCMCIA_MEM_WIN_NO) + mem->map;
1068 /* Setup the window in the pcmcia controller */
1070 w = (void *) &pcmcia->pcmc_pbr0;
1075 reg |= m8xx_get_speed(mem->speed, 0, s->bus_freq);
1077 if(mem->flags & MAP_ATTRIB)
1078 reg |= M8XX_PCMCIA_POR_ATTRMEM;
1080 if(mem->flags & MAP_WRPROT)
1081 reg |= M8XX_PCMCIA_POR_WRPROT;
1083 if(mem->flags & MAP_16BIT)
1084 reg |= M8XX_PCMCIA_POR_16BIT;
1086 if(mem->flags & MAP_ACTIVE)
1087 reg |= M8XX_PCMCIA_POR_VALID;
1089 out_be32(&w->or, reg);
1091 dprintk("Socket %u: Mapped memory window %u at %#8.8x, "
1092 "OR = %#8.8x.\n", lsock, mem->map, w->br, w->or);
1094 if(mem->flags & MAP_ACTIVE) {
1095 /* get the new base address */
1096 mem->static_start = PCMCIA_MEM_WIN_BASE +
1097 (PCMCIA_MEM_WIN_SIZE * winnr)
1101 dprintk("SetMemMap(%d, %d, %#2.2x, %d ns, "
1102 "%#5.5lx, %#5.5x)\n", lsock, mem->map, mem->flags,
1103 mem->speed, mem->static_start, mem->card_start);
1105 /* copy the struct and modify the copy */
1107 old = &s->mem_win[mem->map];
1110 old->flags &= (MAP_ATTRIB
1118 static int m8xx_sock_init(struct pcmcia_socket *sock)
1121 pccard_io_map io = { 0, 0, 0, 0, 1 };
1122 pccard_mem_map mem = { 0, 0, 0, 0, 0, 0 };
1124 dprintk( "sock_init(%d)\n", s);
1126 m8xx_set_socket(sock, &dead_socket);
1127 for (i = 0; i < PCMCIA_IO_WIN_NO; i++) {
1129 m8xx_set_io_map(sock, &io);
1131 for (i = 0; i < PCMCIA_MEM_WIN_NO; i++) {
1133 m8xx_set_mem_map(sock, &mem);
1140 static int m8xx_sock_suspend(struct pcmcia_socket *sock)
1142 return m8xx_set_socket(sock, &dead_socket);
1145 static struct pccard_operations m8xx_services = {
1146 .init = m8xx_sock_init,
1147 .suspend = m8xx_sock_suspend,
1148 .get_status = m8xx_get_status,
1149 .set_socket = m8xx_set_socket,
1150 .set_io_map = m8xx_set_io_map,
1151 .set_mem_map = m8xx_set_mem_map,
1154 static int __init m8xx_probe(struct of_device *ofdev, const struct of_device_id *match)
1156 struct pcmcia_win *w;
1157 unsigned int i, m, hwirq;
1158 pcmconf8xx_t *pcmcia;
1160 struct device_node *np = ofdev->node;
1162 pcmcia_info("%s\n", version);
1164 pcmcia = of_iomap(np, 0);
1168 pcmcia_schlvl = irq_of_parse_and_map(np, 0);
1169 hwirq = irq_map[pcmcia_schlvl].hwirq;
1170 if (pcmcia_schlvl < 0)
1173 m8xx_pgcrx[0] = &pcmcia->pcmc_pgcra;
1174 m8xx_pgcrx[1] = &pcmcia->pcmc_pgcrb;
1177 pcmcia_info(PCMCIA_BOARD_MSG " using " PCMCIA_SLOT_MSG
1178 " with IRQ %u (%d). \n", pcmcia_schlvl, hwirq);
1180 /* Configure Status change interrupt */
1182 if(request_irq(pcmcia_schlvl, m8xx_interrupt, IRQF_SHARED,
1183 driver_name, socket)) {
1184 pcmcia_error("Cannot allocate IRQ %u for SCHLVL!\n",
1189 w = (void *) &pcmcia->pcmc_pbr0;
1191 out_be32(&pcmcia->pcmc_pscr, M8XX_PCMCIA_MASK(0)| M8XX_PCMCIA_MASK(1));
1192 clrbits32(&pcmcia->pcmc_per, M8XX_PCMCIA_MASK(0) | M8XX_PCMCIA_MASK(1));
1194 /* connect interrupt and disable CxOE */
1196 out_be32(M8XX_PGCRX(0), M8XX_PGCRX_CXOE | (mk_int_int_mask(hwirq) << 16));
1197 out_be32(M8XX_PGCRX(1), M8XX_PGCRX_CXOE | (mk_int_int_mask(hwirq) << 16));
1199 /* intialize the fixed memory windows */
1201 for(i = 0; i < PCMCIA_SOCKETS_NO; i++){
1202 for (m = 0; m < PCMCIA_MEM_WIN_NO; m++) {
1203 out_be32(&w->br, PCMCIA_MEM_WIN_BASE +
1204 (PCMCIA_MEM_WIN_SIZE
1205 * (m + i * PCMCIA_MEM_WIN_NO)));
1207 out_be32(&w->or, 0); /* set to not valid */
1213 /* turn off voltage */
1214 voltage_set(0, 0, 0);
1215 voltage_set(1, 0, 0);
1217 /* Enable external hardware */
1221 for (i = 0 ; i < PCMCIA_SOCKETS_NO; i++) {
1223 socket[i].socket.owner = THIS_MODULE;
1224 socket[i].socket.features = SS_CAP_PCCARD | SS_CAP_MEM_ALIGN | SS_CAP_STATIC_MAP;
1225 socket[i].socket.irq_mask = 0x000;
1226 socket[i].socket.map_size = 0x1000;
1227 socket[i].socket.io_offset = 0;
1228 socket[i].socket.pci_irq = pcmcia_schlvl;
1229 socket[i].socket.ops = &m8xx_services;
1230 socket[i].socket.resource_ops = &pccard_nonstatic_ops;
1231 socket[i].socket.cb_dev = NULL;
1232 socket[i].socket.dev.parent = &ofdev->dev;
1233 socket[i].pcmcia = pcmcia;
1234 socket[i].bus_freq = ppc_proc_freq;
1235 socket[i].hwirq = hwirq;
1240 for (i = 0; i < PCMCIA_SOCKETS_NO; i++) {
1241 status = pcmcia_register_socket(&socket[i].socket);
1243 pcmcia_error("Socket register failed\n");
1249 static int m8xx_remove(struct of_device* ofdev)
1252 struct pcmcia_win *w;
1253 pcmconf8xx_t *pcmcia = socket[0].pcmcia;
1255 for (i = 0; i < PCMCIA_SOCKETS_NO; i++) {
1256 w = (void *) &pcmcia->pcmc_pbr0;
1258 out_be32(&pcmcia->pcmc_pscr, M8XX_PCMCIA_MASK(i));
1259 out_be32(&pcmcia->pcmc_per,
1260 in_be32(&pcmcia->pcmc_per) & ~M8XX_PCMCIA_MASK(i));
1262 /* turn off interrupt and disable CxOE */
1263 out_be32(M8XX_PGCRX(i), M8XX_PGCRX_CXOE);
1265 /* turn off memory windows */
1266 for (m = 0; m < PCMCIA_MEM_WIN_NO; m++) {
1267 out_be32(&w->or, 0); /* set to not valid */
1271 /* turn off voltage */
1272 voltage_set(i, 0, 0);
1274 /* disable external hardware */
1275 hardware_disable(i);
1277 for (i = 0; i < PCMCIA_SOCKETS_NO; i++)
1278 pcmcia_unregister_socket(&socket[i].socket);
1280 free_irq(pcmcia_schlvl, NULL);
1286 static int m8xx_suspend(struct platform_device *pdev, pm_message_t state)
1288 return pcmcia_socket_dev_suspend(&pdev->dev, state);
1291 static int m8xx_resume(struct platform_device *pdev)
1293 return pcmcia_socket_dev_resume(&pdev->dev);
1296 #define m8xx_suspend NULL
1297 #define m8xx_resume NULL
1300 static struct of_device_id m8xx_pcmcia_match[] = {
1303 .compatible = "fsl,pq-pcmcia",
1308 MODULE_DEVICE_TABLE(of, m8xx_pcmcia_match);
1310 static struct of_platform_driver m8xx_pcmcia_driver = {
1311 .name = (char *) driver_name,
1312 .match_table = m8xx_pcmcia_match,
1313 .probe = m8xx_probe,
1314 .remove = m8xx_remove,
1315 .suspend = m8xx_suspend,
1316 .resume = m8xx_resume,
1319 static int __init m8xx_init(void)
1321 return of_register_platform_driver(&m8xx_pcmcia_driver);
1324 static void __exit m8xx_exit(void)
1326 of_unregister_platform_driver(&m8xx_pcmcia_driver);
1329 module_init(m8xx_init);
1330 module_exit(m8xx_exit);