2 * drivers/pci/setup-bus.c
4 * Extruded from code written by
5 * Dave Rusling (david.rusling@reo.mts.dec.com)
6 * David Mosberger (davidm@cs.arizona.edu)
7 * David Miller (davem@redhat.com)
9 * Support routines for initializing a PCI subsystem.
13 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
14 * PCI-PCI bridges cleanup, sorted resource allocation.
15 * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
16 * Converted to allocation in 3 passes, which gives
17 * tighter packing. Prefetchable range support.
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/pci.h>
24 #include <linux/errno.h>
25 #include <linux/ioport.h>
26 #include <linux/cache.h>
27 #include <linux/slab.h>
30 struct resource_list_x {
31 struct resource_list_x *next;
34 resource_size_t start;
39 static void add_to_failed_list(struct resource_list_x *head,
40 struct pci_dev *dev, struct resource *res)
42 struct resource_list_x *list = head;
43 struct resource_list_x *ln = list->next;
44 struct resource_list_x *tmp;
46 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
48 pr_warning("add_to_failed_list: kmalloc() failed!\n");
55 tmp->start = res->start;
57 tmp->flags = res->flags;
61 static void free_failed_list(struct resource_list_x *head)
63 struct resource_list_x *list, *tmp;
65 for (list = head->next; list;) {
74 static void __dev_sort_resources(struct pci_dev *dev,
75 struct resource_list *head)
77 u16 class = dev->class >> 8;
79 /* Don't touch classless devices or host bridges or ioapics. */
80 if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST)
83 /* Don't touch ioapic devices already enabled by firmware */
84 if (class == PCI_CLASS_SYSTEM_PIC) {
86 pci_read_config_word(dev, PCI_COMMAND, &command);
87 if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY))
91 pdev_sort_resources(dev, head);
94 static void __assign_resources_sorted(struct resource_list *head,
95 struct resource_list_x *fail_head)
98 struct resource_list *list, *tmp;
101 for (list = head->next; list;) {
103 idx = res - &list->dev->resource[0];
104 if (pci_assign_resource(list->dev, idx)) {
105 if (fail_head && !pci_is_root_bus(list->dev->bus))
106 add_to_failed_list(fail_head, list->dev, res);
117 static void pdev_assign_resources_sorted(struct pci_dev *dev,
118 struct resource_list_x *fail_head)
120 struct resource_list head;
123 __dev_sort_resources(dev, &head);
124 __assign_resources_sorted(&head, fail_head);
128 static void pbus_assign_resources_sorted(const struct pci_bus *bus,
129 struct resource_list_x *fail_head)
132 struct resource_list head;
135 list_for_each_entry(dev, &bus->devices, bus_list)
136 __dev_sort_resources(dev, &head);
138 __assign_resources_sorted(&head, fail_head);
141 void pci_setup_cardbus(struct pci_bus *bus)
143 struct pci_dev *bridge = bus->self;
144 struct resource *res;
145 struct pci_bus_region region;
147 dev_info(&bridge->dev, "CardBus bridge to [bus %02x-%02x]\n",
148 bus->secondary, bus->subordinate);
150 res = bus->resource[0];
151 pcibios_resource_to_bus(bridge, ®ion, res);
152 if (res->flags & IORESOURCE_IO) {
154 * The IO resource is allocated a range twice as large as it
155 * would normally need. This allows us to set both IO regs.
157 dev_info(&bridge->dev, " bridge window %pR\n", res);
158 pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
160 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
164 res = bus->resource[1];
165 pcibios_resource_to_bus(bridge, ®ion, res);
166 if (res->flags & IORESOURCE_IO) {
167 dev_info(&bridge->dev, " bridge window %pR\n", res);
168 pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
170 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
174 res = bus->resource[2];
175 pcibios_resource_to_bus(bridge, ®ion, res);
176 if (res->flags & IORESOURCE_MEM) {
177 dev_info(&bridge->dev, " bridge window %pR\n", res);
178 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
180 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
184 res = bus->resource[3];
185 pcibios_resource_to_bus(bridge, ®ion, res);
186 if (res->flags & IORESOURCE_MEM) {
187 dev_info(&bridge->dev, " bridge window %pR\n", res);
188 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
190 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
194 EXPORT_SYMBOL(pci_setup_cardbus);
196 /* Initialize bridges with base/limit values we have collected.
197 PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998)
198 requires that if there is no I/O ports or memory behind the
199 bridge, corresponding range must be turned off by writing base
200 value greater than limit to the bridge's base/limit registers.
202 Note: care must be taken when updating I/O base/limit registers
203 of bridges which support 32-bit I/O. This update requires two
204 config space writes, so it's quite possible that an I/O window of
205 the bridge will have some undesirable address (e.g. 0) after the
206 first write. Ditto 64-bit prefetchable MMIO. */
207 static void pci_setup_bridge_io(struct pci_bus *bus)
209 struct pci_dev *bridge = bus->self;
210 struct resource *res;
211 struct pci_bus_region region;
214 /* Set up the top and bottom of the PCI I/O segment for this bus. */
215 res = bus->resource[0];
216 pcibios_resource_to_bus(bridge, ®ion, res);
217 if (res->flags & IORESOURCE_IO) {
218 pci_read_config_dword(bridge, PCI_IO_BASE, &l);
220 l |= (region.start >> 8) & 0x00f0;
221 l |= region.end & 0xf000;
222 /* Set up upper 16 bits of I/O base/limit. */
223 io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
224 dev_info(&bridge->dev, " bridge window %pR\n", res);
226 /* Clear upper 16 bits of I/O base/limit. */
229 dev_info(&bridge->dev, " bridge window [io disabled]\n");
231 /* Temporarily disable the I/O range before updating PCI_IO_BASE. */
232 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
233 /* Update lower 16 bits of I/O base/limit. */
234 pci_write_config_dword(bridge, PCI_IO_BASE, l);
235 /* Update upper 16 bits of I/O base/limit. */
236 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);
239 static void pci_setup_bridge_mmio(struct pci_bus *bus)
241 struct pci_dev *bridge = bus->self;
242 struct resource *res;
243 struct pci_bus_region region;
246 /* Set up the top and bottom of the PCI Memory segment for this bus. */
247 res = bus->resource[1];
248 pcibios_resource_to_bus(bridge, ®ion, res);
249 if (res->flags & IORESOURCE_MEM) {
250 l = (region.start >> 16) & 0xfff0;
251 l |= region.end & 0xfff00000;
252 dev_info(&bridge->dev, " bridge window %pR\n", res);
255 dev_info(&bridge->dev, " bridge window [mem disabled]\n");
257 pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
260 static void pci_setup_bridge_mmio_pref(struct pci_bus *bus)
262 struct pci_dev *bridge = bus->self;
263 struct resource *res;
264 struct pci_bus_region region;
267 /* Clear out the upper 32 bits of PREF limit.
268 If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily
269 disables PREF range, which is ok. */
270 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);
272 /* Set up PREF base/limit. */
274 res = bus->resource[2];
275 pcibios_resource_to_bus(bridge, ®ion, res);
276 if (res->flags & IORESOURCE_PREFETCH) {
277 l = (region.start >> 16) & 0xfff0;
278 l |= region.end & 0xfff00000;
279 if (res->flags & IORESOURCE_MEM_64) {
280 bu = upper_32_bits(region.start);
281 lu = upper_32_bits(region.end);
283 dev_info(&bridge->dev, " bridge window %pR\n", res);
286 dev_info(&bridge->dev, " bridge window [mem pref disabled]\n");
288 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
290 /* Set the upper 32 bits of PREF base & limit. */
291 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu);
292 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu);
295 static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type)
297 struct pci_dev *bridge = bus->self;
299 dev_info(&bridge->dev, "PCI bridge to [bus %02x-%02x]\n",
300 bus->secondary, bus->subordinate);
302 if (type & IORESOURCE_IO)
303 pci_setup_bridge_io(bus);
305 if (type & IORESOURCE_MEM)
306 pci_setup_bridge_mmio(bus);
308 if (type & IORESOURCE_PREFETCH)
309 pci_setup_bridge_mmio_pref(bus);
311 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
314 static void pci_setup_bridge(struct pci_bus *bus)
316 unsigned long type = IORESOURCE_IO | IORESOURCE_MEM |
319 __pci_setup_bridge(bus, type);
322 /* Check whether the bridge supports optional I/O and
323 prefetchable memory ranges. If not, the respective
324 base/limit registers must be read-only and read as 0. */
325 static void pci_bridge_check_ranges(struct pci_bus *bus)
329 struct pci_dev *bridge = bus->self;
330 struct resource *b_res;
332 b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
333 b_res[1].flags |= IORESOURCE_MEM;
335 pci_read_config_word(bridge, PCI_IO_BASE, &io);
337 pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0);
338 pci_read_config_word(bridge, PCI_IO_BASE, &io);
339 pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
342 b_res[0].flags |= IORESOURCE_IO;
343 /* DECchip 21050 pass 2 errata: the bridge may miss an address
344 disconnect boundary by one PCI data phase.
345 Workaround: do not use prefetching on this device. */
346 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
348 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
350 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
352 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
353 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
356 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
357 if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64)
358 b_res[2].flags |= IORESOURCE_MEM_64;
361 /* double check if bridge does support 64 bit pref */
362 if (b_res[2].flags & IORESOURCE_MEM_64) {
363 u32 mem_base_hi, tmp;
364 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32,
366 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
368 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp);
370 b_res[2].flags &= ~IORESOURCE_MEM_64;
371 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
376 /* Helper function for sizing routines: find first available
377 bus resource of a given type. Note: we intentionally skip
378 the bus resources which have already been assigned (that is,
379 have non-NULL parent resource). */
380 static struct resource *find_free_bus_resource(struct pci_bus *bus, unsigned long type)
384 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
387 for (i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
388 r = bus->resource[i];
389 if (r == &ioport_resource || r == &iomem_resource)
391 if (r && (r->flags & type_mask) == type && !r->parent)
397 /* Sizing the IO windows of the PCI-PCI bridge is trivial,
398 since these windows have 4K granularity and the IO ranges
399 of non-bridge PCI devices are limited to 256 bytes.
400 We must be careful with the ISA aliasing though. */
401 static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size)
404 struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO);
405 unsigned long size = 0, size1 = 0, old_size;
410 list_for_each_entry(dev, &bus->devices, bus_list) {
413 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
414 struct resource *r = &dev->resource[i];
415 unsigned long r_size;
417 if (r->parent || !(r->flags & IORESOURCE_IO))
419 r_size = resource_size(r);
422 /* Might be re-aligned for ISA */
430 old_size = resource_size(b_res);
433 /* To be fixed in 2.5: we should have sort of HAVE_ISA
434 flag in the struct pci_bus. */
435 #if defined(CONFIG_ISA) || defined(CONFIG_EISA)
436 size = (size & 0xff) + ((size & ~0xffUL) << 2);
438 size = ALIGN(size + size1, 4096);
442 if (b_res->start || b_res->end)
443 dev_info(&bus->self->dev, "disabling bridge window "
444 "%pR to [bus %02x-%02x] (unused)\n", b_res,
445 bus->secondary, bus->subordinate);
449 /* Alignment of the IO window is always 4K */
451 b_res->end = b_res->start + size - 1;
452 b_res->flags |= IORESOURCE_STARTALIGN;
455 /* Calculate the size of the bus and minimal alignment which
456 guarantees that all child resources fit in this size. */
457 static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
458 unsigned long type, resource_size_t min_size)
461 resource_size_t min_align, align, size, old_size;
462 resource_size_t aligns[12]; /* Alignments from 1Mb to 2Gb */
463 int order, max_order;
464 struct resource *b_res = find_free_bus_resource(bus, type);
465 unsigned int mem64_mask = 0;
470 memset(aligns, 0, sizeof(aligns));
474 mem64_mask = b_res->flags & IORESOURCE_MEM_64;
475 b_res->flags &= ~IORESOURCE_MEM_64;
477 list_for_each_entry(dev, &bus->devices, bus_list) {
480 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
481 struct resource *r = &dev->resource[i];
482 resource_size_t r_size;
484 if (r->parent || (r->flags & mask) != type)
486 r_size = resource_size(r);
487 /* For bridges size != alignment */
488 align = pci_resource_alignment(dev, r);
489 order = __ffs(align) - 20;
491 dev_warn(&dev->dev, "disabling BAR %d: %pR "
492 "(bad alignment %#llx)\n", i, r,
493 (unsigned long long) align);
500 /* Exclude ranges with size > align from
501 calculation of the alignment. */
503 aligns[order] += align;
504 if (order > max_order)
506 mem64_mask &= r->flags & IORESOURCE_MEM_64;
511 old_size = resource_size(b_res);
519 for (order = 0; order <= max_order; order++) {
520 resource_size_t align1 = 1;
522 align1 <<= (order + 20);
526 else if (ALIGN(align + min_align, min_align) < align1)
527 min_align = align1 >> 1;
528 align += aligns[order];
530 size = ALIGN(size, min_align);
532 if (b_res->start || b_res->end)
533 dev_info(&bus->self->dev, "disabling bridge window "
534 "%pR to [bus %02x-%02x] (unused)\n", b_res,
535 bus->secondary, bus->subordinate);
539 b_res->start = min_align;
540 b_res->end = size + min_align - 1;
541 b_res->flags |= IORESOURCE_STARTALIGN;
542 b_res->flags |= mem64_mask;
546 static void pci_bus_size_cardbus(struct pci_bus *bus)
548 struct pci_dev *bridge = bus->self;
549 struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
553 * Reserve some resources for CardBus. We reserve
554 * a fixed amount of bus space for CardBus bridges.
557 b_res[0].end = pci_cardbus_io_size - 1;
558 b_res[0].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN;
561 b_res[1].end = pci_cardbus_io_size - 1;
562 b_res[1].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN;
565 * Check whether prefetchable memory is supported
568 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
569 if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) {
570 ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
571 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
572 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
576 * If we have prefetchable memory support, allocate
577 * two regions. Otherwise, allocate one region of
580 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
582 b_res[2].end = pci_cardbus_mem_size - 1;
583 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH | IORESOURCE_SIZEALIGN;
586 b_res[3].end = pci_cardbus_mem_size - 1;
587 b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN;
590 b_res[3].end = pci_cardbus_mem_size * 2 - 1;
591 b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN;
595 void __ref pci_bus_size_bridges(struct pci_bus *bus)
598 unsigned long mask, prefmask;
599 resource_size_t min_mem_size = 0, min_io_size = 0;
601 list_for_each_entry(dev, &bus->devices, bus_list) {
602 struct pci_bus *b = dev->subordinate;
606 switch (dev->class >> 8) {
607 case PCI_CLASS_BRIDGE_CARDBUS:
608 pci_bus_size_cardbus(b);
611 case PCI_CLASS_BRIDGE_PCI:
613 pci_bus_size_bridges(b);
622 switch (bus->self->class >> 8) {
623 case PCI_CLASS_BRIDGE_CARDBUS:
624 /* don't size cardbuses yet. */
627 case PCI_CLASS_BRIDGE_PCI:
628 pci_bridge_check_ranges(bus);
629 if (bus->self->is_hotplug_bridge) {
630 min_io_size = pci_hotplug_io_size;
631 min_mem_size = pci_hotplug_mem_size;
634 pbus_size_io(bus, min_io_size);
635 /* If the bridge supports prefetchable range, size it
636 separately. If it doesn't, or its prefetchable window
637 has already been allocated by arch code, try
638 non-prefetchable range for both types of PCI memory
640 mask = IORESOURCE_MEM;
641 prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH;
642 if (pbus_size_mem(bus, prefmask, prefmask, min_mem_size))
643 mask = prefmask; /* Success, size non-prefetch only. */
645 min_mem_size += min_mem_size;
646 pbus_size_mem(bus, mask, IORESOURCE_MEM, min_mem_size);
650 EXPORT_SYMBOL(pci_bus_size_bridges);
652 static void __ref __pci_bus_assign_resources(const struct pci_bus *bus,
653 struct resource_list_x *fail_head)
658 pbus_assign_resources_sorted(bus, fail_head);
660 list_for_each_entry(dev, &bus->devices, bus_list) {
661 b = dev->subordinate;
665 __pci_bus_assign_resources(b, fail_head);
667 switch (dev->class >> 8) {
668 case PCI_CLASS_BRIDGE_PCI:
669 if (!pci_is_enabled(dev))
673 case PCI_CLASS_BRIDGE_CARDBUS:
674 pci_setup_cardbus(b);
678 dev_info(&dev->dev, "not setting up bridge for bus "
679 "%04x:%02x\n", pci_domain_nr(b), b->number);
685 void __ref pci_bus_assign_resources(const struct pci_bus *bus)
687 __pci_bus_assign_resources(bus, NULL);
689 EXPORT_SYMBOL(pci_bus_assign_resources);
691 static void __ref __pci_bridge_assign_resources(const struct pci_dev *bridge,
692 struct resource_list_x *fail_head)
696 pdev_assign_resources_sorted((struct pci_dev *)bridge, fail_head);
698 b = bridge->subordinate;
702 __pci_bus_assign_resources(b, fail_head);
704 switch (bridge->class >> 8) {
705 case PCI_CLASS_BRIDGE_PCI:
709 case PCI_CLASS_BRIDGE_CARDBUS:
710 pci_setup_cardbus(b);
714 dev_info(&bridge->dev, "not setting up bridge for bus "
715 "%04x:%02x\n", pci_domain_nr(b), b->number);
719 static void pci_bridge_release_resources(struct pci_bus *bus,
723 bool changed = false;
726 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
730 for (idx = PCI_BRIDGE_RESOURCES; idx <= PCI_BRIDGE_RESOURCE_END;
732 r = &dev->resource[idx];
733 if ((r->flags & type_mask) != type)
738 * if there are children under that, we should release them
741 release_child_resources(r);
742 if (!release_resource(r)) {
743 dev_printk(KERN_DEBUG, &dev->dev,
744 "resource %d %pR released\n", idx, r);
745 /* keep the old size */
746 r->end = resource_size(r) - 1;
754 /* avoiding touch the one without PREF */
755 if (type & IORESOURCE_PREFETCH)
756 type = IORESOURCE_PREFETCH;
757 __pci_setup_bridge(bus, type);
766 * try to release pci bridge resources that is from leaf bridge,
767 * so we can allocate big new one later
769 static void __ref pci_bus_release_bridge_resources(struct pci_bus *bus,
771 enum release_type rel_type)
774 bool is_leaf_bridge = true;
776 list_for_each_entry(dev, &bus->devices, bus_list) {
777 struct pci_bus *b = dev->subordinate;
781 is_leaf_bridge = false;
783 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
786 if (rel_type == whole_subtree)
787 pci_bus_release_bridge_resources(b, type,
791 if (pci_is_root_bus(bus))
794 if ((bus->self->class >> 8) != PCI_CLASS_BRIDGE_PCI)
797 if ((rel_type == whole_subtree) || is_leaf_bridge)
798 pci_bridge_release_resources(bus, type);
801 static void pci_bus_dump_res(struct pci_bus *bus)
805 for (i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
806 struct resource *res = bus->resource[i];
808 if (!res || !res->end || !res->flags)
811 dev_printk(KERN_DEBUG, &bus->dev, "resource %d %pR\n", i, res);
815 static void pci_bus_dump_resources(struct pci_bus *bus)
821 pci_bus_dump_res(bus);
823 list_for_each_entry(dev, &bus->devices, bus_list) {
824 b = dev->subordinate;
828 pci_bus_dump_resources(b);
832 static int __init pci_bus_get_depth(struct pci_bus *bus)
837 list_for_each_entry(dev, &bus->devices, bus_list) {
839 struct pci_bus *b = dev->subordinate;
843 ret = pci_bus_get_depth(b);
850 static int __init pci_get_max_depth(void)
855 list_for_each_entry(bus, &pci_root_buses, node) {
858 ret = pci_bus_get_depth(bus);
867 * first try will not touch pci bridge res
868 * second and later try will clear small leaf bridge res
869 * will stop till to the max deepth if can not find good one
872 pci_assign_unassigned_resources(void)
876 enum release_type rel_type = leaf_only;
877 struct resource_list_x head, *list;
878 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
880 unsigned long failed_type;
881 int max_depth = pci_get_max_depth();
886 pci_try_num = max_depth + 1;
887 printk(KERN_DEBUG "PCI: max bus depth: %d pci_try_num: %d\n",
888 max_depth, pci_try_num);
891 /* Depth first, calculate sizes and alignments of all
892 subordinate buses. */
893 list_for_each_entry(bus, &pci_root_buses, node) {
894 pci_bus_size_bridges(bus);
896 /* Depth last, allocate resources and update the hardware. */
897 list_for_each_entry(bus, &pci_root_buses, node) {
898 __pci_bus_assign_resources(bus, &head);
902 /* any device complain? */
904 goto enable_and_dump;
906 for (list = head.next; list;) {
907 failed_type |= list->flags;
911 * io port are tight, don't try extra
912 * or if reach the limit, don't want to try more
914 failed_type &= type_mask;
915 if ((failed_type == IORESOURCE_IO) || (tried_times >= pci_try_num)) {
916 free_failed_list(&head);
917 goto enable_and_dump;
920 printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n",
923 /* third times and later will not check if it is leaf */
924 if ((tried_times + 1) > 2)
925 rel_type = whole_subtree;
928 * Try to release leaf bridge's resources that doesn't fit resource of
929 * child device under that bridge
931 for (list = head.next; list;) {
932 bus = list->dev->bus;
933 pci_bus_release_bridge_resources(bus, list->flags & type_mask,
937 /* restore size and flags */
938 for (list = head.next; list;) {
939 struct resource *res = list->res;
941 res->start = list->start;
942 res->end = list->end;
943 res->flags = list->flags;
944 if (list->dev->subordinate)
949 free_failed_list(&head);
954 /* Depth last, update the hardware. */
955 list_for_each_entry(bus, &pci_root_buses, node)
956 pci_enable_bridges(bus);
958 /* dump the resource on buses */
959 list_for_each_entry(bus, &pci_root_buses, node) {
960 pci_bus_dump_resources(bus);
964 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge)
966 struct pci_bus *parent = bridge->subordinate;
969 pci_bus_size_bridges(parent);
970 __pci_bridge_assign_resources(bridge, NULL);
971 retval = pci_reenable_device(bridge);
972 pci_set_master(bridge);
973 pci_enable_bridges(parent);
975 EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources);