2 * probe.c - PCI detection and setup code
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
9 #include <linux/slab.h>
10 #include <linux/module.h>
11 #include <linux/cpumask.h>
12 #include <linux/pci-aspm.h>
15 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
16 #define CARDBUS_RESERVE_BUSNR 3
18 /* Ugh. Need to stop exporting this to modules. */
19 LIST_HEAD(pci_root_buses);
20 EXPORT_SYMBOL(pci_root_buses);
23 static int find_anything(struct device *dev, void *data)
29 * Some device drivers need know if pci is initiated.
30 * Basically, we think pci is not initiated when there
31 * is no device to be found on the pci_bus_type.
33 int no_pci_devices(void)
38 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
39 no_devices = (dev == NULL);
43 EXPORT_SYMBOL(no_pci_devices);
46 * PCI Bus Class Devices
48 static ssize_t pci_bus_show_cpuaffinity(struct device *dev,
50 struct device_attribute *attr,
54 const struct cpumask *cpumask;
56 cpumask = cpumask_of_pcibus(to_pci_bus(dev));
58 cpulist_scnprintf(buf, PAGE_SIZE-2, cpumask) :
59 cpumask_scnprintf(buf, PAGE_SIZE-2, cpumask);
65 static ssize_t inline pci_bus_show_cpumaskaffinity(struct device *dev,
66 struct device_attribute *attr,
69 return pci_bus_show_cpuaffinity(dev, 0, attr, buf);
72 static ssize_t inline pci_bus_show_cpulistaffinity(struct device *dev,
73 struct device_attribute *attr,
76 return pci_bus_show_cpuaffinity(dev, 1, attr, buf);
79 DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpumaskaffinity, NULL);
80 DEVICE_ATTR(cpulistaffinity, S_IRUGO, pci_bus_show_cpulistaffinity, NULL);
85 static void release_pcibus_dev(struct device *dev)
87 struct pci_bus *pci_bus = to_pci_bus(dev);
90 put_device(pci_bus->bridge);
94 static struct class pcibus_class = {
96 .dev_release = &release_pcibus_dev,
99 static int __init pcibus_class_init(void)
101 return class_register(&pcibus_class);
103 postcore_initcall(pcibus_class_init);
106 * Translate the low bits of the PCI base
107 * to the resource type
109 static inline unsigned int pci_calc_resource_flags(unsigned int flags)
111 if (flags & PCI_BASE_ADDRESS_SPACE_IO)
112 return IORESOURCE_IO;
114 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
115 return IORESOURCE_MEM | IORESOURCE_PREFETCH;
117 return IORESOURCE_MEM;
120 static u64 pci_size(u64 base, u64 maxbase, u64 mask)
122 u64 size = mask & maxbase; /* Find the significant bits */
126 /* Get the lowest of them to find the decode size, and
127 from that the extent. */
128 size = (size & ~(size-1)) - 1;
130 /* base == maxbase can be valid only if the BAR has
131 already been programmed with all 1s. */
132 if (base == maxbase && ((base | size) & mask) != mask)
138 static inline enum pci_bar_type decode_bar(struct resource *res, u32 bar)
140 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
141 res->flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
145 res->flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
147 if (res->flags & PCI_BASE_ADDRESS_MEM_TYPE_64)
148 return pci_bar_mem64;
149 return pci_bar_mem32;
153 * pci_read_base - read a PCI BAR
154 * @dev: the PCI device
155 * @type: type of the BAR
156 * @res: resource buffer to be filled in
157 * @pos: BAR position in the config space
159 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
161 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
162 struct resource *res, unsigned int pos)
166 mask = type ? ~PCI_ROM_ADDRESS_ENABLE : ~0;
168 res->name = pci_name(dev);
170 pci_read_config_dword(dev, pos, &l);
171 pci_write_config_dword(dev, pos, mask);
172 pci_read_config_dword(dev, pos, &sz);
173 pci_write_config_dword(dev, pos, l);
176 * All bits set in sz means the device isn't working properly.
177 * If the BAR isn't implemented, all bits must be 0. If it's a
178 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
181 if (!sz || sz == 0xffffffff)
185 * I don't know how l can have all bits set. Copied from old code.
186 * Maybe it fixes a bug on some ancient platform.
191 if (type == pci_bar_unknown) {
192 type = decode_bar(res, l);
193 res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN;
194 if (type == pci_bar_io) {
195 l &= PCI_BASE_ADDRESS_IO_MASK;
196 mask = PCI_BASE_ADDRESS_IO_MASK & IO_SPACE_LIMIT;
198 l &= PCI_BASE_ADDRESS_MEM_MASK;
199 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
202 res->flags |= (l & IORESOURCE_ROM_ENABLE);
203 l &= PCI_ROM_ADDRESS_MASK;
204 mask = (u32)PCI_ROM_ADDRESS_MASK;
207 if (type == pci_bar_mem64) {
210 u64 mask64 = mask | (u64)~0 << 32;
212 pci_read_config_dword(dev, pos + 4, &l);
213 pci_write_config_dword(dev, pos + 4, ~0);
214 pci_read_config_dword(dev, pos + 4, &sz);
215 pci_write_config_dword(dev, pos + 4, l);
217 l64 |= ((u64)l << 32);
218 sz64 |= ((u64)sz << 32);
220 sz64 = pci_size(l64, sz64, mask64);
225 if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) {
226 dev_err(&dev->dev, "can't handle 64-bit BAR\n");
228 } else if ((sizeof(resource_size_t) < 8) && l) {
229 /* Address above 32-bit boundary; disable the BAR */
230 pci_write_config_dword(dev, pos, 0);
231 pci_write_config_dword(dev, pos + 4, 0);
236 res->end = l64 + sz64;
237 dev_printk(KERN_DEBUG, &dev->dev,
238 "reg %x %s: %pR\n", pos,
239 (res->flags & IORESOURCE_PREFETCH) ?
240 "64bit mmio pref" : "64bit mmio",
244 res->flags |= IORESOURCE_MEM_64;
246 sz = pci_size(l, sz, mask);
254 dev_printk(KERN_DEBUG, &dev->dev, "reg %x %s: %pR\n", pos,
255 (res->flags & IORESOURCE_IO) ? "io port" :
256 ((res->flags & IORESOURCE_PREFETCH) ?
257 "32bit mmio pref" : "32bit mmio"),
262 return (type == pci_bar_mem64) ? 1 : 0;
268 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
270 unsigned int pos, reg;
272 for (pos = 0; pos < howmany; pos++) {
273 struct resource *res = &dev->resource[pos];
274 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
275 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
279 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
280 dev->rom_base_reg = rom;
281 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
282 IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
283 IORESOURCE_SIZEALIGN;
284 __pci_read_base(dev, pci_bar_mem32, res, rom);
288 void __devinit pci_read_bridge_bases(struct pci_bus *child)
290 struct pci_dev *dev = child->self;
291 u8 io_base_lo, io_limit_lo;
292 u16 mem_base_lo, mem_limit_lo;
293 unsigned long base, limit;
294 struct resource *res;
297 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
300 if (dev->transparent) {
301 dev_info(&dev->dev, "transparent bridge\n");
302 for(i = 3; i < PCI_BUS_NUM_RESOURCES; i++)
303 child->resource[i] = child->parent->resource[i - 3];
306 res = child->resource[0];
307 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
308 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
309 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
310 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
312 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
313 u16 io_base_hi, io_limit_hi;
314 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
315 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
316 base |= (io_base_hi << 16);
317 limit |= (io_limit_hi << 16);
321 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
325 res->end = limit + 0xfff;
326 dev_printk(KERN_DEBUG, &dev->dev, "bridge io port: %pR\n", res);
329 res = child->resource[1];
330 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
331 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
332 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
333 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
335 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
337 res->end = limit + 0xfffff;
338 dev_printk(KERN_DEBUG, &dev->dev, "bridge 32bit mmio: %pR\n",
342 res = child->resource[2];
343 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
344 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
345 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
346 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
348 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
349 u32 mem_base_hi, mem_limit_hi;
350 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
351 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
354 * Some bridges set the base > limit by default, and some
355 * (broken) BIOSes do not initialize them. If we find
356 * this, just assume they are not being used.
358 if (mem_base_hi <= mem_limit_hi) {
359 #if BITS_PER_LONG == 64
360 base |= ((long) mem_base_hi) << 32;
361 limit |= ((long) mem_limit_hi) << 32;
363 if (mem_base_hi || mem_limit_hi) {
364 dev_err(&dev->dev, "can't handle 64-bit "
365 "address space for bridge\n");
372 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
373 IORESOURCE_MEM | IORESOURCE_PREFETCH;
374 if (res->flags & PCI_PREF_RANGE_TYPE_64)
375 res->flags |= IORESOURCE_MEM_64;
377 res->end = limit + 0xfffff;
378 dev_printk(KERN_DEBUG, &dev->dev, "bridge %sbit mmio pref: %pR\n",
379 (res->flags & PCI_PREF_RANGE_TYPE_64) ? "64" : "32",
384 static struct pci_bus * pci_alloc_bus(void)
388 b = kzalloc(sizeof(*b), GFP_KERNEL);
390 INIT_LIST_HEAD(&b->node);
391 INIT_LIST_HEAD(&b->children);
392 INIT_LIST_HEAD(&b->devices);
393 INIT_LIST_HEAD(&b->slots);
398 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
399 struct pci_dev *bridge, int busnr)
401 struct pci_bus *child;
405 * Allocate a new bus, and inherit stuff from the parent..
407 child = pci_alloc_bus();
411 child->parent = parent;
412 child->ops = parent->ops;
413 child->sysdata = parent->sysdata;
414 child->bus_flags = parent->bus_flags;
416 /* initialize some portions of the bus device, but don't register it
417 * now as the parent is not properly set up yet. This device will get
418 * registered later in pci_bus_add_devices()
420 child->dev.class = &pcibus_class;
421 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
424 * Set up the primary, secondary and subordinate
427 child->number = child->secondary = busnr;
428 child->primary = parent->secondary;
429 child->subordinate = 0xff;
434 child->self = bridge;
435 child->bridge = get_device(&bridge->dev);
437 /* Set up default resource pointers and names.. */
438 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
439 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
440 child->resource[i]->name = child->name;
442 bridge->subordinate = child;
447 struct pci_bus *__ref pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
449 struct pci_bus *child;
451 child = pci_alloc_child_bus(parent, dev, busnr);
453 down_write(&pci_bus_sem);
454 list_add_tail(&child->node, &parent->children);
455 up_write(&pci_bus_sem);
460 static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
462 struct pci_bus *parent = child->parent;
464 /* Attempts to fix that up are really dangerous unless
465 we're going to re-assign all bus numbers. */
466 if (!pcibios_assign_all_busses())
469 while (parent->parent && parent->subordinate < max) {
470 parent->subordinate = max;
471 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
472 parent = parent->parent;
477 * If it's a bridge, configure it and scan the bus behind it.
478 * For CardBus bridges, we don't scan behind as the devices will
479 * be handled by the bridge driver itself.
481 * We need to process bridges in two passes -- first we scan those
482 * already configured by the BIOS and after we are done with all of
483 * them, we proceed to assigning numbers to the remaining buses in
484 * order to avoid overlaps between old and new bus numbers.
486 int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
488 struct pci_bus *child;
489 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
494 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
496 dev_dbg(&dev->dev, "scanning behind bridge, config %06x, pass %d\n",
497 buses & 0xffffff, pass);
499 /* Check if setup is sensible at all */
501 ((buses & 0xff) != bus->number || ((buses >> 8) & 0xff) <= bus->number)) {
502 dev_dbg(&dev->dev, "bus configuration invalid, reconfiguring\n");
506 /* Disable MasterAbortMode during probing to avoid reporting
507 of bus errors (in some architectures) */
508 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
509 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
510 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
512 if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus && !broken) {
513 unsigned int cmax, busnr;
515 * Bus already configured by firmware, process it in the first
516 * pass and just note the configuration.
520 busnr = (buses >> 8) & 0xFF;
523 * If we already got to this bus through a different bridge,
524 * don't re-add it. This can happen with the i450NX chipset.
526 * However, we continue to descend down the hierarchy and
527 * scan remaining child buses.
529 child = pci_find_bus(pci_domain_nr(bus), busnr);
531 child = pci_add_new_bus(bus, dev, busnr);
534 child->primary = buses & 0xFF;
535 child->subordinate = (buses >> 16) & 0xFF;
536 child->bridge_ctl = bctl;
539 cmax = pci_scan_child_bus(child);
542 if (child->subordinate > max)
543 max = child->subordinate;
546 * We need to assign a number to this bus which we always
547 * do in the second pass.
550 if (pcibios_assign_all_busses() || broken)
551 /* Temporarily disable forwarding of the
552 configuration cycles on all bridges in
553 this bus segment to avoid possible
554 conflicts in the second pass between two
555 bridges programmed with overlapping
557 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
563 pci_write_config_word(dev, PCI_STATUS, 0xffff);
565 /* Prevent assigning a bus number that already exists.
566 * This can happen when a bridge is hot-plugged */
567 if (pci_find_bus(pci_domain_nr(bus), max+1))
569 child = pci_add_new_bus(bus, dev, ++max);
570 buses = (buses & 0xff000000)
571 | ((unsigned int)(child->primary) << 0)
572 | ((unsigned int)(child->secondary) << 8)
573 | ((unsigned int)(child->subordinate) << 16);
576 * yenta.c forces a secondary latency timer of 176.
577 * Copy that behaviour here.
580 buses &= ~0xff000000;
581 buses |= CARDBUS_LATENCY_TIMER << 24;
585 * We need to blast all three values with a single write.
587 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
590 child->bridge_ctl = bctl;
592 * Adjust subordinate busnr in parent buses.
593 * We do this before scanning for children because
594 * some devices may not be detected if the bios
597 pci_fixup_parent_subordinate_busnr(child, max);
598 /* Now we can scan all subordinate buses... */
599 max = pci_scan_child_bus(child);
601 * now fix it up again since we have found
602 * the real value of max.
604 pci_fixup_parent_subordinate_busnr(child, max);
607 * For CardBus bridges, we leave 4 bus numbers
608 * as cards with a PCI-to-PCI bridge can be
611 for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) {
612 struct pci_bus *parent = bus;
613 if (pci_find_bus(pci_domain_nr(bus),
616 while (parent->parent) {
617 if ((!pcibios_assign_all_busses()) &&
618 (parent->subordinate > max) &&
619 (parent->subordinate <= max+i)) {
622 parent = parent->parent;
626 * Often, there are two cardbus bridges
627 * -- try to leave one valid bus number
635 pci_fixup_parent_subordinate_busnr(child, max);
638 * Set the subordinate bus number to its real value.
640 child->subordinate = max;
641 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
645 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
646 pci_domain_nr(bus), child->number);
648 /* Has only triggered on CardBus, fixup is in yenta_socket */
649 while (bus->parent) {
650 if ((child->subordinate > bus->subordinate) ||
651 (child->number > bus->subordinate) ||
652 (child->number < bus->number) ||
653 (child->subordinate < bus->number)) {
654 pr_debug("PCI: Bus #%02x (-#%02x) is %s "
655 "hidden behind%s bridge #%02x (-#%02x)\n",
656 child->number, child->subordinate,
657 (bus->number > child->subordinate &&
658 bus->subordinate < child->number) ?
659 "wholly" : "partially",
660 bus->self->transparent ? " transparent" : "",
661 bus->number, bus->subordinate);
667 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
673 * Read interrupt line and base address registers.
674 * The architecture-dependent code can tweak these, of course.
676 static void pci_read_irq(struct pci_dev *dev)
680 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
683 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
687 static void set_pcie_port_type(struct pci_dev *pdev)
692 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
696 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
697 pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4;
700 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
703 * pci_setup_device - fill in class and map information of a device
704 * @dev: the device structure to fill
706 * Initialize the device structure with information about the device's
707 * vendor,class,memory and IO-space addresses,IRQ lines etc.
708 * Called at initialisation of the PCI subsystem and by CardBus services.
709 * Returns 0 on success and negative if unknown type of device (not normal,
710 * bridge or CardBus).
712 int pci_setup_device(struct pci_dev *dev)
716 struct pci_slot *slot;
718 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
721 dev->sysdata = dev->bus->sysdata;
722 dev->dev.parent = dev->bus->bridge;
723 dev->dev.bus = &pci_bus_type;
724 dev->hdr_type = hdr_type & 0x7f;
725 dev->multifunction = !!(hdr_type & 0x80);
726 dev->error_state = pci_channel_io_normal;
727 set_pcie_port_type(dev);
729 list_for_each_entry(slot, &dev->bus->slots, list)
730 if (PCI_SLOT(dev->devfn) == slot->number)
733 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
734 set this higher, assuming the system even supports it. */
735 dev->dma_mask = 0xffffffff;
737 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
738 dev->bus->number, PCI_SLOT(dev->devfn),
739 PCI_FUNC(dev->devfn));
741 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
742 dev->revision = class & 0xff;
743 class >>= 8; /* upper 3 bytes */
747 dev_dbg(&dev->dev, "found [%04x:%04x] class %06x header type %02x\n",
748 dev->vendor, dev->device, class, dev->hdr_type);
750 /* need to have dev->class ready */
751 dev->cfg_size = pci_cfg_space_size(dev);
753 /* "Unknown power state" */
754 dev->current_state = PCI_UNKNOWN;
756 /* Early fixups, before probing the BARs */
757 pci_fixup_device(pci_fixup_early, dev);
758 /* device class may be changed after fixup */
759 class = dev->class >> 8;
761 switch (dev->hdr_type) { /* header type */
762 case PCI_HEADER_TYPE_NORMAL: /* standard header */
763 if (class == PCI_CLASS_BRIDGE_PCI)
766 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
767 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
768 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
771 * Do the ugly legacy mode stuff here rather than broken chip
772 * quirk code. Legacy mode ATA controllers have fixed
773 * addresses. These are not always echoed in BAR0-3, and
774 * BAR0-3 in a few cases contain junk!
776 if (class == PCI_CLASS_STORAGE_IDE) {
778 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
779 if ((progif & 1) == 0) {
780 dev->resource[0].start = 0x1F0;
781 dev->resource[0].end = 0x1F7;
782 dev->resource[0].flags = LEGACY_IO_RESOURCE;
783 dev->resource[1].start = 0x3F6;
784 dev->resource[1].end = 0x3F6;
785 dev->resource[1].flags = LEGACY_IO_RESOURCE;
787 if ((progif & 4) == 0) {
788 dev->resource[2].start = 0x170;
789 dev->resource[2].end = 0x177;
790 dev->resource[2].flags = LEGACY_IO_RESOURCE;
791 dev->resource[3].start = 0x376;
792 dev->resource[3].end = 0x376;
793 dev->resource[3].flags = LEGACY_IO_RESOURCE;
798 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
799 if (class != PCI_CLASS_BRIDGE_PCI)
801 /* The PCI-to-PCI bridge spec requires that subtractive
802 decoding (i.e. transparent) bridge must have programming
803 interface code of 0x01. */
805 dev->transparent = ((dev->class & 0xff) == 1);
806 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
809 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
810 if (class != PCI_CLASS_BRIDGE_CARDBUS)
813 pci_read_bases(dev, 1, 0);
814 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
815 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
818 default: /* unknown header */
819 dev_err(&dev->dev, "unknown header type %02x, "
820 "ignoring device\n", dev->hdr_type);
824 dev_err(&dev->dev, "ignoring class %02x (doesn't match header "
825 "type %02x)\n", class, dev->hdr_type);
826 dev->class = PCI_CLASS_NOT_DEFINED;
829 /* We found a fine healthy device, go go go... */
833 static void pci_release_capabilities(struct pci_dev *dev)
835 pci_vpd_release(dev);
836 pci_iov_release(dev);
840 * pci_release_dev - free a pci device structure when all users of it are finished.
841 * @dev: device that's been disconnected
843 * Will be called only by the device core when all users of this pci device are
846 static void pci_release_dev(struct device *dev)
848 struct pci_dev *pci_dev;
850 pci_dev = to_pci_dev(dev);
851 pci_release_capabilities(pci_dev);
856 * pci_cfg_space_size - get the configuration space size of the PCI device.
859 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
860 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
861 * access it. Maybe we don't have a way to generate extended config space
862 * accesses, or the device is behind a reverse Express bridge. So we try
863 * reading the dword at 0x100 which must either be 0 or a valid extended
866 int pci_cfg_space_size_ext(struct pci_dev *dev)
869 int pos = PCI_CFG_SPACE_SIZE;
871 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
873 if (status == 0xffffffff)
876 return PCI_CFG_SPACE_EXP_SIZE;
879 return PCI_CFG_SPACE_SIZE;
882 int pci_cfg_space_size(struct pci_dev *dev)
888 class = dev->class >> 8;
889 if (class == PCI_CLASS_BRIDGE_HOST)
890 return pci_cfg_space_size_ext(dev);
892 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
894 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
898 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
899 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
903 return pci_cfg_space_size_ext(dev);
906 return PCI_CFG_SPACE_SIZE;
909 static void pci_release_bus_bridge_dev(struct device *dev)
914 struct pci_dev *alloc_pci_dev(void)
918 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
922 INIT_LIST_HEAD(&dev->bus_list);
926 EXPORT_SYMBOL(alloc_pci_dev);
929 * Read the config data for a PCI device, sanity-check it
930 * and fill in the dev structure...
932 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
938 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
941 /* some broken boards return 0 or ~0 if a slot is empty: */
942 if (l == 0xffffffff || l == 0x00000000 ||
943 l == 0x0000ffff || l == 0xffff0000)
946 /* Configuration request Retry Status */
947 while (l == 0xffff0001) {
950 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
952 /* Card hasn't responded in 60 seconds? Must be stuck. */
953 if (delay > 60 * 1000) {
954 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not "
955 "responding\n", pci_domain_nr(bus),
956 bus->number, PCI_SLOT(devfn),
962 dev = alloc_pci_dev();
968 dev->vendor = l & 0xffff;
969 dev->device = (l >> 16) & 0xffff;
971 if (pci_setup_device(dev)) {
979 static void pci_init_capabilities(struct pci_dev *dev)
982 pci_msi_init_pci_dev(dev);
984 /* Buffers for saving PCIe and PCI-X capabilities */
985 pci_allocate_cap_save_buffers(dev);
987 /* Power Management */
989 platform_pci_wakeup_init(dev);
991 /* Vital Product Data */
992 pci_vpd_pci22_init(dev);
994 /* Alternative Routing-ID Forwarding */
997 /* Single Root I/O Virtualization */
1001 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
1003 device_initialize(&dev->dev);
1004 dev->dev.release = pci_release_dev;
1007 dev->dev.dma_mask = &dev->dma_mask;
1008 dev->dev.dma_parms = &dev->dma_parms;
1009 dev->dev.coherent_dma_mask = 0xffffffffull;
1011 pci_set_dma_max_seg_size(dev, 65536);
1012 pci_set_dma_seg_boundary(dev, 0xffffffff);
1014 /* Fix up broken headers */
1015 pci_fixup_device(pci_fixup_header, dev);
1017 /* Initialize various capabilities */
1018 pci_init_capabilities(dev);
1021 * Add the device to our list of discovered devices
1022 * and the bus list for fixup functions, etc.
1024 down_write(&pci_bus_sem);
1025 list_add_tail(&dev->bus_list, &bus->devices);
1026 up_write(&pci_bus_sem);
1029 struct pci_dev *__ref pci_scan_single_device(struct pci_bus *bus, int devfn)
1031 struct pci_dev *dev;
1033 dev = pci_get_slot(bus, devfn);
1039 dev = pci_scan_device(bus, devfn);
1043 pci_device_add(dev, bus);
1047 EXPORT_SYMBOL(pci_scan_single_device);
1050 * pci_scan_slot - scan a PCI slot on a bus for devices.
1051 * @bus: PCI bus to scan
1052 * @devfn: slot number to scan (must have zero function.)
1054 * Scan a PCI slot on the specified PCI bus for devices, adding
1055 * discovered devices to the @bus->devices list. New devices
1056 * will not have is_added set.
1058 * Returns the number of new devices found.
1060 int pci_scan_slot(struct pci_bus *bus, int devfn)
1063 struct pci_dev *dev;
1065 dev = pci_scan_single_device(bus, devfn);
1066 if (dev && !dev->is_added) /* new device? */
1069 if (dev && dev->multifunction) {
1070 for (fn = 1; fn < 8; fn++) {
1071 dev = pci_scan_single_device(bus, devfn + fn);
1075 dev->multifunction = 1;
1080 /* only one slot has pcie device */
1081 if (bus->self && nr)
1082 pcie_aspm_init_link_state(bus->self);
1087 unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
1089 unsigned int devfn, pass, max = bus->secondary;
1090 struct pci_dev *dev;
1092 pr_debug("PCI: Scanning bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
1094 /* Go find them, Rover! */
1095 for (devfn = 0; devfn < 0x100; devfn += 8)
1096 pci_scan_slot(bus, devfn);
1098 /* Reserve buses for SR-IOV capability. */
1099 max += pci_iov_bus_range(bus);
1102 * After performing arch-dependent fixup of the bus, look behind
1103 * all PCI-to-PCI bridges on this bus.
1105 if (!bus->is_added) {
1106 pr_debug("PCI: Fixups for bus %04x:%02x\n",
1107 pci_domain_nr(bus), bus->number);
1108 pcibios_fixup_bus(bus);
1109 if (pci_is_root_bus(bus))
1113 for (pass=0; pass < 2; pass++)
1114 list_for_each_entry(dev, &bus->devices, bus_list) {
1115 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1116 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1117 max = pci_scan_bridge(bus, dev, max, pass);
1121 * We've scanned the bus and so we know all about what's on
1122 * the other side of any bridges that may be on this bus plus
1125 * Return how far we've got finding sub-buses.
1127 pr_debug("PCI: Bus scan for %04x:%02x returning with max=%02x\n",
1128 pci_domain_nr(bus), bus->number, max);
1132 struct pci_bus * pci_create_bus(struct device *parent,
1133 int bus, struct pci_ops *ops, void *sysdata)
1139 b = pci_alloc_bus();
1143 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1149 b->sysdata = sysdata;
1152 if (pci_find_bus(pci_domain_nr(b), bus)) {
1153 /* If we already got to this bus through a different bridge, ignore it */
1154 pr_debug("PCI: Bus %04x:%02x already known\n", pci_domain_nr(b), bus);
1158 down_write(&pci_bus_sem);
1159 list_add_tail(&b->node, &pci_root_buses);
1160 up_write(&pci_bus_sem);
1162 dev->parent = parent;
1163 dev->release = pci_release_bus_bridge_dev;
1164 dev_set_name(dev, "pci%04x:%02x", pci_domain_nr(b), bus);
1165 error = device_register(dev);
1168 b->bridge = get_device(dev);
1171 set_dev_node(b->bridge, pcibus_to_node(b));
1173 b->dev.class = &pcibus_class;
1174 b->dev.parent = b->bridge;
1175 dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus);
1176 error = device_register(&b->dev);
1178 goto class_dev_reg_err;
1179 error = device_create_file(&b->dev, &dev_attr_cpuaffinity);
1181 goto dev_create_file_err;
1183 /* Create legacy_io and legacy_mem files for this bus */
1184 pci_create_legacy_files(b);
1186 b->number = b->secondary = bus;
1187 b->resource[0] = &ioport_resource;
1188 b->resource[1] = &iomem_resource;
1192 dev_create_file_err:
1193 device_unregister(&b->dev);
1195 device_unregister(dev);
1197 down_write(&pci_bus_sem);
1199 up_write(&pci_bus_sem);
1206 struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent,
1207 int bus, struct pci_ops *ops, void *sysdata)
1211 b = pci_create_bus(parent, bus, ops, sysdata);
1213 b->subordinate = pci_scan_child_bus(b);
1216 EXPORT_SYMBOL(pci_scan_bus_parented);
1218 #ifdef CONFIG_HOTPLUG
1220 * pci_rescan_bus - scan a PCI bus for devices.
1221 * @bus: PCI bus to scan
1223 * Scan a PCI bus and child buses for new devices, adds them,
1226 * Returns the max number of subordinate bus discovered.
1228 unsigned int __ref pci_rescan_bus(struct pci_bus *bus)
1231 struct pci_dev *dev;
1233 max = pci_scan_child_bus(bus);
1235 down_read(&pci_bus_sem);
1236 list_for_each_entry(dev, &bus->devices, bus_list)
1237 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1238 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1239 if (dev->subordinate)
1240 pci_bus_size_bridges(dev->subordinate);
1241 up_read(&pci_bus_sem);
1243 pci_bus_assign_resources(bus);
1244 pci_enable_bridges(bus);
1245 pci_bus_add_devices(bus);
1249 EXPORT_SYMBOL_GPL(pci_rescan_bus);
1251 EXPORT_SYMBOL(pci_add_new_bus);
1252 EXPORT_SYMBOL(pci_scan_slot);
1253 EXPORT_SYMBOL(pci_scan_bridge);
1254 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
1257 static int __init pci_sort_bf_cmp(const struct device *d_a, const struct device *d_b)
1259 const struct pci_dev *a = to_pci_dev(d_a);
1260 const struct pci_dev *b = to_pci_dev(d_b);
1262 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
1263 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
1265 if (a->bus->number < b->bus->number) return -1;
1266 else if (a->bus->number > b->bus->number) return 1;
1268 if (a->devfn < b->devfn) return -1;
1269 else if (a->devfn > b->devfn) return 1;
1274 void __init pci_sort_breadthfirst(void)
1276 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);