2 * probe.c - PCI detection and setup code
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
9 #include <linux/slab.h>
10 #include <linux/module.h>
11 #include <linux/cpumask.h>
12 #include <linux/pci-aspm.h>
15 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
16 #define CARDBUS_RESERVE_BUSNR 3
18 /* Ugh. Need to stop exporting this to modules. */
19 LIST_HEAD(pci_root_buses);
20 EXPORT_SYMBOL(pci_root_buses);
23 static int find_anything(struct device *dev, void *data)
29 * Some device drivers need know if pci is initiated.
30 * Basically, we think pci is not initiated when there
31 * is no device to be found on the pci_bus_type.
33 int no_pci_devices(void)
38 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
39 no_devices = (dev == NULL);
43 EXPORT_SYMBOL(no_pci_devices);
48 static void release_pcibus_dev(struct device *dev)
50 struct pci_bus *pci_bus = to_pci_bus(dev);
53 put_device(pci_bus->bridge);
54 pci_bus_remove_resources(pci_bus);
55 pci_release_bus_of_node(pci_bus);
59 static struct class pcibus_class = {
61 .dev_release = &release_pcibus_dev,
62 .dev_attrs = pcibus_dev_attrs,
65 static int __init pcibus_class_init(void)
67 return class_register(&pcibus_class);
69 postcore_initcall(pcibus_class_init);
71 static u64 pci_size(u64 base, u64 maxbase, u64 mask)
73 u64 size = mask & maxbase; /* Find the significant bits */
77 /* Get the lowest of them to find the decode size, and
78 from that the extent. */
79 size = (size & ~(size-1)) - 1;
81 /* base == maxbase can be valid only if the BAR has
82 already been programmed with all 1s. */
83 if (base == maxbase && ((base | size) & mask) != mask)
89 static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
94 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
95 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
96 flags |= IORESOURCE_IO;
100 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
101 flags |= IORESOURCE_MEM;
102 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
103 flags |= IORESOURCE_PREFETCH;
105 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
107 case PCI_BASE_ADDRESS_MEM_TYPE_32:
109 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
110 dev_info(&dev->dev, "1M mem BAR treated as 32-bit BAR\n");
112 case PCI_BASE_ADDRESS_MEM_TYPE_64:
113 flags |= IORESOURCE_MEM_64;
117 "mem unknown type %x treated as 32-bit BAR\n",
125 * pci_read_base - read a PCI BAR
126 * @dev: the PCI device
127 * @type: type of the BAR
128 * @res: resource buffer to be filled in
129 * @pos: BAR position in the config space
131 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
133 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
134 struct resource *res, unsigned int pos)
139 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
141 if (!dev->mmio_always_on) {
142 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
143 pci_write_config_word(dev, PCI_COMMAND,
144 orig_cmd & ~(PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
147 res->name = pci_name(dev);
149 pci_read_config_dword(dev, pos, &l);
150 pci_write_config_dword(dev, pos, l | mask);
151 pci_read_config_dword(dev, pos, &sz);
152 pci_write_config_dword(dev, pos, l);
154 if (!dev->mmio_always_on)
155 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
158 * All bits set in sz means the device isn't working properly.
159 * If the BAR isn't implemented, all bits must be 0. If it's a
160 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
163 if (!sz || sz == 0xffffffff)
167 * I don't know how l can have all bits set. Copied from old code.
168 * Maybe it fixes a bug on some ancient platform.
173 if (type == pci_bar_unknown) {
174 res->flags = decode_bar(dev, l);
175 res->flags |= IORESOURCE_SIZEALIGN;
176 if (res->flags & IORESOURCE_IO) {
177 l &= PCI_BASE_ADDRESS_IO_MASK;
178 sz &= PCI_BASE_ADDRESS_IO_MASK;
179 mask = PCI_BASE_ADDRESS_IO_MASK & (u32) IO_SPACE_LIMIT;
181 l &= PCI_BASE_ADDRESS_MEM_MASK;
182 sz &= PCI_BASE_ADDRESS_MEM_MASK;
183 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
186 res->flags |= (l & IORESOURCE_ROM_ENABLE);
187 l &= PCI_ROM_ADDRESS_MASK;
188 sz &= PCI_ROM_ADDRESS_MASK;
189 mask = (u32)PCI_ROM_ADDRESS_MASK;
192 if (res->flags & IORESOURCE_MEM_64) {
195 u64 mask64 = mask | (u64)~0 << 32;
197 pci_read_config_dword(dev, pos + 4, &l);
198 pci_write_config_dword(dev, pos + 4, ~0);
199 pci_read_config_dword(dev, pos + 4, &sz);
200 pci_write_config_dword(dev, pos + 4, l);
202 l64 |= ((u64)l << 32);
203 sz64 |= ((u64)sz << 32);
205 sz64 = pci_size(l64, sz64, mask64);
210 if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) {
211 dev_err(&dev->dev, "reg %x: can't handle 64-bit BAR\n",
216 if ((sizeof(resource_size_t) < 8) && l) {
217 /* Address above 32-bit boundary; disable the BAR */
218 pci_write_config_dword(dev, pos, 0);
219 pci_write_config_dword(dev, pos + 4, 0);
224 res->end = l64 + sz64;
225 dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n",
229 sz = pci_size(l, sz, mask);
237 dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n", pos, res);
241 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
247 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
249 unsigned int pos, reg;
251 if (dev->non_compliant_bars)
254 for (pos = 0; pos < howmany; pos++) {
255 struct resource *res = &dev->resource[pos];
256 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
257 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
261 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
262 dev->rom_base_reg = rom;
263 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
264 IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
265 IORESOURCE_SIZEALIGN;
266 __pci_read_base(dev, pci_bar_mem32, res, rom);
270 static void __devinit pci_read_bridge_io(struct pci_bus *child)
272 struct pci_dev *dev = child->self;
273 u8 io_base_lo, io_limit_lo;
274 unsigned long base, limit;
275 struct resource *res;
277 res = child->resource[0];
278 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
279 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
280 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
281 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
283 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
284 u16 io_base_hi, io_limit_hi;
285 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
286 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
287 base |= (io_base_hi << 16);
288 limit |= (io_limit_hi << 16);
291 if (base && base <= limit) {
292 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
296 res->end = limit + 0xfff;
297 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
301 static void __devinit pci_read_bridge_mmio(struct pci_bus *child)
303 struct pci_dev *dev = child->self;
304 u16 mem_base_lo, mem_limit_lo;
305 unsigned long base, limit;
306 struct resource *res;
308 res = child->resource[1];
309 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
310 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
311 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
312 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
313 if (base && base <= limit) {
314 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
316 res->end = limit + 0xfffff;
317 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
321 static void __devinit pci_read_bridge_mmio_pref(struct pci_bus *child)
323 struct pci_dev *dev = child->self;
324 u16 mem_base_lo, mem_limit_lo;
325 unsigned long base, limit;
326 struct resource *res;
328 res = child->resource[2];
329 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
330 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
331 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
332 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
334 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
335 u32 mem_base_hi, mem_limit_hi;
336 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
337 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
340 * Some bridges set the base > limit by default, and some
341 * (broken) BIOSes do not initialize them. If we find
342 * this, just assume they are not being used.
344 if (mem_base_hi <= mem_limit_hi) {
345 #if BITS_PER_LONG == 64
346 base |= ((long) mem_base_hi) << 32;
347 limit |= ((long) mem_limit_hi) << 32;
349 if (mem_base_hi || mem_limit_hi) {
350 dev_err(&dev->dev, "can't handle 64-bit "
351 "address space for bridge\n");
357 if (base && base <= limit) {
358 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
359 IORESOURCE_MEM | IORESOURCE_PREFETCH;
360 if (res->flags & PCI_PREF_RANGE_TYPE_64)
361 res->flags |= IORESOURCE_MEM_64;
363 res->end = limit + 0xfffff;
364 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
368 void __devinit pci_read_bridge_bases(struct pci_bus *child)
370 struct pci_dev *dev = child->self;
371 struct resource *res;
374 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
377 dev_info(&dev->dev, "PCI bridge to [bus %02x-%02x]%s\n",
378 child->secondary, child->subordinate,
379 dev->transparent ? " (subtractive decode)" : "");
381 pci_bus_remove_resources(child);
382 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
383 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
385 pci_read_bridge_io(child);
386 pci_read_bridge_mmio(child);
387 pci_read_bridge_mmio_pref(child);
389 if (dev->transparent) {
390 pci_bus_for_each_resource(child->parent, res, i) {
392 pci_bus_add_resource(child, res,
393 PCI_SUBTRACTIVE_DECODE);
394 dev_printk(KERN_DEBUG, &dev->dev,
395 " bridge window %pR (subtractive decode)\n",
402 static struct pci_bus * pci_alloc_bus(void)
406 b = kzalloc(sizeof(*b), GFP_KERNEL);
408 INIT_LIST_HEAD(&b->node);
409 INIT_LIST_HEAD(&b->children);
410 INIT_LIST_HEAD(&b->devices);
411 INIT_LIST_HEAD(&b->slots);
412 INIT_LIST_HEAD(&b->resources);
413 b->max_bus_speed = PCI_SPEED_UNKNOWN;
414 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
419 static unsigned char pcix_bus_speed[] = {
420 PCI_SPEED_UNKNOWN, /* 0 */
421 PCI_SPEED_66MHz_PCIX, /* 1 */
422 PCI_SPEED_100MHz_PCIX, /* 2 */
423 PCI_SPEED_133MHz_PCIX, /* 3 */
424 PCI_SPEED_UNKNOWN, /* 4 */
425 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
426 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
427 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
428 PCI_SPEED_UNKNOWN, /* 8 */
429 PCI_SPEED_66MHz_PCIX_266, /* 9 */
430 PCI_SPEED_100MHz_PCIX_266, /* A */
431 PCI_SPEED_133MHz_PCIX_266, /* B */
432 PCI_SPEED_UNKNOWN, /* C */
433 PCI_SPEED_66MHz_PCIX_533, /* D */
434 PCI_SPEED_100MHz_PCIX_533, /* E */
435 PCI_SPEED_133MHz_PCIX_533 /* F */
438 static unsigned char pcie_link_speed[] = {
439 PCI_SPEED_UNKNOWN, /* 0 */
440 PCIE_SPEED_2_5GT, /* 1 */
441 PCIE_SPEED_5_0GT, /* 2 */
442 PCIE_SPEED_8_0GT, /* 3 */
443 PCI_SPEED_UNKNOWN, /* 4 */
444 PCI_SPEED_UNKNOWN, /* 5 */
445 PCI_SPEED_UNKNOWN, /* 6 */
446 PCI_SPEED_UNKNOWN, /* 7 */
447 PCI_SPEED_UNKNOWN, /* 8 */
448 PCI_SPEED_UNKNOWN, /* 9 */
449 PCI_SPEED_UNKNOWN, /* A */
450 PCI_SPEED_UNKNOWN, /* B */
451 PCI_SPEED_UNKNOWN, /* C */
452 PCI_SPEED_UNKNOWN, /* D */
453 PCI_SPEED_UNKNOWN, /* E */
454 PCI_SPEED_UNKNOWN /* F */
457 void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
459 bus->cur_bus_speed = pcie_link_speed[linksta & 0xf];
461 EXPORT_SYMBOL_GPL(pcie_update_link_speed);
463 static unsigned char agp_speeds[] = {
471 static enum pci_bus_speed agp_speed(int agp3, int agpstat)
477 else if (agpstat & 2)
479 else if (agpstat & 1)
491 return agp_speeds[index];
495 static void pci_set_bus_speed(struct pci_bus *bus)
497 struct pci_dev *bridge = bus->self;
500 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
502 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
506 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
507 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
509 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
510 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
513 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
516 enum pci_bus_speed max;
517 pci_read_config_word(bridge, pos + 2, &status);
519 if (status & 0x8000) {
520 max = PCI_SPEED_133MHz_PCIX_533;
521 } else if (status & 0x4000) {
522 max = PCI_SPEED_133MHz_PCIX_266;
523 } else if (status & 0x0002) {
524 if (((status >> 12) & 0x3) == 2) {
525 max = PCI_SPEED_133MHz_PCIX_ECC;
527 max = PCI_SPEED_133MHz_PCIX;
530 max = PCI_SPEED_66MHz_PCIX;
533 bus->max_bus_speed = max;
534 bus->cur_bus_speed = pcix_bus_speed[(status >> 6) & 0xf];
539 pos = pci_find_capability(bridge, PCI_CAP_ID_EXP);
544 pci_read_config_dword(bridge, pos + PCI_EXP_LNKCAP, &linkcap);
545 bus->max_bus_speed = pcie_link_speed[linkcap & 0xf];
547 pci_read_config_word(bridge, pos + PCI_EXP_LNKSTA, &linksta);
548 pcie_update_link_speed(bus, linksta);
553 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
554 struct pci_dev *bridge, int busnr)
556 struct pci_bus *child;
560 * Allocate a new bus, and inherit stuff from the parent..
562 child = pci_alloc_bus();
566 child->parent = parent;
567 child->ops = parent->ops;
568 child->sysdata = parent->sysdata;
569 child->bus_flags = parent->bus_flags;
571 /* initialize some portions of the bus device, but don't register it
572 * now as the parent is not properly set up yet. This device will get
573 * registered later in pci_bus_add_devices()
575 child->dev.class = &pcibus_class;
576 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
579 * Set up the primary, secondary and subordinate
582 child->number = child->secondary = busnr;
583 child->primary = parent->secondary;
584 child->subordinate = 0xff;
589 child->self = bridge;
590 child->bridge = get_device(&bridge->dev);
591 pci_set_bus_of_node(child);
592 pci_set_bus_speed(child);
594 /* Set up default resource pointers and names.. */
595 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
596 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
597 child->resource[i]->name = child->name;
599 bridge->subordinate = child;
604 struct pci_bus *__ref pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
606 struct pci_bus *child;
608 child = pci_alloc_child_bus(parent, dev, busnr);
610 down_write(&pci_bus_sem);
611 list_add_tail(&child->node, &parent->children);
612 up_write(&pci_bus_sem);
617 static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
619 struct pci_bus *parent = child->parent;
621 /* Attempts to fix that up are really dangerous unless
622 we're going to re-assign all bus numbers. */
623 if (!pcibios_assign_all_busses())
626 while (parent->parent && parent->subordinate < max) {
627 parent->subordinate = max;
628 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
629 parent = parent->parent;
634 * If it's a bridge, configure it and scan the bus behind it.
635 * For CardBus bridges, we don't scan behind as the devices will
636 * be handled by the bridge driver itself.
638 * We need to process bridges in two passes -- first we scan those
639 * already configured by the BIOS and after we are done with all of
640 * them, we proceed to assigning numbers to the remaining buses in
641 * order to avoid overlaps between old and new bus numbers.
643 int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
645 struct pci_bus *child;
646 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
649 u8 primary, secondary, subordinate;
652 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
653 primary = buses & 0xFF;
654 secondary = (buses >> 8) & 0xFF;
655 subordinate = (buses >> 16) & 0xFF;
657 dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
658 secondary, subordinate, pass);
660 if (!primary && (primary != bus->number) && secondary && subordinate) {
661 dev_warn(&dev->dev, "Primary bus is hard wired to 0\n");
662 primary = bus->number;
665 /* Check if setup is sensible at all */
667 (primary != bus->number || secondary <= bus->number ||
668 secondary > subordinate)) {
669 dev_info(&dev->dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
670 secondary, subordinate);
674 /* Disable MasterAbortMode during probing to avoid reporting
675 of bus errors (in some architectures) */
676 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
677 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
678 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
680 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
681 !is_cardbus && !broken) {
684 * Bus already configured by firmware, process it in the first
685 * pass and just note the configuration.
691 * If we already got to this bus through a different bridge,
692 * don't re-add it. This can happen with the i450NX chipset.
694 * However, we continue to descend down the hierarchy and
695 * scan remaining child buses.
697 child = pci_find_bus(pci_domain_nr(bus), secondary);
699 child = pci_add_new_bus(bus, dev, secondary);
702 child->primary = primary;
703 child->subordinate = subordinate;
704 child->bridge_ctl = bctl;
707 cmax = pci_scan_child_bus(child);
710 if (child->subordinate > max)
711 max = child->subordinate;
714 * We need to assign a number to this bus which we always
715 * do in the second pass.
718 if (pcibios_assign_all_busses() || broken)
719 /* Temporarily disable forwarding of the
720 configuration cycles on all bridges in
721 this bus segment to avoid possible
722 conflicts in the second pass between two
723 bridges programmed with overlapping
725 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
731 pci_write_config_word(dev, PCI_STATUS, 0xffff);
733 /* Prevent assigning a bus number that already exists.
734 * This can happen when a bridge is hot-plugged, so in
735 * this case we only re-scan this bus. */
736 child = pci_find_bus(pci_domain_nr(bus), max+1);
738 child = pci_add_new_bus(bus, dev, ++max);
742 buses = (buses & 0xff000000)
743 | ((unsigned int)(child->primary) << 0)
744 | ((unsigned int)(child->secondary) << 8)
745 | ((unsigned int)(child->subordinate) << 16);
748 * yenta.c forces a secondary latency timer of 176.
749 * Copy that behaviour here.
752 buses &= ~0xff000000;
753 buses |= CARDBUS_LATENCY_TIMER << 24;
757 * We need to blast all three values with a single write.
759 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
762 child->bridge_ctl = bctl;
764 * Adjust subordinate busnr in parent buses.
765 * We do this before scanning for children because
766 * some devices may not be detected if the bios
769 pci_fixup_parent_subordinate_busnr(child, max);
770 /* Now we can scan all subordinate buses... */
771 max = pci_scan_child_bus(child);
773 * now fix it up again since we have found
774 * the real value of max.
776 pci_fixup_parent_subordinate_busnr(child, max);
779 * For CardBus bridges, we leave 4 bus numbers
780 * as cards with a PCI-to-PCI bridge can be
783 for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) {
784 struct pci_bus *parent = bus;
785 if (pci_find_bus(pci_domain_nr(bus),
788 while (parent->parent) {
789 if ((!pcibios_assign_all_busses()) &&
790 (parent->subordinate > max) &&
791 (parent->subordinate <= max+i)) {
794 parent = parent->parent;
798 * Often, there are two cardbus bridges
799 * -- try to leave one valid bus number
807 pci_fixup_parent_subordinate_busnr(child, max);
810 * Set the subordinate bus number to its real value.
812 child->subordinate = max;
813 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
817 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
818 pci_domain_nr(bus), child->number);
820 /* Has only triggered on CardBus, fixup is in yenta_socket */
821 while (bus->parent) {
822 if ((child->subordinate > bus->subordinate) ||
823 (child->number > bus->subordinate) ||
824 (child->number < bus->number) ||
825 (child->subordinate < bus->number)) {
826 dev_info(&child->dev, "[bus %02x-%02x] %s "
827 "hidden behind%s bridge %s [bus %02x-%02x]\n",
828 child->number, child->subordinate,
829 (bus->number > child->subordinate &&
830 bus->subordinate < child->number) ?
831 "wholly" : "partially",
832 bus->self->transparent ? " transparent" : "",
834 bus->number, bus->subordinate);
840 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
846 * Read interrupt line and base address registers.
847 * The architecture-dependent code can tweak these, of course.
849 static void pci_read_irq(struct pci_dev *dev)
853 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
856 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
860 void set_pcie_port_type(struct pci_dev *pdev)
865 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
869 pdev->pcie_cap = pos;
870 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
871 pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4;
872 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16);
873 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
876 void set_pcie_hotplug_bridge(struct pci_dev *pdev)
882 pos = pci_pcie_cap(pdev);
885 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
886 if (!(reg16 & PCI_EXP_FLAGS_SLOT))
888 pci_read_config_dword(pdev, pos + PCI_EXP_SLTCAP, ®32);
889 if (reg32 & PCI_EXP_SLTCAP_HPC)
890 pdev->is_hotplug_bridge = 1;
893 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
896 * pci_setup_device - fill in class and map information of a device
897 * @dev: the device structure to fill
899 * Initialize the device structure with information about the device's
900 * vendor,class,memory and IO-space addresses,IRQ lines etc.
901 * Called at initialisation of the PCI subsystem and by CardBus services.
902 * Returns 0 on success and negative if unknown type of device (not normal,
903 * bridge or CardBus).
905 int pci_setup_device(struct pci_dev *dev)
910 struct pci_slot *slot;
913 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
916 dev->sysdata = dev->bus->sysdata;
917 dev->dev.parent = dev->bus->bridge;
918 dev->dev.bus = &pci_bus_type;
919 dev->hdr_type = hdr_type & 0x7f;
920 dev->multifunction = !!(hdr_type & 0x80);
921 dev->error_state = pci_channel_io_normal;
922 set_pcie_port_type(dev);
924 list_for_each_entry(slot, &dev->bus->slots, list)
925 if (PCI_SLOT(dev->devfn) == slot->number)
928 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
929 set this higher, assuming the system even supports it. */
930 dev->dma_mask = 0xffffffff;
932 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
933 dev->bus->number, PCI_SLOT(dev->devfn),
934 PCI_FUNC(dev->devfn));
936 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
937 dev->revision = class & 0xff;
938 class >>= 8; /* upper 3 bytes */
942 dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %d class %#08x\n",
943 dev->vendor, dev->device, dev->hdr_type, class);
945 /* need to have dev->class ready */
946 dev->cfg_size = pci_cfg_space_size(dev);
948 /* "Unknown power state" */
949 dev->current_state = PCI_UNKNOWN;
951 /* Early fixups, before probing the BARs */
952 pci_fixup_device(pci_fixup_early, dev);
953 /* device class may be changed after fixup */
954 class = dev->class >> 8;
956 if (dev->non_compliant_bars) {
957 pci_read_config_word(dev, PCI_COMMAND, &cmd);
958 if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
959 dev_info(&dev->dev, "device has non-compliant BARs; disabling IO/MEM decoding\n");
960 cmd &= ~PCI_COMMAND_IO;
961 cmd &= ~PCI_COMMAND_MEMORY;
962 pci_write_config_word(dev, PCI_COMMAND, cmd);
966 switch (dev->hdr_type) { /* header type */
967 case PCI_HEADER_TYPE_NORMAL: /* standard header */
968 if (class == PCI_CLASS_BRIDGE_PCI)
971 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
972 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
973 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
976 * Do the ugly legacy mode stuff here rather than broken chip
977 * quirk code. Legacy mode ATA controllers have fixed
978 * addresses. These are not always echoed in BAR0-3, and
979 * BAR0-3 in a few cases contain junk!
981 if (class == PCI_CLASS_STORAGE_IDE) {
983 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
984 if ((progif & 1) == 0) {
985 dev->resource[0].start = 0x1F0;
986 dev->resource[0].end = 0x1F7;
987 dev->resource[0].flags = LEGACY_IO_RESOURCE;
988 dev->resource[1].start = 0x3F6;
989 dev->resource[1].end = 0x3F6;
990 dev->resource[1].flags = LEGACY_IO_RESOURCE;
992 if ((progif & 4) == 0) {
993 dev->resource[2].start = 0x170;
994 dev->resource[2].end = 0x177;
995 dev->resource[2].flags = LEGACY_IO_RESOURCE;
996 dev->resource[3].start = 0x376;
997 dev->resource[3].end = 0x376;
998 dev->resource[3].flags = LEGACY_IO_RESOURCE;
1003 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
1004 if (class != PCI_CLASS_BRIDGE_PCI)
1006 /* The PCI-to-PCI bridge spec requires that subtractive
1007 decoding (i.e. transparent) bridge must have programming
1008 interface code of 0x01. */
1010 dev->transparent = ((dev->class & 0xff) == 1);
1011 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
1012 set_pcie_hotplug_bridge(dev);
1013 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
1015 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1016 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1020 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
1021 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1024 pci_read_bases(dev, 1, 0);
1025 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1026 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1029 default: /* unknown header */
1030 dev_err(&dev->dev, "unknown header type %02x, "
1031 "ignoring device\n", dev->hdr_type);
1035 dev_err(&dev->dev, "ignoring class %02x (doesn't match header "
1036 "type %02x)\n", class, dev->hdr_type);
1037 dev->class = PCI_CLASS_NOT_DEFINED;
1040 /* We found a fine healthy device, go go go... */
1044 static void pci_release_capabilities(struct pci_dev *dev)
1046 pci_vpd_release(dev);
1047 pci_iov_release(dev);
1051 * pci_release_dev - free a pci device structure when all users of it are finished.
1052 * @dev: device that's been disconnected
1054 * Will be called only by the device core when all users of this pci device are
1057 static void pci_release_dev(struct device *dev)
1059 struct pci_dev *pci_dev;
1061 pci_dev = to_pci_dev(dev);
1062 pci_release_capabilities(pci_dev);
1063 pci_release_of_node(pci_dev);
1068 * pci_cfg_space_size - get the configuration space size of the PCI device.
1071 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1072 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1073 * access it. Maybe we don't have a way to generate extended config space
1074 * accesses, or the device is behind a reverse Express bridge. So we try
1075 * reading the dword at 0x100 which must either be 0 or a valid extended
1076 * capability header.
1078 int pci_cfg_space_size_ext(struct pci_dev *dev)
1081 int pos = PCI_CFG_SPACE_SIZE;
1083 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1085 if (status == 0xffffffff)
1088 return PCI_CFG_SPACE_EXP_SIZE;
1091 return PCI_CFG_SPACE_SIZE;
1094 int pci_cfg_space_size(struct pci_dev *dev)
1100 class = dev->class >> 8;
1101 if (class == PCI_CLASS_BRIDGE_HOST)
1102 return pci_cfg_space_size_ext(dev);
1104 pos = pci_pcie_cap(dev);
1106 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1110 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1111 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
1115 return pci_cfg_space_size_ext(dev);
1118 return PCI_CFG_SPACE_SIZE;
1121 static void pci_release_bus_bridge_dev(struct device *dev)
1126 struct pci_dev *alloc_pci_dev(void)
1128 struct pci_dev *dev;
1130 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
1134 INIT_LIST_HEAD(&dev->bus_list);
1138 EXPORT_SYMBOL(alloc_pci_dev);
1141 * Read the config data for a PCI device, sanity-check it
1142 * and fill in the dev structure...
1144 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
1146 struct pci_dev *dev;
1150 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
1153 /* some broken boards return 0 or ~0 if a slot is empty: */
1154 if (l == 0xffffffff || l == 0x00000000 ||
1155 l == 0x0000ffff || l == 0xffff0000)
1158 /* Configuration request Retry Status */
1159 while (l == 0xffff0001) {
1162 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
1164 /* Card hasn't responded in 60 seconds? Must be stuck. */
1165 if (delay > 60 * 1000) {
1166 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not "
1167 "responding\n", pci_domain_nr(bus),
1168 bus->number, PCI_SLOT(devfn),
1174 dev = alloc_pci_dev();
1180 dev->vendor = l & 0xffff;
1181 dev->device = (l >> 16) & 0xffff;
1183 pci_set_of_node(dev);
1185 if (pci_setup_device(dev)) {
1193 static void pci_init_capabilities(struct pci_dev *dev)
1195 /* MSI/MSI-X list */
1196 pci_msi_init_pci_dev(dev);
1198 /* Buffers for saving PCIe and PCI-X capabilities */
1199 pci_allocate_cap_save_buffers(dev);
1201 /* Power Management */
1203 platform_pci_wakeup_init(dev);
1205 /* Vital Product Data */
1206 pci_vpd_pci22_init(dev);
1208 /* Alternative Routing-ID Forwarding */
1209 pci_enable_ari(dev);
1211 /* Single Root I/O Virtualization */
1214 /* Enable ACS P2P upstream forwarding */
1215 pci_enable_acs(dev);
1218 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
1220 device_initialize(&dev->dev);
1221 dev->dev.release = pci_release_dev;
1224 dev->dev.dma_mask = &dev->dma_mask;
1225 dev->dev.dma_parms = &dev->dma_parms;
1226 dev->dev.coherent_dma_mask = 0xffffffffull;
1228 pci_set_dma_max_seg_size(dev, 65536);
1229 pci_set_dma_seg_boundary(dev, 0xffffffff);
1231 /* Fix up broken headers */
1232 pci_fixup_device(pci_fixup_header, dev);
1234 /* Clear the state_saved flag. */
1235 dev->state_saved = false;
1237 /* Initialize various capabilities */
1238 pci_init_capabilities(dev);
1241 * Add the device to our list of discovered devices
1242 * and the bus list for fixup functions, etc.
1244 down_write(&pci_bus_sem);
1245 list_add_tail(&dev->bus_list, &bus->devices);
1246 up_write(&pci_bus_sem);
1249 struct pci_dev *__ref pci_scan_single_device(struct pci_bus *bus, int devfn)
1251 struct pci_dev *dev;
1253 dev = pci_get_slot(bus, devfn);
1259 dev = pci_scan_device(bus, devfn);
1263 pci_device_add(dev, bus);
1267 EXPORT_SYMBOL(pci_scan_single_device);
1269 static unsigned next_ari_fn(struct pci_dev *dev, unsigned fn)
1272 unsigned pos, next_fn;
1277 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1280 pci_read_config_word(dev, pos + 4, &cap);
1287 static unsigned next_trad_fn(struct pci_dev *dev, unsigned fn)
1289 return (fn + 1) % 8;
1292 static unsigned no_next_fn(struct pci_dev *dev, unsigned fn)
1297 static int only_one_child(struct pci_bus *bus)
1299 struct pci_dev *parent = bus->self;
1300 if (!parent || !pci_is_pcie(parent))
1302 if (parent->pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
1303 parent->pcie_type == PCI_EXP_TYPE_DOWNSTREAM)
1309 * pci_scan_slot - scan a PCI slot on a bus for devices.
1310 * @bus: PCI bus to scan
1311 * @devfn: slot number to scan (must have zero function.)
1313 * Scan a PCI slot on the specified PCI bus for devices, adding
1314 * discovered devices to the @bus->devices list. New devices
1315 * will not have is_added set.
1317 * Returns the number of new devices found.
1319 int pci_scan_slot(struct pci_bus *bus, int devfn)
1321 unsigned fn, nr = 0;
1322 struct pci_dev *dev;
1323 unsigned (*next_fn)(struct pci_dev *, unsigned) = no_next_fn;
1325 if (only_one_child(bus) && (devfn > 0))
1326 return 0; /* Already scanned the entire slot */
1328 dev = pci_scan_single_device(bus, devfn);
1334 if (pci_ari_enabled(bus))
1335 next_fn = next_ari_fn;
1336 else if (dev->multifunction)
1337 next_fn = next_trad_fn;
1339 for (fn = next_fn(dev, 0); fn > 0; fn = next_fn(dev, fn)) {
1340 dev = pci_scan_single_device(bus, devfn + fn);
1344 dev->multifunction = 1;
1348 /* only one slot has pcie device */
1349 if (bus->self && nr)
1350 pcie_aspm_init_link_state(bus->self);
1355 static int pcie_find_smpss(struct pci_dev *dev, void *data)
1359 if (!pci_is_pcie(dev))
1362 /* For PCIE hotplug enabled slots not connected directly to a
1363 * PCI-E root port, there can be problems when hotplugging
1364 * devices. This is due to the possibility of hotplugging a
1365 * device into the fabric with a smaller MPS that the devices
1366 * currently running have configured. Modifying the MPS on the
1367 * running devices could cause a fatal bus error due to an
1368 * incoming frame being larger than the newly configured MPS.
1369 * To work around this, the MPS for the entire fabric must be
1370 * set to the minimum size. Any devices hotplugged into this
1371 * fabric will have the minimum MPS set. If the PCI hotplug
1372 * slot is directly connected to the root port and there are not
1373 * other devices on the fabric (which seems to be the most
1374 * common case), then this is not an issue and MPS discovery
1375 * will occur as normal.
1377 if (dev->is_hotplug_bridge && (!list_is_singular(&dev->bus->devices) ||
1379 dev->bus->self->pcie_type != PCI_EXP_TYPE_ROOT_PORT)))
1382 if (*smpss > dev->pcie_mpss)
1383 *smpss = dev->pcie_mpss;
1388 static void pcie_write_mps(struct pci_dev *dev, int mps)
1392 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
1393 mps = 128 << dev->pcie_mpss;
1395 if (dev->pcie_type != PCI_EXP_TYPE_ROOT_PORT && dev->bus->self)
1396 /* For "Performance", the assumption is made that
1397 * downstream communication will never be larger than
1398 * the MRRS. So, the MPS only needs to be configured
1399 * for the upstream communication. This being the case,
1400 * walk from the top down and set the MPS of the child
1401 * to that of the parent bus.
1403 * Configure the device MPS with the smaller of the
1404 * device MPSS or the bridge MPS (which is assumed to be
1405 * properly configured at this point to the largest
1406 * allowable MPS based on its parent bus).
1408 mps = min(mps, pcie_get_mps(dev->bus->self));
1411 rc = pcie_set_mps(dev, mps);
1413 dev_err(&dev->dev, "Failed attempting to set the MPS\n");
1416 static void pcie_write_mrrs(struct pci_dev *dev)
1420 /* In the "safe" case, do not configure the MRRS. There appear to be
1421 * issues with setting MRRS to 0 on a number of devices.
1423 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
1426 /* For Max performance, the MRRS must be set to the largest supported
1427 * value. However, it cannot be configured larger than the MPS the
1428 * device or the bus can support. This should already be properly
1429 * configured by a prior call to pcie_write_mps.
1431 mrrs = pcie_get_mps(dev);
1433 /* MRRS is a R/W register. Invalid values can be written, but a
1434 * subsequent read will verify if the value is acceptable or not.
1435 * If the MRRS value provided is not acceptable (e.g., too large),
1436 * shrink the value until it is acceptable to the HW.
1438 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
1439 rc = pcie_set_readrq(dev, mrrs);
1443 dev_warn(&dev->dev, "Failed attempting to set the MRRS\n");
1448 dev_err(&dev->dev, "MRRS was unable to be configured with a "
1449 "safe value. If problems are experienced, try running "
1450 "with pci=pcie_bus_safe.\n");
1453 static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
1457 if (!pci_is_pcie(dev))
1460 mps = 128 << *(u8 *)data;
1461 orig_mps = pcie_get_mps(dev);
1463 pcie_write_mps(dev, mps);
1464 pcie_write_mrrs(dev);
1466 dev_info(&dev->dev, "PCI-E Max Payload Size set to %4d/%4d (was %4d), "
1467 "Max Read Rq %4d\n", pcie_get_mps(dev), 128 << dev->pcie_mpss,
1468 orig_mps, pcie_get_readrq(dev));
1473 /* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down,
1474 * parents then children fashion. If this changes, then this code will not
1477 void pcie_bus_configure_settings(struct pci_bus *bus, u8 mpss)
1481 if (!pci_is_pcie(bus->self))
1484 if (pcie_bus_config == PCIE_BUS_TUNE_OFF)
1487 /* FIXME - Peer to peer DMA is possible, though the endpoint would need
1488 * to be aware to the MPS of the destination. To work around this,
1489 * simply force the MPS of the entire system to the smallest possible.
1491 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
1494 if (pcie_bus_config == PCIE_BUS_SAFE) {
1497 pcie_find_smpss(bus->self, &smpss);
1498 pci_walk_bus(bus, pcie_find_smpss, &smpss);
1501 pcie_bus_configure_set(bus->self, &smpss);
1502 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
1504 EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
1506 unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
1508 unsigned int devfn, pass, max = bus->secondary;
1509 struct pci_dev *dev;
1511 dev_dbg(&bus->dev, "scanning bus\n");
1513 /* Go find them, Rover! */
1514 for (devfn = 0; devfn < 0x100; devfn += 8)
1515 pci_scan_slot(bus, devfn);
1517 /* Reserve buses for SR-IOV capability. */
1518 max += pci_iov_bus_range(bus);
1521 * After performing arch-dependent fixup of the bus, look behind
1522 * all PCI-to-PCI bridges on this bus.
1524 if (!bus->is_added) {
1525 dev_dbg(&bus->dev, "fixups for bus\n");
1526 pcibios_fixup_bus(bus);
1527 if (pci_is_root_bus(bus))
1531 for (pass=0; pass < 2; pass++)
1532 list_for_each_entry(dev, &bus->devices, bus_list) {
1533 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1534 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1535 max = pci_scan_bridge(bus, dev, max, pass);
1539 * We've scanned the bus and so we know all about what's on
1540 * the other side of any bridges that may be on this bus plus
1543 * Return how far we've got finding sub-buses.
1545 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
1549 struct pci_bus * pci_create_bus(struct device *parent,
1550 int bus, struct pci_ops *ops, void *sysdata)
1553 struct pci_bus *b, *b2;
1556 b = pci_alloc_bus();
1560 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1566 b->sysdata = sysdata;
1569 b2 = pci_find_bus(pci_domain_nr(b), bus);
1571 /* If we already got to this bus through a different bridge, ignore it */
1572 dev_dbg(&b2->dev, "bus already known\n");
1576 down_write(&pci_bus_sem);
1577 list_add_tail(&b->node, &pci_root_buses);
1578 up_write(&pci_bus_sem);
1580 dev->parent = parent;
1581 dev->release = pci_release_bus_bridge_dev;
1582 dev_set_name(dev, "pci%04x:%02x", pci_domain_nr(b), bus);
1583 error = device_register(dev);
1586 b->bridge = get_device(dev);
1587 device_enable_async_suspend(b->bridge);
1588 pci_set_bus_of_node(b);
1591 set_dev_node(b->bridge, pcibus_to_node(b));
1593 b->dev.class = &pcibus_class;
1594 b->dev.parent = b->bridge;
1595 dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus);
1596 error = device_register(&b->dev);
1598 goto class_dev_reg_err;
1600 /* Create legacy_io and legacy_mem files for this bus */
1601 pci_create_legacy_files(b);
1603 b->number = b->secondary = bus;
1604 b->resource[0] = &ioport_resource;
1605 b->resource[1] = &iomem_resource;
1610 device_unregister(dev);
1612 down_write(&pci_bus_sem);
1614 up_write(&pci_bus_sem);
1621 struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent,
1622 int bus, struct pci_ops *ops, void *sysdata)
1626 b = pci_create_bus(parent, bus, ops, sysdata);
1628 b->subordinate = pci_scan_child_bus(b);
1631 EXPORT_SYMBOL(pci_scan_bus_parented);
1633 #ifdef CONFIG_HOTPLUG
1635 * pci_rescan_bus - scan a PCI bus for devices.
1636 * @bus: PCI bus to scan
1638 * Scan a PCI bus and child buses for new devices, adds them,
1641 * Returns the max number of subordinate bus discovered.
1643 unsigned int __ref pci_rescan_bus(struct pci_bus *bus)
1646 struct pci_dev *dev;
1648 max = pci_scan_child_bus(bus);
1650 down_read(&pci_bus_sem);
1651 list_for_each_entry(dev, &bus->devices, bus_list)
1652 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1653 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1654 if (dev->subordinate)
1655 pci_bus_size_bridges(dev->subordinate);
1656 up_read(&pci_bus_sem);
1658 pci_bus_assign_resources(bus);
1659 pci_enable_bridges(bus);
1660 pci_bus_add_devices(bus);
1664 EXPORT_SYMBOL_GPL(pci_rescan_bus);
1666 EXPORT_SYMBOL(pci_add_new_bus);
1667 EXPORT_SYMBOL(pci_scan_slot);
1668 EXPORT_SYMBOL(pci_scan_bridge);
1669 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
1672 static int __init pci_sort_bf_cmp(const struct device *d_a, const struct device *d_b)
1674 const struct pci_dev *a = to_pci_dev(d_a);
1675 const struct pci_dev *b = to_pci_dev(d_b);
1677 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
1678 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
1680 if (a->bus->number < b->bus->number) return -1;
1681 else if (a->bus->number > b->bus->number) return 1;
1683 if (a->devfn < b->devfn) return -1;
1684 else if (a->devfn > b->devfn) return 1;
1689 void __init pci_sort_breadthfirst(void)
1691 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);