1 // SPDX-License-Identifier: GPL-2.0+ OR X11
5 * PCIe DM U-Boot driver for Freescale PowerPC SoCs
6 * Author: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
14 #include <asm/fsl_pci.h>
15 #include <asm/fsl_serdes.h>
16 #include <asm/global_data.h>
18 #include <linux/delay.h>
20 #include <dm/device_compat.h>
22 LIST_HEAD(fsl_pcie_list);
24 static int fsl_pcie_link_up(struct fsl_pcie *pcie);
26 static int fsl_pcie_addr_valid(struct fsl_pcie *pcie, pci_dev_t bdf)
28 struct udevice *bus = pcie->bus;
33 if (PCI_BUS(bdf) < dev_seq(bus))
36 if (PCI_BUS(bdf) > dev_seq(bus) && (!fsl_pcie_link_up(pcie) || pcie->mode))
39 if (PCI_BUS(bdf) == dev_seq(bus) && (PCI_DEV(bdf) > 0 || PCI_FUNC(bdf) > 0))
42 if (PCI_BUS(bdf) == (dev_seq(bus) + 1) && (PCI_DEV(bdf) > 0))
48 static int fsl_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
49 uint offset, ulong *valuep,
52 struct fsl_pcie *pcie = dev_get_priv(bus);
53 ccsr_fsl_pci_t *regs = pcie->regs;
56 if (fsl_pcie_addr_valid(pcie, bdf)) {
57 *valuep = pci_get_ff(size);
61 bdf = bdf - PCI_BDF(dev_seq(bus), 0, 0);
62 val = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000;
63 out_be32(®s->cfg_addr, val);
69 *valuep = in_8((u8 *)®s->cfg_data + (offset & 3));
72 *valuep = in_le16((u16 *)((u8 *)®s->cfg_data +
76 *valuep = in_le32(®s->cfg_data);
83 static int fsl_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
84 uint offset, ulong value,
87 struct fsl_pcie *pcie = dev_get_priv(bus);
88 ccsr_fsl_pci_t *regs = pcie->regs;
94 if (fsl_pcie_addr_valid(pcie, bdf))
97 bdf = bdf - PCI_BDF(dev_seq(bus), 0, 0);
98 val = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000;
99 out_be32(®s->cfg_addr, val);
106 out_8((u8 *)®s->cfg_data + (offset & 3), val_8);
110 out_le16((u16 *)((u8 *)®s->cfg_data + (offset & 2)), val_16);
114 out_le32(®s->cfg_data, val_32);
121 static int fsl_pcie_hose_read_config(struct fsl_pcie *pcie, uint offset,
122 ulong *valuep, enum pci_size_t size)
125 struct udevice *bus = pcie->bus;
127 ret = fsl_pcie_read_config(bus, PCI_BDF(dev_seq(bus), 0, 0),
128 offset, valuep, size);
133 static int fsl_pcie_hose_write_config(struct fsl_pcie *pcie, uint offset,
134 ulong value, enum pci_size_t size)
136 struct udevice *bus = pcie->bus;
138 return fsl_pcie_write_config(bus, PCI_BDF(dev_seq(bus), 0, 0),
139 offset, value, size);
142 static int fsl_pcie_hose_read_config_byte(struct fsl_pcie *pcie, uint offset,
148 ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_8);
154 static int fsl_pcie_hose_read_config_word(struct fsl_pcie *pcie, uint offset,
160 ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_16);
166 static int fsl_pcie_hose_read_config_dword(struct fsl_pcie *pcie, uint offset,
172 ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_32);
178 static int fsl_pcie_hose_write_config_byte(struct fsl_pcie *pcie, uint offset,
181 return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_8);
184 static int fsl_pcie_hose_write_config_word(struct fsl_pcie *pcie, uint offset,
187 return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_16);
190 static int fsl_pcie_hose_write_config_dword(struct fsl_pcie *pcie, uint offset,
193 return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_32);
196 static int fsl_pcie_link_up(struct fsl_pcie *pcie)
198 ccsr_fsl_pci_t *regs = pcie->regs;
201 if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
202 ltssm = (in_be32(®s->pex_csr0)
203 & PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT;
204 return ltssm == LTSSM_L0_REV3;
207 fsl_pcie_hose_read_config_word(pcie, PCI_LTSSM, <ssm);
209 return ltssm == LTSSM_L0;
212 static bool fsl_pcie_is_agent(struct fsl_pcie *pcie)
216 fsl_pcie_hose_read_config_byte(pcie, PCI_HEADER_TYPE, &header_type);
218 return (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL;
221 static int fsl_pcie_setup_law(struct fsl_pcie *pcie)
223 struct pci_region *io, *mem, *pref;
225 pci_get_regions(pcie->bus, &io, &mem, &pref);
228 set_next_law(mem->phys_start,
229 law_size_bits(mem->size),
233 set_next_law(io->phys_start,
234 law_size_bits(io->size),
240 static void fsl_pcie_config_ready(struct fsl_pcie *pcie)
242 ccsr_fsl_pci_t *regs = pcie->regs;
244 if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
245 setbits_be32(®s->config, FSL_PCIE_V3_CFG_RDY);
249 fsl_pcie_hose_write_config_byte(pcie, FSL_PCIE_CFG_RDY, 0x1);
252 static int fsl_pcie_setup_outbound_win(struct fsl_pcie *pcie, int idx,
253 int type, u64 phys, u64 bus_addr,
256 ccsr_fsl_pci_t *regs = pcie->regs;
257 pot_t *po = ®s->pot[idx];
263 out_be32(&po->powbar, phys >> 12);
264 out_be32(&po->potar, bus_addr >> 12);
265 #ifdef CONFIG_SYS_PCI_64BIT
266 out_be32(&po->potear, bus_addr >> 44);
268 out_be32(&po->potear, 0);
271 sz = (__ilog2_u64((u64)size) - 1);
274 if (type == PCI_REGION_IO)
275 war |= POWAR_IO_READ | POWAR_IO_WRITE;
277 war |= POWAR_MEM_READ | POWAR_MEM_WRITE;
279 out_be32(&po->powar, war);
284 static int fsl_pcie_setup_inbound_win(struct fsl_pcie *pcie, int idx,
285 bool pf, u64 phys, u64 bus_addr,
288 ccsr_fsl_pci_t *regs = pcie->regs;
289 pit_t *pi = ®s->pit[idx];
290 u32 sz = (__ilog2_u64(size) - 1);
291 u32 flag = PIWAR_LOCAL;
296 out_be32(&pi->pitar, phys >> 12);
297 out_be32(&pi->piwbar, bus_addr >> 12);
299 #ifdef CONFIG_SYS_PCI_64BIT
300 out_be32(&pi->piwbear, bus_addr >> 44);
302 out_be32(&pi->piwbear, 0);
305 #ifdef CONFIG_SYS_FSL_ERRATUM_A005434
309 flag |= PIWAR_EN | PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
312 out_be32(&pi->piwar, flag | sz);
317 static int fsl_pcie_setup_outbound_wins(struct fsl_pcie *pcie)
319 struct pci_region *io, *mem, *pref;
320 int idx = 1; /* skip 0 */
322 pci_get_regions(pcie->bus, &io, &mem, &pref);
325 /* ATU : OUTBOUND : IO */
326 fsl_pcie_setup_outbound_win(pcie, idx++,
333 /* ATU : OUTBOUND : MEM */
334 fsl_pcie_setup_outbound_win(pcie, idx++,
342 static int fsl_pcie_setup_inbound_wins(struct fsl_pcie *pcie)
344 phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS;
345 pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS;
346 u64 sz = min((u64)gd->ram_size, (1ull << 32));
350 if (pcie->block_rev >= PEX_IP_BLK_REV_2_2)
355 pci_sz = 1ull << __ilog2_u64(sz);
357 dev_dbg(pcie->bus, "R0 bus_start: %llx phys_start: %llx size: %llx\n",
358 (u64)bus_start, (u64)phys_start, (u64)sz);
360 /* if we aren't an exact power of two match, pci_sz is smaller
361 * round it up to the next power of two. We report the actual
362 * size to pci region tracking.
365 sz = 2ull << __ilog2_u64(sz);
367 fsl_pcie_setup_inbound_win(pcie, idx--, true,
368 CONFIG_SYS_PCI_MEMORY_PHYS,
369 CONFIG_SYS_PCI_MEMORY_BUS, sz);
370 #if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT)
372 * On 64-bit capable systems, set up a mapping for all of DRAM
373 * in high pci address space.
375 pci_sz = 1ull << __ilog2_u64(gd->ram_size);
376 /* round up to the next largest power of two */
377 if (gd->ram_size > pci_sz)
378 pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1);
380 dev_dbg(pcie->bus, "R64 bus_start: %llx phys_start: %llx size: %llx\n",
381 (u64)CONFIG_SYS_PCI64_MEMORY_BUS,
382 (u64)CONFIG_SYS_PCI_MEMORY_PHYS, (u64)pci_sz);
384 fsl_pcie_setup_inbound_win(pcie, idx--, true,
385 CONFIG_SYS_PCI_MEMORY_PHYS,
386 CONFIG_SYS_PCI64_MEMORY_BUS, pci_sz);
392 static int fsl_pcie_init_atmu(struct fsl_pcie *pcie)
394 fsl_pcie_setup_outbound_wins(pcie);
395 fsl_pcie_setup_inbound_wins(pcie);
400 static void fsl_pcie_dbi_read_only_reg_write_enable(struct fsl_pcie *pcie,
405 fsl_pcie_hose_read_config_dword(pcie, DBI_RO_WR_EN, &val);
410 fsl_pcie_hose_write_config_dword(pcie, DBI_RO_WR_EN, val);
413 static int fsl_pcie_init_port(struct fsl_pcie *pcie)
415 ccsr_fsl_pci_t *regs = pcie->regs;
419 fsl_pcie_init_atmu(pcie);
421 #ifdef CONFIG_FSL_PCIE_DISABLE_ASPM
423 fsl_pcie_hose_read_config_dword(pcie, PCI_LCR, &val_32);
425 fsl_pcie_hose_write_config_dword(pcie, PCI_LCR, val_32);
429 #ifdef CONFIG_FSL_PCIE_RESET
433 if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
434 /* assert PCIe reset */
435 setbits_be32(®s->pdb_stat, 0x08000000);
436 (void)in_be32(®s->pdb_stat);
438 /* clear PCIe reset */
439 clrbits_be32(®s->pdb_stat, 0x08000000);
441 for (i = 0; i < 100 && !fsl_pcie_link_up(pcie); i++)
444 fsl_pcie_hose_read_config_word(pcie, PCI_LTSSM, <ssm);
446 /* assert PCIe reset */
447 setbits_be32(®s->pdb_stat, 0x08000000);
448 (void)in_be32(®s->pdb_stat);
450 /* clear PCIe reset */
451 clrbits_be32(®s->pdb_stat, 0x08000000);
453 for (i = 0; i < 100 &&
454 !fsl_pcie_link_up(pcie); i++)
460 #ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
461 if (!fsl_pcie_link_up(pcie)) {
462 serdes_corenet_t *srds_regs;
464 srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
465 val_32 = in_be32(&srds_regs->srdspccr0);
467 if ((val_32 >> 28) == 3) {
470 out_be32(&srds_regs->srdspccr0, 2 << 28);
471 setbits_be32(®s->pdb_stat, 0x08000000);
472 in_be32(®s->pdb_stat);
474 clrbits_be32(®s->pdb_stat, 0x08000000);
476 for (i = 0; i < 100 && !fsl_pcie_link_up(pcie); i++)
483 * The Read-Only Write Enable bit defaults to 1 instead of 0.
484 * Set to 0 to protect the read-only registers.
486 #ifdef CONFIG_SYS_FSL_ERRATUM_A007815
487 fsl_pcie_dbi_read_only_reg_write_enable(pcie, false);
491 * Enable All Error Interrupts except
492 * - Master abort (pci)
493 * - Master PERR (pci)
496 out_be32(®s->peer, ~0x20140);
498 /* set URR, FER, NFER (but not CER) */
499 fsl_pcie_hose_read_config_dword(pcie, PCI_DCR, &val_32);
501 fsl_pcie_hose_write_config_dword(pcie, PCI_DCR, val_32);
503 /* Clear all error indications */
504 out_be32(®s->pme_msg_det, 0xffffffff);
505 out_be32(®s->pme_msg_int_en, 0xffffffff);
506 out_be32(®s->pedr, 0xffffffff);
508 fsl_pcie_hose_read_config_word(pcie, PCI_DSR, &val_16);
510 fsl_pcie_hose_write_config_word(pcie, PCI_DSR, 0xffff);
512 fsl_pcie_hose_read_config_word(pcie, PCI_SEC_STATUS, &val_16);
514 fsl_pcie_hose_write_config_word(pcie, PCI_SEC_STATUS, 0xffff);
519 static int fsl_pcie_fixup_classcode(struct fsl_pcie *pcie)
524 if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
525 classcode_reg = PCI_CLASS_REVISION;
526 fsl_pcie_dbi_read_only_reg_write_enable(pcie, true);
528 classcode_reg = CSR_CLASSCODE;
531 fsl_pcie_hose_read_config_dword(pcie, classcode_reg, &val);
533 val |= PCI_CLASS_BRIDGE_PCI << 16;
534 fsl_pcie_hose_write_config_dword(pcie, classcode_reg, val);
536 if (pcie->block_rev >= PEX_IP_BLK_REV_3_0)
537 fsl_pcie_dbi_read_only_reg_write_enable(pcie, false);
542 static int fsl_pcie_init_rc(struct fsl_pcie *pcie)
544 return fsl_pcie_fixup_classcode(pcie);
547 static int fsl_pcie_init_ep(struct fsl_pcie *pcie)
549 fsl_pcie_config_ready(pcie);
554 static int fsl_pcie_probe(struct udevice *dev)
556 struct fsl_pcie *pcie = dev_get_priv(dev);
557 ccsr_fsl_pci_t *regs = pcie->regs;
561 pcie->block_rev = in_be32(®s->block_rev1);
563 list_add(&pcie->list, &fsl_pcie_list);
564 pcie->enabled = is_serdes_configured(PCIE1 + pcie->idx);
565 if (!pcie->enabled) {
566 printf("PCIe%d: %s disabled\n", pcie->idx, dev->name);
570 fsl_pcie_setup_law(pcie);
572 pcie->mode = fsl_pcie_is_agent(pcie);
574 fsl_pcie_init_port(pcie);
576 printf("PCIe%d: %s ", pcie->idx, dev->name);
580 fsl_pcie_init_ep(pcie);
582 printf("Root Complex");
583 fsl_pcie_init_rc(pcie);
586 if (!fsl_pcie_link_up(pcie)) {
587 printf(": %s\n", pcie->mode ? "undetermined link" : "no link");
591 fsl_pcie_hose_read_config_word(pcie, PCI_LSR, &val_16);
592 printf(": x%d gen%d\n", (val_16 & 0x3f0) >> 4, (val_16 & 0xf));
597 static int fsl_pcie_of_to_plat(struct udevice *dev)
599 struct fsl_pcie *pcie = dev_get_priv(dev);
600 struct fsl_pcie_data *info;
603 pcie->regs = dev_remap_addr(dev);
605 pr_err("\"reg\" resource not found\n");
609 ret = dev_read_u32(dev, "law_trgt_if", &pcie->law_trgt_if);
611 pr_err("\"law_trgt_if\" not found\n");
615 info = (struct fsl_pcie_data *)dev_get_driver_data(dev);
617 pcie->idx = abs((u32)(dev_read_addr(dev) & info->block_offset_mask) -
618 info->block_offset) / info->stride;
623 static const struct dm_pci_ops fsl_pcie_ops = {
624 .read_config = fsl_pcie_read_config,
625 .write_config = fsl_pcie_write_config,
628 static struct fsl_pcie_data p1_p2_data = {
629 .block_offset = 0xa000,
630 .block_offset_mask = 0xffff,
634 static struct fsl_pcie_data p2041_data = {
635 .block_offset = 0x200000,
636 .block_offset_mask = 0x3fffff,
640 static struct fsl_pcie_data t2080_data = {
641 .block_offset = 0x240000,
642 .block_offset_mask = 0x3fffff,
646 static const struct udevice_id fsl_pcie_ids[] = {
647 { .compatible = "fsl,pcie-mpc8548", .data = (ulong)&p1_p2_data },
648 { .compatible = "fsl,pcie-p1_p2", .data = (ulong)&p1_p2_data },
649 { .compatible = "fsl,pcie-p2041", .data = (ulong)&p2041_data },
650 { .compatible = "fsl,pcie-p3041", .data = (ulong)&p2041_data },
651 { .compatible = "fsl,pcie-p4080", .data = (ulong)&p2041_data },
652 { .compatible = "fsl,pcie-p5040", .data = (ulong)&p2041_data },
653 { .compatible = "fsl,pcie-t102x", .data = (ulong)&t2080_data },
654 { .compatible = "fsl,pcie-t104x", .data = (ulong)&t2080_data },
655 { .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data },
656 { .compatible = "fsl,pcie-t4240", .data = (ulong)&t2080_data },
660 U_BOOT_DRIVER(fsl_pcie) = {
663 .of_match = fsl_pcie_ids,
664 .ops = &fsl_pcie_ops,
665 .of_to_plat = fsl_pcie_of_to_plat,
666 .probe = fsl_pcie_probe,
667 .priv_auto = sizeof(struct fsl_pcie),