1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe driver for Marvell MVEBU SoCs
5 * Based on Barebox drivers/pci/pci-mvebu.c
8 * Anton Schubert <anton.schubert@gmx.de>
9 * Stefan Roese <sr@denx.de>
16 #include <dm/device-internal.h>
18 #include <dm/of_access.h>
21 #include <asm/arch/cpu.h>
22 #include <asm/arch/soc.h>
23 #include <linux/bitops.h>
24 #include <linux/errno.h>
25 #include <linux/ioport.h>
26 #include <linux/mbus.h>
28 DECLARE_GLOBAL_DATA_PTR;
30 /* PCIe unit register offsets */
31 #define SELECT(x, n) ((x >> n) & 1UL)
33 #define PCIE_DEV_ID_OFF 0x0000
34 #define PCIE_CMD_OFF 0x0004
35 #define PCIE_DEV_REV_OFF 0x0008
36 #define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3))
37 #define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3))
38 #define PCIE_CAPAB_OFF 0x0060
39 #define PCIE_CTRL_STAT_OFF 0x0068
40 #define PCIE_HEADER_LOG_4_OFF 0x0128
41 #define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4))
42 #define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4))
43 #define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4))
44 #define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4))
45 #define PCIE_WIN5_CTRL_OFF 0x1880
46 #define PCIE_WIN5_BASE_OFF 0x1884
47 #define PCIE_WIN5_REMAP_OFF 0x188c
48 #define PCIE_CONF_ADDR_OFF 0x18f8
49 #define PCIE_CONF_ADDR_EN BIT(31)
50 #define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc))
51 #define PCIE_CONF_BUS(b) (((b) & 0xff) << 16)
52 #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11)
53 #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8)
54 #define PCIE_CONF_ADDR(dev, reg) \
55 (PCIE_CONF_BUS(PCI_BUS(dev)) | PCIE_CONF_DEV(PCI_DEV(dev)) | \
56 PCIE_CONF_FUNC(PCI_FUNC(dev)) | PCIE_CONF_REG(reg) | \
58 #define PCIE_CONF_DATA_OFF 0x18fc
59 #define PCIE_MASK_OFF 0x1910
60 #define PCIE_MASK_ENABLE_INTS (0xf << 24)
61 #define PCIE_CTRL_OFF 0x1a00
62 #define PCIE_CTRL_X1_MODE BIT(0)
63 #define PCIE_STAT_OFF 0x1a04
64 #define PCIE_STAT_BUS (0xff << 8)
65 #define PCIE_STAT_DEV (0x1f << 16)
66 #define PCIE_STAT_LINK_DOWN BIT(0)
67 #define PCIE_DEBUG_CTRL 0x1a60
68 #define PCIE_DEBUG_SOFT_RESET BIT(20)
71 struct pci_controller hose;
73 void __iomem *membase;
83 unsigned int mem_target;
84 unsigned int mem_attr;
85 unsigned int io_target;
90 * MVEBU PCIe controller needs MEMORY and I/O BARs to be mapped
91 * into SoCs address space. Each controller will map 128M of MEM
92 * and 64K of I/O space when registered.
94 static void __iomem *mvebu_pcie_membase = (void __iomem *)MBUS_PCI_MEM_BASE;
95 #define PCIE_MEM_SIZE (128 << 20)
96 static void __iomem *mvebu_pcie_iobase = (void __iomem *)MBUS_PCI_IO_BASE;
98 static inline bool mvebu_pcie_link_up(struct mvebu_pcie *pcie)
101 val = readl(pcie->base + PCIE_STAT_OFF);
102 return !(val & PCIE_STAT_LINK_DOWN);
105 static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie *pcie, int busno)
109 stat = readl(pcie->base + PCIE_STAT_OFF);
110 stat &= ~PCIE_STAT_BUS;
112 writel(stat, pcie->base + PCIE_STAT_OFF);
115 static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie *pcie, int devno)
119 stat = readl(pcie->base + PCIE_STAT_OFF);
120 stat &= ~PCIE_STAT_DEV;
122 writel(stat, pcie->base + PCIE_STAT_OFF);
125 static int mvebu_pcie_get_local_bus_nr(struct mvebu_pcie *pcie)
129 stat = readl(pcie->base + PCIE_STAT_OFF);
130 return (stat & PCIE_STAT_BUS) >> 8;
133 static int mvebu_pcie_get_local_dev_nr(struct mvebu_pcie *pcie)
137 stat = readl(pcie->base + PCIE_STAT_OFF);
138 return (stat & PCIE_STAT_DEV) >> 16;
141 static inline struct mvebu_pcie *hose_to_pcie(struct pci_controller *hose)
143 return container_of(hose, struct mvebu_pcie, hose);
146 static int mvebu_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
147 uint offset, ulong *valuep,
148 enum pci_size_t size)
150 struct mvebu_pcie *pcie = dev_get_plat(bus);
151 int local_bus = PCI_BUS(pcie->dev);
152 int local_dev = PCI_DEV(pcie->dev);
156 debug("PCIE CFG read: (b,d,f)=(%2d,%2d,%2d) ",
157 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
159 /* Only allow one other device besides the local one on the local bus */
160 if (PCI_BUS(bdf) == local_bus && PCI_DEV(bdf) != local_dev) {
161 if (local_dev == 0 && PCI_DEV(bdf) != 1) {
162 debug("- out of range\n");
164 * If local dev is 0, the first other dev can
167 *valuep = pci_get_ff(size);
169 } else if (local_dev != 0 && PCI_DEV(bdf) != 0) {
170 debug("- out of range\n");
172 * If local dev is not 0, the first other dev can
175 *valuep = pci_get_ff(size);
181 reg = PCIE_CONF_ADDR(bdf, offset);
182 writel(reg, pcie->base + PCIE_CONF_ADDR_OFF);
183 data = readl(pcie->base + PCIE_CONF_DATA_OFF);
184 debug("(addr,val)=(0x%04x, 0x%08x)\n", offset, data);
185 *valuep = pci_conv_32_to_size(data, offset, size);
190 static int mvebu_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
191 uint offset, ulong value,
192 enum pci_size_t size)
194 struct mvebu_pcie *pcie = dev_get_plat(bus);
195 int local_bus = PCI_BUS(pcie->dev);
196 int local_dev = PCI_DEV(pcie->dev);
199 debug("PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ",
200 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
201 debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value);
203 /* Only allow one other device besides the local one on the local bus */
204 if (PCI_BUS(bdf) == local_bus && PCI_DEV(bdf) != local_dev) {
205 if (local_dev == 0 && PCI_DEV(bdf) != 1) {
207 * If local dev is 0, the first other dev can
211 } else if (local_dev != 0 && PCI_DEV(bdf) != 0) {
213 * If local dev is not 0, the first other dev can
220 writel(PCIE_CONF_ADDR(bdf, offset), pcie->base + PCIE_CONF_ADDR_OFF);
221 data = pci_conv_size_to_32(0, value, offset, size);
222 writel(data, pcie->base + PCIE_CONF_DATA_OFF);
228 * Setup PCIE BARs and Address Decode Wins:
229 * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
230 * WIN[0-3] -> DRAM bank[0-3]
232 static void mvebu_pcie_setup_wins(struct mvebu_pcie *pcie)
234 const struct mbus_dram_target_info *dram = mvebu_mbus_dram_info();
238 /* First, disable and clear BARs and windows. */
239 for (i = 1; i < 3; i++) {
240 writel(0, pcie->base + PCIE_BAR_CTRL_OFF(i));
241 writel(0, pcie->base + PCIE_BAR_LO_OFF(i));
242 writel(0, pcie->base + PCIE_BAR_HI_OFF(i));
245 for (i = 0; i < 5; i++) {
246 writel(0, pcie->base + PCIE_WIN04_CTRL_OFF(i));
247 writel(0, pcie->base + PCIE_WIN04_BASE_OFF(i));
248 writel(0, pcie->base + PCIE_WIN04_REMAP_OFF(i));
251 writel(0, pcie->base + PCIE_WIN5_CTRL_OFF);
252 writel(0, pcie->base + PCIE_WIN5_BASE_OFF);
253 writel(0, pcie->base + PCIE_WIN5_REMAP_OFF);
255 /* Setup windows for DDR banks. Count total DDR size on the fly. */
257 for (i = 0; i < dram->num_cs; i++) {
258 const struct mbus_dram_window *cs = dram->cs + i;
260 writel(cs->base & 0xffff0000,
261 pcie->base + PCIE_WIN04_BASE_OFF(i));
262 writel(0, pcie->base + PCIE_WIN04_REMAP_OFF(i));
263 writel(((cs->size - 1) & 0xffff0000) |
264 (cs->mbus_attr << 8) |
265 (dram->mbus_dram_target_id << 4) | 1,
266 pcie->base + PCIE_WIN04_CTRL_OFF(i));
271 /* Round up 'size' to the nearest power of two. */
272 if ((size & (size - 1)) != 0)
273 size = 1 << fls(size);
275 /* Setup BAR[1] to all DRAM banks. */
276 writel(dram->cs[0].base | 0xc, pcie->base + PCIE_BAR_LO_OFF(1));
277 writel(0, pcie->base + PCIE_BAR_HI_OFF(1));
278 writel(((size - 1) & 0xffff0000) | 0x1,
279 pcie->base + PCIE_BAR_CTRL_OFF(1));
282 static int mvebu_pcie_probe(struct udevice *dev)
284 struct mvebu_pcie *pcie = dev_get_plat(dev);
285 struct udevice *ctlr = pci_get_controller(dev);
286 struct pci_controller *hose = dev_get_uclass_priv(ctlr);
290 debug("%s: PCIe %d.%d - up, base %08x\n", __func__,
291 pcie->port, pcie->lane, (u32)pcie->base);
293 /* Read Id info and local bus/dev */
294 debug("direct conf read %08x, local bus %d, local dev %d\n",
295 readl(pcie->base), mvebu_pcie_get_local_bus_nr(pcie),
296 mvebu_pcie_get_local_dev_nr(pcie));
298 mvebu_pcie_set_local_bus_nr(pcie, bus);
299 mvebu_pcie_set_local_dev_nr(pcie, 0);
300 pcie->dev = PCI_BDF(bus, 0, 0);
302 pcie->mem.start = (u32)mvebu_pcie_membase;
303 pcie->mem.end = pcie->mem.start + PCIE_MEM_SIZE - 1;
304 mvebu_pcie_membase += PCIE_MEM_SIZE;
306 if (mvebu_mbus_add_window_by_id(pcie->mem_target, pcie->mem_attr,
307 (phys_addr_t)pcie->mem.start,
309 printf("PCIe unable to add mbus window for mem at %08x+%08x\n",
310 (u32)pcie->mem.start, PCIE_MEM_SIZE);
313 pcie->io.start = (u32)mvebu_pcie_iobase;
314 pcie->io.end = pcie->io.start + MBUS_PCI_IO_SIZE - 1;
315 mvebu_pcie_iobase += MBUS_PCI_IO_SIZE;
317 if (mvebu_mbus_add_window_by_id(pcie->io_target, pcie->io_attr,
318 (phys_addr_t)pcie->io.start,
320 printf("PCIe unable to add mbus window for IO at %08x+%08x\n",
321 (u32)pcie->io.start, MBUS_PCI_IO_SIZE);
324 /* Setup windows and configure host bridge */
325 mvebu_pcie_setup_wins(pcie);
327 /* Master + slave enable. */
328 reg = readl(pcie->base + PCIE_CMD_OFF);
329 reg |= PCI_COMMAND_MEMORY;
330 reg |= PCI_COMMAND_IO;
331 reg |= PCI_COMMAND_MASTER;
332 reg |= BIT(10); /* disable interrupts */
333 writel(reg, pcie->base + PCIE_CMD_OFF);
335 /* PCI memory space */
336 pci_set_region(hose->regions + 0, pcie->mem.start,
337 pcie->mem.start, PCIE_MEM_SIZE, PCI_REGION_MEM);
338 pci_set_region(hose->regions + 1,
341 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
342 pci_set_region(hose->regions + 2, pcie->io.start,
343 pcie->io.start, MBUS_PCI_IO_SIZE, PCI_REGION_IO);
344 hose->region_count = 3;
346 /* Set BAR0 to internal registers */
347 writel(SOC_REGS_PHY_BASE, pcie->base + PCIE_BAR_LO_OFF(0));
348 writel(0, pcie->base + PCIE_BAR_HI_OFF(0));
355 static int mvebu_pcie_port_parse_dt(ofnode node, struct mvebu_pcie *pcie)
360 addr = ofnode_get_property(node, "assigned-addresses", &len);
362 pr_err("property \"assigned-addresses\" not found");
363 return -FDT_ERR_NOTFOUND;
366 pcie->base = (void *)(fdt32_to_cpu(addr[2]) + SOC_REGS_PHY_BASE);
371 #define DT_FLAGS_TO_TYPE(flags) (((flags) >> 24) & 0x03)
372 #define DT_TYPE_IO 0x1
373 #define DT_TYPE_MEM32 0x2
374 #define DT_CPUADDR_TO_TARGET(cpuaddr) (((cpuaddr) >> 56) & 0xFF)
375 #define DT_CPUADDR_TO_ATTR(cpuaddr) (((cpuaddr) >> 48) & 0xFF)
377 static int mvebu_get_tgt_attr(ofnode node, int devfn,
382 const int na = 3, ns = 2;
384 int rlen, nranges, rangesz, pna, i;
389 range = ofnode_get_property(node, "ranges", &rlen);
394 * Linux uses of_n_addr_cells() to get the number of address cells
395 * here. Currently this function is only available in U-Boot when
396 * CONFIG_OF_LIVE is enabled. Until this is enabled for MVEBU in
397 * general, lets't hardcode the "pna" value in the U-Boot code.
399 pna = 2; /* hardcoded for now because of lack of of_n_addr_cells() */
400 rangesz = pna + na + ns;
401 nranges = rlen / sizeof(__be32) / rangesz;
403 for (i = 0; i < nranges; i++, range += rangesz) {
404 u32 flags = of_read_number(range, 1);
405 u32 slot = of_read_number(range + 1, 1);
406 u64 cpuaddr = of_read_number(range + na, pna);
409 if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_IO)
410 rtype = IORESOURCE_IO;
411 else if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_MEM32)
412 rtype = IORESOURCE_MEM;
417 * The Linux code used PCI_SLOT() here, which expects devfn
418 * in bits 7..0. PCI_DEV() in U-Boot is similar to PCI_SLOT(),
419 * only expects devfn in 15..8, where its saved in this driver.
421 if (slot == PCI_DEV(devfn) && type == rtype) {
422 *tgt = DT_CPUADDR_TO_TARGET(cpuaddr);
423 *attr = DT_CPUADDR_TO_ATTR(cpuaddr);
431 static int mvebu_pcie_of_to_plat(struct udevice *dev)
433 struct mvebu_pcie *pcie = dev_get_plat(dev);
436 /* Get port number, lane number and memory target / attr */
437 if (ofnode_read_u32(dev_ofnode(dev), "marvell,pcie-port",
443 if (ofnode_read_u32(dev_ofnode(dev), "marvell,pcie-lane", &pcie->lane))
446 sprintf(pcie->name, "pcie%d.%d", pcie->port, pcie->lane);
448 /* pci_get_devfn() returns devfn in bits 15..8, see PCI_DEV usage */
449 pcie->devfn = pci_get_devfn(dev);
450 if (pcie->devfn < 0) {
455 ret = mvebu_get_tgt_attr(dev_ofnode(dev->parent), pcie->devfn,
457 &pcie->mem_target, &pcie->mem_attr);
459 printf("%s: cannot get tgt/attr for mem window\n", pcie->name);
463 ret = mvebu_get_tgt_attr(dev_ofnode(dev->parent), pcie->devfn,
465 &pcie->io_target, &pcie->io_attr);
467 printf("%s: cannot get tgt/attr for IO window\n", pcie->name);
471 /* Parse PCIe controller register base from DT */
472 ret = mvebu_pcie_port_parse_dt(dev_ofnode(dev), pcie);
476 /* Check link and skip ports that have no link */
477 if (!mvebu_pcie_link_up(pcie)) {
478 debug("%s: %s - down\n", __func__, pcie->name);
489 static const struct dm_pci_ops mvebu_pcie_ops = {
490 .read_config = mvebu_pcie_read_config,
491 .write_config = mvebu_pcie_write_config,
494 static struct driver pcie_mvebu_drv = {
495 .name = "pcie_mvebu",
497 .ops = &mvebu_pcie_ops,
498 .probe = mvebu_pcie_probe,
499 .of_to_plat = mvebu_pcie_of_to_plat,
500 .plat_auto = sizeof(struct mvebu_pcie),
504 * Use a MISC device to bind the n instances (child nodes) of the
505 * PCIe base controller in UCLASS_PCI.
507 static int mvebu_pcie_bind(struct udevice *parent)
509 struct mvebu_pcie *pcie;
510 struct uclass_driver *drv;
514 /* Lookup eth driver */
515 drv = lists_uclass_lookup(UCLASS_PCI);
517 puts("Cannot find PCI driver\n");
521 ofnode_for_each_subnode(subnode, dev_ofnode(parent)) {
522 if (!ofnode_is_available(subnode))
525 pcie = calloc(1, sizeof(*pcie));
529 /* Create child device UCLASS_PCI and bind it */
530 device_bind(parent, &pcie_mvebu_drv, pcie->name, pcie, subnode,
537 static const struct udevice_id mvebu_pcie_ids[] = {
538 { .compatible = "marvell,armada-xp-pcie" },
539 { .compatible = "marvell,armada-370-pcie" },
543 U_BOOT_DRIVER(pcie_mvebu_base) = {
544 .name = "pcie_mvebu_base",
546 .of_match = mvebu_pcie_ids,
547 .bind = mvebu_pcie_bind,