1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe driver for Marvell MVEBU SoCs
5 * Based on Barebox drivers/pci/pci-mvebu.c
8 * Anton Schubert <anton.schubert@gmx.de>
9 * Stefan Roese <sr@denx.de>
16 #include <asm/global_data.h>
17 #include <dm/device-internal.h>
19 #include <dm/of_access.h>
22 #include <asm/arch/cpu.h>
23 #include <asm/arch/soc.h>
24 #include <linux/bitops.h>
25 #include <linux/errno.h>
26 #include <linux/ioport.h>
27 #include <linux/mbus.h>
29 DECLARE_GLOBAL_DATA_PTR;
31 /* PCIe unit register offsets */
32 #define SELECT(x, n) ((x >> n) & 1UL)
34 #define PCIE_DEV_ID_OFF 0x0000
35 #define PCIE_CMD_OFF 0x0004
36 #define PCIE_DEV_REV_OFF 0x0008
37 #define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3))
38 #define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3))
39 #define PCIE_CAPAB_OFF 0x0060
40 #define PCIE_CTRL_STAT_OFF 0x0068
41 #define PCIE_HEADER_LOG_4_OFF 0x0128
42 #define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4))
43 #define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4))
44 #define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4))
45 #define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4))
46 #define PCIE_WIN5_CTRL_OFF 0x1880
47 #define PCIE_WIN5_BASE_OFF 0x1884
48 #define PCIE_WIN5_REMAP_OFF 0x188c
49 #define PCIE_CONF_ADDR_OFF 0x18f8
50 #define PCIE_CONF_ADDR_EN BIT(31)
51 #define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc))
52 #define PCIE_CONF_BUS(b) (((b) & 0xff) << 16)
53 #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11)
54 #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8)
55 #define PCIE_CONF_ADDR(dev, reg) \
56 (PCIE_CONF_BUS(PCI_BUS(dev)) | PCIE_CONF_DEV(PCI_DEV(dev)) | \
57 PCIE_CONF_FUNC(PCI_FUNC(dev)) | PCIE_CONF_REG(reg) | \
59 #define PCIE_CONF_DATA_OFF 0x18fc
60 #define PCIE_MASK_OFF 0x1910
61 #define PCIE_MASK_ENABLE_INTS (0xf << 24)
62 #define PCIE_CTRL_OFF 0x1a00
63 #define PCIE_CTRL_X1_MODE BIT(0)
64 #define PCIE_STAT_OFF 0x1a04
65 #define PCIE_STAT_BUS (0xff << 8)
66 #define PCIE_STAT_DEV (0x1f << 16)
67 #define PCIE_STAT_LINK_DOWN BIT(0)
68 #define PCIE_DEBUG_CTRL 0x1a60
69 #define PCIE_DEBUG_SOFT_RESET BIT(20)
72 struct pci_controller hose;
74 void __iomem *membase;
84 unsigned int mem_target;
85 unsigned int mem_attr;
86 unsigned int io_target;
91 * MVEBU PCIe controller needs MEMORY and I/O BARs to be mapped
92 * into SoCs address space. Each controller will map 128M of MEM
93 * and 64K of I/O space when registered.
95 static void __iomem *mvebu_pcie_membase = (void __iomem *)MBUS_PCI_MEM_BASE;
96 #define PCIE_MEM_SIZE (128 << 20)
97 static void __iomem *mvebu_pcie_iobase = (void __iomem *)MBUS_PCI_IO_BASE;
99 static inline bool mvebu_pcie_link_up(struct mvebu_pcie *pcie)
102 val = readl(pcie->base + PCIE_STAT_OFF);
103 return !(val & PCIE_STAT_LINK_DOWN);
106 static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie *pcie, int busno)
110 stat = readl(pcie->base + PCIE_STAT_OFF);
111 stat &= ~PCIE_STAT_BUS;
113 writel(stat, pcie->base + PCIE_STAT_OFF);
116 static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie *pcie, int devno)
120 stat = readl(pcie->base + PCIE_STAT_OFF);
121 stat &= ~PCIE_STAT_DEV;
123 writel(stat, pcie->base + PCIE_STAT_OFF);
126 static int mvebu_pcie_get_local_bus_nr(struct mvebu_pcie *pcie)
130 stat = readl(pcie->base + PCIE_STAT_OFF);
131 return (stat & PCIE_STAT_BUS) >> 8;
134 static int mvebu_pcie_get_local_dev_nr(struct mvebu_pcie *pcie)
138 stat = readl(pcie->base + PCIE_STAT_OFF);
139 return (stat & PCIE_STAT_DEV) >> 16;
142 static inline struct mvebu_pcie *hose_to_pcie(struct pci_controller *hose)
144 return container_of(hose, struct mvebu_pcie, hose);
147 static int mvebu_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
148 uint offset, ulong *valuep,
149 enum pci_size_t size)
151 struct mvebu_pcie *pcie = dev_get_plat(bus);
152 int local_bus = PCI_BUS(pcie->dev);
153 int local_dev = PCI_DEV(pcie->dev);
157 debug("PCIE CFG read: loc_bus=%d loc_dev=%d (b,d,f)=(%2d,%2d,%2d) ",
158 local_bus, local_dev, PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
160 /* Don't access the local host controller via this API */
161 if (PCI_BUS(bdf) == local_bus && PCI_DEV(bdf) == local_dev) {
162 debug("- skipping host controller\n");
163 *valuep = pci_get_ff(size);
167 /* If local dev is 0, the first other dev can only be 1 */
168 if (PCI_BUS(bdf) == local_bus && local_dev == 0 && PCI_DEV(bdf) != 1) {
169 debug("- out of range\n");
170 *valuep = pci_get_ff(size);
175 reg = PCIE_CONF_ADDR(bdf, offset);
176 writel(reg, pcie->base + PCIE_CONF_ADDR_OFF);
177 data = readl(pcie->base + PCIE_CONF_DATA_OFF);
178 debug("(addr,val)=(0x%04x, 0x%08x)\n", offset, data);
179 *valuep = pci_conv_32_to_size(data, offset, size);
184 static int mvebu_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
185 uint offset, ulong value,
186 enum pci_size_t size)
188 struct mvebu_pcie *pcie = dev_get_plat(bus);
189 int local_bus = PCI_BUS(pcie->dev);
190 int local_dev = PCI_DEV(pcie->dev);
193 debug("PCIE CFG write: loc_bus=%d loc_dev=%d (b,d,f)=(%2d,%2d,%2d) ",
194 local_bus, local_dev, PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
195 debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value);
197 /* Don't access the local host controller via this API */
198 if (PCI_BUS(bdf) == local_bus && PCI_DEV(bdf) == local_dev) {
199 debug("- skipping host controller\n");
203 /* If local dev is 0, the first other dev can only be 1 */
204 if (PCI_BUS(bdf) == local_bus && local_dev == 0 && PCI_DEV(bdf) != 1) {
205 debug("- out of range\n");
209 writel(PCIE_CONF_ADDR(bdf, offset), pcie->base + PCIE_CONF_ADDR_OFF);
210 data = pci_conv_size_to_32(0, value, offset, size);
211 writel(data, pcie->base + PCIE_CONF_DATA_OFF);
217 * Setup PCIE BARs and Address Decode Wins:
218 * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
219 * WIN[0-3] -> DRAM bank[0-3]
221 static void mvebu_pcie_setup_wins(struct mvebu_pcie *pcie)
223 const struct mbus_dram_target_info *dram = mvebu_mbus_dram_info();
227 /* First, disable and clear BARs and windows. */
228 for (i = 1; i < 3; i++) {
229 writel(0, pcie->base + PCIE_BAR_CTRL_OFF(i));
230 writel(0, pcie->base + PCIE_BAR_LO_OFF(i));
231 writel(0, pcie->base + PCIE_BAR_HI_OFF(i));
234 for (i = 0; i < 5; i++) {
235 writel(0, pcie->base + PCIE_WIN04_CTRL_OFF(i));
236 writel(0, pcie->base + PCIE_WIN04_BASE_OFF(i));
237 writel(0, pcie->base + PCIE_WIN04_REMAP_OFF(i));
240 writel(0, pcie->base + PCIE_WIN5_CTRL_OFF);
241 writel(0, pcie->base + PCIE_WIN5_BASE_OFF);
242 writel(0, pcie->base + PCIE_WIN5_REMAP_OFF);
244 /* Setup windows for DDR banks. Count total DDR size on the fly. */
246 for (i = 0; i < dram->num_cs; i++) {
247 const struct mbus_dram_window *cs = dram->cs + i;
249 writel(cs->base & 0xffff0000,
250 pcie->base + PCIE_WIN04_BASE_OFF(i));
251 writel(0, pcie->base + PCIE_WIN04_REMAP_OFF(i));
252 writel(((cs->size - 1) & 0xffff0000) |
253 (cs->mbus_attr << 8) |
254 (dram->mbus_dram_target_id << 4) | 1,
255 pcie->base + PCIE_WIN04_CTRL_OFF(i));
260 /* Round up 'size' to the nearest power of two. */
261 if ((size & (size - 1)) != 0)
262 size = 1 << fls(size);
264 /* Setup BAR[1] to all DRAM banks. */
265 writel(dram->cs[0].base | 0xc, pcie->base + PCIE_BAR_LO_OFF(1));
266 writel(0, pcie->base + PCIE_BAR_HI_OFF(1));
267 writel(((size - 1) & 0xffff0000) | 0x1,
268 pcie->base + PCIE_BAR_CTRL_OFF(1));
271 static int mvebu_pcie_probe(struct udevice *dev)
273 struct mvebu_pcie *pcie = dev_get_plat(dev);
274 struct udevice *ctlr = pci_get_controller(dev);
275 struct pci_controller *hose = dev_get_uclass_priv(ctlr);
279 debug("%s: PCIe %d.%d - up, base %08x\n", __func__,
280 pcie->port, pcie->lane, (u32)pcie->base);
282 /* Read Id info and local bus/dev */
283 debug("direct conf read %08x, local bus %d, local dev %d\n",
284 readl(pcie->base), mvebu_pcie_get_local_bus_nr(pcie),
285 mvebu_pcie_get_local_dev_nr(pcie));
287 mvebu_pcie_set_local_bus_nr(pcie, bus);
288 mvebu_pcie_set_local_dev_nr(pcie, 0);
289 pcie->dev = PCI_BDF(bus, 0, 0);
291 pcie->mem.start = (u32)mvebu_pcie_membase;
292 pcie->mem.end = pcie->mem.start + PCIE_MEM_SIZE - 1;
293 mvebu_pcie_membase += PCIE_MEM_SIZE;
295 if (mvebu_mbus_add_window_by_id(pcie->mem_target, pcie->mem_attr,
296 (phys_addr_t)pcie->mem.start,
298 printf("PCIe unable to add mbus window for mem at %08x+%08x\n",
299 (u32)pcie->mem.start, PCIE_MEM_SIZE);
302 pcie->io.start = (u32)mvebu_pcie_iobase;
303 pcie->io.end = pcie->io.start + MBUS_PCI_IO_SIZE - 1;
304 mvebu_pcie_iobase += MBUS_PCI_IO_SIZE;
306 if (mvebu_mbus_add_window_by_id(pcie->io_target, pcie->io_attr,
307 (phys_addr_t)pcie->io.start,
309 printf("PCIe unable to add mbus window for IO at %08x+%08x\n",
310 (u32)pcie->io.start, MBUS_PCI_IO_SIZE);
313 /* Setup windows and configure host bridge */
314 mvebu_pcie_setup_wins(pcie);
316 /* Master + slave enable. */
317 reg = readl(pcie->base + PCIE_CMD_OFF);
318 reg |= PCI_COMMAND_MEMORY;
319 reg |= PCI_COMMAND_IO;
320 reg |= PCI_COMMAND_MASTER;
321 reg |= BIT(10); /* disable interrupts */
322 writel(reg, pcie->base + PCIE_CMD_OFF);
324 /* PCI memory space */
325 pci_set_region(hose->regions + 0, pcie->mem.start,
326 pcie->mem.start, PCIE_MEM_SIZE, PCI_REGION_MEM);
327 pci_set_region(hose->regions + 1,
330 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
331 pci_set_region(hose->regions + 2, pcie->io.start,
332 pcie->io.start, MBUS_PCI_IO_SIZE, PCI_REGION_IO);
333 hose->region_count = 3;
335 /* Set BAR0 to internal registers */
336 writel(SOC_REGS_PHY_BASE, pcie->base + PCIE_BAR_LO_OFF(0));
337 writel(0, pcie->base + PCIE_BAR_HI_OFF(0));
344 static int mvebu_pcie_port_parse_dt(ofnode node, struct mvebu_pcie *pcie)
349 addr = ofnode_get_property(node, "assigned-addresses", &len);
351 pr_err("property \"assigned-addresses\" not found");
352 return -FDT_ERR_NOTFOUND;
355 pcie->base = (void *)(fdt32_to_cpu(addr[2]) + SOC_REGS_PHY_BASE);
360 #define DT_FLAGS_TO_TYPE(flags) (((flags) >> 24) & 0x03)
361 #define DT_TYPE_IO 0x1
362 #define DT_TYPE_MEM32 0x2
363 #define DT_CPUADDR_TO_TARGET(cpuaddr) (((cpuaddr) >> 56) & 0xFF)
364 #define DT_CPUADDR_TO_ATTR(cpuaddr) (((cpuaddr) >> 48) & 0xFF)
366 static int mvebu_get_tgt_attr(ofnode node, int devfn,
371 const int na = 3, ns = 2;
373 int rlen, nranges, rangesz, pna, i;
378 range = ofnode_get_property(node, "ranges", &rlen);
383 * Linux uses of_n_addr_cells() to get the number of address cells
384 * here. Currently this function is only available in U-Boot when
385 * CONFIG_OF_LIVE is enabled. Until this is enabled for MVEBU in
386 * general, lets't hardcode the "pna" value in the U-Boot code.
388 pna = 2; /* hardcoded for now because of lack of of_n_addr_cells() */
389 rangesz = pna + na + ns;
390 nranges = rlen / sizeof(__be32) / rangesz;
392 for (i = 0; i < nranges; i++, range += rangesz) {
393 u32 flags = of_read_number(range, 1);
394 u32 slot = of_read_number(range + 1, 1);
395 u64 cpuaddr = of_read_number(range + na, pna);
398 if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_IO)
399 rtype = IORESOURCE_IO;
400 else if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_MEM32)
401 rtype = IORESOURCE_MEM;
406 * The Linux code used PCI_SLOT() here, which expects devfn
407 * in bits 7..0. PCI_DEV() in U-Boot is similar to PCI_SLOT(),
408 * only expects devfn in 15..8, where its saved in this driver.
410 if (slot == PCI_DEV(devfn) && type == rtype) {
411 *tgt = DT_CPUADDR_TO_TARGET(cpuaddr);
412 *attr = DT_CPUADDR_TO_ATTR(cpuaddr);
420 static int mvebu_pcie_of_to_plat(struct udevice *dev)
422 struct mvebu_pcie *pcie = dev_get_plat(dev);
425 /* Get port number, lane number and memory target / attr */
426 if (ofnode_read_u32(dev_ofnode(dev), "marvell,pcie-port",
432 if (ofnode_read_u32(dev_ofnode(dev), "marvell,pcie-lane", &pcie->lane))
435 sprintf(pcie->name, "pcie%d.%d", pcie->port, pcie->lane);
437 /* pci_get_devfn() returns devfn in bits 15..8, see PCI_DEV usage */
438 pcie->devfn = pci_get_devfn(dev);
439 if (pcie->devfn < 0) {
444 ret = mvebu_get_tgt_attr(dev_ofnode(dev->parent), pcie->devfn,
446 &pcie->mem_target, &pcie->mem_attr);
448 printf("%s: cannot get tgt/attr for mem window\n", pcie->name);
452 ret = mvebu_get_tgt_attr(dev_ofnode(dev->parent), pcie->devfn,
454 &pcie->io_target, &pcie->io_attr);
456 printf("%s: cannot get tgt/attr for IO window\n", pcie->name);
460 /* Parse PCIe controller register base from DT */
461 ret = mvebu_pcie_port_parse_dt(dev_ofnode(dev), pcie);
465 /* Check link and skip ports that have no link */
466 if (!mvebu_pcie_link_up(pcie)) {
467 debug("%s: %s - down\n", __func__, pcie->name);
478 static const struct dm_pci_ops mvebu_pcie_ops = {
479 .read_config = mvebu_pcie_read_config,
480 .write_config = mvebu_pcie_write_config,
483 static struct driver pcie_mvebu_drv = {
484 .name = "pcie_mvebu",
486 .ops = &mvebu_pcie_ops,
487 .probe = mvebu_pcie_probe,
488 .of_to_plat = mvebu_pcie_of_to_plat,
489 .plat_auto = sizeof(struct mvebu_pcie),
493 * Use a MISC device to bind the n instances (child nodes) of the
494 * PCIe base controller in UCLASS_PCI.
496 static int mvebu_pcie_bind(struct udevice *parent)
498 struct mvebu_pcie *pcie;
499 struct uclass_driver *drv;
503 /* Lookup eth driver */
504 drv = lists_uclass_lookup(UCLASS_PCI);
506 puts("Cannot find PCI driver\n");
510 ofnode_for_each_subnode(subnode, dev_ofnode(parent)) {
511 if (!ofnode_is_available(subnode))
514 pcie = calloc(1, sizeof(*pcie));
518 /* Create child device UCLASS_PCI and bind it */
519 device_bind(parent, &pcie_mvebu_drv, pcie->name, pcie, subnode,
526 static const struct udevice_id mvebu_pcie_ids[] = {
527 { .compatible = "marvell,armada-xp-pcie" },
528 { .compatible = "marvell,armada-370-pcie" },
532 U_BOOT_DRIVER(pcie_mvebu_base) = {
533 .name = "pcie_mvebu_base",
535 .of_match = mvebu_pcie_ids,
536 .bind = mvebu_pcie_bind,