drivers/pci/pci_auto_old.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * PCI autoconfiguration library (legacy version, do not change)
   4  *
   5  * Author: Matt Porter <mporter@mvista.com>
   6  *
   7  * Copyright 2000 MontaVista Software Inc.
   8  */
   9
  10 #include <common.h>
  11 #include <errno.h>
  12 #include <log.h>
  13 #include <pci.h>
  14
  15 /*
  16  * Do not change this file. Instead, convert your board to use CONFIG_DM_PCI
  17  * and change pci_auto.c.
  18  */
  19
  20 /* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
  21 #ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
  22 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE  8
  23 #endif
  24
  25 /*
  26  *
  27  */
  28
  29 void pciauto_setup_device(struct pci_controller *hose,
  30                           pci_dev_t dev, int bars_num,
  31                           struct pci_region *mem,
  32                           struct pci_region *prefetch,
  33                           struct pci_region *io)
  34 {
  35         u32 bar_response;
  36         pci_size_t bar_size;
  37         u16 cmdstat = 0;
  38         int bar, bar_nr = 0;
  39         u8 header_type;
  40         int rom_addr;
  41         pci_addr_t bar_value;
  42         struct pci_region *bar_res;
  43         int found_mem64 = 0;
  44         u16 class;
  45
  46         pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
  47         cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER;
  48
  49         for (bar = PCI_BASE_ADDRESS_0;
  50                 bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) {
  51                 /* Tickle the BAR and get the response */
  52                 pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
  53                 pci_hose_read_config_dword(hose, dev, bar, &bar_response);
  54
  55                 /* If BAR is not implemented go to the next BAR */
  56                 if (!bar_response)
  57                         continue;
  58
  59                 found_mem64 = 0;
  60
  61                 /* Check the BAR type and set our address mask */
  62                 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
  63                         bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK))
  64                                    & 0xffff) + 1;
  65                         bar_res = io;
  66
  67                         debug("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ",
  68                               bar_nr, (unsigned long long)bar_size);
  69                 } else {
  70                         if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
  71                              PCI_BASE_ADDRESS_MEM_TYPE_64) {
  72                                 u32 bar_response_upper;
  73                                 u64 bar64;
  74
  75                                 pci_hose_write_config_dword(hose, dev, bar + 4,
  76                                         0xffffffff);
  77                                 pci_hose_read_config_dword(hose, dev, bar + 4,
  78                                         &bar_response_upper);
  79
  80                                 bar64 = ((u64)bar_response_upper << 32) | bar_response;
  81
  82                                 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
  83                                 found_mem64 = 1;
  84                         } else {
  85                                 bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
  86                         }
  87                         if (prefetch && (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH))
  88                                 bar_res = prefetch;
  89                         else
  90                                 bar_res = mem;
  91
  92                         debug("PCI Autoconfig: BAR %d, %s, size=0x%llx, ",
  93                               bar_nr, bar_res == prefetch ? "Prf" : "Mem",
  94                               (unsigned long long)bar_size);
  95                 }
  96
  97                 if (pciauto_region_allocate(bar_res, bar_size,
  98                                             &bar_value, found_mem64) == 0) {
  99                         /* Write it out and update our limit */
 100                         pci_hose_write_config_dword(hose, dev, bar, (u32)bar_value);
 101
 102                         if (found_mem64) {
 103                                 bar += 4;
 104 #ifdef CONFIG_SYS_PCI_64BIT
 105                                 pci_hose_write_config_dword(hose, dev, bar, (u32)(bar_value>>32));
 106 #else
 107                                 /*
 108                                  * If we are a 64-bit decoder then increment to the
 109                                  * upper 32 bits of the bar and force it to locate
 110                                  * in the lower 4GB of memory.
 111                                  */
 112                                 pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
 113 #endif
 114                         }
 115
 116                 }
 117                 cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
 118                         PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
 119
 120                 debug("\n");
 121
 122                 bar_nr++;
 123         }
 124
 125         /* Configure the expansion ROM address */
 126         pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
 127         header_type &= 0x7f;
 128         if (header_type != PCI_HEADER_TYPE_CARDBUS) {
 129                 rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ?
 130                            PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1;
 131                 pci_hose_write_config_dword(hose, dev, rom_addr, 0xfffffffe);
 132                 pci_hose_read_config_dword(hose, dev, rom_addr, &bar_response);
 133                 if (bar_response) {
 134                         bar_size = -(bar_response & ~1);
 135                         debug("PCI Autoconfig: ROM, size=%#x, ",
 136                               (unsigned int)bar_size);
 137                         if (pciauto_region_allocate(mem, bar_size,
 138                                                     &bar_value, false) == 0) {
 139                                 pci_hose_write_config_dword(hose, dev, rom_addr,
 140                                                             bar_value);
 141                         }
 142                         cmdstat |= PCI_COMMAND_MEMORY;
 143                         debug("\n");
 144                 }
 145         }
 146
 147         /* PCI_COMMAND_IO must be set for VGA device */
 148         pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
 149         if (class == PCI_CLASS_DISPLAY_VGA)
 150                 cmdstat |= PCI_COMMAND_IO;
 151
 152         pci_hose_write_config_word(hose, dev, PCI_COMMAND, cmdstat);
 153         pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE,
 154                 CONFIG_SYS_PCI_CACHE_LINE_SIZE);
 155         pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
 156 }
 157
 158 void pciauto_prescan_setup_bridge(struct pci_controller *hose,
 159                                          pci_dev_t dev, int sub_bus)
 160 {
 161         struct pci_region *pci_mem;
 162         struct pci_region *pci_prefetch;
 163         struct pci_region *pci_io;
 164         u16 cmdstat, prefechable_64;
 165
 166         pci_mem = hose->pci_mem;
 167         pci_prefetch = hose->pci_prefetch;
 168         pci_io = hose->pci_io;
 169
 170         pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
 171         pci_hose_read_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
 172                                 &prefechable_64);
 173         prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
 174
 175         /* Configure bus number registers */
 176         pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS,
 177                                    PCI_BUS(dev) - hose->first_busno);
 178         pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS,
 179                                    sub_bus - hose->first_busno);
 180         pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff);
 181
 182         if (pci_mem) {
 183                 /* Round memory allocator to 1MB boundary */
 184                 pciauto_region_align(pci_mem, 0x100000);
 185
 186                 /* Set up memory and I/O filter limits, assume 32-bit I/O space */
 187                 pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE,
 188                                         (pci_mem->bus_lower & 0xfff00000) >> 16);
 189
 190                 cmdstat |= PCI_COMMAND_MEMORY;
 191         }
 192
 193         if (pci_prefetch) {
 194                 /* Round memory allocator to 1MB boundary */
 195                 pciauto_region_align(pci_prefetch, 0x100000);
 196
 197                 /* Set up memory and I/O filter limits, assume 32-bit I/O space */
 198                 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
 199                                         (pci_prefetch->bus_lower & 0xfff00000) >> 16);
 200                 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
 201 #ifdef CONFIG_SYS_PCI_64BIT
 202                         pci_hose_write_config_dword(hose, dev,
 203                                         PCI_PREF_BASE_UPPER32,
 204                                         pci_prefetch->bus_lower >> 32);
 205 #else
 206                         pci_hose_write_config_dword(hose, dev,
 207                                         PCI_PREF_BASE_UPPER32,
 208                                         0x0);
 209 #endif
 210
 211                 cmdstat |= PCI_COMMAND_MEMORY;
 212         } else {
 213                 /* We don't support prefetchable memory for now, so disable */
 214                 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
 215                 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0);
 216                 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) {
 217                         pci_hose_write_config_word(hose, dev, PCI_PREF_BASE_UPPER32, 0x0);
 218                         pci_hose_write_config_word(hose, dev, PCI_PREF_LIMIT_UPPER32, 0x0);
 219                 }
 220         }
 221
 222         if (pci_io) {
 223                 /* Round I/O allocator to 4KB boundary */
 224                 pciauto_region_align(pci_io, 0x1000);
 225
 226                 pci_hose_write_config_byte(hose, dev, PCI_IO_BASE,
 227                                         (pci_io->bus_lower & 0x0000f000) >> 8);
 228                 pci_hose_write_config_word(hose, dev, PCI_IO_BASE_UPPER16,
 229                                         (pci_io->bus_lower & 0xffff0000) >> 16);
 230
 231                 cmdstat |= PCI_COMMAND_IO;
 232         }
 233
 234         /* Enable memory and I/O accesses, enable bus master */
 235         pci_hose_write_config_word(hose, dev, PCI_COMMAND,
 236                                         cmdstat | PCI_COMMAND_MASTER);
 237 }
 238
 239 void pciauto_postscan_setup_bridge(struct pci_controller *hose,
 240                                           pci_dev_t dev, int sub_bus)
 241 {
 242         struct pci_region *pci_mem;
 243         struct pci_region *pci_prefetch;
 244         struct pci_region *pci_io;
 245
 246         pci_mem = hose->pci_mem;
 247         pci_prefetch = hose->pci_prefetch;
 248         pci_io = hose->pci_io;
 249
 250         /* Configure bus number registers */
 251         pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS,
 252                                    sub_bus - hose->first_busno);
 253
 254         if (pci_mem) {
 255                 /* Round memory allocator to 1MB boundary */
 256                 pciauto_region_align(pci_mem, 0x100000);
 257
 258                 pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT,
 259                                 (pci_mem->bus_lower - 1) >> 16);
 260         }
 261
 262         if (pci_prefetch) {
 263                 u16 prefechable_64;
 264
 265                 pci_hose_read_config_word(hose, dev,
 266                                         PCI_PREF_MEMORY_LIMIT,
 267                                         &prefechable_64);
 268                 prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
 269
 270                 /* Round memory allocator to 1MB boundary */
 271                 pciauto_region_align(pci_prefetch, 0x100000);
 272
 273                 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT,
 274                                 (pci_prefetch->bus_lower - 1) >> 16);
 275                 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
 276 #ifdef CONFIG_SYS_PCI_64BIT
 277                         pci_hose_write_config_dword(hose, dev,
 278                                         PCI_PREF_LIMIT_UPPER32,
 279                                         (pci_prefetch->bus_lower - 1) >> 32);
 280 #else
 281                         pci_hose_write_config_dword(hose, dev,
 282                                         PCI_PREF_LIMIT_UPPER32,
 283                                         0x0);
 284 #endif
 285         }
 286
 287         if (pci_io) {
 288                 /* Round I/O allocator to 4KB boundary */
 289                 pciauto_region_align(pci_io, 0x1000);
 290
 291                 pci_hose_write_config_byte(hose, dev, PCI_IO_LIMIT,
 292                                 ((pci_io->bus_lower - 1) & 0x0000f000) >> 8);
 293                 pci_hose_write_config_word(hose, dev, PCI_IO_LIMIT_UPPER16,
 294                                 ((pci_io->bus_lower - 1) & 0xffff0000) >> 16);
 295         }
 296 }
 297
 298
 299 /*
 300  * HJF: Changed this to return int. I think this is required
 301  * to get the correct result when scanning bridges
 302  */
 303 int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
 304 {
 305         struct pci_region *pci_mem;
 306         struct pci_region *pci_prefetch;
 307         struct pci_region *pci_io;
 308         unsigned int sub_bus = PCI_BUS(dev);
 309         unsigned short class;
 310         int n;
 311
 312         pci_mem = hose->pci_mem;
 313         pci_prefetch = hose->pci_prefetch;
 314         pci_io = hose->pci_io;
 315
 316         pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
 317
 318         switch (class) {
 319         case PCI_CLASS_BRIDGE_PCI:
 320                 debug("PCI Autoconfig: Found P2P bridge, device %d\n",
 321                       PCI_DEV(dev));
 322
 323                 pciauto_setup_device(hose, dev, 2, pci_mem,
 324                                      pci_prefetch, pci_io);
 325
 326                 /* Passing in current_busno allows for sibling P2P bridges */
 327                 hose->current_busno++;
 328                 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
 329                 /*
 330                  * need to figure out if this is a subordinate bridge on the bus
 331                  * to be able to properly set the pri/sec/sub bridge registers.
 332                  */
 333                 n = pci_hose_scan_bus(hose, hose->current_busno);
 334
 335                 /* figure out the deepest we've gone for this leg */
 336                 sub_bus = max((unsigned int)n, sub_bus);
 337                 pciauto_postscan_setup_bridge(hose, dev, sub_bus);
 338
 339                 sub_bus = hose->current_busno;
 340                 break;
 341
 342         case PCI_CLASS_BRIDGE_CARDBUS:
 343                 /*
 344                  * just do a minimal setup of the bridge,
 345                  * let the OS take care of the rest
 346                  */
 347                 pciauto_setup_device(hose, dev, 0, pci_mem,
 348                                      pci_prefetch, pci_io);
 349
 350                 debug("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
 351                       PCI_DEV(dev));
 352
 353                 hose->current_busno++;
 354                 break;
 355
 356 #if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
 357         case PCI_CLASS_BRIDGE_OTHER:
 358                 debug("PCI Autoconfig: Skipping bridge device %d\n",
 359                       PCI_DEV(dev));
 360                 break;
 361 #endif
 362 #if defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_TARGET_VME8349) && \
 363                 !defined(CONFIG_TARGET_CADDY2)
 364         case PCI_CLASS_BRIDGE_OTHER:
 365                 /*
 366                  * The host/PCI bridge 1 seems broken in 8349 - it presents
 367                  * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
 368                  * device claiming resources io/mem/irq.. we only allow for
 369                  * the PIMMR window to be allocated (BAR0 - 1MB size)
 370                  */
 371                 debug("PCI Autoconfig: Broken bridge found, only minimal config\n");
 372                 pciauto_setup_device(hose, dev, 0, hose->pci_mem,
 373                         hose->pci_prefetch, hose->pci_io);
 374                 break;
 375 #endif
 376
 377         case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
 378                 debug("PCI AutoConfig: Found PowerPC device\n");
 379
 380         default:
 381                 pciauto_setup_device(hose, dev, 6, pci_mem,
 382                                      pci_prefetch, pci_io);
 383                 break;
 384         }
 385
 386         return sub_bus;
 387 }