2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/pci.h>
15 #include <linux/slab.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <linux/string.h>
19 #include <linux/log2.h>
20 #include <linux/pci-aspm.h>
21 #include <linux/pm_wakeup.h>
22 #include <linux/interrupt.h>
23 #include <linux/device.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/pci_hotplug.h>
26 #include <asm-generic/pci-bridge.h>
27 #include <asm/setup.h>
30 const char *pci_power_names[] = {
31 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
33 EXPORT_SYMBOL_GPL(pci_power_names);
35 int isa_dma_bridge_buggy;
36 EXPORT_SYMBOL(isa_dma_bridge_buggy);
39 EXPORT_SYMBOL(pci_pci_problems);
41 unsigned int pci_pm_d3_delay;
43 static void pci_pme_list_scan(struct work_struct *work);
45 static LIST_HEAD(pci_pme_list);
46 static DEFINE_MUTEX(pci_pme_list_mutex);
47 static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
49 struct pci_pme_device {
50 struct list_head list;
54 #define PME_TIMEOUT 1000 /* How long between PME checks */
56 static void pci_dev_d3_sleep(struct pci_dev *dev)
58 unsigned int delay = dev->d3_delay;
60 if (delay < pci_pm_d3_delay)
61 delay = pci_pm_d3_delay;
66 #ifdef CONFIG_PCI_DOMAINS
67 int pci_domains_supported = 1;
70 #define DEFAULT_CARDBUS_IO_SIZE (256)
71 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
72 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
73 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
74 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
76 #define DEFAULT_HOTPLUG_IO_SIZE (256)
77 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
78 /* pci=hpmemsize=nnM,hpiosize=nn can override this */
79 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
80 unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
82 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF;
85 * The default CLS is used if arch didn't set CLS explicitly and not
86 * all pci devices agree on the same value. Arch can override either
87 * the dfl or actual value as it sees fit. Don't forget this is
88 * measured in 32-bit words, not bytes.
90 u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2;
91 u8 pci_cache_line_size;
94 * If we set up a device for bus mastering, we need to check the latency
95 * timer as certain BIOSes forget to set it properly.
97 unsigned int pcibios_max_latency = 255;
99 /* If set, the PCIe ARI capability will not be used. */
100 static bool pcie_ari_disabled;
103 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
104 * @bus: pointer to PCI bus structure to search
106 * Given a PCI bus, returns the highest PCI bus number present in the set
107 * including the given PCI bus and its list of child PCI buses.
109 unsigned char pci_bus_max_busnr(struct pci_bus* bus)
111 struct list_head *tmp;
112 unsigned char max, n;
114 max = bus->busn_res.end;
115 list_for_each(tmp, &bus->children) {
116 n = pci_bus_max_busnr(pci_bus_b(tmp));
122 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
124 #ifdef CONFIG_HAS_IOMEM
125 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
128 * Make sure the BAR is actually a memory resource, not an IO resource
130 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
134 return ioremap_nocache(pci_resource_start(pdev, bar),
135 pci_resource_len(pdev, bar));
137 EXPORT_SYMBOL_GPL(pci_ioremap_bar);
140 #define PCI_FIND_CAP_TTL 48
142 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
143 u8 pos, int cap, int *ttl)
148 pci_bus_read_config_byte(bus, devfn, pos, &pos);
152 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
158 pos += PCI_CAP_LIST_NEXT;
163 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
166 int ttl = PCI_FIND_CAP_TTL;
168 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
171 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
173 return __pci_find_next_cap(dev->bus, dev->devfn,
174 pos + PCI_CAP_LIST_NEXT, cap);
176 EXPORT_SYMBOL_GPL(pci_find_next_capability);
178 static int __pci_bus_find_cap_start(struct pci_bus *bus,
179 unsigned int devfn, u8 hdr_type)
183 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
184 if (!(status & PCI_STATUS_CAP_LIST))
188 case PCI_HEADER_TYPE_NORMAL:
189 case PCI_HEADER_TYPE_BRIDGE:
190 return PCI_CAPABILITY_LIST;
191 case PCI_HEADER_TYPE_CARDBUS:
192 return PCI_CB_CAPABILITY_LIST;
201 * pci_find_capability - query for devices' capabilities
202 * @dev: PCI device to query
203 * @cap: capability code
205 * Tell if a device supports a given PCI capability.
206 * Returns the address of the requested capability structure within the
207 * device's PCI configuration space or 0 in case the device does not
208 * support it. Possible values for @cap:
210 * %PCI_CAP_ID_PM Power Management
211 * %PCI_CAP_ID_AGP Accelerated Graphics Port
212 * %PCI_CAP_ID_VPD Vital Product Data
213 * %PCI_CAP_ID_SLOTID Slot Identification
214 * %PCI_CAP_ID_MSI Message Signalled Interrupts
215 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
216 * %PCI_CAP_ID_PCIX PCI-X
217 * %PCI_CAP_ID_EXP PCI Express
219 int pci_find_capability(struct pci_dev *dev, int cap)
223 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
225 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
231 * pci_bus_find_capability - query for devices' capabilities
232 * @bus: the PCI bus to query
233 * @devfn: PCI device to query
234 * @cap: capability code
236 * Like pci_find_capability() but works for pci devices that do not have a
237 * pci_dev structure set up yet.
239 * Returns the address of the requested capability structure within the
240 * device's PCI configuration space or 0 in case the device does not
243 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
248 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
250 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
252 pos = __pci_find_next_cap(bus, devfn, pos, cap);
258 * pci_find_next_ext_capability - Find an extended capability
259 * @dev: PCI device to query
260 * @start: address at which to start looking (0 to start at beginning of list)
261 * @cap: capability code
263 * Returns the address of the next matching extended capability structure
264 * within the device's PCI configuration space or 0 if the device does
265 * not support it. Some capabilities can occur several times, e.g., the
266 * vendor-specific capability, and this provides a way to find them all.
268 int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap)
272 int pos = PCI_CFG_SPACE_SIZE;
274 /* minimum 8 bytes per capability */
275 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
277 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
283 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
287 * If we have no capabilities, this is indicated by cap ID,
288 * cap version and next pointer all being 0.
294 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
297 pos = PCI_EXT_CAP_NEXT(header);
298 if (pos < PCI_CFG_SPACE_SIZE)
301 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
307 EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
310 * pci_find_ext_capability - Find an extended capability
311 * @dev: PCI device to query
312 * @cap: capability code
314 * Returns the address of the requested extended capability structure
315 * within the device's PCI configuration space or 0 if the device does
316 * not support it. Possible values for @cap:
318 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
319 * %PCI_EXT_CAP_ID_VC Virtual Channel
320 * %PCI_EXT_CAP_ID_DSN Device Serial Number
321 * %PCI_EXT_CAP_ID_PWR Power Budgeting
323 int pci_find_ext_capability(struct pci_dev *dev, int cap)
325 return pci_find_next_ext_capability(dev, 0, cap);
327 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
329 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
331 int rc, ttl = PCI_FIND_CAP_TTL;
334 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
335 mask = HT_3BIT_CAP_MASK;
337 mask = HT_5BIT_CAP_MASK;
339 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
340 PCI_CAP_ID_HT, &ttl);
342 rc = pci_read_config_byte(dev, pos + 3, &cap);
343 if (rc != PCIBIOS_SUCCESSFUL)
346 if ((cap & mask) == ht_cap)
349 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
350 pos + PCI_CAP_LIST_NEXT,
351 PCI_CAP_ID_HT, &ttl);
357 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
358 * @dev: PCI device to query
359 * @pos: Position from which to continue searching
360 * @ht_cap: Hypertransport capability code
362 * To be used in conjunction with pci_find_ht_capability() to search for
363 * all capabilities matching @ht_cap. @pos should always be a value returned
364 * from pci_find_ht_capability().
366 * NB. To be 100% safe against broken PCI devices, the caller should take
367 * steps to avoid an infinite loop.
369 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
371 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
373 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
376 * pci_find_ht_capability - query a device's Hypertransport capabilities
377 * @dev: PCI device to query
378 * @ht_cap: Hypertransport capability code
380 * Tell if a device supports a given Hypertransport capability.
381 * Returns an address within the device's PCI configuration space
382 * or 0 in case the device does not support the request capability.
383 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
384 * which has a Hypertransport capability matching @ht_cap.
386 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
390 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
392 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
396 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
399 * pci_find_parent_resource - return resource region of parent bus of given region
400 * @dev: PCI device structure contains resources to be searched
401 * @res: child resource record for which parent is sought
403 * For given resource region of given device, return the resource
404 * region of parent bus the given region is contained in or where
405 * it should be allocated from.
408 pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
410 const struct pci_bus *bus = dev->bus;
412 struct resource *best = NULL, *r;
414 pci_bus_for_each_resource(bus, r, i) {
417 if (res->start && !(res->start >= r->start && res->end <= r->end))
418 continue; /* Not contained */
419 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
420 continue; /* Wrong type */
421 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
422 return r; /* Exact match */
423 /* We can't insert a non-prefetch resource inside a prefetchable parent .. */
424 if (r->flags & IORESOURCE_PREFETCH)
426 /* .. but we can put a prefetchable resource inside a non-prefetchable one */
434 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
435 * @dev: PCI device to have its BARs restored
437 * Restore the BAR values for a given device, so as to make it
438 * accessible by its driver.
441 pci_restore_bars(struct pci_dev *dev)
445 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
446 pci_update_resource(dev, i);
449 static struct pci_platform_pm_ops *pci_platform_pm;
451 int pci_set_platform_pm(struct pci_platform_pm_ops *ops)
453 if (!ops->is_manageable || !ops->set_state || !ops->choose_state
456 pci_platform_pm = ops;
460 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
462 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
465 static inline int platform_pci_set_power_state(struct pci_dev *dev,
468 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
471 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
473 return pci_platform_pm ?
474 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
477 static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
479 return pci_platform_pm ?
480 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
483 static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable)
485 return pci_platform_pm ?
486 pci_platform_pm->run_wake(dev, enable) : -ENODEV;
490 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
492 * @dev: PCI device to handle.
493 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
496 * -EINVAL if the requested state is invalid.
497 * -EIO if device does not support PCI PM or its PM capabilities register has a
498 * wrong version, or device doesn't support the requested state.
499 * 0 if device already is in the requested state.
500 * 0 if device's power state has been successfully changed.
502 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
505 bool need_restore = false;
507 /* Check if we're already there */
508 if (dev->current_state == state)
514 if (state < PCI_D0 || state > PCI_D3hot)
517 /* Validate current state:
518 * Can enter D0 from any state, but if we can only go deeper
519 * to sleep if we're already in a low power state
521 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
522 && dev->current_state > state) {
523 dev_err(&dev->dev, "invalid power transition "
524 "(from state %d to %d)\n", dev->current_state, state);
528 /* check if this device supports the desired state */
529 if ((state == PCI_D1 && !dev->d1_support)
530 || (state == PCI_D2 && !dev->d2_support))
533 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
535 /* If we're (effectively) in D3, force entire word to 0.
536 * This doesn't affect PME_Status, disables PME_En, and
537 * sets PowerState to 0.
539 switch (dev->current_state) {
543 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
548 case PCI_UNKNOWN: /* Boot-up */
549 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
550 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
552 /* Fall-through: force to D0 */
558 /* enter specified state */
559 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
561 /* Mandatory power management transition delays */
562 /* see PCI PM 1.1 5.6.1 table 18 */
563 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
564 pci_dev_d3_sleep(dev);
565 else if (state == PCI_D2 || dev->current_state == PCI_D2)
566 udelay(PCI_PM_D2_DELAY);
568 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
569 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
570 if (dev->current_state != state && printk_ratelimit())
571 dev_info(&dev->dev, "Refused to change power state, "
572 "currently in D%d\n", dev->current_state);
575 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
576 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
577 * from D3hot to D0 _may_ perform an internal reset, thereby
578 * going to "D0 Uninitialized" rather than "D0 Initialized".
579 * For example, at least some versions of the 3c905B and the
580 * 3c556B exhibit this behaviour.
582 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
583 * devices in a D3hot state at boot. Consequently, we need to
584 * restore at least the BARs so that the device will be
585 * accessible to its driver.
588 pci_restore_bars(dev);
591 pcie_aspm_pm_state_change(dev->bus->self);
597 * pci_update_current_state - Read PCI power state of given device from its
598 * PCI PM registers and cache it
599 * @dev: PCI device to handle.
600 * @state: State to cache in case the device doesn't have the PM capability
602 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
608 * Configuration space is not accessible for device in
609 * D3cold, so just keep or set D3cold for safety
611 if (dev->current_state == PCI_D3cold)
613 if (state == PCI_D3cold) {
614 dev->current_state = PCI_D3cold;
617 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
618 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
620 dev->current_state = state;
625 * pci_power_up - Put the given device into D0 forcibly
626 * @dev: PCI device to power up
628 void pci_power_up(struct pci_dev *dev)
630 if (platform_pci_power_manageable(dev))
631 platform_pci_set_power_state(dev, PCI_D0);
633 pci_raw_set_power_state(dev, PCI_D0);
634 pci_update_current_state(dev, PCI_D0);
638 * pci_platform_power_transition - Use platform to change device power state
639 * @dev: PCI device to handle.
640 * @state: State to put the device into.
642 static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
646 if (platform_pci_power_manageable(dev)) {
647 error = platform_pci_set_power_state(dev, state);
649 pci_update_current_state(dev, state);
653 if (error && !dev->pm_cap) /* Fall back to PCI_D0 */
654 dev->current_state = PCI_D0;
660 * __pci_start_power_transition - Start power transition of a PCI device
661 * @dev: PCI device to handle.
662 * @state: State to put the device into.
664 static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
666 if (state == PCI_D0) {
667 pci_platform_power_transition(dev, PCI_D0);
669 * Mandatory power management transition delays, see
670 * PCI Express Base Specification Revision 2.0 Section
671 * 6.6.1: Conventional Reset. Do not delay for
672 * devices powered on/off by corresponding bridge,
673 * because have already delayed for the bridge.
675 if (dev->runtime_d3cold) {
676 msleep(dev->d3cold_delay);
678 * When powering on a bridge from D3cold, the
679 * whole hierarchy may be powered on into
680 * D0uninitialized state, resume them to give
681 * them a chance to suspend again
683 pci_wakeup_bus(dev->subordinate);
689 * __pci_dev_set_current_state - Set current state of a PCI device
690 * @dev: Device to handle
691 * @data: pointer to state to be set
693 static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
695 pci_power_t state = *(pci_power_t *)data;
697 dev->current_state = state;
702 * __pci_bus_set_current_state - Walk given bus and set current state of devices
703 * @bus: Top bus of the subtree to walk.
704 * @state: state to be set
706 static void __pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
709 pci_walk_bus(bus, __pci_dev_set_current_state, &state);
713 * __pci_complete_power_transition - Complete power transition of a PCI device
714 * @dev: PCI device to handle.
715 * @state: State to put the device into.
717 * This function should not be called directly by device drivers.
719 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
725 ret = pci_platform_power_transition(dev, state);
726 /* Power off the bridge may power off the whole hierarchy */
727 if (!ret && state == PCI_D3cold)
728 __pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
731 EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
734 * pci_set_power_state - Set the power state of a PCI device
735 * @dev: PCI device to handle.
736 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
738 * Transition a device to a new power state, using the platform firmware and/or
739 * the device's PCI PM registers.
742 * -EINVAL if the requested state is invalid.
743 * -EIO if device does not support PCI PM or its PM capabilities register has a
744 * wrong version, or device doesn't support the requested state.
745 * 0 if device already is in the requested state.
746 * 0 if device's power state has been successfully changed.
748 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
752 /* bound the state we're entering */
753 if (state > PCI_D3cold)
755 else if (state < PCI_D0)
757 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
759 * If the device or the parent bridge do not support PCI PM,
760 * ignore the request if we're doing anything other than putting
761 * it into D0 (which would only happen on boot).
765 /* Check if we're already there */
766 if (dev->current_state == state)
769 __pci_start_power_transition(dev, state);
771 /* This device is quirked not to be put into D3, so
772 don't put it in D3 */
773 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
777 * To put device in D3cold, we put device into D3hot in native
778 * way, then put device into D3cold with platform ops
780 error = pci_raw_set_power_state(dev, state > PCI_D3hot ?
783 if (!__pci_complete_power_transition(dev, state))
786 * When aspm_policy is "powersave" this call ensures
787 * that ASPM is configured.
789 if (!error && dev->bus->self)
790 pcie_aspm_powersave_config_link(dev->bus->self);
796 * pci_choose_state - Choose the power state of a PCI device
797 * @dev: PCI device to be suspended
798 * @state: target sleep state for the whole system. This is the value
799 * that is passed to suspend() function.
801 * Returns PCI power state suitable for given device and given system
805 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
812 ret = platform_pci_choose_state(dev);
813 if (ret != PCI_POWER_ERROR)
816 switch (state.event) {
819 case PM_EVENT_FREEZE:
820 case PM_EVENT_PRETHAW:
821 /* REVISIT both freeze and pre-thaw "should" use D0 */
822 case PM_EVENT_SUSPEND:
823 case PM_EVENT_HIBERNATE:
826 dev_info(&dev->dev, "unrecognized suspend event %d\n",
833 EXPORT_SYMBOL(pci_choose_state);
835 #define PCI_EXP_SAVE_REGS 7
838 static struct pci_cap_saved_state *pci_find_saved_cap(
839 struct pci_dev *pci_dev, char cap)
841 struct pci_cap_saved_state *tmp;
843 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) {
844 if (tmp->cap.cap_nr == cap)
850 static int pci_save_pcie_state(struct pci_dev *dev)
853 struct pci_cap_saved_state *save_state;
856 if (!pci_is_pcie(dev))
859 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
861 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
865 cap = (u16 *)&save_state->cap.data[0];
866 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
867 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
868 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
869 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
870 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
871 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
872 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
877 static void pci_restore_pcie_state(struct pci_dev *dev)
880 struct pci_cap_saved_state *save_state;
883 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
887 cap = (u16 *)&save_state->cap.data[0];
888 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
889 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
890 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
891 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
892 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
893 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
894 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
898 static int pci_save_pcix_state(struct pci_dev *dev)
901 struct pci_cap_saved_state *save_state;
903 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
907 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
909 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
913 pci_read_config_word(dev, pos + PCI_X_CMD,
914 (u16 *)save_state->cap.data);
919 static void pci_restore_pcix_state(struct pci_dev *dev)
922 struct pci_cap_saved_state *save_state;
925 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
926 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
927 if (!save_state || pos <= 0)
929 cap = (u16 *)&save_state->cap.data[0];
931 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
936 * pci_save_state - save the PCI configuration space of a device before suspending
937 * @dev: - PCI device that we're dealing with
940 pci_save_state(struct pci_dev *dev)
943 /* XXX: 100% dword access ok here? */
944 for (i = 0; i < 16; i++)
945 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
946 dev->state_saved = true;
947 if ((i = pci_save_pcie_state(dev)) != 0)
949 if ((i = pci_save_pcix_state(dev)) != 0)
954 static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
955 u32 saved_val, int retry)
959 pci_read_config_dword(pdev, offset, &val);
960 if (val == saved_val)
964 dev_dbg(&pdev->dev, "restoring config space at offset "
965 "%#x (was %#x, writing %#x)\n", offset, val, saved_val);
966 pci_write_config_dword(pdev, offset, saved_val);
970 pci_read_config_dword(pdev, offset, &val);
971 if (val == saved_val)
978 static void pci_restore_config_space_range(struct pci_dev *pdev,
979 int start, int end, int retry)
983 for (index = end; index >= start; index--)
984 pci_restore_config_dword(pdev, 4 * index,
985 pdev->saved_config_space[index],
989 static void pci_restore_config_space(struct pci_dev *pdev)
991 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
992 pci_restore_config_space_range(pdev, 10, 15, 0);
993 /* Restore BARs before the command register. */
994 pci_restore_config_space_range(pdev, 4, 9, 10);
995 pci_restore_config_space_range(pdev, 0, 3, 0);
997 pci_restore_config_space_range(pdev, 0, 15, 0);
1002 * pci_restore_state - Restore the saved state of a PCI device
1003 * @dev: - PCI device that we're dealing with
1005 void pci_restore_state(struct pci_dev *dev)
1007 if (!dev->state_saved)
1010 /* PCI Express register must be restored first */
1011 pci_restore_pcie_state(dev);
1012 pci_restore_ats_state(dev);
1014 pci_restore_config_space(dev);
1016 pci_restore_pcix_state(dev);
1017 pci_restore_msi_state(dev);
1018 pci_restore_iov_state(dev);
1020 dev->state_saved = false;
1023 struct pci_saved_state {
1024 u32 config_space[16];
1025 struct pci_cap_saved_data cap[0];
1029 * pci_store_saved_state - Allocate and return an opaque struct containing
1030 * the device saved state.
1031 * @dev: PCI device that we're dealing with
1033 * Return NULL if no state or error.
1035 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
1037 struct pci_saved_state *state;
1038 struct pci_cap_saved_state *tmp;
1039 struct pci_cap_saved_data *cap;
1042 if (!dev->state_saved)
1045 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1047 hlist_for_each_entry(tmp, &dev->saved_cap_space, next)
1048 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1050 state = kzalloc(size, GFP_KERNEL);
1054 memcpy(state->config_space, dev->saved_config_space,
1055 sizeof(state->config_space));
1058 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) {
1059 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1060 memcpy(cap, &tmp->cap, len);
1061 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1063 /* Empty cap_save terminates list */
1067 EXPORT_SYMBOL_GPL(pci_store_saved_state);
1070 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1071 * @dev: PCI device that we're dealing with
1072 * @state: Saved state returned from pci_store_saved_state()
1074 int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state)
1076 struct pci_cap_saved_data *cap;
1078 dev->state_saved = false;
1083 memcpy(dev->saved_config_space, state->config_space,
1084 sizeof(state->config_space));
1088 struct pci_cap_saved_state *tmp;
1090 tmp = pci_find_saved_cap(dev, cap->cap_nr);
1091 if (!tmp || tmp->cap.size != cap->size)
1094 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1095 cap = (struct pci_cap_saved_data *)((u8 *)cap +
1096 sizeof(struct pci_cap_saved_data) + cap->size);
1099 dev->state_saved = true;
1102 EXPORT_SYMBOL_GPL(pci_load_saved_state);
1105 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1106 * and free the memory allocated for it.
1107 * @dev: PCI device that we're dealing with
1108 * @state: Pointer to saved state returned from pci_store_saved_state()
1110 int pci_load_and_free_saved_state(struct pci_dev *dev,
1111 struct pci_saved_state **state)
1113 int ret = pci_load_saved_state(dev, *state);
1118 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1120 static int do_pci_enable_device(struct pci_dev *dev, int bars)
1124 err = pci_set_power_state(dev, PCI_D0);
1125 if (err < 0 && err != -EIO)
1127 err = pcibios_enable_device(dev, bars);
1130 pci_fixup_device(pci_fixup_enable, dev);
1136 * pci_reenable_device - Resume abandoned device
1137 * @dev: PCI device to be resumed
1139 * Note this function is a backend of pci_default_resume and is not supposed
1140 * to be called by normal code, write proper resume handler and use it instead.
1142 int pci_reenable_device(struct pci_dev *dev)
1144 if (pci_is_enabled(dev))
1145 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1149 static void pci_enable_bridge(struct pci_dev *dev)
1151 struct pci_dev *bridge;
1154 bridge = pci_upstream_bridge(dev);
1156 pci_enable_bridge(bridge);
1158 if (pci_is_enabled(dev)) {
1159 if (!dev->is_busmaster)
1160 pci_set_master(dev);
1164 retval = pci_enable_device(dev);
1166 dev_err(&dev->dev, "Error enabling bridge (%d), continuing\n",
1168 pci_set_master(dev);
1171 static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
1173 struct pci_dev *bridge;
1178 * Power state could be unknown at this point, either due to a fresh
1179 * boot or a device removal call. So get the current power state
1180 * so that things like MSI message writing will behave as expected
1181 * (e.g. if the device really is in D0 at enable time).
1185 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1186 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1189 if (atomic_inc_return(&dev->enable_cnt) > 1)
1190 return 0; /* already enabled */
1192 bridge = pci_upstream_bridge(dev);
1194 pci_enable_bridge(bridge);
1196 /* only skip sriov related */
1197 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
1198 if (dev->resource[i].flags & flags)
1200 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
1201 if (dev->resource[i].flags & flags)
1204 err = do_pci_enable_device(dev, bars);
1206 atomic_dec(&dev->enable_cnt);
1211 * pci_enable_device_io - Initialize a device for use with IO space
1212 * @dev: PCI device to be initialized
1214 * Initialize device before it's used by a driver. Ask low-level code
1215 * to enable I/O resources. Wake up the device if it was suspended.
1216 * Beware, this function can fail.
1218 int pci_enable_device_io(struct pci_dev *dev)
1220 return pci_enable_device_flags(dev, IORESOURCE_IO);
1224 * pci_enable_device_mem - Initialize a device for use with Memory space
1225 * @dev: PCI device to be initialized
1227 * Initialize device before it's used by a driver. Ask low-level code
1228 * to enable Memory resources. Wake up the device if it was suspended.
1229 * Beware, this function can fail.
1231 int pci_enable_device_mem(struct pci_dev *dev)
1233 return pci_enable_device_flags(dev, IORESOURCE_MEM);
1237 * pci_enable_device - Initialize device before it's used by a driver.
1238 * @dev: PCI device to be initialized
1240 * Initialize device before it's used by a driver. Ask low-level code
1241 * to enable I/O and memory. Wake up the device if it was suspended.
1242 * Beware, this function can fail.
1244 * Note we don't actually enable the device many times if we call
1245 * this function repeatedly (we just increment the count).
1247 int pci_enable_device(struct pci_dev *dev)
1249 return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
1253 * Managed PCI resources. This manages device on/off, intx/msi/msix
1254 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1255 * there's no need to track it separately. pci_devres is initialized
1256 * when a device is enabled using managed PCI device enable interface.
1259 unsigned int enabled:1;
1260 unsigned int pinned:1;
1261 unsigned int orig_intx:1;
1262 unsigned int restore_intx:1;
1266 static void pcim_release(struct device *gendev, void *res)
1268 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
1269 struct pci_devres *this = res;
1272 if (dev->msi_enabled)
1273 pci_disable_msi(dev);
1274 if (dev->msix_enabled)
1275 pci_disable_msix(dev);
1277 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1278 if (this->region_mask & (1 << i))
1279 pci_release_region(dev, i);
1281 if (this->restore_intx)
1282 pci_intx(dev, this->orig_intx);
1284 if (this->enabled && !this->pinned)
1285 pci_disable_device(dev);
1288 static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
1290 struct pci_devres *dr, *new_dr;
1292 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1296 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1299 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1302 static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
1304 if (pci_is_managed(pdev))
1305 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1310 * pcim_enable_device - Managed pci_enable_device()
1311 * @pdev: PCI device to be initialized
1313 * Managed pci_enable_device().
1315 int pcim_enable_device(struct pci_dev *pdev)
1317 struct pci_devres *dr;
1320 dr = get_pci_dr(pdev);
1326 rc = pci_enable_device(pdev);
1328 pdev->is_managed = 1;
1335 * pcim_pin_device - Pin managed PCI device
1336 * @pdev: PCI device to pin
1338 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1339 * driver detach. @pdev must have been enabled with
1340 * pcim_enable_device().
1342 void pcim_pin_device(struct pci_dev *pdev)
1344 struct pci_devres *dr;
1346 dr = find_pci_dr(pdev);
1347 WARN_ON(!dr || !dr->enabled);
1353 * pcibios_add_device - provide arch specific hooks when adding device dev
1354 * @dev: the PCI device being added
1356 * Permits the platform to provide architecture specific functionality when
1357 * devices are added. This is the default implementation. Architecture
1358 * implementations can override this.
1360 int __weak pcibios_add_device (struct pci_dev *dev)
1366 * pcibios_release_device - provide arch specific hooks when releasing device dev
1367 * @dev: the PCI device being released
1369 * Permits the platform to provide architecture specific functionality when
1370 * devices are released. This is the default implementation. Architecture
1371 * implementations can override this.
1373 void __weak pcibios_release_device(struct pci_dev *dev) {}
1376 * pcibios_disable_device - disable arch specific PCI resources for device dev
1377 * @dev: the PCI device to disable
1379 * Disables architecture specific PCI resources for the device. This
1380 * is the default implementation. Architecture implementations can
1383 void __weak pcibios_disable_device (struct pci_dev *dev) {}
1385 static void do_pci_disable_device(struct pci_dev *dev)
1389 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1390 if (pci_command & PCI_COMMAND_MASTER) {
1391 pci_command &= ~PCI_COMMAND_MASTER;
1392 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1395 pcibios_disable_device(dev);
1399 * pci_disable_enabled_device - Disable device without updating enable_cnt
1400 * @dev: PCI device to disable
1402 * NOTE: This function is a backend of PCI power management routines and is
1403 * not supposed to be called drivers.
1405 void pci_disable_enabled_device(struct pci_dev *dev)
1407 if (pci_is_enabled(dev))
1408 do_pci_disable_device(dev);
1412 * pci_disable_device - Disable PCI device after use
1413 * @dev: PCI device to be disabled
1415 * Signal to the system that the PCI device is not in use by the system
1416 * anymore. This only involves disabling PCI bus-mastering, if active.
1418 * Note we don't actually disable the device until all callers of
1419 * pci_enable_device() have called pci_disable_device().
1422 pci_disable_device(struct pci_dev *dev)
1424 struct pci_devres *dr;
1426 dr = find_pci_dr(dev);
1430 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0,
1431 "disabling already-disabled device");
1433 if (atomic_dec_return(&dev->enable_cnt) != 0)
1436 do_pci_disable_device(dev);
1438 dev->is_busmaster = 0;
1442 * pcibios_set_pcie_reset_state - set reset state for device dev
1443 * @dev: the PCIe device reset
1444 * @state: Reset state to enter into
1447 * Sets the PCIe reset state for the device. This is the default
1448 * implementation. Architecture implementations can override this.
1450 int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
1451 enum pcie_reset_state state)
1457 * pci_set_pcie_reset_state - set reset state for device dev
1458 * @dev: the PCIe device reset
1459 * @state: Reset state to enter into
1462 * Sets the PCI reset state for the device.
1464 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1466 return pcibios_set_pcie_reset_state(dev, state);
1470 * pci_check_pme_status - Check if given device has generated PME.
1471 * @dev: Device to check.
1473 * Check the PME status of the device and if set, clear it and clear PME enable
1474 * (if set). Return 'true' if PME status and PME enable were both set or
1475 * 'false' otherwise.
1477 bool pci_check_pme_status(struct pci_dev *dev)
1486 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
1487 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
1488 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
1491 /* Clear PME status. */
1492 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1493 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
1494 /* Disable PME to avoid interrupt flood. */
1495 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1499 pci_write_config_word(dev, pmcsr_pos, pmcsr);
1505 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1506 * @dev: Device to handle.
1507 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
1509 * Check if @dev has generated PME and queue a resume request for it in that
1512 static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
1514 if (pme_poll_reset && dev->pme_poll)
1515 dev->pme_poll = false;
1517 if (pci_check_pme_status(dev)) {
1518 pci_wakeup_event(dev);
1519 pm_request_resume(&dev->dev);
1525 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1526 * @bus: Top bus of the subtree to walk.
1528 void pci_pme_wakeup_bus(struct pci_bus *bus)
1531 pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
1535 * pci_wakeup - Wake up a PCI device
1536 * @pci_dev: Device to handle.
1537 * @ign: ignored parameter
1539 static int pci_wakeup(struct pci_dev *pci_dev, void *ign)
1541 pci_wakeup_event(pci_dev);
1542 pm_request_resume(&pci_dev->dev);
1547 * pci_wakeup_bus - Walk given bus and wake up devices on it
1548 * @bus: Top bus of the subtree to walk.
1550 void pci_wakeup_bus(struct pci_bus *bus)
1553 pci_walk_bus(bus, pci_wakeup, NULL);
1557 * pci_pme_capable - check the capability of PCI device to generate PME#
1558 * @dev: PCI device to handle.
1559 * @state: PCI state from which device will issue PME#.
1561 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
1566 return !!(dev->pme_support & (1 << state));
1569 static void pci_pme_list_scan(struct work_struct *work)
1571 struct pci_pme_device *pme_dev, *n;
1573 mutex_lock(&pci_pme_list_mutex);
1574 if (!list_empty(&pci_pme_list)) {
1575 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
1576 if (pme_dev->dev->pme_poll) {
1577 struct pci_dev *bridge;
1579 bridge = pme_dev->dev->bus->self;
1581 * If bridge is in low power state, the
1582 * configuration space of subordinate devices
1583 * may be not accessible
1585 if (bridge && bridge->current_state != PCI_D0)
1587 pci_pme_wakeup(pme_dev->dev, NULL);
1589 list_del(&pme_dev->list);
1593 if (!list_empty(&pci_pme_list))
1594 schedule_delayed_work(&pci_pme_work,
1595 msecs_to_jiffies(PME_TIMEOUT));
1597 mutex_unlock(&pci_pme_list_mutex);
1601 * pci_pme_active - enable or disable PCI device's PME# function
1602 * @dev: PCI device to handle.
1603 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1605 * The caller must verify that the device is capable of generating PME# before
1606 * calling this function with @enable equal to 'true'.
1608 void pci_pme_active(struct pci_dev *dev, bool enable)
1612 if (!dev->pme_support)
1615 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1616 /* Clear PME_Status by writing 1 to it and enable PME# */
1617 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1619 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1621 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1624 * PCI (as opposed to PCIe) PME requires that the device have
1625 * its PME# line hooked up correctly. Not all hardware vendors
1626 * do this, so the PME never gets delivered and the device
1627 * remains asleep. The easiest way around this is to
1628 * periodically walk the list of suspended devices and check
1629 * whether any have their PME flag set. The assumption is that
1630 * we'll wake up often enough anyway that this won't be a huge
1631 * hit, and the power savings from the devices will still be a
1634 * Although PCIe uses in-band PME message instead of PME# line
1635 * to report PME, PME does not work for some PCIe devices in
1636 * reality. For example, there are devices that set their PME
1637 * status bits, but don't really bother to send a PME message;
1638 * there are PCI Express Root Ports that don't bother to
1639 * trigger interrupts when they receive PME messages from the
1640 * devices below. So PME poll is used for PCIe devices too.
1643 if (dev->pme_poll) {
1644 struct pci_pme_device *pme_dev;
1646 pme_dev = kmalloc(sizeof(struct pci_pme_device),
1649 dev_warn(&dev->dev, "can't enable PME#\n");
1653 mutex_lock(&pci_pme_list_mutex);
1654 list_add(&pme_dev->list, &pci_pme_list);
1655 if (list_is_singular(&pci_pme_list))
1656 schedule_delayed_work(&pci_pme_work,
1657 msecs_to_jiffies(PME_TIMEOUT));
1658 mutex_unlock(&pci_pme_list_mutex);
1660 mutex_lock(&pci_pme_list_mutex);
1661 list_for_each_entry(pme_dev, &pci_pme_list, list) {
1662 if (pme_dev->dev == dev) {
1663 list_del(&pme_dev->list);
1668 mutex_unlock(&pci_pme_list_mutex);
1672 dev_dbg(&dev->dev, "PME# %s\n", enable ? "enabled" : "disabled");
1676 * __pci_enable_wake - enable PCI device as wakeup event source
1677 * @dev: PCI device affected
1678 * @state: PCI state from which device will issue wakeup events
1679 * @runtime: True if the events are to be generated at run time
1680 * @enable: True to enable event generation; false to disable
1682 * This enables the device as a wakeup event source, or disables it.
1683 * When such events involves platform-specific hooks, those hooks are
1684 * called automatically by this routine.
1686 * Devices with legacy power management (no standard PCI PM capabilities)
1687 * always require such platform hooks.
1690 * 0 is returned on success
1691 * -EINVAL is returned if device is not supposed to wake up the system
1692 * Error code depending on the platform is returned if both the platform and
1693 * the native mechanism fail to enable the generation of wake-up events
1695 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1696 bool runtime, bool enable)
1700 if (enable && !runtime && !device_may_wakeup(&dev->dev))
1703 /* Don't do the same thing twice in a row for one device. */
1704 if (!!enable == !!dev->wakeup_prepared)
1708 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1709 * Anderson we should be doing PME# wake enable followed by ACPI wake
1710 * enable. To disable wake-up we call the platform first, for symmetry.
1716 if (pci_pme_capable(dev, state))
1717 pci_pme_active(dev, true);
1720 error = runtime ? platform_pci_run_wake(dev, true) :
1721 platform_pci_sleep_wake(dev, true);
1725 dev->wakeup_prepared = true;
1728 platform_pci_run_wake(dev, false);
1730 platform_pci_sleep_wake(dev, false);
1731 pci_pme_active(dev, false);
1732 dev->wakeup_prepared = false;
1737 EXPORT_SYMBOL(__pci_enable_wake);
1740 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1741 * @dev: PCI device to prepare
1742 * @enable: True to enable wake-up event generation; false to disable
1744 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1745 * and this function allows them to set that up cleanly - pci_enable_wake()
1746 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1747 * ordering constraints.
1749 * This function only returns error code if the device is not capable of
1750 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1751 * enable wake-up power for it.
1753 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1755 return pci_pme_capable(dev, PCI_D3cold) ?
1756 pci_enable_wake(dev, PCI_D3cold, enable) :
1757 pci_enable_wake(dev, PCI_D3hot, enable);
1761 * pci_target_state - find an appropriate low power state for a given PCI dev
1764 * Use underlying platform code to find a supported low power state for @dev.
1765 * If the platform can't manage @dev, return the deepest state from which it
1766 * can generate wake events, based on any available PME info.
1768 pci_power_t pci_target_state(struct pci_dev *dev)
1770 pci_power_t target_state = PCI_D3hot;
1772 if (platform_pci_power_manageable(dev)) {
1774 * Call the platform to choose the target state of the device
1775 * and enable wake-up from this state if supported.
1777 pci_power_t state = platform_pci_choose_state(dev);
1780 case PCI_POWER_ERROR:
1785 if (pci_no_d1d2(dev))
1788 target_state = state;
1790 } else if (!dev->pm_cap) {
1791 target_state = PCI_D0;
1792 } else if (device_may_wakeup(&dev->dev)) {
1794 * Find the deepest state from which the device can generate
1795 * wake-up events, make it the target state and enable device
1798 if (dev->pme_support) {
1800 && !(dev->pme_support & (1 << target_state)))
1805 return target_state;
1809 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1810 * @dev: Device to handle.
1812 * Choose the power state appropriate for the device depending on whether
1813 * it can wake up the system and/or is power manageable by the platform
1814 * (PCI_D3hot is the default) and put the device into that state.
1816 int pci_prepare_to_sleep(struct pci_dev *dev)
1818 pci_power_t target_state = pci_target_state(dev);
1821 if (target_state == PCI_POWER_ERROR)
1824 /* D3cold during system suspend/hibernate is not supported */
1825 if (target_state > PCI_D3hot)
1826 target_state = PCI_D3hot;
1828 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
1830 error = pci_set_power_state(dev, target_state);
1833 pci_enable_wake(dev, target_state, false);
1839 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
1840 * @dev: Device to handle.
1842 * Disable device's system wake-up capability and put it into D0.
1844 int pci_back_from_sleep(struct pci_dev *dev)
1846 pci_enable_wake(dev, PCI_D0, false);
1847 return pci_set_power_state(dev, PCI_D0);
1851 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
1852 * @dev: PCI device being suspended.
1854 * Prepare @dev to generate wake-up events at run time and put it into a low
1857 int pci_finish_runtime_suspend(struct pci_dev *dev)
1859 pci_power_t target_state = pci_target_state(dev);
1862 if (target_state == PCI_POWER_ERROR)
1865 dev->runtime_d3cold = target_state == PCI_D3cold;
1867 __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev));
1869 error = pci_set_power_state(dev, target_state);
1872 __pci_enable_wake(dev, target_state, true, false);
1873 dev->runtime_d3cold = false;
1880 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
1881 * @dev: Device to check.
1883 * Return true if the device itself is capable of generating wake-up events
1884 * (through the platform or using the native PCIe PME) or if the device supports
1885 * PME and one of its upstream bridges can generate wake-up events.
1887 bool pci_dev_run_wake(struct pci_dev *dev)
1889 struct pci_bus *bus = dev->bus;
1891 if (device_run_wake(&dev->dev))
1894 if (!dev->pme_support)
1897 while (bus->parent) {
1898 struct pci_dev *bridge = bus->self;
1900 if (device_run_wake(&bridge->dev))
1906 /* We have reached the root bus. */
1908 return device_run_wake(bus->bridge);
1912 EXPORT_SYMBOL_GPL(pci_dev_run_wake);
1914 void pci_config_pm_runtime_get(struct pci_dev *pdev)
1916 struct device *dev = &pdev->dev;
1917 struct device *parent = dev->parent;
1920 pm_runtime_get_sync(parent);
1921 pm_runtime_get_noresume(dev);
1923 * pdev->current_state is set to PCI_D3cold during suspending,
1924 * so wait until suspending completes
1926 pm_runtime_barrier(dev);
1928 * Only need to resume devices in D3cold, because config
1929 * registers are still accessible for devices suspended but
1932 if (pdev->current_state == PCI_D3cold)
1933 pm_runtime_resume(dev);
1936 void pci_config_pm_runtime_put(struct pci_dev *pdev)
1938 struct device *dev = &pdev->dev;
1939 struct device *parent = dev->parent;
1941 pm_runtime_put(dev);
1943 pm_runtime_put_sync(parent);
1947 * pci_pm_init - Initialize PM functions of given PCI device
1948 * @dev: PCI device to handle.
1950 void pci_pm_init(struct pci_dev *dev)
1955 pm_runtime_forbid(&dev->dev);
1956 pm_runtime_set_active(&dev->dev);
1957 pm_runtime_enable(&dev->dev);
1958 device_enable_async_suspend(&dev->dev);
1959 dev->wakeup_prepared = false;
1962 dev->pme_support = 0;
1964 /* find PCI PM capability in list */
1965 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1968 /* Check device's ability to generate PME# */
1969 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
1971 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
1972 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
1973 pmc & PCI_PM_CAP_VER_MASK);
1978 dev->d3_delay = PCI_PM_D3_WAIT;
1979 dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
1980 dev->d3cold_allowed = true;
1982 dev->d1_support = false;
1983 dev->d2_support = false;
1984 if (!pci_no_d1d2(dev)) {
1985 if (pmc & PCI_PM_CAP_D1)
1986 dev->d1_support = true;
1987 if (pmc & PCI_PM_CAP_D2)
1988 dev->d2_support = true;
1990 if (dev->d1_support || dev->d2_support)
1991 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
1992 dev->d1_support ? " D1" : "",
1993 dev->d2_support ? " D2" : "");
1996 pmc &= PCI_PM_CAP_PME_MASK;
1998 dev_printk(KERN_DEBUG, &dev->dev,
1999 "PME# supported from%s%s%s%s%s\n",
2000 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
2001 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
2002 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
2003 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
2004 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
2005 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
2006 dev->pme_poll = true;
2008 * Make device's PM flags reflect the wake-up capability, but
2009 * let the user space enable it to wake up the system as needed.
2011 device_set_wakeup_capable(&dev->dev, true);
2012 /* Disable the PME# generation functionality */
2013 pci_pme_active(dev, false);
2017 static void pci_add_saved_cap(struct pci_dev *pci_dev,
2018 struct pci_cap_saved_state *new_cap)
2020 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
2024 * pci_add_cap_save_buffer - allocate buffer for saving given capability registers
2025 * @dev: the PCI device
2026 * @cap: the capability to allocate the buffer for
2027 * @size: requested size of the buffer
2029 static int pci_add_cap_save_buffer(
2030 struct pci_dev *dev, char cap, unsigned int size)
2033 struct pci_cap_saved_state *save_state;
2035 pos = pci_find_capability(dev, cap);
2039 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
2043 save_state->cap.cap_nr = cap;
2044 save_state->cap.size = size;
2045 pci_add_saved_cap(dev, save_state);
2051 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
2052 * @dev: the PCI device
2054 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
2058 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
2059 PCI_EXP_SAVE_REGS * sizeof(u16));
2062 "unable to preallocate PCI Express save buffer\n");
2064 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
2067 "unable to preallocate PCI-X save buffer\n");
2070 void pci_free_cap_save_buffers(struct pci_dev *dev)
2072 struct pci_cap_saved_state *tmp;
2073 struct hlist_node *n;
2075 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next)
2080 * pci_configure_ari - enable or disable ARI forwarding
2081 * @dev: the PCI device
2083 * If @dev and its upstream bridge both support ARI, enable ARI in the
2084 * bridge. Otherwise, disable ARI in the bridge.
2086 void pci_configure_ari(struct pci_dev *dev)
2089 struct pci_dev *bridge;
2091 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
2094 bridge = dev->bus->self;
2098 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
2099 if (!(cap & PCI_EXP_DEVCAP2_ARI))
2102 if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) {
2103 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
2104 PCI_EXP_DEVCTL2_ARI);
2105 bridge->ari_enabled = 1;
2107 pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2,
2108 PCI_EXP_DEVCTL2_ARI);
2109 bridge->ari_enabled = 0;
2113 static int pci_acs_enable;
2116 * pci_request_acs - ask for ACS to be enabled if supported
2118 void pci_request_acs(void)
2124 * pci_enable_acs - enable ACS if hardware support it
2125 * @dev: the PCI device
2127 void pci_enable_acs(struct pci_dev *dev)
2133 if (!pci_acs_enable)
2136 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
2140 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
2141 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
2143 /* Source Validation */
2144 ctrl |= (cap & PCI_ACS_SV);
2146 /* P2P Request Redirect */
2147 ctrl |= (cap & PCI_ACS_RR);
2149 /* P2P Completion Redirect */
2150 ctrl |= (cap & PCI_ACS_CR);
2152 /* Upstream Forwarding */
2153 ctrl |= (cap & PCI_ACS_UF);
2155 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
2158 static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags)
2163 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS);
2168 * Except for egress control, capabilities are either required
2169 * or only required if controllable. Features missing from the
2170 * capability field can therefore be assumed as hard-wired enabled.
2172 pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap);
2173 acs_flags &= (cap | PCI_ACS_EC);
2175 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
2176 return (ctrl & acs_flags) == acs_flags;
2180 * pci_acs_enabled - test ACS against required flags for a given device
2181 * @pdev: device to test
2182 * @acs_flags: required PCI ACS flags
2184 * Return true if the device supports the provided flags. Automatically
2185 * filters out flags that are not implemented on multifunction devices.
2187 * Note that this interface checks the effective ACS capabilities of the
2188 * device rather than the actual capabilities. For instance, most single
2189 * function endpoints are not required to support ACS because they have no
2190 * opportunity for peer-to-peer access. We therefore return 'true'
2191 * regardless of whether the device exposes an ACS capability. This makes
2192 * it much easier for callers of this function to ignore the actual type
2193 * or topology of the device when testing ACS support.
2195 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
2199 ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
2204 * Conventional PCI and PCI-X devices never support ACS, either
2205 * effectively or actually. The shared bus topology implies that
2206 * any device on the bus can receive or snoop DMA.
2208 if (!pci_is_pcie(pdev))
2211 switch (pci_pcie_type(pdev)) {
2213 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
2214 * but since their primary interface is PCI/X, we conservatively
2215 * handle them as we would a non-PCIe device.
2217 case PCI_EXP_TYPE_PCIE_BRIDGE:
2219 * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never
2220 * applicable... must never implement an ACS Extended Capability...".
2221 * This seems arbitrary, but we take a conservative interpretation
2222 * of this statement.
2224 case PCI_EXP_TYPE_PCI_BRIDGE:
2225 case PCI_EXP_TYPE_RC_EC:
2228 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should
2229 * implement ACS in order to indicate their peer-to-peer capabilities,
2230 * regardless of whether they are single- or multi-function devices.
2232 case PCI_EXP_TYPE_DOWNSTREAM:
2233 case PCI_EXP_TYPE_ROOT_PORT:
2234 return pci_acs_flags_enabled(pdev, acs_flags);
2236 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
2237 * implemented by the remaining PCIe types to indicate peer-to-peer
2238 * capabilities, but only when they are part of a multifunction
2239 * device. The footnote for section 6.12 indicates the specific
2240 * PCIe types included here.
2242 case PCI_EXP_TYPE_ENDPOINT:
2243 case PCI_EXP_TYPE_UPSTREAM:
2244 case PCI_EXP_TYPE_LEG_END:
2245 case PCI_EXP_TYPE_RC_END:
2246 if (!pdev->multifunction)
2249 return pci_acs_flags_enabled(pdev, acs_flags);
2253 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable
2254 * to single function devices with the exception of downstream ports.
2260 * pci_acs_path_enable - test ACS flags from start to end in a hierarchy
2261 * @start: starting downstream device
2262 * @end: ending upstream device or NULL to search to the root bus
2263 * @acs_flags: required flags
2265 * Walk up a device tree from start to end testing PCI ACS support. If
2266 * any step along the way does not support the required flags, return false.
2268 bool pci_acs_path_enabled(struct pci_dev *start,
2269 struct pci_dev *end, u16 acs_flags)
2271 struct pci_dev *pdev, *parent = start;
2276 if (!pci_acs_enabled(pdev, acs_flags))
2279 if (pci_is_root_bus(pdev->bus))
2280 return (end == NULL);
2282 parent = pdev->bus->self;
2283 } while (pdev != end);
2289 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
2290 * @dev: the PCI device
2291 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
2293 * Perform INTx swizzling for a device behind one level of bridge. This is
2294 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
2295 * behind bridges on add-in cards. For devices with ARI enabled, the slot
2296 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
2297 * the PCI Express Base Specification, Revision 2.1)
2299 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
2303 if (pci_ari_enabled(dev->bus))
2306 slot = PCI_SLOT(dev->devfn);
2308 return (((pin - 1) + slot) % 4) + 1;
2312 pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
2320 while (!pci_is_root_bus(dev->bus)) {
2321 pin = pci_swizzle_interrupt_pin(dev, pin);
2322 dev = dev->bus->self;
2329 * pci_common_swizzle - swizzle INTx all the way to root bridge
2330 * @dev: the PCI device
2331 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2333 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
2334 * bridges all the way up to a PCI root bus.
2336 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
2340 while (!pci_is_root_bus(dev->bus)) {
2341 pin = pci_swizzle_interrupt_pin(dev, pin);
2342 dev = dev->bus->self;
2345 return PCI_SLOT(dev->devfn);
2349 * pci_release_region - Release a PCI bar
2350 * @pdev: PCI device whose resources were previously reserved by pci_request_region
2351 * @bar: BAR to release
2353 * Releases the PCI I/O and memory resources previously reserved by a
2354 * successful call to pci_request_region. Call this function only
2355 * after all use of the PCI regions has ceased.
2357 void pci_release_region(struct pci_dev *pdev, int bar)
2359 struct pci_devres *dr;
2361 if (pci_resource_len(pdev, bar) == 0)
2363 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
2364 release_region(pci_resource_start(pdev, bar),
2365 pci_resource_len(pdev, bar));
2366 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
2367 release_mem_region(pci_resource_start(pdev, bar),
2368 pci_resource_len(pdev, bar));
2370 dr = find_pci_dr(pdev);
2372 dr->region_mask &= ~(1 << bar);
2376 * __pci_request_region - Reserved PCI I/O and memory resource
2377 * @pdev: PCI device whose resources are to be reserved
2378 * @bar: BAR to be reserved
2379 * @res_name: Name to be associated with resource.
2380 * @exclusive: whether the region access is exclusive or not
2382 * Mark the PCI region associated with PCI device @pdev BR @bar as
2383 * being reserved by owner @res_name. Do not access any
2384 * address inside the PCI regions unless this call returns
2387 * If @exclusive is set, then the region is marked so that userspace
2388 * is explicitly not allowed to map the resource via /dev/mem or
2389 * sysfs MMIO access.
2391 * Returns 0 on success, or %EBUSY on error. A warning
2392 * message is also printed on failure.
2394 static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name,
2397 struct pci_devres *dr;
2399 if (pci_resource_len(pdev, bar) == 0)
2402 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
2403 if (!request_region(pci_resource_start(pdev, bar),
2404 pci_resource_len(pdev, bar), res_name))
2407 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
2408 if (!__request_mem_region(pci_resource_start(pdev, bar),
2409 pci_resource_len(pdev, bar), res_name,
2414 dr = find_pci_dr(pdev);
2416 dr->region_mask |= 1 << bar;
2421 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar,
2422 &pdev->resource[bar]);
2427 * pci_request_region - Reserve PCI I/O and memory resource
2428 * @pdev: PCI device whose resources are to be reserved
2429 * @bar: BAR to be reserved
2430 * @res_name: Name to be associated with resource
2432 * Mark the PCI region associated with PCI device @pdev BAR @bar as
2433 * being reserved by owner @res_name. Do not access any
2434 * address inside the PCI regions unless this call returns
2437 * Returns 0 on success, or %EBUSY on error. A warning
2438 * message is also printed on failure.
2440 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
2442 return __pci_request_region(pdev, bar, res_name, 0);
2446 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
2447 * @pdev: PCI device whose resources are to be reserved
2448 * @bar: BAR to be reserved
2449 * @res_name: Name to be associated with resource.
2451 * Mark the PCI region associated with PCI device @pdev BR @bar as
2452 * being reserved by owner @res_name. Do not access any
2453 * address inside the PCI regions unless this call returns
2456 * Returns 0 on success, or %EBUSY on error. A warning
2457 * message is also printed on failure.
2459 * The key difference that _exclusive makes it that userspace is
2460 * explicitly not allowed to map the resource via /dev/mem or
2463 int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name)
2465 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
2468 * pci_release_selected_regions - Release selected PCI I/O and memory resources
2469 * @pdev: PCI device whose resources were previously reserved
2470 * @bars: Bitmask of BARs to be released
2472 * Release selected PCI I/O and memory resources previously reserved.
2473 * Call this function only after all use of the PCI regions has ceased.
2475 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
2479 for (i = 0; i < 6; i++)
2480 if (bars & (1 << i))
2481 pci_release_region(pdev, i);
2484 static int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
2485 const char *res_name, int excl)
2489 for (i = 0; i < 6; i++)
2490 if (bars & (1 << i))
2491 if (__pci_request_region(pdev, i, res_name, excl))
2497 if (bars & (1 << i))
2498 pci_release_region(pdev, i);
2505 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
2506 * @pdev: PCI device whose resources are to be reserved
2507 * @bars: Bitmask of BARs to be requested
2508 * @res_name: Name to be associated with resource
2510 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
2511 const char *res_name)
2513 return __pci_request_selected_regions(pdev, bars, res_name, 0);
2516 int pci_request_selected_regions_exclusive(struct pci_dev *pdev,
2517 int bars, const char *res_name)
2519 return __pci_request_selected_regions(pdev, bars, res_name,
2520 IORESOURCE_EXCLUSIVE);
2524 * pci_release_regions - Release reserved PCI I/O and memory resources
2525 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
2527 * Releases all PCI I/O and memory resources previously reserved by a
2528 * successful call to pci_request_regions. Call this function only
2529 * after all use of the PCI regions has ceased.
2532 void pci_release_regions(struct pci_dev *pdev)
2534 pci_release_selected_regions(pdev, (1 << 6) - 1);
2538 * pci_request_regions - Reserved PCI I/O and memory resources
2539 * @pdev: PCI device whose resources are to be reserved
2540 * @res_name: Name to be associated with resource.
2542 * Mark all PCI regions associated with PCI device @pdev as
2543 * being reserved by owner @res_name. Do not access any
2544 * address inside the PCI regions unless this call returns
2547 * Returns 0 on success, or %EBUSY on error. A warning
2548 * message is also printed on failure.
2550 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
2552 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
2556 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
2557 * @pdev: PCI device whose resources are to be reserved
2558 * @res_name: Name to be associated with resource.
2560 * Mark all PCI regions associated with PCI device @pdev as
2561 * being reserved by owner @res_name. Do not access any
2562 * address inside the PCI regions unless this call returns
2565 * pci_request_regions_exclusive() will mark the region so that
2566 * /dev/mem and the sysfs MMIO access will not be allowed.
2568 * Returns 0 on success, or %EBUSY on error. A warning
2569 * message is also printed on failure.
2571 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
2573 return pci_request_selected_regions_exclusive(pdev,
2574 ((1 << 6) - 1), res_name);
2577 static void __pci_set_master(struct pci_dev *dev, bool enable)
2581 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
2583 cmd = old_cmd | PCI_COMMAND_MASTER;
2585 cmd = old_cmd & ~PCI_COMMAND_MASTER;
2586 if (cmd != old_cmd) {
2587 dev_dbg(&dev->dev, "%s bus mastering\n",
2588 enable ? "enabling" : "disabling");
2589 pci_write_config_word(dev, PCI_COMMAND, cmd);
2591 dev->is_busmaster = enable;
2595 * pcibios_setup - process "pci=" kernel boot arguments
2596 * @str: string used to pass in "pci=" kernel boot arguments
2598 * Process kernel boot arguments. This is the default implementation.
2599 * Architecture specific implementations can override this as necessary.
2601 char * __weak __init pcibios_setup(char *str)
2607 * pcibios_set_master - enable PCI bus-mastering for device dev
2608 * @dev: the PCI device to enable
2610 * Enables PCI bus-mastering for the device. This is the default
2611 * implementation. Architecture specific implementations can override
2612 * this if necessary.
2614 void __weak pcibios_set_master(struct pci_dev *dev)
2618 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
2619 if (pci_is_pcie(dev))
2622 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
2624 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
2625 else if (lat > pcibios_max_latency)
2626 lat = pcibios_max_latency;
2630 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
2634 * pci_set_master - enables bus-mastering for device dev
2635 * @dev: the PCI device to enable
2637 * Enables bus-mastering on the device and calls pcibios_set_master()
2638 * to do the needed arch specific settings.
2640 void pci_set_master(struct pci_dev *dev)
2642 __pci_set_master(dev, true);
2643 pcibios_set_master(dev);
2647 * pci_clear_master - disables bus-mastering for device dev
2648 * @dev: the PCI device to disable
2650 void pci_clear_master(struct pci_dev *dev)
2652 __pci_set_master(dev, false);
2656 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
2657 * @dev: the PCI device for which MWI is to be enabled
2659 * Helper function for pci_set_mwi.
2660 * Originally copied from drivers/net/acenic.c.
2661 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
2663 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2665 int pci_set_cacheline_size(struct pci_dev *dev)
2669 if (!pci_cache_line_size)
2672 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
2673 equal to or multiple of the right value. */
2674 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2675 if (cacheline_size >= pci_cache_line_size &&
2676 (cacheline_size % pci_cache_line_size) == 0)
2679 /* Write the correct value. */
2680 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
2682 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2683 if (cacheline_size == pci_cache_line_size)
2686 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not "
2687 "supported\n", pci_cache_line_size << 2);
2691 EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
2693 #ifdef PCI_DISABLE_MWI
2694 int pci_set_mwi(struct pci_dev *dev)
2699 int pci_try_set_mwi(struct pci_dev *dev)
2704 void pci_clear_mwi(struct pci_dev *dev)
2711 * pci_set_mwi - enables memory-write-invalidate PCI transaction
2712 * @dev: the PCI device for which MWI is enabled
2714 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2716 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2719 pci_set_mwi(struct pci_dev *dev)
2724 rc = pci_set_cacheline_size(dev);
2728 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2729 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
2730 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
2731 cmd |= PCI_COMMAND_INVALIDATE;
2732 pci_write_config_word(dev, PCI_COMMAND, cmd);
2739 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
2740 * @dev: the PCI device for which MWI is enabled
2742 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2743 * Callers are not required to check the return value.
2745 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2747 int pci_try_set_mwi(struct pci_dev *dev)
2749 int rc = pci_set_mwi(dev);
2754 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
2755 * @dev: the PCI device to disable
2757 * Disables PCI Memory-Write-Invalidate transaction on the device
2760 pci_clear_mwi(struct pci_dev *dev)
2764 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2765 if (cmd & PCI_COMMAND_INVALIDATE) {
2766 cmd &= ~PCI_COMMAND_INVALIDATE;
2767 pci_write_config_word(dev, PCI_COMMAND, cmd);
2770 #endif /* ! PCI_DISABLE_MWI */
2773 * pci_intx - enables/disables PCI INTx for device dev
2774 * @pdev: the PCI device to operate on
2775 * @enable: boolean: whether to enable or disable PCI INTx
2777 * Enables/disables PCI INTx for device dev
2780 pci_intx(struct pci_dev *pdev, int enable)
2782 u16 pci_command, new;
2784 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
2787 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
2789 new = pci_command | PCI_COMMAND_INTX_DISABLE;
2792 if (new != pci_command) {
2793 struct pci_devres *dr;
2795 pci_write_config_word(pdev, PCI_COMMAND, new);
2797 dr = find_pci_dr(pdev);
2798 if (dr && !dr->restore_intx) {
2799 dr->restore_intx = 1;
2800 dr->orig_intx = !enable;
2806 * pci_intx_mask_supported - probe for INTx masking support
2807 * @dev: the PCI device to operate on
2809 * Check if the device dev support INTx masking via the config space
2812 bool pci_intx_mask_supported(struct pci_dev *dev)
2814 bool mask_supported = false;
2817 if (dev->broken_intx_masking)
2820 pci_cfg_access_lock(dev);
2822 pci_read_config_word(dev, PCI_COMMAND, &orig);
2823 pci_write_config_word(dev, PCI_COMMAND,
2824 orig ^ PCI_COMMAND_INTX_DISABLE);
2825 pci_read_config_word(dev, PCI_COMMAND, &new);
2828 * There's no way to protect against hardware bugs or detect them
2829 * reliably, but as long as we know what the value should be, let's
2830 * go ahead and check it.
2832 if ((new ^ orig) & ~PCI_COMMAND_INTX_DISABLE) {
2833 dev_err(&dev->dev, "Command register changed from "
2834 "0x%x to 0x%x: driver or hardware bug?\n", orig, new);
2835 } else if ((new ^ orig) & PCI_COMMAND_INTX_DISABLE) {
2836 mask_supported = true;
2837 pci_write_config_word(dev, PCI_COMMAND, orig);
2840 pci_cfg_access_unlock(dev);
2841 return mask_supported;
2843 EXPORT_SYMBOL_GPL(pci_intx_mask_supported);
2845 static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
2847 struct pci_bus *bus = dev->bus;
2848 bool mask_updated = true;
2849 u32 cmd_status_dword;
2850 u16 origcmd, newcmd;
2851 unsigned long flags;
2855 * We do a single dword read to retrieve both command and status.
2856 * Document assumptions that make this possible.
2858 BUILD_BUG_ON(PCI_COMMAND % 4);
2859 BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
2861 raw_spin_lock_irqsave(&pci_lock, flags);
2863 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
2865 irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
2868 * Check interrupt status register to see whether our device
2869 * triggered the interrupt (when masking) or the next IRQ is
2870 * already pending (when unmasking).
2872 if (mask != irq_pending) {
2873 mask_updated = false;
2877 origcmd = cmd_status_dword;
2878 newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
2880 newcmd |= PCI_COMMAND_INTX_DISABLE;
2881 if (newcmd != origcmd)
2882 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
2885 raw_spin_unlock_irqrestore(&pci_lock, flags);
2887 return mask_updated;
2891 * pci_check_and_mask_intx - mask INTx on pending interrupt
2892 * @dev: the PCI device to operate on
2894 * Check if the device dev has its INTx line asserted, mask it and
2895 * return true in that case. False is returned if not interrupt was
2898 bool pci_check_and_mask_intx(struct pci_dev *dev)
2900 return pci_check_and_set_intx_mask(dev, true);
2902 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
2905 * pci_check_and_mask_intx - unmask INTx of no interrupt is pending
2906 * @dev: the PCI device to operate on
2908 * Check if the device dev has its INTx line asserted, unmask it if not
2909 * and return true. False is returned and the mask remains active if
2910 * there was still an interrupt pending.
2912 bool pci_check_and_unmask_intx(struct pci_dev *dev)
2914 return pci_check_and_set_intx_mask(dev, false);
2916 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
2919 * pci_msi_off - disables any MSI or MSI-X capabilities
2920 * @dev: the PCI device to operate on
2922 * If you want to use MSI, see pci_enable_msi() and friends.
2923 * This is a lower-level primitive that allows us to disable
2924 * MSI operation at the device level.
2926 void pci_msi_off(struct pci_dev *dev)
2932 * This looks like it could go in msi.c, but we need it even when
2933 * CONFIG_PCI_MSI=n. For the same reason, we can't use
2934 * dev->msi_cap or dev->msix_cap here.
2936 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
2938 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
2939 control &= ~PCI_MSI_FLAGS_ENABLE;
2940 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
2942 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
2944 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
2945 control &= ~PCI_MSIX_FLAGS_ENABLE;
2946 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
2949 EXPORT_SYMBOL_GPL(pci_msi_off);
2951 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
2953 return dma_set_max_seg_size(&dev->dev, size);
2955 EXPORT_SYMBOL(pci_set_dma_max_seg_size);
2957 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
2959 return dma_set_seg_boundary(&dev->dev, mask);
2961 EXPORT_SYMBOL(pci_set_dma_seg_boundary);
2964 * pci_wait_for_pending_transaction - waits for pending transaction
2965 * @dev: the PCI device to operate on
2967 * Return 0 if transaction is pending 1 otherwise.
2969 int pci_wait_for_pending_transaction(struct pci_dev *dev)
2974 /* Wait for Transaction Pending bit clean */
2975 for (i = 0; i < 4; i++) {
2977 msleep((1 << (i - 1)) * 100);
2979 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
2980 if (!(status & PCI_EXP_DEVSTA_TRPND))
2986 EXPORT_SYMBOL(pci_wait_for_pending_transaction);
2988 static int pcie_flr(struct pci_dev *dev, int probe)
2992 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
2993 if (!(cap & PCI_EXP_DEVCAP_FLR))
2999 if (!pci_wait_for_pending_transaction(dev))
3000 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
3002 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3009 static int pci_af_flr(struct pci_dev *dev, int probe)
3016 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
3020 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
3021 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
3027 /* Wait for Transaction Pending bit clean */
3028 for (i = 0; i < 4; i++) {
3030 msleep((1 << (i - 1)) * 100);
3032 pci_read_config_byte(dev, pos + PCI_AF_STATUS, &status);
3033 if (!(status & PCI_AF_STATUS_TP))
3037 dev_err(&dev->dev, "transaction is not cleared; "
3038 "proceeding with reset anyway\n");
3041 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
3048 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
3049 * @dev: Device to reset.
3050 * @probe: If set, only check if the device can be reset this way.
3052 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
3053 * unset, it will be reinitialized internally when going from PCI_D3hot to
3054 * PCI_D0. If that's the case and the device is not in a low-power state
3055 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
3057 * NOTE: This causes the caller to sleep for twice the device power transition
3058 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
3059 * by default (i.e. unless the @dev's d3_delay field has a different value).
3060 * Moreover, only devices in D0 can be reset by this function.
3062 static int pci_pm_reset(struct pci_dev *dev, int probe)
3069 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
3070 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
3076 if (dev->current_state != PCI_D0)
3079 csr &= ~PCI_PM_CTRL_STATE_MASK;
3081 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
3082 pci_dev_d3_sleep(dev);
3084 csr &= ~PCI_PM_CTRL_STATE_MASK;
3086 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
3087 pci_dev_d3_sleep(dev);
3093 * pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge.
3094 * @dev: Bridge device
3096 * Use the bridge control register to assert reset on the secondary bus.
3097 * Devices on the secondary bus are left in power-on state.
3099 void pci_reset_bridge_secondary_bus(struct pci_dev *dev)
3103 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
3104 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
3105 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
3107 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
3108 * this to 2ms to ensure that we meet the minimum requirement.
3112 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
3113 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
3116 * Trhfa for conventional PCI is 2^25 clock cycles.
3117 * Assuming a minimum 33MHz clock this results in a 1s
3118 * delay before we can consider subordinate devices to
3119 * be re-initialized. PCIe has some ways to shorten this,
3120 * but we don't make use of them yet.
3124 EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus);
3126 static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
3128 struct pci_dev *pdev;
3130 if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self)
3133 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
3140 pci_reset_bridge_secondary_bus(dev->bus->self);
3145 static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe)
3149 if (!hotplug || !try_module_get(hotplug->ops->owner))
3152 if (hotplug->ops->reset_slot)
3153 rc = hotplug->ops->reset_slot(hotplug, probe);
3155 module_put(hotplug->ops->owner);
3160 static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe)
3162 struct pci_dev *pdev;
3164 if (dev->subordinate || !dev->slot)
3167 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
3168 if (pdev != dev && pdev->slot == dev->slot)
3171 return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
3174 static int __pci_dev_reset(struct pci_dev *dev, int probe)
3180 rc = pci_dev_specific_reset(dev, probe);
3184 rc = pcie_flr(dev, probe);
3188 rc = pci_af_flr(dev, probe);
3192 rc = pci_pm_reset(dev, probe);
3196 rc = pci_dev_reset_slot_function(dev, probe);
3200 rc = pci_parent_bus_reset(dev, probe);
3205 static void pci_dev_lock(struct pci_dev *dev)
3207 pci_cfg_access_lock(dev);
3208 /* block PM suspend, driver probe, etc. */
3209 device_lock(&dev->dev);
3212 static void pci_dev_unlock(struct pci_dev *dev)
3214 device_unlock(&dev->dev);
3215 pci_cfg_access_unlock(dev);
3218 static void pci_dev_save_and_disable(struct pci_dev *dev)
3221 * Wake-up device prior to save. PM registers default to D0 after
3222 * reset and a simple register restore doesn't reliably return
3223 * to a non-D0 state anyway.
3225 pci_set_power_state(dev, PCI_D0);
3227 pci_save_state(dev);
3229 * Disable the device by clearing the Command register, except for
3230 * INTx-disable which is set. This not only disables MMIO and I/O port
3231 * BARs, but also prevents the device from being Bus Master, preventing
3232 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3
3233 * compliant devices, INTx-disable prevents legacy interrupts.
3235 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
3238 static void pci_dev_restore(struct pci_dev *dev)
3240 pci_restore_state(dev);
3243 static int pci_dev_reset(struct pci_dev *dev, int probe)
3250 rc = __pci_dev_reset(dev, probe);
3253 pci_dev_unlock(dev);
3258 * __pci_reset_function - reset a PCI device function
3259 * @dev: PCI device to reset
3261 * Some devices allow an individual function to be reset without affecting
3262 * other functions in the same device. The PCI device must be responsive
3263 * to PCI config space in order to use this function.
3265 * The device function is presumed to be unused when this function is called.
3266 * Resetting the device will make the contents of PCI configuration space
3267 * random, so any caller of this must be prepared to reinitialise the
3268 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3271 * Returns 0 if the device function was successfully reset or negative if the
3272 * device doesn't support resetting a single function.
3274 int __pci_reset_function(struct pci_dev *dev)
3276 return pci_dev_reset(dev, 0);
3278 EXPORT_SYMBOL_GPL(__pci_reset_function);
3281 * __pci_reset_function_locked - reset a PCI device function while holding
3282 * the @dev mutex lock.
3283 * @dev: PCI device to reset
3285 * Some devices allow an individual function to be reset without affecting
3286 * other functions in the same device. The PCI device must be responsive
3287 * to PCI config space in order to use this function.
3289 * The device function is presumed to be unused and the caller is holding
3290 * the device mutex lock when this function is called.
3291 * Resetting the device will make the contents of PCI configuration space
3292 * random, so any caller of this must be prepared to reinitialise the
3293 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3296 * Returns 0 if the device function was successfully reset or negative if the
3297 * device doesn't support resetting a single function.
3299 int __pci_reset_function_locked(struct pci_dev *dev)
3301 return __pci_dev_reset(dev, 0);
3303 EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
3306 * pci_probe_reset_function - check whether the device can be safely reset
3307 * @dev: PCI device to reset
3309 * Some devices allow an individual function to be reset without affecting
3310 * other functions in the same device. The PCI device must be responsive
3311 * to PCI config space in order to use this function.
3313 * Returns 0 if the device function can be reset or negative if the
3314 * device doesn't support resetting a single function.
3316 int pci_probe_reset_function(struct pci_dev *dev)
3318 return pci_dev_reset(dev, 1);
3322 * pci_reset_function - quiesce and reset a PCI device function
3323 * @dev: PCI device to reset
3325 * Some devices allow an individual function to be reset without affecting
3326 * other functions in the same device. The PCI device must be responsive
3327 * to PCI config space in order to use this function.
3329 * This function does not just reset the PCI portion of a device, but
3330 * clears all the state associated with the device. This function differs
3331 * from __pci_reset_function in that it saves and restores device state
3334 * Returns 0 if the device function was successfully reset or negative if the
3335 * device doesn't support resetting a single function.
3337 int pci_reset_function(struct pci_dev *dev)
3341 rc = pci_dev_reset(dev, 1);
3345 pci_dev_save_and_disable(dev);
3347 rc = pci_dev_reset(dev, 0);
3349 pci_dev_restore(dev);
3353 EXPORT_SYMBOL_GPL(pci_reset_function);
3355 /* Lock devices from the top of the tree down */
3356 static void pci_bus_lock(struct pci_bus *bus)
3358 struct pci_dev *dev;
3360 list_for_each_entry(dev, &bus->devices, bus_list) {
3362 if (dev->subordinate)
3363 pci_bus_lock(dev->subordinate);
3367 /* Unlock devices from the bottom of the tree up */
3368 static void pci_bus_unlock(struct pci_bus *bus)
3370 struct pci_dev *dev;
3372 list_for_each_entry(dev, &bus->devices, bus_list) {
3373 if (dev->subordinate)
3374 pci_bus_unlock(dev->subordinate);
3375 pci_dev_unlock(dev);
3379 /* Lock devices from the top of the tree down */
3380 static void pci_slot_lock(struct pci_slot *slot)
3382 struct pci_dev *dev;
3384 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3385 if (!dev->slot || dev->slot != slot)
3388 if (dev->subordinate)
3389 pci_bus_lock(dev->subordinate);
3393 /* Unlock devices from the bottom of the tree up */
3394 static void pci_slot_unlock(struct pci_slot *slot)
3396 struct pci_dev *dev;
3398 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3399 if (!dev->slot || dev->slot != slot)
3401 if (dev->subordinate)
3402 pci_bus_unlock(dev->subordinate);
3403 pci_dev_unlock(dev);
3407 /* Save and disable devices from the top of the tree down */
3408 static void pci_bus_save_and_disable(struct pci_bus *bus)
3410 struct pci_dev *dev;
3412 list_for_each_entry(dev, &bus->devices, bus_list) {
3413 pci_dev_save_and_disable(dev);
3414 if (dev->subordinate)
3415 pci_bus_save_and_disable(dev->subordinate);
3420 * Restore devices from top of the tree down - parent bridges need to be
3421 * restored before we can get to subordinate devices.
3423 static void pci_bus_restore(struct pci_bus *bus)
3425 struct pci_dev *dev;
3427 list_for_each_entry(dev, &bus->devices, bus_list) {
3428 pci_dev_restore(dev);
3429 if (dev->subordinate)
3430 pci_bus_restore(dev->subordinate);
3434 /* Save and disable devices from the top of the tree down */
3435 static void pci_slot_save_and_disable(struct pci_slot *slot)
3437 struct pci_dev *dev;
3439 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3440 if (!dev->slot || dev->slot != slot)
3442 pci_dev_save_and_disable(dev);
3443 if (dev->subordinate)
3444 pci_bus_save_and_disable(dev->subordinate);
3449 * Restore devices from top of the tree down - parent bridges need to be
3450 * restored before we can get to subordinate devices.
3452 static void pci_slot_restore(struct pci_slot *slot)
3454 struct pci_dev *dev;
3456 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3457 if (!dev->slot || dev->slot != slot)
3459 pci_dev_restore(dev);
3460 if (dev->subordinate)
3461 pci_bus_restore(dev->subordinate);
3465 static int pci_slot_reset(struct pci_slot *slot, int probe)
3473 pci_slot_lock(slot);
3477 rc = pci_reset_hotplug_slot(slot->hotplug, probe);
3480 pci_slot_unlock(slot);
3486 * pci_probe_reset_slot - probe whether a PCI slot can be reset
3487 * @slot: PCI slot to probe
3489 * Return 0 if slot can be reset, negative if a slot reset is not supported.
3491 int pci_probe_reset_slot(struct pci_slot *slot)
3493 return pci_slot_reset(slot, 1);
3495 EXPORT_SYMBOL_GPL(pci_probe_reset_slot);
3498 * pci_reset_slot - reset a PCI slot
3499 * @slot: PCI slot to reset
3501 * A PCI bus may host multiple slots, each slot may support a reset mechanism
3502 * independent of other slots. For instance, some slots may support slot power
3503 * control. In the case of a 1:1 bus to slot architecture, this function may
3504 * wrap the bus reset to avoid spurious slot related events such as hotplug.
3505 * Generally a slot reset should be attempted before a bus reset. All of the
3506 * function of the slot and any subordinate buses behind the slot are reset
3507 * through this function. PCI config space of all devices in the slot and
3508 * behind the slot is saved before and restored after reset.
3510 * Return 0 on success, non-zero on error.
3512 int pci_reset_slot(struct pci_slot *slot)
3516 rc = pci_slot_reset(slot, 1);
3520 pci_slot_save_and_disable(slot);
3522 rc = pci_slot_reset(slot, 0);
3524 pci_slot_restore(slot);
3528 EXPORT_SYMBOL_GPL(pci_reset_slot);
3530 static int pci_bus_reset(struct pci_bus *bus, int probe)
3542 pci_reset_bridge_secondary_bus(bus->self);
3544 pci_bus_unlock(bus);
3550 * pci_probe_reset_bus - probe whether a PCI bus can be reset
3551 * @bus: PCI bus to probe
3553 * Return 0 if bus can be reset, negative if a bus reset is not supported.
3555 int pci_probe_reset_bus(struct pci_bus *bus)
3557 return pci_bus_reset(bus, 1);
3559 EXPORT_SYMBOL_GPL(pci_probe_reset_bus);
3562 * pci_reset_bus - reset a PCI bus
3563 * @bus: top level PCI bus to reset
3565 * Do a bus reset on the given bus and any subordinate buses, saving
3566 * and restoring state of all devices.
3568 * Return 0 on success, non-zero on error.
3570 int pci_reset_bus(struct pci_bus *bus)
3574 rc = pci_bus_reset(bus, 1);
3578 pci_bus_save_and_disable(bus);
3580 rc = pci_bus_reset(bus, 0);
3582 pci_bus_restore(bus);
3586 EXPORT_SYMBOL_GPL(pci_reset_bus);
3589 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
3590 * @dev: PCI device to query
3592 * Returns mmrbc: maximum designed memory read count in bytes
3593 * or appropriate error value.
3595 int pcix_get_max_mmrbc(struct pci_dev *dev)
3600 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3604 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
3607 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
3609 EXPORT_SYMBOL(pcix_get_max_mmrbc);
3612 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
3613 * @dev: PCI device to query
3615 * Returns mmrbc: maximum memory read count in bytes
3616 * or appropriate error value.
3618 int pcix_get_mmrbc(struct pci_dev *dev)
3623 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3627 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
3630 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
3632 EXPORT_SYMBOL(pcix_get_mmrbc);
3635 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
3636 * @dev: PCI device to query
3637 * @mmrbc: maximum memory read count in bytes
3638 * valid values are 512, 1024, 2048, 4096
3640 * If possible sets maximum memory read byte count, some bridges have erratas
3641 * that prevent this.
3643 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
3649 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
3652 v = ffs(mmrbc) - 10;
3654 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3658 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
3661 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
3664 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
3667 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
3669 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
3672 cmd &= ~PCI_X_CMD_MAX_READ;
3674 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
3679 EXPORT_SYMBOL(pcix_set_mmrbc);
3682 * pcie_get_readrq - get PCI Express read request size
3683 * @dev: PCI device to query
3685 * Returns maximum memory read request in bytes
3686 * or appropriate error value.
3688 int pcie_get_readrq(struct pci_dev *dev)
3692 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
3694 return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
3696 EXPORT_SYMBOL(pcie_get_readrq);
3699 * pcie_set_readrq - set PCI Express maximum memory read request
3700 * @dev: PCI device to query
3701 * @rq: maximum memory read count in bytes
3702 * valid values are 128, 256, 512, 1024, 2048, 4096
3704 * If possible sets maximum memory read request in bytes
3706 int pcie_set_readrq(struct pci_dev *dev, int rq)
3710 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
3714 * If using the "performance" PCIe config, we clamp the
3715 * read rq size to the max packet size to prevent the
3716 * host bridge generating requests larger than we can
3719 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
3720 int mps = pcie_get_mps(dev);
3726 v = (ffs(rq) - 8) << 12;
3728 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
3729 PCI_EXP_DEVCTL_READRQ, v);
3731 EXPORT_SYMBOL(pcie_set_readrq);
3734 * pcie_get_mps - get PCI Express maximum payload size
3735 * @dev: PCI device to query
3737 * Returns maximum payload size in bytes
3739 int pcie_get_mps(struct pci_dev *dev)
3743 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
3745 return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
3747 EXPORT_SYMBOL(pcie_get_mps);
3750 * pcie_set_mps - set PCI Express maximum payload size
3751 * @dev: PCI device to query
3752 * @mps: maximum payload size in bytes
3753 * valid values are 128, 256, 512, 1024, 2048, 4096
3755 * If possible sets maximum payload size
3757 int pcie_set_mps(struct pci_dev *dev, int mps)
3761 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
3765 if (v > dev->pcie_mpss)
3769 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
3770 PCI_EXP_DEVCTL_PAYLOAD, v);
3772 EXPORT_SYMBOL(pcie_set_mps);
3775 * pcie_get_minimum_link - determine minimum link settings of a PCI device
3776 * @dev: PCI device to query
3777 * @speed: storage for minimum speed
3778 * @width: storage for minimum width
3780 * This function will walk up the PCI device chain and determine the minimum
3781 * link width and speed of the device.
3783 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
3784 enum pcie_link_width *width)
3788 *speed = PCI_SPEED_UNKNOWN;
3789 *width = PCIE_LNK_WIDTH_UNKNOWN;
3793 enum pci_bus_speed next_speed;
3794 enum pcie_link_width next_width;
3796 ret = pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
3800 next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS];
3801 next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >>
3802 PCI_EXP_LNKSTA_NLW_SHIFT;
3804 if (next_speed < *speed)
3805 *speed = next_speed;
3807 if (next_width < *width)
3808 *width = next_width;
3810 dev = dev->bus->self;
3815 EXPORT_SYMBOL(pcie_get_minimum_link);
3818 * pci_select_bars - Make BAR mask from the type of resource
3819 * @dev: the PCI device for which BAR mask is made
3820 * @flags: resource type mask to be selected
3822 * This helper routine makes bar mask from the type of resource.
3824 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
3827 for (i = 0; i < PCI_NUM_RESOURCES; i++)
3828 if (pci_resource_flags(dev, i) & flags)
3834 * pci_resource_bar - get position of the BAR associated with a resource
3835 * @dev: the PCI device
3836 * @resno: the resource number
3837 * @type: the BAR type to be filled in
3839 * Returns BAR position in config space, or 0 if the BAR is invalid.
3841 int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type)
3845 if (resno < PCI_ROM_RESOURCE) {
3846 *type = pci_bar_unknown;
3847 return PCI_BASE_ADDRESS_0 + 4 * resno;
3848 } else if (resno == PCI_ROM_RESOURCE) {
3849 *type = pci_bar_mem32;
3850 return dev->rom_base_reg;
3851 } else if (resno < PCI_BRIDGE_RESOURCES) {
3852 /* device specific resource */
3853 reg = pci_iov_resource_bar(dev, resno, type);
3858 dev_err(&dev->dev, "BAR %d: invalid resource\n", resno);
3862 /* Some architectures require additional programming to enable VGA */
3863 static arch_set_vga_state_t arch_set_vga_state;
3865 void __init pci_register_set_vga_state(arch_set_vga_state_t func)
3867 arch_set_vga_state = func; /* NULL disables */
3870 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
3871 unsigned int command_bits, u32 flags)
3873 if (arch_set_vga_state)
3874 return arch_set_vga_state(dev, decode, command_bits,
3880 * pci_set_vga_state - set VGA decode state on device and parents if requested
3881 * @dev: the PCI device
3882 * @decode: true = enable decoding, false = disable decoding
3883 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
3884 * @flags: traverse ancestors and change bridges
3885 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
3887 int pci_set_vga_state(struct pci_dev *dev, bool decode,
3888 unsigned int command_bits, u32 flags)
3890 struct pci_bus *bus;
3891 struct pci_dev *bridge;
3895 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) & (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
3897 /* ARCH specific VGA enables */
3898 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
3902 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
3903 pci_read_config_word(dev, PCI_COMMAND, &cmd);
3905 cmd |= command_bits;
3907 cmd &= ~command_bits;
3908 pci_write_config_word(dev, PCI_COMMAND, cmd);
3911 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
3918 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
3921 cmd |= PCI_BRIDGE_CTL_VGA;
3923 cmd &= ~PCI_BRIDGE_CTL_VGA;
3924 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
3932 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
3933 static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
3934 static DEFINE_SPINLOCK(resource_alignment_lock);
3937 * pci_specified_resource_alignment - get resource alignment specified by user.
3938 * @dev: the PCI device to get
3940 * RETURNS: Resource alignment if it is specified.
3941 * Zero if it is not specified.
3943 static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev)
3945 int seg, bus, slot, func, align_order, count;
3946 resource_size_t align = 0;
3949 spin_lock(&resource_alignment_lock);
3950 p = resource_alignment_param;
3953 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
3959 if (sscanf(p, "%x:%x:%x.%x%n",
3960 &seg, &bus, &slot, &func, &count) != 4) {
3962 if (sscanf(p, "%x:%x.%x%n",
3963 &bus, &slot, &func, &count) != 3) {
3964 /* Invalid format */
3965 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
3971 if (seg == pci_domain_nr(dev->bus) &&
3972 bus == dev->bus->number &&
3973 slot == PCI_SLOT(dev->devfn) &&
3974 func == PCI_FUNC(dev->devfn)) {
3975 if (align_order == -1) {
3978 align = 1 << align_order;
3983 if (*p != ';' && *p != ',') {
3984 /* End of param or invalid format */
3989 spin_unlock(&resource_alignment_lock);
3994 * This function disables memory decoding and releases memory resources
3995 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
3996 * It also rounds up size to specified alignment.
3997 * Later on, the kernel will assign page-aligned memory resource back
4000 void pci_reassigndev_resource_alignment(struct pci_dev *dev)
4004 resource_size_t align, size;
4007 /* check if specified PCI is target device to reassign */
4008 align = pci_specified_resource_alignment(dev);
4012 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
4013 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
4015 "Can't reassign resources to host bridge.\n");
4020 "Disabling memory decoding and releasing memory resources.\n");
4021 pci_read_config_word(dev, PCI_COMMAND, &command);
4022 command &= ~PCI_COMMAND_MEMORY;
4023 pci_write_config_word(dev, PCI_COMMAND, command);
4025 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
4026 r = &dev->resource[i];
4027 if (!(r->flags & IORESOURCE_MEM))
4029 size = resource_size(r);
4033 "Rounding up size of resource #%d to %#llx.\n",
4034 i, (unsigned long long)size);
4039 /* Need to disable bridge's resource window,
4040 * to enable the kernel to reassign new resource
4043 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
4044 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
4045 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
4046 r = &dev->resource[i];
4047 if (!(r->flags & IORESOURCE_MEM))
4049 r->end = resource_size(r) - 1;
4052 pci_disable_bridge_window(dev);
4056 static ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
4058 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
4059 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
4060 spin_lock(&resource_alignment_lock);
4061 strncpy(resource_alignment_param, buf, count);
4062 resource_alignment_param[count] = '\0';
4063 spin_unlock(&resource_alignment_lock);
4067 static ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
4070 spin_lock(&resource_alignment_lock);
4071 count = snprintf(buf, size, "%s", resource_alignment_param);
4072 spin_unlock(&resource_alignment_lock);
4076 static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
4078 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
4081 static ssize_t pci_resource_alignment_store(struct bus_type *bus,
4082 const char *buf, size_t count)
4084 return pci_set_resource_alignment_param(buf, count);
4087 BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
4088 pci_resource_alignment_store);
4090 static int __init pci_resource_alignment_sysfs_init(void)
4092 return bus_create_file(&pci_bus_type,
4093 &bus_attr_resource_alignment);
4096 late_initcall(pci_resource_alignment_sysfs_init);
4098 static void pci_no_domains(void)
4100 #ifdef CONFIG_PCI_DOMAINS
4101 pci_domains_supported = 0;
4106 * pci_ext_cfg_avail - can we access extended PCI config space?
4108 * Returns 1 if we can access PCI extended config space (offsets
4109 * greater than 0xff). This is the default implementation. Architecture
4110 * implementations can override this.
4112 int __weak pci_ext_cfg_avail(void)
4117 void __weak pci_fixup_cardbus(struct pci_bus *bus)
4120 EXPORT_SYMBOL(pci_fixup_cardbus);
4122 static int __init pci_setup(char *str)
4125 char *k = strchr(str, ',');
4128 if (*str && (str = pcibios_setup(str)) && *str) {
4129 if (!strcmp(str, "nomsi")) {
4131 } else if (!strcmp(str, "noaer")) {
4133 } else if (!strncmp(str, "realloc=", 8)) {
4134 pci_realloc_get_opt(str + 8);
4135 } else if (!strncmp(str, "realloc", 7)) {
4136 pci_realloc_get_opt("on");
4137 } else if (!strcmp(str, "nodomains")) {
4139 } else if (!strncmp(str, "noari", 5)) {
4140 pcie_ari_disabled = true;
4141 } else if (!strncmp(str, "cbiosize=", 9)) {
4142 pci_cardbus_io_size = memparse(str + 9, &str);
4143 } else if (!strncmp(str, "cbmemsize=", 10)) {
4144 pci_cardbus_mem_size = memparse(str + 10, &str);
4145 } else if (!strncmp(str, "resource_alignment=", 19)) {
4146 pci_set_resource_alignment_param(str + 19,
4148 } else if (!strncmp(str, "ecrc=", 5)) {
4149 pcie_ecrc_get_policy(str + 5);
4150 } else if (!strncmp(str, "hpiosize=", 9)) {
4151 pci_hotplug_io_size = memparse(str + 9, &str);
4152 } else if (!strncmp(str, "hpmemsize=", 10)) {
4153 pci_hotplug_mem_size = memparse(str + 10, &str);
4154 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
4155 pcie_bus_config = PCIE_BUS_TUNE_OFF;
4156 } else if (!strncmp(str, "pcie_bus_safe", 13)) {
4157 pcie_bus_config = PCIE_BUS_SAFE;
4158 } else if (!strncmp(str, "pcie_bus_perf", 13)) {
4159 pcie_bus_config = PCIE_BUS_PERFORMANCE;
4160 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
4161 pcie_bus_config = PCIE_BUS_PEER2PEER;
4162 } else if (!strncmp(str, "pcie_scan_all", 13)) {
4163 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
4165 printk(KERN_ERR "PCI: Unknown option `%s'\n",
4173 early_param("pci", pci_setup);
4175 EXPORT_SYMBOL(pci_reenable_device);
4176 EXPORT_SYMBOL(pci_enable_device_io);
4177 EXPORT_SYMBOL(pci_enable_device_mem);
4178 EXPORT_SYMBOL(pci_enable_device);
4179 EXPORT_SYMBOL(pcim_enable_device);
4180 EXPORT_SYMBOL(pcim_pin_device);
4181 EXPORT_SYMBOL(pci_disable_device);
4182 EXPORT_SYMBOL(pci_find_capability);
4183 EXPORT_SYMBOL(pci_bus_find_capability);
4184 EXPORT_SYMBOL(pci_release_regions);
4185 EXPORT_SYMBOL(pci_request_regions);
4186 EXPORT_SYMBOL(pci_request_regions_exclusive);
4187 EXPORT_SYMBOL(pci_release_region);
4188 EXPORT_SYMBOL(pci_request_region);
4189 EXPORT_SYMBOL(pci_request_region_exclusive);
4190 EXPORT_SYMBOL(pci_release_selected_regions);
4191 EXPORT_SYMBOL(pci_request_selected_regions);
4192 EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
4193 EXPORT_SYMBOL(pci_set_master);
4194 EXPORT_SYMBOL(pci_clear_master);
4195 EXPORT_SYMBOL(pci_set_mwi);
4196 EXPORT_SYMBOL(pci_try_set_mwi);
4197 EXPORT_SYMBOL(pci_clear_mwi);
4198 EXPORT_SYMBOL_GPL(pci_intx);
4199 EXPORT_SYMBOL(pci_assign_resource);
4200 EXPORT_SYMBOL(pci_find_parent_resource);
4201 EXPORT_SYMBOL(pci_select_bars);
4203 EXPORT_SYMBOL(pci_set_power_state);
4204 EXPORT_SYMBOL(pci_save_state);
4205 EXPORT_SYMBOL(pci_restore_state);
4206 EXPORT_SYMBOL(pci_pme_capable);
4207 EXPORT_SYMBOL(pci_pme_active);
4208 EXPORT_SYMBOL(pci_wake_from_d3);
4209 EXPORT_SYMBOL(pci_target_state);
4210 EXPORT_SYMBOL(pci_prepare_to_sleep);
4211 EXPORT_SYMBOL(pci_back_from_sleep);
4212 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);