2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/pci.h>
15 #include <linux/slab.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <linux/string.h>
19 #include <linux/log2.h>
20 #include <linux/pci-aspm.h>
21 #include <linux/pm_wakeup.h>
22 #include <linux/interrupt.h>
23 #include <linux/device.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/pci_hotplug.h>
26 #include <asm-generic/pci-bridge.h>
27 #include <asm/setup.h>
30 const char *pci_power_names[] = {
31 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
33 EXPORT_SYMBOL_GPL(pci_power_names);
35 int isa_dma_bridge_buggy;
36 EXPORT_SYMBOL(isa_dma_bridge_buggy);
39 EXPORT_SYMBOL(pci_pci_problems);
41 unsigned int pci_pm_d3_delay;
43 static void pci_pme_list_scan(struct work_struct *work);
45 static LIST_HEAD(pci_pme_list);
46 static DEFINE_MUTEX(pci_pme_list_mutex);
47 static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
49 struct pci_pme_device {
50 struct list_head list;
54 #define PME_TIMEOUT 1000 /* How long between PME checks */
56 static void pci_dev_d3_sleep(struct pci_dev *dev)
58 unsigned int delay = dev->d3_delay;
60 if (delay < pci_pm_d3_delay)
61 delay = pci_pm_d3_delay;
66 #ifdef CONFIG_PCI_DOMAINS
67 int pci_domains_supported = 1;
70 #define DEFAULT_CARDBUS_IO_SIZE (256)
71 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
72 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
73 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
74 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
76 #define DEFAULT_HOTPLUG_IO_SIZE (256)
77 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
78 /* pci=hpmemsize=nnM,hpiosize=nn can override this */
79 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
80 unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
82 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF;
85 * The default CLS is used if arch didn't set CLS explicitly and not
86 * all pci devices agree on the same value. Arch can override either
87 * the dfl or actual value as it sees fit. Don't forget this is
88 * measured in 32-bit words, not bytes.
90 u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2;
91 u8 pci_cache_line_size;
94 * If we set up a device for bus mastering, we need to check the latency
95 * timer as certain BIOSes forget to set it properly.
97 unsigned int pcibios_max_latency = 255;
99 /* If set, the PCIe ARI capability will not be used. */
100 static bool pcie_ari_disabled;
103 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
104 * @bus: pointer to PCI bus structure to search
106 * Given a PCI bus, returns the highest PCI bus number present in the set
107 * including the given PCI bus and its list of child PCI buses.
109 unsigned char pci_bus_max_busnr(struct pci_bus* bus)
111 struct list_head *tmp;
112 unsigned char max, n;
114 max = bus->busn_res.end;
115 list_for_each(tmp, &bus->children) {
116 n = pci_bus_max_busnr(pci_bus_b(tmp));
122 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
124 #ifdef CONFIG_HAS_IOMEM
125 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
128 * Make sure the BAR is actually a memory resource, not an IO resource
130 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
134 return ioremap_nocache(pci_resource_start(pdev, bar),
135 pci_resource_len(pdev, bar));
137 EXPORT_SYMBOL_GPL(pci_ioremap_bar);
140 #define PCI_FIND_CAP_TTL 48
142 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
143 u8 pos, int cap, int *ttl)
148 pci_bus_read_config_byte(bus, devfn, pos, &pos);
152 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
158 pos += PCI_CAP_LIST_NEXT;
163 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
166 int ttl = PCI_FIND_CAP_TTL;
168 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
171 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
173 return __pci_find_next_cap(dev->bus, dev->devfn,
174 pos + PCI_CAP_LIST_NEXT, cap);
176 EXPORT_SYMBOL_GPL(pci_find_next_capability);
178 static int __pci_bus_find_cap_start(struct pci_bus *bus,
179 unsigned int devfn, u8 hdr_type)
183 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
184 if (!(status & PCI_STATUS_CAP_LIST))
188 case PCI_HEADER_TYPE_NORMAL:
189 case PCI_HEADER_TYPE_BRIDGE:
190 return PCI_CAPABILITY_LIST;
191 case PCI_HEADER_TYPE_CARDBUS:
192 return PCI_CB_CAPABILITY_LIST;
201 * pci_find_capability - query for devices' capabilities
202 * @dev: PCI device to query
203 * @cap: capability code
205 * Tell if a device supports a given PCI capability.
206 * Returns the address of the requested capability structure within the
207 * device's PCI configuration space or 0 in case the device does not
208 * support it. Possible values for @cap:
210 * %PCI_CAP_ID_PM Power Management
211 * %PCI_CAP_ID_AGP Accelerated Graphics Port
212 * %PCI_CAP_ID_VPD Vital Product Data
213 * %PCI_CAP_ID_SLOTID Slot Identification
214 * %PCI_CAP_ID_MSI Message Signalled Interrupts
215 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
216 * %PCI_CAP_ID_PCIX PCI-X
217 * %PCI_CAP_ID_EXP PCI Express
219 int pci_find_capability(struct pci_dev *dev, int cap)
223 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
225 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
231 * pci_bus_find_capability - query for devices' capabilities
232 * @bus: the PCI bus to query
233 * @devfn: PCI device to query
234 * @cap: capability code
236 * Like pci_find_capability() but works for pci devices that do not have a
237 * pci_dev structure set up yet.
239 * Returns the address of the requested capability structure within the
240 * device's PCI configuration space or 0 in case the device does not
243 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
248 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
250 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
252 pos = __pci_find_next_cap(bus, devfn, pos, cap);
258 * pci_find_next_ext_capability - Find an extended capability
259 * @dev: PCI device to query
260 * @start: address at which to start looking (0 to start at beginning of list)
261 * @cap: capability code
263 * Returns the address of the next matching extended capability structure
264 * within the device's PCI configuration space or 0 if the device does
265 * not support it. Some capabilities can occur several times, e.g., the
266 * vendor-specific capability, and this provides a way to find them all.
268 int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap)
272 int pos = PCI_CFG_SPACE_SIZE;
274 /* minimum 8 bytes per capability */
275 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
277 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
283 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
287 * If we have no capabilities, this is indicated by cap ID,
288 * cap version and next pointer all being 0.
294 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
297 pos = PCI_EXT_CAP_NEXT(header);
298 if (pos < PCI_CFG_SPACE_SIZE)
301 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
307 EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
310 * pci_find_ext_capability - Find an extended capability
311 * @dev: PCI device to query
312 * @cap: capability code
314 * Returns the address of the requested extended capability structure
315 * within the device's PCI configuration space or 0 if the device does
316 * not support it. Possible values for @cap:
318 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
319 * %PCI_EXT_CAP_ID_VC Virtual Channel
320 * %PCI_EXT_CAP_ID_DSN Device Serial Number
321 * %PCI_EXT_CAP_ID_PWR Power Budgeting
323 int pci_find_ext_capability(struct pci_dev *dev, int cap)
325 return pci_find_next_ext_capability(dev, 0, cap);
327 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
329 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
331 int rc, ttl = PCI_FIND_CAP_TTL;
334 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
335 mask = HT_3BIT_CAP_MASK;
337 mask = HT_5BIT_CAP_MASK;
339 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
340 PCI_CAP_ID_HT, &ttl);
342 rc = pci_read_config_byte(dev, pos + 3, &cap);
343 if (rc != PCIBIOS_SUCCESSFUL)
346 if ((cap & mask) == ht_cap)
349 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
350 pos + PCI_CAP_LIST_NEXT,
351 PCI_CAP_ID_HT, &ttl);
357 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
358 * @dev: PCI device to query
359 * @pos: Position from which to continue searching
360 * @ht_cap: Hypertransport capability code
362 * To be used in conjunction with pci_find_ht_capability() to search for
363 * all capabilities matching @ht_cap. @pos should always be a value returned
364 * from pci_find_ht_capability().
366 * NB. To be 100% safe against broken PCI devices, the caller should take
367 * steps to avoid an infinite loop.
369 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
371 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
373 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
376 * pci_find_ht_capability - query a device's Hypertransport capabilities
377 * @dev: PCI device to query
378 * @ht_cap: Hypertransport capability code
380 * Tell if a device supports a given Hypertransport capability.
381 * Returns an address within the device's PCI configuration space
382 * or 0 in case the device does not support the request capability.
383 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
384 * which has a Hypertransport capability matching @ht_cap.
386 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
390 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
392 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
396 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
399 * pci_find_parent_resource - return resource region of parent bus of given region
400 * @dev: PCI device structure contains resources to be searched
401 * @res: child resource record for which parent is sought
403 * For given resource region of given device, return the resource
404 * region of parent bus the given region is contained in or where
405 * it should be allocated from.
408 pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
410 const struct pci_bus *bus = dev->bus;
412 struct resource *best = NULL, *r;
414 pci_bus_for_each_resource(bus, r, i) {
417 if (res->start && !(res->start >= r->start && res->end <= r->end))
418 continue; /* Not contained */
419 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
420 continue; /* Wrong type */
421 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
422 return r; /* Exact match */
423 /* We can't insert a non-prefetch resource inside a prefetchable parent .. */
424 if (r->flags & IORESOURCE_PREFETCH)
426 /* .. but we can put a prefetchable resource inside a non-prefetchable one */
434 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
435 * @dev: PCI device to have its BARs restored
437 * Restore the BAR values for a given device, so as to make it
438 * accessible by its driver.
441 pci_restore_bars(struct pci_dev *dev)
445 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
446 pci_update_resource(dev, i);
449 static struct pci_platform_pm_ops *pci_platform_pm;
451 int pci_set_platform_pm(struct pci_platform_pm_ops *ops)
453 if (!ops->is_manageable || !ops->set_state || !ops->choose_state
456 pci_platform_pm = ops;
460 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
462 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
465 static inline int platform_pci_set_power_state(struct pci_dev *dev,
468 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
471 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
473 return pci_platform_pm ?
474 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
477 static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
479 return pci_platform_pm ?
480 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
483 static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable)
485 return pci_platform_pm ?
486 pci_platform_pm->run_wake(dev, enable) : -ENODEV;
490 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
492 * @dev: PCI device to handle.
493 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
496 * -EINVAL if the requested state is invalid.
497 * -EIO if device does not support PCI PM or its PM capabilities register has a
498 * wrong version, or device doesn't support the requested state.
499 * 0 if device already is in the requested state.
500 * 0 if device's power state has been successfully changed.
502 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
505 bool need_restore = false;
507 /* Check if we're already there */
508 if (dev->current_state == state)
514 if (state < PCI_D0 || state > PCI_D3hot)
517 /* Validate current state:
518 * Can enter D0 from any state, but if we can only go deeper
519 * to sleep if we're already in a low power state
521 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
522 && dev->current_state > state) {
523 dev_err(&dev->dev, "invalid power transition "
524 "(from state %d to %d)\n", dev->current_state, state);
528 /* check if this device supports the desired state */
529 if ((state == PCI_D1 && !dev->d1_support)
530 || (state == PCI_D2 && !dev->d2_support))
533 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
535 /* If we're (effectively) in D3, force entire word to 0.
536 * This doesn't affect PME_Status, disables PME_En, and
537 * sets PowerState to 0.
539 switch (dev->current_state) {
543 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
548 case PCI_UNKNOWN: /* Boot-up */
549 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
550 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
552 /* Fall-through: force to D0 */
558 /* enter specified state */
559 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
561 /* Mandatory power management transition delays */
562 /* see PCI PM 1.1 5.6.1 table 18 */
563 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
564 pci_dev_d3_sleep(dev);
565 else if (state == PCI_D2 || dev->current_state == PCI_D2)
566 udelay(PCI_PM_D2_DELAY);
568 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
569 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
570 if (dev->current_state != state && printk_ratelimit())
571 dev_info(&dev->dev, "Refused to change power state, "
572 "currently in D%d\n", dev->current_state);
575 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
576 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
577 * from D3hot to D0 _may_ perform an internal reset, thereby
578 * going to "D0 Uninitialized" rather than "D0 Initialized".
579 * For example, at least some versions of the 3c905B and the
580 * 3c556B exhibit this behaviour.
582 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
583 * devices in a D3hot state at boot. Consequently, we need to
584 * restore at least the BARs so that the device will be
585 * accessible to its driver.
588 pci_restore_bars(dev);
591 pcie_aspm_pm_state_change(dev->bus->self);
597 * pci_update_current_state - Read PCI power state of given device from its
598 * PCI PM registers and cache it
599 * @dev: PCI device to handle.
600 * @state: State to cache in case the device doesn't have the PM capability
602 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
608 * Configuration space is not accessible for device in
609 * D3cold, so just keep or set D3cold for safety
611 if (dev->current_state == PCI_D3cold)
613 if (state == PCI_D3cold) {
614 dev->current_state = PCI_D3cold;
617 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
618 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
620 dev->current_state = state;
625 * pci_power_up - Put the given device into D0 forcibly
626 * @dev: PCI device to power up
628 void pci_power_up(struct pci_dev *dev)
630 if (platform_pci_power_manageable(dev))
631 platform_pci_set_power_state(dev, PCI_D0);
633 pci_raw_set_power_state(dev, PCI_D0);
634 pci_update_current_state(dev, PCI_D0);
638 * pci_platform_power_transition - Use platform to change device power state
639 * @dev: PCI device to handle.
640 * @state: State to put the device into.
642 static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
646 if (platform_pci_power_manageable(dev)) {
647 error = platform_pci_set_power_state(dev, state);
649 pci_update_current_state(dev, state);
653 if (error && !dev->pm_cap) /* Fall back to PCI_D0 */
654 dev->current_state = PCI_D0;
660 * pci_wakeup - Wake up a PCI device
661 * @pci_dev: Device to handle.
662 * @ign: ignored parameter
664 static int pci_wakeup(struct pci_dev *pci_dev, void *ign)
666 pci_wakeup_event(pci_dev);
667 pm_request_resume(&pci_dev->dev);
672 * pci_wakeup_bus - Walk given bus and wake up devices on it
673 * @bus: Top bus of the subtree to walk.
675 static void pci_wakeup_bus(struct pci_bus *bus)
678 pci_walk_bus(bus, pci_wakeup, NULL);
682 * __pci_start_power_transition - Start power transition of a PCI device
683 * @dev: PCI device to handle.
684 * @state: State to put the device into.
686 static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
688 if (state == PCI_D0) {
689 pci_platform_power_transition(dev, PCI_D0);
691 * Mandatory power management transition delays, see
692 * PCI Express Base Specification Revision 2.0 Section
693 * 6.6.1: Conventional Reset. Do not delay for
694 * devices powered on/off by corresponding bridge,
695 * because have already delayed for the bridge.
697 if (dev->runtime_d3cold) {
698 msleep(dev->d3cold_delay);
700 * When powering on a bridge from D3cold, the
701 * whole hierarchy may be powered on into
702 * D0uninitialized state, resume them to give
703 * them a chance to suspend again
705 pci_wakeup_bus(dev->subordinate);
711 * __pci_dev_set_current_state - Set current state of a PCI device
712 * @dev: Device to handle
713 * @data: pointer to state to be set
715 static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
717 pci_power_t state = *(pci_power_t *)data;
719 dev->current_state = state;
724 * __pci_bus_set_current_state - Walk given bus and set current state of devices
725 * @bus: Top bus of the subtree to walk.
726 * @state: state to be set
728 static void __pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
731 pci_walk_bus(bus, __pci_dev_set_current_state, &state);
735 * __pci_complete_power_transition - Complete power transition of a PCI device
736 * @dev: PCI device to handle.
737 * @state: State to put the device into.
739 * This function should not be called directly by device drivers.
741 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
747 ret = pci_platform_power_transition(dev, state);
748 /* Power off the bridge may power off the whole hierarchy */
749 if (!ret && state == PCI_D3cold)
750 __pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
753 EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
756 * pci_set_power_state - Set the power state of a PCI device
757 * @dev: PCI device to handle.
758 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
760 * Transition a device to a new power state, using the platform firmware and/or
761 * the device's PCI PM registers.
764 * -EINVAL if the requested state is invalid.
765 * -EIO if device does not support PCI PM or its PM capabilities register has a
766 * wrong version, or device doesn't support the requested state.
767 * 0 if device already is in the requested state.
768 * 0 if device's power state has been successfully changed.
770 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
774 /* bound the state we're entering */
775 if (state > PCI_D3cold)
777 else if (state < PCI_D0)
779 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
781 * If the device or the parent bridge do not support PCI PM,
782 * ignore the request if we're doing anything other than putting
783 * it into D0 (which would only happen on boot).
787 /* Check if we're already there */
788 if (dev->current_state == state)
791 __pci_start_power_transition(dev, state);
793 /* This device is quirked not to be put into D3, so
794 don't put it in D3 */
795 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
799 * To put device in D3cold, we put device into D3hot in native
800 * way, then put device into D3cold with platform ops
802 error = pci_raw_set_power_state(dev, state > PCI_D3hot ?
805 if (!__pci_complete_power_transition(dev, state))
808 * When aspm_policy is "powersave" this call ensures
809 * that ASPM is configured.
811 if (!error && dev->bus->self)
812 pcie_aspm_powersave_config_link(dev->bus->self);
818 * pci_choose_state - Choose the power state of a PCI device
819 * @dev: PCI device to be suspended
820 * @state: target sleep state for the whole system. This is the value
821 * that is passed to suspend() function.
823 * Returns PCI power state suitable for given device and given system
827 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
834 ret = platform_pci_choose_state(dev);
835 if (ret != PCI_POWER_ERROR)
838 switch (state.event) {
841 case PM_EVENT_FREEZE:
842 case PM_EVENT_PRETHAW:
843 /* REVISIT both freeze and pre-thaw "should" use D0 */
844 case PM_EVENT_SUSPEND:
845 case PM_EVENT_HIBERNATE:
848 dev_info(&dev->dev, "unrecognized suspend event %d\n",
855 EXPORT_SYMBOL(pci_choose_state);
857 #define PCI_EXP_SAVE_REGS 7
860 static struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *pci_dev,
863 struct pci_cap_saved_state *tmp;
865 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) {
866 if (tmp->cap.cap_nr == cap)
872 static int pci_save_pcie_state(struct pci_dev *dev)
875 struct pci_cap_saved_state *save_state;
878 if (!pci_is_pcie(dev))
881 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
883 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
887 cap = (u16 *)&save_state->cap.data[0];
888 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
889 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
890 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
891 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
892 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
893 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
894 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
899 static void pci_restore_pcie_state(struct pci_dev *dev)
902 struct pci_cap_saved_state *save_state;
905 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
909 cap = (u16 *)&save_state->cap.data[0];
910 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
911 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
912 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
913 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
914 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
915 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
916 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
920 static int pci_save_pcix_state(struct pci_dev *dev)
923 struct pci_cap_saved_state *save_state;
925 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
929 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
931 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
935 pci_read_config_word(dev, pos + PCI_X_CMD,
936 (u16 *)save_state->cap.data);
941 static void pci_restore_pcix_state(struct pci_dev *dev)
944 struct pci_cap_saved_state *save_state;
947 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
948 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
949 if (!save_state || pos <= 0)
951 cap = (u16 *)&save_state->cap.data[0];
953 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
958 * pci_save_state - save the PCI configuration space of a device before suspending
959 * @dev: - PCI device that we're dealing with
962 pci_save_state(struct pci_dev *dev)
965 /* XXX: 100% dword access ok here? */
966 for (i = 0; i < 16; i++)
967 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
968 dev->state_saved = true;
969 if ((i = pci_save_pcie_state(dev)) != 0)
971 if ((i = pci_save_pcix_state(dev)) != 0)
976 static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
977 u32 saved_val, int retry)
981 pci_read_config_dword(pdev, offset, &val);
982 if (val == saved_val)
986 dev_dbg(&pdev->dev, "restoring config space at offset "
987 "%#x (was %#x, writing %#x)\n", offset, val, saved_val);
988 pci_write_config_dword(pdev, offset, saved_val);
992 pci_read_config_dword(pdev, offset, &val);
993 if (val == saved_val)
1000 static void pci_restore_config_space_range(struct pci_dev *pdev,
1001 int start, int end, int retry)
1005 for (index = end; index >= start; index--)
1006 pci_restore_config_dword(pdev, 4 * index,
1007 pdev->saved_config_space[index],
1011 static void pci_restore_config_space(struct pci_dev *pdev)
1013 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
1014 pci_restore_config_space_range(pdev, 10, 15, 0);
1015 /* Restore BARs before the command register. */
1016 pci_restore_config_space_range(pdev, 4, 9, 10);
1017 pci_restore_config_space_range(pdev, 0, 3, 0);
1019 pci_restore_config_space_range(pdev, 0, 15, 0);
1024 * pci_restore_state - Restore the saved state of a PCI device
1025 * @dev: - PCI device that we're dealing with
1027 void pci_restore_state(struct pci_dev *dev)
1029 if (!dev->state_saved)
1032 /* PCI Express register must be restored first */
1033 pci_restore_pcie_state(dev);
1034 pci_restore_ats_state(dev);
1036 pci_restore_config_space(dev);
1038 pci_restore_pcix_state(dev);
1039 pci_restore_msi_state(dev);
1040 pci_restore_iov_state(dev);
1042 dev->state_saved = false;
1045 struct pci_saved_state {
1046 u32 config_space[16];
1047 struct pci_cap_saved_data cap[0];
1051 * pci_store_saved_state - Allocate and return an opaque struct containing
1052 * the device saved state.
1053 * @dev: PCI device that we're dealing with
1055 * Return NULL if no state or error.
1057 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
1059 struct pci_saved_state *state;
1060 struct pci_cap_saved_state *tmp;
1061 struct pci_cap_saved_data *cap;
1064 if (!dev->state_saved)
1067 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1069 hlist_for_each_entry(tmp, &dev->saved_cap_space, next)
1070 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1072 state = kzalloc(size, GFP_KERNEL);
1076 memcpy(state->config_space, dev->saved_config_space,
1077 sizeof(state->config_space));
1080 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) {
1081 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1082 memcpy(cap, &tmp->cap, len);
1083 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1085 /* Empty cap_save terminates list */
1089 EXPORT_SYMBOL_GPL(pci_store_saved_state);
1092 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1093 * @dev: PCI device that we're dealing with
1094 * @state: Saved state returned from pci_store_saved_state()
1096 static int pci_load_saved_state(struct pci_dev *dev,
1097 struct pci_saved_state *state)
1099 struct pci_cap_saved_data *cap;
1101 dev->state_saved = false;
1106 memcpy(dev->saved_config_space, state->config_space,
1107 sizeof(state->config_space));
1111 struct pci_cap_saved_state *tmp;
1113 tmp = pci_find_saved_cap(dev, cap->cap_nr);
1114 if (!tmp || tmp->cap.size != cap->size)
1117 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1118 cap = (struct pci_cap_saved_data *)((u8 *)cap +
1119 sizeof(struct pci_cap_saved_data) + cap->size);
1122 dev->state_saved = true;
1127 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1128 * and free the memory allocated for it.
1129 * @dev: PCI device that we're dealing with
1130 * @state: Pointer to saved state returned from pci_store_saved_state()
1132 int pci_load_and_free_saved_state(struct pci_dev *dev,
1133 struct pci_saved_state **state)
1135 int ret = pci_load_saved_state(dev, *state);
1140 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1142 static int do_pci_enable_device(struct pci_dev *dev, int bars)
1146 err = pci_set_power_state(dev, PCI_D0);
1147 if (err < 0 && err != -EIO)
1149 err = pcibios_enable_device(dev, bars);
1152 pci_fixup_device(pci_fixup_enable, dev);
1158 * pci_reenable_device - Resume abandoned device
1159 * @dev: PCI device to be resumed
1161 * Note this function is a backend of pci_default_resume and is not supposed
1162 * to be called by normal code, write proper resume handler and use it instead.
1164 int pci_reenable_device(struct pci_dev *dev)
1166 if (pci_is_enabled(dev))
1167 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1171 static void pci_enable_bridge(struct pci_dev *dev)
1173 struct pci_dev *bridge;
1176 bridge = pci_upstream_bridge(dev);
1178 pci_enable_bridge(bridge);
1180 if (pci_is_enabled(dev)) {
1181 if (!dev->is_busmaster)
1182 pci_set_master(dev);
1186 retval = pci_enable_device(dev);
1188 dev_err(&dev->dev, "Error enabling bridge (%d), continuing\n",
1190 pci_set_master(dev);
1193 static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
1195 struct pci_dev *bridge;
1200 * Power state could be unknown at this point, either due to a fresh
1201 * boot or a device removal call. So get the current power state
1202 * so that things like MSI message writing will behave as expected
1203 * (e.g. if the device really is in D0 at enable time).
1207 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1208 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1211 if (atomic_inc_return(&dev->enable_cnt) > 1)
1212 return 0; /* already enabled */
1214 bridge = pci_upstream_bridge(dev);
1216 pci_enable_bridge(bridge);
1218 /* only skip sriov related */
1219 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
1220 if (dev->resource[i].flags & flags)
1222 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
1223 if (dev->resource[i].flags & flags)
1226 err = do_pci_enable_device(dev, bars);
1228 atomic_dec(&dev->enable_cnt);
1233 * pci_enable_device_io - Initialize a device for use with IO space
1234 * @dev: PCI device to be initialized
1236 * Initialize device before it's used by a driver. Ask low-level code
1237 * to enable I/O resources. Wake up the device if it was suspended.
1238 * Beware, this function can fail.
1240 int pci_enable_device_io(struct pci_dev *dev)
1242 return pci_enable_device_flags(dev, IORESOURCE_IO);
1246 * pci_enable_device_mem - Initialize a device for use with Memory space
1247 * @dev: PCI device to be initialized
1249 * Initialize device before it's used by a driver. Ask low-level code
1250 * to enable Memory resources. Wake up the device if it was suspended.
1251 * Beware, this function can fail.
1253 int pci_enable_device_mem(struct pci_dev *dev)
1255 return pci_enable_device_flags(dev, IORESOURCE_MEM);
1259 * pci_enable_device - Initialize device before it's used by a driver.
1260 * @dev: PCI device to be initialized
1262 * Initialize device before it's used by a driver. Ask low-level code
1263 * to enable I/O and memory. Wake up the device if it was suspended.
1264 * Beware, this function can fail.
1266 * Note we don't actually enable the device many times if we call
1267 * this function repeatedly (we just increment the count).
1269 int pci_enable_device(struct pci_dev *dev)
1271 return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
1275 * Managed PCI resources. This manages device on/off, intx/msi/msix
1276 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1277 * there's no need to track it separately. pci_devres is initialized
1278 * when a device is enabled using managed PCI device enable interface.
1281 unsigned int enabled:1;
1282 unsigned int pinned:1;
1283 unsigned int orig_intx:1;
1284 unsigned int restore_intx:1;
1288 static void pcim_release(struct device *gendev, void *res)
1290 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
1291 struct pci_devres *this = res;
1294 if (dev->msi_enabled)
1295 pci_disable_msi(dev);
1296 if (dev->msix_enabled)
1297 pci_disable_msix(dev);
1299 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1300 if (this->region_mask & (1 << i))
1301 pci_release_region(dev, i);
1303 if (this->restore_intx)
1304 pci_intx(dev, this->orig_intx);
1306 if (this->enabled && !this->pinned)
1307 pci_disable_device(dev);
1310 static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
1312 struct pci_devres *dr, *new_dr;
1314 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1318 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1321 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1324 static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
1326 if (pci_is_managed(pdev))
1327 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1332 * pcim_enable_device - Managed pci_enable_device()
1333 * @pdev: PCI device to be initialized
1335 * Managed pci_enable_device().
1337 int pcim_enable_device(struct pci_dev *pdev)
1339 struct pci_devres *dr;
1342 dr = get_pci_dr(pdev);
1348 rc = pci_enable_device(pdev);
1350 pdev->is_managed = 1;
1357 * pcim_pin_device - Pin managed PCI device
1358 * @pdev: PCI device to pin
1360 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1361 * driver detach. @pdev must have been enabled with
1362 * pcim_enable_device().
1364 void pcim_pin_device(struct pci_dev *pdev)
1366 struct pci_devres *dr;
1368 dr = find_pci_dr(pdev);
1369 WARN_ON(!dr || !dr->enabled);
1375 * pcibios_add_device - provide arch specific hooks when adding device dev
1376 * @dev: the PCI device being added
1378 * Permits the platform to provide architecture specific functionality when
1379 * devices are added. This is the default implementation. Architecture
1380 * implementations can override this.
1382 int __weak pcibios_add_device (struct pci_dev *dev)
1388 * pcibios_release_device - provide arch specific hooks when releasing device dev
1389 * @dev: the PCI device being released
1391 * Permits the platform to provide architecture specific functionality when
1392 * devices are released. This is the default implementation. Architecture
1393 * implementations can override this.
1395 void __weak pcibios_release_device(struct pci_dev *dev) {}
1398 * pcibios_disable_device - disable arch specific PCI resources for device dev
1399 * @dev: the PCI device to disable
1401 * Disables architecture specific PCI resources for the device. This
1402 * is the default implementation. Architecture implementations can
1405 void __weak pcibios_disable_device (struct pci_dev *dev) {}
1407 static void do_pci_disable_device(struct pci_dev *dev)
1411 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1412 if (pci_command & PCI_COMMAND_MASTER) {
1413 pci_command &= ~PCI_COMMAND_MASTER;
1414 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1417 pcibios_disable_device(dev);
1421 * pci_disable_enabled_device - Disable device without updating enable_cnt
1422 * @dev: PCI device to disable
1424 * NOTE: This function is a backend of PCI power management routines and is
1425 * not supposed to be called drivers.
1427 void pci_disable_enabled_device(struct pci_dev *dev)
1429 if (pci_is_enabled(dev))
1430 do_pci_disable_device(dev);
1434 * pci_disable_device - Disable PCI device after use
1435 * @dev: PCI device to be disabled
1437 * Signal to the system that the PCI device is not in use by the system
1438 * anymore. This only involves disabling PCI bus-mastering, if active.
1440 * Note we don't actually disable the device until all callers of
1441 * pci_enable_device() have called pci_disable_device().
1444 pci_disable_device(struct pci_dev *dev)
1446 struct pci_devres *dr;
1448 dr = find_pci_dr(dev);
1452 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0,
1453 "disabling already-disabled device");
1455 if (atomic_dec_return(&dev->enable_cnt) != 0)
1458 do_pci_disable_device(dev);
1460 dev->is_busmaster = 0;
1464 * pcibios_set_pcie_reset_state - set reset state for device dev
1465 * @dev: the PCIe device reset
1466 * @state: Reset state to enter into
1469 * Sets the PCIe reset state for the device. This is the default
1470 * implementation. Architecture implementations can override this.
1472 int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
1473 enum pcie_reset_state state)
1479 * pci_set_pcie_reset_state - set reset state for device dev
1480 * @dev: the PCIe device reset
1481 * @state: Reset state to enter into
1484 * Sets the PCI reset state for the device.
1486 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1488 return pcibios_set_pcie_reset_state(dev, state);
1492 * pci_check_pme_status - Check if given device has generated PME.
1493 * @dev: Device to check.
1495 * Check the PME status of the device and if set, clear it and clear PME enable
1496 * (if set). Return 'true' if PME status and PME enable were both set or
1497 * 'false' otherwise.
1499 bool pci_check_pme_status(struct pci_dev *dev)
1508 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
1509 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
1510 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
1513 /* Clear PME status. */
1514 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1515 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
1516 /* Disable PME to avoid interrupt flood. */
1517 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1521 pci_write_config_word(dev, pmcsr_pos, pmcsr);
1527 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1528 * @dev: Device to handle.
1529 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
1531 * Check if @dev has generated PME and queue a resume request for it in that
1534 static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
1536 if (pme_poll_reset && dev->pme_poll)
1537 dev->pme_poll = false;
1539 if (pci_check_pme_status(dev)) {
1540 pci_wakeup_event(dev);
1541 pm_request_resume(&dev->dev);
1547 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1548 * @bus: Top bus of the subtree to walk.
1550 void pci_pme_wakeup_bus(struct pci_bus *bus)
1553 pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
1558 * pci_pme_capable - check the capability of PCI device to generate PME#
1559 * @dev: PCI device to handle.
1560 * @state: PCI state from which device will issue PME#.
1562 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
1567 return !!(dev->pme_support & (1 << state));
1570 static void pci_pme_list_scan(struct work_struct *work)
1572 struct pci_pme_device *pme_dev, *n;
1574 mutex_lock(&pci_pme_list_mutex);
1575 if (!list_empty(&pci_pme_list)) {
1576 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
1577 if (pme_dev->dev->pme_poll) {
1578 struct pci_dev *bridge;
1580 bridge = pme_dev->dev->bus->self;
1582 * If bridge is in low power state, the
1583 * configuration space of subordinate devices
1584 * may be not accessible
1586 if (bridge && bridge->current_state != PCI_D0)
1588 pci_pme_wakeup(pme_dev->dev, NULL);
1590 list_del(&pme_dev->list);
1594 if (!list_empty(&pci_pme_list))
1595 schedule_delayed_work(&pci_pme_work,
1596 msecs_to_jiffies(PME_TIMEOUT));
1598 mutex_unlock(&pci_pme_list_mutex);
1602 * pci_pme_active - enable or disable PCI device's PME# function
1603 * @dev: PCI device to handle.
1604 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1606 * The caller must verify that the device is capable of generating PME# before
1607 * calling this function with @enable equal to 'true'.
1609 void pci_pme_active(struct pci_dev *dev, bool enable)
1613 if (!dev->pme_support)
1616 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1617 /* Clear PME_Status by writing 1 to it and enable PME# */
1618 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1620 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1622 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1625 * PCI (as opposed to PCIe) PME requires that the device have
1626 * its PME# line hooked up correctly. Not all hardware vendors
1627 * do this, so the PME never gets delivered and the device
1628 * remains asleep. The easiest way around this is to
1629 * periodically walk the list of suspended devices and check
1630 * whether any have their PME flag set. The assumption is that
1631 * we'll wake up often enough anyway that this won't be a huge
1632 * hit, and the power savings from the devices will still be a
1635 * Although PCIe uses in-band PME message instead of PME# line
1636 * to report PME, PME does not work for some PCIe devices in
1637 * reality. For example, there are devices that set their PME
1638 * status bits, but don't really bother to send a PME message;
1639 * there are PCI Express Root Ports that don't bother to
1640 * trigger interrupts when they receive PME messages from the
1641 * devices below. So PME poll is used for PCIe devices too.
1644 if (dev->pme_poll) {
1645 struct pci_pme_device *pme_dev;
1647 pme_dev = kmalloc(sizeof(struct pci_pme_device),
1650 dev_warn(&dev->dev, "can't enable PME#\n");
1654 mutex_lock(&pci_pme_list_mutex);
1655 list_add(&pme_dev->list, &pci_pme_list);
1656 if (list_is_singular(&pci_pme_list))
1657 schedule_delayed_work(&pci_pme_work,
1658 msecs_to_jiffies(PME_TIMEOUT));
1659 mutex_unlock(&pci_pme_list_mutex);
1661 mutex_lock(&pci_pme_list_mutex);
1662 list_for_each_entry(pme_dev, &pci_pme_list, list) {
1663 if (pme_dev->dev == dev) {
1664 list_del(&pme_dev->list);
1669 mutex_unlock(&pci_pme_list_mutex);
1673 dev_dbg(&dev->dev, "PME# %s\n", enable ? "enabled" : "disabled");
1677 * __pci_enable_wake - enable PCI device as wakeup event source
1678 * @dev: PCI device affected
1679 * @state: PCI state from which device will issue wakeup events
1680 * @runtime: True if the events are to be generated at run time
1681 * @enable: True to enable event generation; false to disable
1683 * This enables the device as a wakeup event source, or disables it.
1684 * When such events involves platform-specific hooks, those hooks are
1685 * called automatically by this routine.
1687 * Devices with legacy power management (no standard PCI PM capabilities)
1688 * always require such platform hooks.
1691 * 0 is returned on success
1692 * -EINVAL is returned if device is not supposed to wake up the system
1693 * Error code depending on the platform is returned if both the platform and
1694 * the native mechanism fail to enable the generation of wake-up events
1696 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1697 bool runtime, bool enable)
1701 if (enable && !runtime && !device_may_wakeup(&dev->dev))
1704 /* Don't do the same thing twice in a row for one device. */
1705 if (!!enable == !!dev->wakeup_prepared)
1709 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1710 * Anderson we should be doing PME# wake enable followed by ACPI wake
1711 * enable. To disable wake-up we call the platform first, for symmetry.
1717 if (pci_pme_capable(dev, state))
1718 pci_pme_active(dev, true);
1721 error = runtime ? platform_pci_run_wake(dev, true) :
1722 platform_pci_sleep_wake(dev, true);
1726 dev->wakeup_prepared = true;
1729 platform_pci_run_wake(dev, false);
1731 platform_pci_sleep_wake(dev, false);
1732 pci_pme_active(dev, false);
1733 dev->wakeup_prepared = false;
1738 EXPORT_SYMBOL(__pci_enable_wake);
1741 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1742 * @dev: PCI device to prepare
1743 * @enable: True to enable wake-up event generation; false to disable
1745 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1746 * and this function allows them to set that up cleanly - pci_enable_wake()
1747 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1748 * ordering constraints.
1750 * This function only returns error code if the device is not capable of
1751 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1752 * enable wake-up power for it.
1754 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1756 return pci_pme_capable(dev, PCI_D3cold) ?
1757 pci_enable_wake(dev, PCI_D3cold, enable) :
1758 pci_enable_wake(dev, PCI_D3hot, enable);
1762 * pci_target_state - find an appropriate low power state for a given PCI dev
1765 * Use underlying platform code to find a supported low power state for @dev.
1766 * If the platform can't manage @dev, return the deepest state from which it
1767 * can generate wake events, based on any available PME info.
1769 static pci_power_t pci_target_state(struct pci_dev *dev)
1771 pci_power_t target_state = PCI_D3hot;
1773 if (platform_pci_power_manageable(dev)) {
1775 * Call the platform to choose the target state of the device
1776 * and enable wake-up from this state if supported.
1778 pci_power_t state = platform_pci_choose_state(dev);
1781 case PCI_POWER_ERROR:
1786 if (pci_no_d1d2(dev))
1789 target_state = state;
1791 } else if (!dev->pm_cap) {
1792 target_state = PCI_D0;
1793 } else if (device_may_wakeup(&dev->dev)) {
1795 * Find the deepest state from which the device can generate
1796 * wake-up events, make it the target state and enable device
1799 if (dev->pme_support) {
1801 && !(dev->pme_support & (1 << target_state)))
1806 return target_state;
1810 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1811 * @dev: Device to handle.
1813 * Choose the power state appropriate for the device depending on whether
1814 * it can wake up the system and/or is power manageable by the platform
1815 * (PCI_D3hot is the default) and put the device into that state.
1817 int pci_prepare_to_sleep(struct pci_dev *dev)
1819 pci_power_t target_state = pci_target_state(dev);
1822 if (target_state == PCI_POWER_ERROR)
1825 /* D3cold during system suspend/hibernate is not supported */
1826 if (target_state > PCI_D3hot)
1827 target_state = PCI_D3hot;
1829 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
1831 error = pci_set_power_state(dev, target_state);
1834 pci_enable_wake(dev, target_state, false);
1840 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
1841 * @dev: Device to handle.
1843 * Disable device's system wake-up capability and put it into D0.
1845 int pci_back_from_sleep(struct pci_dev *dev)
1847 pci_enable_wake(dev, PCI_D0, false);
1848 return pci_set_power_state(dev, PCI_D0);
1852 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
1853 * @dev: PCI device being suspended.
1855 * Prepare @dev to generate wake-up events at run time and put it into a low
1858 int pci_finish_runtime_suspend(struct pci_dev *dev)
1860 pci_power_t target_state = pci_target_state(dev);
1863 if (target_state == PCI_POWER_ERROR)
1866 dev->runtime_d3cold = target_state == PCI_D3cold;
1868 __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev));
1870 error = pci_set_power_state(dev, target_state);
1873 __pci_enable_wake(dev, target_state, true, false);
1874 dev->runtime_d3cold = false;
1881 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
1882 * @dev: Device to check.
1884 * Return true if the device itself is capable of generating wake-up events
1885 * (through the platform or using the native PCIe PME) or if the device supports
1886 * PME and one of its upstream bridges can generate wake-up events.
1888 bool pci_dev_run_wake(struct pci_dev *dev)
1890 struct pci_bus *bus = dev->bus;
1892 if (device_run_wake(&dev->dev))
1895 if (!dev->pme_support)
1898 while (bus->parent) {
1899 struct pci_dev *bridge = bus->self;
1901 if (device_run_wake(&bridge->dev))
1907 /* We have reached the root bus. */
1909 return device_run_wake(bus->bridge);
1913 EXPORT_SYMBOL_GPL(pci_dev_run_wake);
1915 void pci_config_pm_runtime_get(struct pci_dev *pdev)
1917 struct device *dev = &pdev->dev;
1918 struct device *parent = dev->parent;
1921 pm_runtime_get_sync(parent);
1922 pm_runtime_get_noresume(dev);
1924 * pdev->current_state is set to PCI_D3cold during suspending,
1925 * so wait until suspending completes
1927 pm_runtime_barrier(dev);
1929 * Only need to resume devices in D3cold, because config
1930 * registers are still accessible for devices suspended but
1933 if (pdev->current_state == PCI_D3cold)
1934 pm_runtime_resume(dev);
1937 void pci_config_pm_runtime_put(struct pci_dev *pdev)
1939 struct device *dev = &pdev->dev;
1940 struct device *parent = dev->parent;
1942 pm_runtime_put(dev);
1944 pm_runtime_put_sync(parent);
1948 * pci_pm_init - Initialize PM functions of given PCI device
1949 * @dev: PCI device to handle.
1951 void pci_pm_init(struct pci_dev *dev)
1956 pm_runtime_forbid(&dev->dev);
1957 pm_runtime_set_active(&dev->dev);
1958 pm_runtime_enable(&dev->dev);
1959 device_enable_async_suspend(&dev->dev);
1960 dev->wakeup_prepared = false;
1963 dev->pme_support = 0;
1965 /* find PCI PM capability in list */
1966 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1969 /* Check device's ability to generate PME# */
1970 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
1972 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
1973 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
1974 pmc & PCI_PM_CAP_VER_MASK);
1979 dev->d3_delay = PCI_PM_D3_WAIT;
1980 dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
1981 dev->d3cold_allowed = true;
1983 dev->d1_support = false;
1984 dev->d2_support = false;
1985 if (!pci_no_d1d2(dev)) {
1986 if (pmc & PCI_PM_CAP_D1)
1987 dev->d1_support = true;
1988 if (pmc & PCI_PM_CAP_D2)
1989 dev->d2_support = true;
1991 if (dev->d1_support || dev->d2_support)
1992 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
1993 dev->d1_support ? " D1" : "",
1994 dev->d2_support ? " D2" : "");
1997 pmc &= PCI_PM_CAP_PME_MASK;
1999 dev_printk(KERN_DEBUG, &dev->dev,
2000 "PME# supported from%s%s%s%s%s\n",
2001 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
2002 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
2003 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
2004 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
2005 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
2006 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
2007 dev->pme_poll = true;
2009 * Make device's PM flags reflect the wake-up capability, but
2010 * let the user space enable it to wake up the system as needed.
2012 device_set_wakeup_capable(&dev->dev, true);
2013 /* Disable the PME# generation functionality */
2014 pci_pme_active(dev, false);
2018 static void pci_add_saved_cap(struct pci_dev *pci_dev,
2019 struct pci_cap_saved_state *new_cap)
2021 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
2025 * pci_add_cap_save_buffer - allocate buffer for saving given capability registers
2026 * @dev: the PCI device
2027 * @cap: the capability to allocate the buffer for
2028 * @size: requested size of the buffer
2030 static int pci_add_cap_save_buffer(
2031 struct pci_dev *dev, char cap, unsigned int size)
2034 struct pci_cap_saved_state *save_state;
2036 pos = pci_find_capability(dev, cap);
2040 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
2044 save_state->cap.cap_nr = cap;
2045 save_state->cap.size = size;
2046 pci_add_saved_cap(dev, save_state);
2052 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
2053 * @dev: the PCI device
2055 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
2059 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
2060 PCI_EXP_SAVE_REGS * sizeof(u16));
2063 "unable to preallocate PCI Express save buffer\n");
2065 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
2068 "unable to preallocate PCI-X save buffer\n");
2071 void pci_free_cap_save_buffers(struct pci_dev *dev)
2073 struct pci_cap_saved_state *tmp;
2074 struct hlist_node *n;
2076 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next)
2081 * pci_configure_ari - enable or disable ARI forwarding
2082 * @dev: the PCI device
2084 * If @dev and its upstream bridge both support ARI, enable ARI in the
2085 * bridge. Otherwise, disable ARI in the bridge.
2087 void pci_configure_ari(struct pci_dev *dev)
2090 struct pci_dev *bridge;
2092 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
2095 bridge = dev->bus->self;
2099 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
2100 if (!(cap & PCI_EXP_DEVCAP2_ARI))
2103 if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) {
2104 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
2105 PCI_EXP_DEVCTL2_ARI);
2106 bridge->ari_enabled = 1;
2108 pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2,
2109 PCI_EXP_DEVCTL2_ARI);
2110 bridge->ari_enabled = 0;
2114 static int pci_acs_enable;
2117 * pci_request_acs - ask for ACS to be enabled if supported
2119 void pci_request_acs(void)
2125 * pci_enable_acs - enable ACS if hardware support it
2126 * @dev: the PCI device
2128 void pci_enable_acs(struct pci_dev *dev)
2134 if (!pci_acs_enable)
2137 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
2141 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
2142 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
2144 /* Source Validation */
2145 ctrl |= (cap & PCI_ACS_SV);
2147 /* P2P Request Redirect */
2148 ctrl |= (cap & PCI_ACS_RR);
2150 /* P2P Completion Redirect */
2151 ctrl |= (cap & PCI_ACS_CR);
2153 /* Upstream Forwarding */
2154 ctrl |= (cap & PCI_ACS_UF);
2156 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
2159 static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags)
2164 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS);
2169 * Except for egress control, capabilities are either required
2170 * or only required if controllable. Features missing from the
2171 * capability field can therefore be assumed as hard-wired enabled.
2173 pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap);
2174 acs_flags &= (cap | PCI_ACS_EC);
2176 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
2177 return (ctrl & acs_flags) == acs_flags;
2181 * pci_acs_enabled - test ACS against required flags for a given device
2182 * @pdev: device to test
2183 * @acs_flags: required PCI ACS flags
2185 * Return true if the device supports the provided flags. Automatically
2186 * filters out flags that are not implemented on multifunction devices.
2188 * Note that this interface checks the effective ACS capabilities of the
2189 * device rather than the actual capabilities. For instance, most single
2190 * function endpoints are not required to support ACS because they have no
2191 * opportunity for peer-to-peer access. We therefore return 'true'
2192 * regardless of whether the device exposes an ACS capability. This makes
2193 * it much easier for callers of this function to ignore the actual type
2194 * or topology of the device when testing ACS support.
2196 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
2200 ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
2205 * Conventional PCI and PCI-X devices never support ACS, either
2206 * effectively or actually. The shared bus topology implies that
2207 * any device on the bus can receive or snoop DMA.
2209 if (!pci_is_pcie(pdev))
2212 switch (pci_pcie_type(pdev)) {
2214 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
2215 * but since their primary interface is PCI/X, we conservatively
2216 * handle them as we would a non-PCIe device.
2218 case PCI_EXP_TYPE_PCIE_BRIDGE:
2220 * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never
2221 * applicable... must never implement an ACS Extended Capability...".
2222 * This seems arbitrary, but we take a conservative interpretation
2223 * of this statement.
2225 case PCI_EXP_TYPE_PCI_BRIDGE:
2226 case PCI_EXP_TYPE_RC_EC:
2229 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should
2230 * implement ACS in order to indicate their peer-to-peer capabilities,
2231 * regardless of whether they are single- or multi-function devices.
2233 case PCI_EXP_TYPE_DOWNSTREAM:
2234 case PCI_EXP_TYPE_ROOT_PORT:
2235 return pci_acs_flags_enabled(pdev, acs_flags);
2237 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
2238 * implemented by the remaining PCIe types to indicate peer-to-peer
2239 * capabilities, but only when they are part of a multifunction
2240 * device. The footnote for section 6.12 indicates the specific
2241 * PCIe types included here.
2243 case PCI_EXP_TYPE_ENDPOINT:
2244 case PCI_EXP_TYPE_UPSTREAM:
2245 case PCI_EXP_TYPE_LEG_END:
2246 case PCI_EXP_TYPE_RC_END:
2247 if (!pdev->multifunction)
2250 return pci_acs_flags_enabled(pdev, acs_flags);
2254 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable
2255 * to single function devices with the exception of downstream ports.
2261 * pci_acs_path_enable - test ACS flags from start to end in a hierarchy
2262 * @start: starting downstream device
2263 * @end: ending upstream device or NULL to search to the root bus
2264 * @acs_flags: required flags
2266 * Walk up a device tree from start to end testing PCI ACS support. If
2267 * any step along the way does not support the required flags, return false.
2269 bool pci_acs_path_enabled(struct pci_dev *start,
2270 struct pci_dev *end, u16 acs_flags)
2272 struct pci_dev *pdev, *parent = start;
2277 if (!pci_acs_enabled(pdev, acs_flags))
2280 if (pci_is_root_bus(pdev->bus))
2281 return (end == NULL);
2283 parent = pdev->bus->self;
2284 } while (pdev != end);
2290 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
2291 * @dev: the PCI device
2292 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
2294 * Perform INTx swizzling for a device behind one level of bridge. This is
2295 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
2296 * behind bridges on add-in cards. For devices with ARI enabled, the slot
2297 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
2298 * the PCI Express Base Specification, Revision 2.1)
2300 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
2304 if (pci_ari_enabled(dev->bus))
2307 slot = PCI_SLOT(dev->devfn);
2309 return (((pin - 1) + slot) % 4) + 1;
2313 pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
2321 while (!pci_is_root_bus(dev->bus)) {
2322 pin = pci_swizzle_interrupt_pin(dev, pin);
2323 dev = dev->bus->self;
2330 * pci_common_swizzle - swizzle INTx all the way to root bridge
2331 * @dev: the PCI device
2332 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2334 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
2335 * bridges all the way up to a PCI root bus.
2337 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
2341 while (!pci_is_root_bus(dev->bus)) {
2342 pin = pci_swizzle_interrupt_pin(dev, pin);
2343 dev = dev->bus->self;
2346 return PCI_SLOT(dev->devfn);
2350 * pci_release_region - Release a PCI bar
2351 * @pdev: PCI device whose resources were previously reserved by pci_request_region
2352 * @bar: BAR to release
2354 * Releases the PCI I/O and memory resources previously reserved by a
2355 * successful call to pci_request_region. Call this function only
2356 * after all use of the PCI regions has ceased.
2358 void pci_release_region(struct pci_dev *pdev, int bar)
2360 struct pci_devres *dr;
2362 if (pci_resource_len(pdev, bar) == 0)
2364 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
2365 release_region(pci_resource_start(pdev, bar),
2366 pci_resource_len(pdev, bar));
2367 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
2368 release_mem_region(pci_resource_start(pdev, bar),
2369 pci_resource_len(pdev, bar));
2371 dr = find_pci_dr(pdev);
2373 dr->region_mask &= ~(1 << bar);
2377 * __pci_request_region - Reserved PCI I/O and memory resource
2378 * @pdev: PCI device whose resources are to be reserved
2379 * @bar: BAR to be reserved
2380 * @res_name: Name to be associated with resource.
2381 * @exclusive: whether the region access is exclusive or not
2383 * Mark the PCI region associated with PCI device @pdev BR @bar as
2384 * being reserved by owner @res_name. Do not access any
2385 * address inside the PCI regions unless this call returns
2388 * If @exclusive is set, then the region is marked so that userspace
2389 * is explicitly not allowed to map the resource via /dev/mem or
2390 * sysfs MMIO access.
2392 * Returns 0 on success, or %EBUSY on error. A warning
2393 * message is also printed on failure.
2395 static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name,
2398 struct pci_devres *dr;
2400 if (pci_resource_len(pdev, bar) == 0)
2403 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
2404 if (!request_region(pci_resource_start(pdev, bar),
2405 pci_resource_len(pdev, bar), res_name))
2408 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
2409 if (!__request_mem_region(pci_resource_start(pdev, bar),
2410 pci_resource_len(pdev, bar), res_name,
2415 dr = find_pci_dr(pdev);
2417 dr->region_mask |= 1 << bar;
2422 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar,
2423 &pdev->resource[bar]);
2428 * pci_request_region - Reserve PCI I/O and memory resource
2429 * @pdev: PCI device whose resources are to be reserved
2430 * @bar: BAR to be reserved
2431 * @res_name: Name to be associated with resource
2433 * Mark the PCI region associated with PCI device @pdev BAR @bar as
2434 * being reserved by owner @res_name. Do not access any
2435 * address inside the PCI regions unless this call returns
2438 * Returns 0 on success, or %EBUSY on error. A warning
2439 * message is also printed on failure.
2441 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
2443 return __pci_request_region(pdev, bar, res_name, 0);
2447 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
2448 * @pdev: PCI device whose resources are to be reserved
2449 * @bar: BAR to be reserved
2450 * @res_name: Name to be associated with resource.
2452 * Mark the PCI region associated with PCI device @pdev BR @bar as
2453 * being reserved by owner @res_name. Do not access any
2454 * address inside the PCI regions unless this call returns
2457 * Returns 0 on success, or %EBUSY on error. A warning
2458 * message is also printed on failure.
2460 * The key difference that _exclusive makes it that userspace is
2461 * explicitly not allowed to map the resource via /dev/mem or
2464 int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name)
2466 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
2469 * pci_release_selected_regions - Release selected PCI I/O and memory resources
2470 * @pdev: PCI device whose resources were previously reserved
2471 * @bars: Bitmask of BARs to be released
2473 * Release selected PCI I/O and memory resources previously reserved.
2474 * Call this function only after all use of the PCI regions has ceased.
2476 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
2480 for (i = 0; i < 6; i++)
2481 if (bars & (1 << i))
2482 pci_release_region(pdev, i);
2485 static int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
2486 const char *res_name, int excl)
2490 for (i = 0; i < 6; i++)
2491 if (bars & (1 << i))
2492 if (__pci_request_region(pdev, i, res_name, excl))
2498 if (bars & (1 << i))
2499 pci_release_region(pdev, i);
2506 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
2507 * @pdev: PCI device whose resources are to be reserved
2508 * @bars: Bitmask of BARs to be requested
2509 * @res_name: Name to be associated with resource
2511 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
2512 const char *res_name)
2514 return __pci_request_selected_regions(pdev, bars, res_name, 0);
2517 int pci_request_selected_regions_exclusive(struct pci_dev *pdev,
2518 int bars, const char *res_name)
2520 return __pci_request_selected_regions(pdev, bars, res_name,
2521 IORESOURCE_EXCLUSIVE);
2525 * pci_release_regions - Release reserved PCI I/O and memory resources
2526 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
2528 * Releases all PCI I/O and memory resources previously reserved by a
2529 * successful call to pci_request_regions. Call this function only
2530 * after all use of the PCI regions has ceased.
2533 void pci_release_regions(struct pci_dev *pdev)
2535 pci_release_selected_regions(pdev, (1 << 6) - 1);
2539 * pci_request_regions - Reserved PCI I/O and memory resources
2540 * @pdev: PCI device whose resources are to be reserved
2541 * @res_name: Name to be associated with resource.
2543 * Mark all PCI regions associated with PCI device @pdev as
2544 * being reserved by owner @res_name. Do not access any
2545 * address inside the PCI regions unless this call returns
2548 * Returns 0 on success, or %EBUSY on error. A warning
2549 * message is also printed on failure.
2551 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
2553 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
2557 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
2558 * @pdev: PCI device whose resources are to be reserved
2559 * @res_name: Name to be associated with resource.
2561 * Mark all PCI regions associated with PCI device @pdev as
2562 * being reserved by owner @res_name. Do not access any
2563 * address inside the PCI regions unless this call returns
2566 * pci_request_regions_exclusive() will mark the region so that
2567 * /dev/mem and the sysfs MMIO access will not be allowed.
2569 * Returns 0 on success, or %EBUSY on error. A warning
2570 * message is also printed on failure.
2572 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
2574 return pci_request_selected_regions_exclusive(pdev,
2575 ((1 << 6) - 1), res_name);
2578 static void __pci_set_master(struct pci_dev *dev, bool enable)
2582 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
2584 cmd = old_cmd | PCI_COMMAND_MASTER;
2586 cmd = old_cmd & ~PCI_COMMAND_MASTER;
2587 if (cmd != old_cmd) {
2588 dev_dbg(&dev->dev, "%s bus mastering\n",
2589 enable ? "enabling" : "disabling");
2590 pci_write_config_word(dev, PCI_COMMAND, cmd);
2592 dev->is_busmaster = enable;
2596 * pcibios_setup - process "pci=" kernel boot arguments
2597 * @str: string used to pass in "pci=" kernel boot arguments
2599 * Process kernel boot arguments. This is the default implementation.
2600 * Architecture specific implementations can override this as necessary.
2602 char * __weak __init pcibios_setup(char *str)
2608 * pcibios_set_master - enable PCI bus-mastering for device dev
2609 * @dev: the PCI device to enable
2611 * Enables PCI bus-mastering for the device. This is the default
2612 * implementation. Architecture specific implementations can override
2613 * this if necessary.
2615 void __weak pcibios_set_master(struct pci_dev *dev)
2619 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
2620 if (pci_is_pcie(dev))
2623 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
2625 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
2626 else if (lat > pcibios_max_latency)
2627 lat = pcibios_max_latency;
2631 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
2635 * pci_set_master - enables bus-mastering for device dev
2636 * @dev: the PCI device to enable
2638 * Enables bus-mastering on the device and calls pcibios_set_master()
2639 * to do the needed arch specific settings.
2641 void pci_set_master(struct pci_dev *dev)
2643 __pci_set_master(dev, true);
2644 pcibios_set_master(dev);
2648 * pci_clear_master - disables bus-mastering for device dev
2649 * @dev: the PCI device to disable
2651 void pci_clear_master(struct pci_dev *dev)
2653 __pci_set_master(dev, false);
2657 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
2658 * @dev: the PCI device for which MWI is to be enabled
2660 * Helper function for pci_set_mwi.
2661 * Originally copied from drivers/net/acenic.c.
2662 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
2664 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2666 int pci_set_cacheline_size(struct pci_dev *dev)
2670 if (!pci_cache_line_size)
2673 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
2674 equal to or multiple of the right value. */
2675 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2676 if (cacheline_size >= pci_cache_line_size &&
2677 (cacheline_size % pci_cache_line_size) == 0)
2680 /* Write the correct value. */
2681 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
2683 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2684 if (cacheline_size == pci_cache_line_size)
2687 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not "
2688 "supported\n", pci_cache_line_size << 2);
2692 EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
2694 #ifdef PCI_DISABLE_MWI
2695 int pci_set_mwi(struct pci_dev *dev)
2700 int pci_try_set_mwi(struct pci_dev *dev)
2705 void pci_clear_mwi(struct pci_dev *dev)
2712 * pci_set_mwi - enables memory-write-invalidate PCI transaction
2713 * @dev: the PCI device for which MWI is enabled
2715 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2717 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2720 pci_set_mwi(struct pci_dev *dev)
2725 rc = pci_set_cacheline_size(dev);
2729 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2730 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
2731 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
2732 cmd |= PCI_COMMAND_INVALIDATE;
2733 pci_write_config_word(dev, PCI_COMMAND, cmd);
2740 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
2741 * @dev: the PCI device for which MWI is enabled
2743 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2744 * Callers are not required to check the return value.
2746 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2748 int pci_try_set_mwi(struct pci_dev *dev)
2750 int rc = pci_set_mwi(dev);
2755 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
2756 * @dev: the PCI device to disable
2758 * Disables PCI Memory-Write-Invalidate transaction on the device
2761 pci_clear_mwi(struct pci_dev *dev)
2765 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2766 if (cmd & PCI_COMMAND_INVALIDATE) {
2767 cmd &= ~PCI_COMMAND_INVALIDATE;
2768 pci_write_config_word(dev, PCI_COMMAND, cmd);
2771 #endif /* ! PCI_DISABLE_MWI */
2774 * pci_intx - enables/disables PCI INTx for device dev
2775 * @pdev: the PCI device to operate on
2776 * @enable: boolean: whether to enable or disable PCI INTx
2778 * Enables/disables PCI INTx for device dev
2781 pci_intx(struct pci_dev *pdev, int enable)
2783 u16 pci_command, new;
2785 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
2788 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
2790 new = pci_command | PCI_COMMAND_INTX_DISABLE;
2793 if (new != pci_command) {
2794 struct pci_devres *dr;
2796 pci_write_config_word(pdev, PCI_COMMAND, new);
2798 dr = find_pci_dr(pdev);
2799 if (dr && !dr->restore_intx) {
2800 dr->restore_intx = 1;
2801 dr->orig_intx = !enable;
2807 * pci_intx_mask_supported - probe for INTx masking support
2808 * @dev: the PCI device to operate on
2810 * Check if the device dev support INTx masking via the config space
2813 bool pci_intx_mask_supported(struct pci_dev *dev)
2815 bool mask_supported = false;
2818 if (dev->broken_intx_masking)
2821 pci_cfg_access_lock(dev);
2823 pci_read_config_word(dev, PCI_COMMAND, &orig);
2824 pci_write_config_word(dev, PCI_COMMAND,
2825 orig ^ PCI_COMMAND_INTX_DISABLE);
2826 pci_read_config_word(dev, PCI_COMMAND, &new);
2829 * There's no way to protect against hardware bugs or detect them
2830 * reliably, but as long as we know what the value should be, let's
2831 * go ahead and check it.
2833 if ((new ^ orig) & ~PCI_COMMAND_INTX_DISABLE) {
2834 dev_err(&dev->dev, "Command register changed from "
2835 "0x%x to 0x%x: driver or hardware bug?\n", orig, new);
2836 } else if ((new ^ orig) & PCI_COMMAND_INTX_DISABLE) {
2837 mask_supported = true;
2838 pci_write_config_word(dev, PCI_COMMAND, orig);
2841 pci_cfg_access_unlock(dev);
2842 return mask_supported;
2844 EXPORT_SYMBOL_GPL(pci_intx_mask_supported);
2846 static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
2848 struct pci_bus *bus = dev->bus;
2849 bool mask_updated = true;
2850 u32 cmd_status_dword;
2851 u16 origcmd, newcmd;
2852 unsigned long flags;
2856 * We do a single dword read to retrieve both command and status.
2857 * Document assumptions that make this possible.
2859 BUILD_BUG_ON(PCI_COMMAND % 4);
2860 BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
2862 raw_spin_lock_irqsave(&pci_lock, flags);
2864 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
2866 irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
2869 * Check interrupt status register to see whether our device
2870 * triggered the interrupt (when masking) or the next IRQ is
2871 * already pending (when unmasking).
2873 if (mask != irq_pending) {
2874 mask_updated = false;
2878 origcmd = cmd_status_dword;
2879 newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
2881 newcmd |= PCI_COMMAND_INTX_DISABLE;
2882 if (newcmd != origcmd)
2883 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
2886 raw_spin_unlock_irqrestore(&pci_lock, flags);
2888 return mask_updated;
2892 * pci_check_and_mask_intx - mask INTx on pending interrupt
2893 * @dev: the PCI device to operate on
2895 * Check if the device dev has its INTx line asserted, mask it and
2896 * return true in that case. False is returned if not interrupt was
2899 bool pci_check_and_mask_intx(struct pci_dev *dev)
2901 return pci_check_and_set_intx_mask(dev, true);
2903 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
2906 * pci_check_and_mask_intx - unmask INTx of no interrupt is pending
2907 * @dev: the PCI device to operate on
2909 * Check if the device dev has its INTx line asserted, unmask it if not
2910 * and return true. False is returned and the mask remains active if
2911 * there was still an interrupt pending.
2913 bool pci_check_and_unmask_intx(struct pci_dev *dev)
2915 return pci_check_and_set_intx_mask(dev, false);
2917 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
2920 * pci_msi_off - disables any MSI or MSI-X capabilities
2921 * @dev: the PCI device to operate on
2923 * If you want to use MSI, see pci_enable_msi() and friends.
2924 * This is a lower-level primitive that allows us to disable
2925 * MSI operation at the device level.
2927 void pci_msi_off(struct pci_dev *dev)
2933 * This looks like it could go in msi.c, but we need it even when
2934 * CONFIG_PCI_MSI=n. For the same reason, we can't use
2935 * dev->msi_cap or dev->msix_cap here.
2937 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
2939 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
2940 control &= ~PCI_MSI_FLAGS_ENABLE;
2941 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
2943 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
2945 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
2946 control &= ~PCI_MSIX_FLAGS_ENABLE;
2947 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
2950 EXPORT_SYMBOL_GPL(pci_msi_off);
2952 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
2954 return dma_set_max_seg_size(&dev->dev, size);
2956 EXPORT_SYMBOL(pci_set_dma_max_seg_size);
2958 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
2960 return dma_set_seg_boundary(&dev->dev, mask);
2962 EXPORT_SYMBOL(pci_set_dma_seg_boundary);
2965 * pci_wait_for_pending_transaction - waits for pending transaction
2966 * @dev: the PCI device to operate on
2968 * Return 0 if transaction is pending 1 otherwise.
2970 int pci_wait_for_pending_transaction(struct pci_dev *dev)
2975 /* Wait for Transaction Pending bit clean */
2976 for (i = 0; i < 4; i++) {
2978 msleep((1 << (i - 1)) * 100);
2980 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
2981 if (!(status & PCI_EXP_DEVSTA_TRPND))
2987 EXPORT_SYMBOL(pci_wait_for_pending_transaction);
2989 static int pcie_flr(struct pci_dev *dev, int probe)
2993 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
2994 if (!(cap & PCI_EXP_DEVCAP_FLR))
3000 if (!pci_wait_for_pending_transaction(dev))
3001 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
3003 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3010 static int pci_af_flr(struct pci_dev *dev, int probe)
3017 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
3021 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
3022 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
3028 /* Wait for Transaction Pending bit clean */
3029 for (i = 0; i < 4; i++) {
3031 msleep((1 << (i - 1)) * 100);
3033 pci_read_config_byte(dev, pos + PCI_AF_STATUS, &status);
3034 if (!(status & PCI_AF_STATUS_TP))
3038 dev_err(&dev->dev, "transaction is not cleared; "
3039 "proceeding with reset anyway\n");
3042 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
3049 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
3050 * @dev: Device to reset.
3051 * @probe: If set, only check if the device can be reset this way.
3053 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
3054 * unset, it will be reinitialized internally when going from PCI_D3hot to
3055 * PCI_D0. If that's the case and the device is not in a low-power state
3056 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
3058 * NOTE: This causes the caller to sleep for twice the device power transition
3059 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
3060 * by default (i.e. unless the @dev's d3_delay field has a different value).
3061 * Moreover, only devices in D0 can be reset by this function.
3063 static int pci_pm_reset(struct pci_dev *dev, int probe)
3070 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
3071 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
3077 if (dev->current_state != PCI_D0)
3080 csr &= ~PCI_PM_CTRL_STATE_MASK;
3082 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
3083 pci_dev_d3_sleep(dev);
3085 csr &= ~PCI_PM_CTRL_STATE_MASK;
3087 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
3088 pci_dev_d3_sleep(dev);
3094 * pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge.
3095 * @dev: Bridge device
3097 * Use the bridge control register to assert reset on the secondary bus.
3098 * Devices on the secondary bus are left in power-on state.
3100 void pci_reset_bridge_secondary_bus(struct pci_dev *dev)
3104 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
3105 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
3106 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
3108 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
3109 * this to 2ms to ensure that we meet the minimum requirement.
3113 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
3114 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
3117 * Trhfa for conventional PCI is 2^25 clock cycles.
3118 * Assuming a minimum 33MHz clock this results in a 1s
3119 * delay before we can consider subordinate devices to
3120 * be re-initialized. PCIe has some ways to shorten this,
3121 * but we don't make use of them yet.
3125 EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus);
3127 static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
3129 struct pci_dev *pdev;
3131 if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self)
3134 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
3141 pci_reset_bridge_secondary_bus(dev->bus->self);
3146 static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe)
3150 if (!hotplug || !try_module_get(hotplug->ops->owner))
3153 if (hotplug->ops->reset_slot)
3154 rc = hotplug->ops->reset_slot(hotplug, probe);
3156 module_put(hotplug->ops->owner);
3161 static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe)
3163 struct pci_dev *pdev;
3165 if (dev->subordinate || !dev->slot)
3168 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
3169 if (pdev != dev && pdev->slot == dev->slot)
3172 return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
3175 static int __pci_dev_reset(struct pci_dev *dev, int probe)
3181 rc = pci_dev_specific_reset(dev, probe);
3185 rc = pcie_flr(dev, probe);
3189 rc = pci_af_flr(dev, probe);
3193 rc = pci_pm_reset(dev, probe);
3197 rc = pci_dev_reset_slot_function(dev, probe);
3201 rc = pci_parent_bus_reset(dev, probe);
3206 static void pci_dev_lock(struct pci_dev *dev)
3208 pci_cfg_access_lock(dev);
3209 /* block PM suspend, driver probe, etc. */
3210 device_lock(&dev->dev);
3213 static void pci_dev_unlock(struct pci_dev *dev)
3215 device_unlock(&dev->dev);
3216 pci_cfg_access_unlock(dev);
3219 static void pci_dev_save_and_disable(struct pci_dev *dev)
3222 * Wake-up device prior to save. PM registers default to D0 after
3223 * reset and a simple register restore doesn't reliably return
3224 * to a non-D0 state anyway.
3226 pci_set_power_state(dev, PCI_D0);
3228 pci_save_state(dev);
3230 * Disable the device by clearing the Command register, except for
3231 * INTx-disable which is set. This not only disables MMIO and I/O port
3232 * BARs, but also prevents the device from being Bus Master, preventing
3233 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3
3234 * compliant devices, INTx-disable prevents legacy interrupts.
3236 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
3239 static void pci_dev_restore(struct pci_dev *dev)
3241 pci_restore_state(dev);
3244 static int pci_dev_reset(struct pci_dev *dev, int probe)
3251 rc = __pci_dev_reset(dev, probe);
3254 pci_dev_unlock(dev);
3259 * __pci_reset_function - reset a PCI device function
3260 * @dev: PCI device to reset
3262 * Some devices allow an individual function to be reset without affecting
3263 * other functions in the same device. The PCI device must be responsive
3264 * to PCI config space in order to use this function.
3266 * The device function is presumed to be unused when this function is called.
3267 * Resetting the device will make the contents of PCI configuration space
3268 * random, so any caller of this must be prepared to reinitialise the
3269 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3272 * Returns 0 if the device function was successfully reset or negative if the
3273 * device doesn't support resetting a single function.
3275 int __pci_reset_function(struct pci_dev *dev)
3277 return pci_dev_reset(dev, 0);
3279 EXPORT_SYMBOL_GPL(__pci_reset_function);
3282 * __pci_reset_function_locked - reset a PCI device function while holding
3283 * the @dev mutex lock.
3284 * @dev: PCI device to reset
3286 * Some devices allow an individual function to be reset without affecting
3287 * other functions in the same device. The PCI device must be responsive
3288 * to PCI config space in order to use this function.
3290 * The device function is presumed to be unused and the caller is holding
3291 * the device mutex lock when this function is called.
3292 * Resetting the device will make the contents of PCI configuration space
3293 * random, so any caller of this must be prepared to reinitialise the
3294 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3297 * Returns 0 if the device function was successfully reset or negative if the
3298 * device doesn't support resetting a single function.
3300 int __pci_reset_function_locked(struct pci_dev *dev)
3302 return __pci_dev_reset(dev, 0);
3304 EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
3307 * pci_probe_reset_function - check whether the device can be safely reset
3308 * @dev: PCI device to reset
3310 * Some devices allow an individual function to be reset without affecting
3311 * other functions in the same device. The PCI device must be responsive
3312 * to PCI config space in order to use this function.
3314 * Returns 0 if the device function can be reset or negative if the
3315 * device doesn't support resetting a single function.
3317 int pci_probe_reset_function(struct pci_dev *dev)
3319 return pci_dev_reset(dev, 1);
3323 * pci_reset_function - quiesce and reset a PCI device function
3324 * @dev: PCI device to reset
3326 * Some devices allow an individual function to be reset without affecting
3327 * other functions in the same device. The PCI device must be responsive
3328 * to PCI config space in order to use this function.
3330 * This function does not just reset the PCI portion of a device, but
3331 * clears all the state associated with the device. This function differs
3332 * from __pci_reset_function in that it saves and restores device state
3335 * Returns 0 if the device function was successfully reset or negative if the
3336 * device doesn't support resetting a single function.
3338 int pci_reset_function(struct pci_dev *dev)
3342 rc = pci_dev_reset(dev, 1);
3346 pci_dev_save_and_disable(dev);
3348 rc = pci_dev_reset(dev, 0);
3350 pci_dev_restore(dev);
3354 EXPORT_SYMBOL_GPL(pci_reset_function);
3356 /* Lock devices from the top of the tree down */
3357 static void pci_bus_lock(struct pci_bus *bus)
3359 struct pci_dev *dev;
3361 list_for_each_entry(dev, &bus->devices, bus_list) {
3363 if (dev->subordinate)
3364 pci_bus_lock(dev->subordinate);
3368 /* Unlock devices from the bottom of the tree up */
3369 static void pci_bus_unlock(struct pci_bus *bus)
3371 struct pci_dev *dev;
3373 list_for_each_entry(dev, &bus->devices, bus_list) {
3374 if (dev->subordinate)
3375 pci_bus_unlock(dev->subordinate);
3376 pci_dev_unlock(dev);
3380 /* Lock devices from the top of the tree down */
3381 static void pci_slot_lock(struct pci_slot *slot)
3383 struct pci_dev *dev;
3385 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3386 if (!dev->slot || dev->slot != slot)
3389 if (dev->subordinate)
3390 pci_bus_lock(dev->subordinate);
3394 /* Unlock devices from the bottom of the tree up */
3395 static void pci_slot_unlock(struct pci_slot *slot)
3397 struct pci_dev *dev;
3399 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3400 if (!dev->slot || dev->slot != slot)
3402 if (dev->subordinate)
3403 pci_bus_unlock(dev->subordinate);
3404 pci_dev_unlock(dev);
3408 /* Save and disable devices from the top of the tree down */
3409 static void pci_bus_save_and_disable(struct pci_bus *bus)
3411 struct pci_dev *dev;
3413 list_for_each_entry(dev, &bus->devices, bus_list) {
3414 pci_dev_save_and_disable(dev);
3415 if (dev->subordinate)
3416 pci_bus_save_and_disable(dev->subordinate);
3421 * Restore devices from top of the tree down - parent bridges need to be
3422 * restored before we can get to subordinate devices.
3424 static void pci_bus_restore(struct pci_bus *bus)
3426 struct pci_dev *dev;
3428 list_for_each_entry(dev, &bus->devices, bus_list) {
3429 pci_dev_restore(dev);
3430 if (dev->subordinate)
3431 pci_bus_restore(dev->subordinate);
3435 /* Save and disable devices from the top of the tree down */
3436 static void pci_slot_save_and_disable(struct pci_slot *slot)
3438 struct pci_dev *dev;
3440 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3441 if (!dev->slot || dev->slot != slot)
3443 pci_dev_save_and_disable(dev);
3444 if (dev->subordinate)
3445 pci_bus_save_and_disable(dev->subordinate);
3450 * Restore devices from top of the tree down - parent bridges need to be
3451 * restored before we can get to subordinate devices.
3453 static void pci_slot_restore(struct pci_slot *slot)
3455 struct pci_dev *dev;
3457 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3458 if (!dev->slot || dev->slot != slot)
3460 pci_dev_restore(dev);
3461 if (dev->subordinate)
3462 pci_bus_restore(dev->subordinate);
3466 static int pci_slot_reset(struct pci_slot *slot, int probe)
3474 pci_slot_lock(slot);
3478 rc = pci_reset_hotplug_slot(slot->hotplug, probe);
3481 pci_slot_unlock(slot);
3487 * pci_probe_reset_slot - probe whether a PCI slot can be reset
3488 * @slot: PCI slot to probe
3490 * Return 0 if slot can be reset, negative if a slot reset is not supported.
3492 int pci_probe_reset_slot(struct pci_slot *slot)
3494 return pci_slot_reset(slot, 1);
3496 EXPORT_SYMBOL_GPL(pci_probe_reset_slot);
3499 * pci_reset_slot - reset a PCI slot
3500 * @slot: PCI slot to reset
3502 * A PCI bus may host multiple slots, each slot may support a reset mechanism
3503 * independent of other slots. For instance, some slots may support slot power
3504 * control. In the case of a 1:1 bus to slot architecture, this function may
3505 * wrap the bus reset to avoid spurious slot related events such as hotplug.
3506 * Generally a slot reset should be attempted before a bus reset. All of the
3507 * function of the slot and any subordinate buses behind the slot are reset
3508 * through this function. PCI config space of all devices in the slot and
3509 * behind the slot is saved before and restored after reset.
3511 * Return 0 on success, non-zero on error.
3513 int pci_reset_slot(struct pci_slot *slot)
3517 rc = pci_slot_reset(slot, 1);
3521 pci_slot_save_and_disable(slot);
3523 rc = pci_slot_reset(slot, 0);
3525 pci_slot_restore(slot);
3529 EXPORT_SYMBOL_GPL(pci_reset_slot);
3531 static int pci_bus_reset(struct pci_bus *bus, int probe)
3543 pci_reset_bridge_secondary_bus(bus->self);
3545 pci_bus_unlock(bus);
3551 * pci_probe_reset_bus - probe whether a PCI bus can be reset
3552 * @bus: PCI bus to probe
3554 * Return 0 if bus can be reset, negative if a bus reset is not supported.
3556 int pci_probe_reset_bus(struct pci_bus *bus)
3558 return pci_bus_reset(bus, 1);
3560 EXPORT_SYMBOL_GPL(pci_probe_reset_bus);
3563 * pci_reset_bus - reset a PCI bus
3564 * @bus: top level PCI bus to reset
3566 * Do a bus reset on the given bus and any subordinate buses, saving
3567 * and restoring state of all devices.
3569 * Return 0 on success, non-zero on error.
3571 int pci_reset_bus(struct pci_bus *bus)
3575 rc = pci_bus_reset(bus, 1);
3579 pci_bus_save_and_disable(bus);
3581 rc = pci_bus_reset(bus, 0);
3583 pci_bus_restore(bus);
3587 EXPORT_SYMBOL_GPL(pci_reset_bus);
3590 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
3591 * @dev: PCI device to query
3593 * Returns mmrbc: maximum designed memory read count in bytes
3594 * or appropriate error value.
3596 int pcix_get_max_mmrbc(struct pci_dev *dev)
3601 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3605 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
3608 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
3610 EXPORT_SYMBOL(pcix_get_max_mmrbc);
3613 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
3614 * @dev: PCI device to query
3616 * Returns mmrbc: maximum memory read count in bytes
3617 * or appropriate error value.
3619 int pcix_get_mmrbc(struct pci_dev *dev)
3624 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3628 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
3631 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
3633 EXPORT_SYMBOL(pcix_get_mmrbc);
3636 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
3637 * @dev: PCI device to query
3638 * @mmrbc: maximum memory read count in bytes
3639 * valid values are 512, 1024, 2048, 4096
3641 * If possible sets maximum memory read byte count, some bridges have erratas
3642 * that prevent this.
3644 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
3650 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
3653 v = ffs(mmrbc) - 10;
3655 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3659 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
3662 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
3665 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
3668 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
3670 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
3673 cmd &= ~PCI_X_CMD_MAX_READ;
3675 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
3680 EXPORT_SYMBOL(pcix_set_mmrbc);
3683 * pcie_get_readrq - get PCI Express read request size
3684 * @dev: PCI device to query
3686 * Returns maximum memory read request in bytes
3687 * or appropriate error value.
3689 int pcie_get_readrq(struct pci_dev *dev)
3693 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
3695 return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
3697 EXPORT_SYMBOL(pcie_get_readrq);
3700 * pcie_set_readrq - set PCI Express maximum memory read request
3701 * @dev: PCI device to query
3702 * @rq: maximum memory read count in bytes
3703 * valid values are 128, 256, 512, 1024, 2048, 4096
3705 * If possible sets maximum memory read request in bytes
3707 int pcie_set_readrq(struct pci_dev *dev, int rq)
3711 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
3715 * If using the "performance" PCIe config, we clamp the
3716 * read rq size to the max packet size to prevent the
3717 * host bridge generating requests larger than we can
3720 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
3721 int mps = pcie_get_mps(dev);
3727 v = (ffs(rq) - 8) << 12;
3729 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
3730 PCI_EXP_DEVCTL_READRQ, v);
3732 EXPORT_SYMBOL(pcie_set_readrq);
3735 * pcie_get_mps - get PCI Express maximum payload size
3736 * @dev: PCI device to query
3738 * Returns maximum payload size in bytes
3740 int pcie_get_mps(struct pci_dev *dev)
3744 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
3746 return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
3748 EXPORT_SYMBOL(pcie_get_mps);
3751 * pcie_set_mps - set PCI Express maximum payload size
3752 * @dev: PCI device to query
3753 * @mps: maximum payload size in bytes
3754 * valid values are 128, 256, 512, 1024, 2048, 4096
3756 * If possible sets maximum payload size
3758 int pcie_set_mps(struct pci_dev *dev, int mps)
3762 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
3766 if (v > dev->pcie_mpss)
3770 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
3771 PCI_EXP_DEVCTL_PAYLOAD, v);
3773 EXPORT_SYMBOL(pcie_set_mps);
3776 * pcie_get_minimum_link - determine minimum link settings of a PCI device
3777 * @dev: PCI device to query
3778 * @speed: storage for minimum speed
3779 * @width: storage for minimum width
3781 * This function will walk up the PCI device chain and determine the minimum
3782 * link width and speed of the device.
3784 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
3785 enum pcie_link_width *width)
3789 *speed = PCI_SPEED_UNKNOWN;
3790 *width = PCIE_LNK_WIDTH_UNKNOWN;
3794 enum pci_bus_speed next_speed;
3795 enum pcie_link_width next_width;
3797 ret = pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
3801 next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS];
3802 next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >>
3803 PCI_EXP_LNKSTA_NLW_SHIFT;
3805 if (next_speed < *speed)
3806 *speed = next_speed;
3808 if (next_width < *width)
3809 *width = next_width;
3811 dev = dev->bus->self;
3816 EXPORT_SYMBOL(pcie_get_minimum_link);
3819 * pci_select_bars - Make BAR mask from the type of resource
3820 * @dev: the PCI device for which BAR mask is made
3821 * @flags: resource type mask to be selected
3823 * This helper routine makes bar mask from the type of resource.
3825 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
3828 for (i = 0; i < PCI_NUM_RESOURCES; i++)
3829 if (pci_resource_flags(dev, i) & flags)
3835 * pci_resource_bar - get position of the BAR associated with a resource
3836 * @dev: the PCI device
3837 * @resno: the resource number
3838 * @type: the BAR type to be filled in
3840 * Returns BAR position in config space, or 0 if the BAR is invalid.
3842 int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type)
3846 if (resno < PCI_ROM_RESOURCE) {
3847 *type = pci_bar_unknown;
3848 return PCI_BASE_ADDRESS_0 + 4 * resno;
3849 } else if (resno == PCI_ROM_RESOURCE) {
3850 *type = pci_bar_mem32;
3851 return dev->rom_base_reg;
3852 } else if (resno < PCI_BRIDGE_RESOURCES) {
3853 /* device specific resource */
3854 reg = pci_iov_resource_bar(dev, resno, type);
3859 dev_err(&dev->dev, "BAR %d: invalid resource\n", resno);
3863 /* Some architectures require additional programming to enable VGA */
3864 static arch_set_vga_state_t arch_set_vga_state;
3866 void __init pci_register_set_vga_state(arch_set_vga_state_t func)
3868 arch_set_vga_state = func; /* NULL disables */
3871 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
3872 unsigned int command_bits, u32 flags)
3874 if (arch_set_vga_state)
3875 return arch_set_vga_state(dev, decode, command_bits,
3881 * pci_set_vga_state - set VGA decode state on device and parents if requested
3882 * @dev: the PCI device
3883 * @decode: true = enable decoding, false = disable decoding
3884 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
3885 * @flags: traverse ancestors and change bridges
3886 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
3888 int pci_set_vga_state(struct pci_dev *dev, bool decode,
3889 unsigned int command_bits, u32 flags)
3891 struct pci_bus *bus;
3892 struct pci_dev *bridge;
3896 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) & (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
3898 /* ARCH specific VGA enables */
3899 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
3903 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
3904 pci_read_config_word(dev, PCI_COMMAND, &cmd);
3906 cmd |= command_bits;
3908 cmd &= ~command_bits;
3909 pci_write_config_word(dev, PCI_COMMAND, cmd);
3912 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
3919 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
3922 cmd |= PCI_BRIDGE_CTL_VGA;
3924 cmd &= ~PCI_BRIDGE_CTL_VGA;
3925 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
3933 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
3934 static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
3935 static DEFINE_SPINLOCK(resource_alignment_lock);
3938 * pci_specified_resource_alignment - get resource alignment specified by user.
3939 * @dev: the PCI device to get
3941 * RETURNS: Resource alignment if it is specified.
3942 * Zero if it is not specified.
3944 static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev)
3946 int seg, bus, slot, func, align_order, count;
3947 resource_size_t align = 0;
3950 spin_lock(&resource_alignment_lock);
3951 p = resource_alignment_param;
3954 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
3960 if (sscanf(p, "%x:%x:%x.%x%n",
3961 &seg, &bus, &slot, &func, &count) != 4) {
3963 if (sscanf(p, "%x:%x.%x%n",
3964 &bus, &slot, &func, &count) != 3) {
3965 /* Invalid format */
3966 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
3972 if (seg == pci_domain_nr(dev->bus) &&
3973 bus == dev->bus->number &&
3974 slot == PCI_SLOT(dev->devfn) &&
3975 func == PCI_FUNC(dev->devfn)) {
3976 if (align_order == -1) {
3979 align = 1 << align_order;
3984 if (*p != ';' && *p != ',') {
3985 /* End of param or invalid format */
3990 spin_unlock(&resource_alignment_lock);
3995 * This function disables memory decoding and releases memory resources
3996 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
3997 * It also rounds up size to specified alignment.
3998 * Later on, the kernel will assign page-aligned memory resource back
4001 void pci_reassigndev_resource_alignment(struct pci_dev *dev)
4005 resource_size_t align, size;
4008 /* check if specified PCI is target device to reassign */
4009 align = pci_specified_resource_alignment(dev);
4013 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
4014 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
4016 "Can't reassign resources to host bridge.\n");
4021 "Disabling memory decoding and releasing memory resources.\n");
4022 pci_read_config_word(dev, PCI_COMMAND, &command);
4023 command &= ~PCI_COMMAND_MEMORY;
4024 pci_write_config_word(dev, PCI_COMMAND, command);
4026 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
4027 r = &dev->resource[i];
4028 if (!(r->flags & IORESOURCE_MEM))
4030 size = resource_size(r);
4034 "Rounding up size of resource #%d to %#llx.\n",
4035 i, (unsigned long long)size);
4040 /* Need to disable bridge's resource window,
4041 * to enable the kernel to reassign new resource
4044 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
4045 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
4046 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
4047 r = &dev->resource[i];
4048 if (!(r->flags & IORESOURCE_MEM))
4050 r->end = resource_size(r) - 1;
4053 pci_disable_bridge_window(dev);
4057 static ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
4059 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
4060 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
4061 spin_lock(&resource_alignment_lock);
4062 strncpy(resource_alignment_param, buf, count);
4063 resource_alignment_param[count] = '\0';
4064 spin_unlock(&resource_alignment_lock);
4068 static ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
4071 spin_lock(&resource_alignment_lock);
4072 count = snprintf(buf, size, "%s", resource_alignment_param);
4073 spin_unlock(&resource_alignment_lock);
4077 static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
4079 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
4082 static ssize_t pci_resource_alignment_store(struct bus_type *bus,
4083 const char *buf, size_t count)
4085 return pci_set_resource_alignment_param(buf, count);
4088 BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
4089 pci_resource_alignment_store);
4091 static int __init pci_resource_alignment_sysfs_init(void)
4093 return bus_create_file(&pci_bus_type,
4094 &bus_attr_resource_alignment);
4097 late_initcall(pci_resource_alignment_sysfs_init);
4099 static void pci_no_domains(void)
4101 #ifdef CONFIG_PCI_DOMAINS
4102 pci_domains_supported = 0;
4107 * pci_ext_cfg_avail - can we access extended PCI config space?
4109 * Returns 1 if we can access PCI extended config space (offsets
4110 * greater than 0xff). This is the default implementation. Architecture
4111 * implementations can override this.
4113 int __weak pci_ext_cfg_avail(void)
4118 void __weak pci_fixup_cardbus(struct pci_bus *bus)
4121 EXPORT_SYMBOL(pci_fixup_cardbus);
4123 static int __init pci_setup(char *str)
4126 char *k = strchr(str, ',');
4129 if (*str && (str = pcibios_setup(str)) && *str) {
4130 if (!strcmp(str, "nomsi")) {
4132 } else if (!strcmp(str, "noaer")) {
4134 } else if (!strncmp(str, "realloc=", 8)) {
4135 pci_realloc_get_opt(str + 8);
4136 } else if (!strncmp(str, "realloc", 7)) {
4137 pci_realloc_get_opt("on");
4138 } else if (!strcmp(str, "nodomains")) {
4140 } else if (!strncmp(str, "noari", 5)) {
4141 pcie_ari_disabled = true;
4142 } else if (!strncmp(str, "cbiosize=", 9)) {
4143 pci_cardbus_io_size = memparse(str + 9, &str);
4144 } else if (!strncmp(str, "cbmemsize=", 10)) {
4145 pci_cardbus_mem_size = memparse(str + 10, &str);
4146 } else if (!strncmp(str, "resource_alignment=", 19)) {
4147 pci_set_resource_alignment_param(str + 19,
4149 } else if (!strncmp(str, "ecrc=", 5)) {
4150 pcie_ecrc_get_policy(str + 5);
4151 } else if (!strncmp(str, "hpiosize=", 9)) {
4152 pci_hotplug_io_size = memparse(str + 9, &str);
4153 } else if (!strncmp(str, "hpmemsize=", 10)) {
4154 pci_hotplug_mem_size = memparse(str + 10, &str);
4155 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
4156 pcie_bus_config = PCIE_BUS_TUNE_OFF;
4157 } else if (!strncmp(str, "pcie_bus_safe", 13)) {
4158 pcie_bus_config = PCIE_BUS_SAFE;
4159 } else if (!strncmp(str, "pcie_bus_perf", 13)) {
4160 pcie_bus_config = PCIE_BUS_PERFORMANCE;
4161 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
4162 pcie_bus_config = PCIE_BUS_PEER2PEER;
4163 } else if (!strncmp(str, "pcie_scan_all", 13)) {
4164 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
4166 printk(KERN_ERR "PCI: Unknown option `%s'\n",
4174 early_param("pci", pci_setup);
4176 EXPORT_SYMBOL(pci_reenable_device);
4177 EXPORT_SYMBOL(pci_enable_device_io);
4178 EXPORT_SYMBOL(pci_enable_device_mem);
4179 EXPORT_SYMBOL(pci_enable_device);
4180 EXPORT_SYMBOL(pcim_enable_device);
4181 EXPORT_SYMBOL(pcim_pin_device);
4182 EXPORT_SYMBOL(pci_disable_device);
4183 EXPORT_SYMBOL(pci_find_capability);
4184 EXPORT_SYMBOL(pci_bus_find_capability);
4185 EXPORT_SYMBOL(pci_release_regions);
4186 EXPORT_SYMBOL(pci_request_regions);
4187 EXPORT_SYMBOL(pci_request_regions_exclusive);
4188 EXPORT_SYMBOL(pci_release_region);
4189 EXPORT_SYMBOL(pci_request_region);
4190 EXPORT_SYMBOL(pci_request_region_exclusive);
4191 EXPORT_SYMBOL(pci_release_selected_regions);
4192 EXPORT_SYMBOL(pci_request_selected_regions);
4193 EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
4194 EXPORT_SYMBOL(pci_set_master);
4195 EXPORT_SYMBOL(pci_clear_master);
4196 EXPORT_SYMBOL(pci_set_mwi);
4197 EXPORT_SYMBOL(pci_try_set_mwi);
4198 EXPORT_SYMBOL(pci_clear_mwi);
4199 EXPORT_SYMBOL_GPL(pci_intx);
4200 EXPORT_SYMBOL(pci_assign_resource);
4201 EXPORT_SYMBOL(pci_find_parent_resource);
4202 EXPORT_SYMBOL(pci_select_bars);
4204 EXPORT_SYMBOL(pci_set_power_state);
4205 EXPORT_SYMBOL(pci_save_state);
4206 EXPORT_SYMBOL(pci_restore_state);
4207 EXPORT_SYMBOL(pci_pme_capable);
4208 EXPORT_SYMBOL(pci_pme_active);
4209 EXPORT_SYMBOL(pci_wake_from_d3);
4210 EXPORT_SYMBOL(pci_prepare_to_sleep);
4211 EXPORT_SYMBOL(pci_back_from_sleep);
4212 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);