2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/pci.h>
15 #include <linux/slab.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <linux/string.h>
19 #include <linux/log2.h>
20 #include <linux/pci-aspm.h>
21 #include <linux/pm_wakeup.h>
22 #include <linux/interrupt.h>
23 #include <linux/device.h>
24 #include <linux/pm_runtime.h>
25 #include <asm/setup.h>
28 const char *pci_power_names[] = {
29 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
31 EXPORT_SYMBOL_GPL(pci_power_names);
33 int isa_dma_bridge_buggy;
34 EXPORT_SYMBOL(isa_dma_bridge_buggy);
37 EXPORT_SYMBOL(pci_pci_problems);
39 unsigned int pci_pm_d3_delay;
41 static void pci_pme_list_scan(struct work_struct *work);
43 static LIST_HEAD(pci_pme_list);
44 static DEFINE_MUTEX(pci_pme_list_mutex);
45 static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
47 struct pci_pme_device {
48 struct list_head list;
52 #define PME_TIMEOUT 1000 /* How long between PME checks */
54 static void pci_dev_d3_sleep(struct pci_dev *dev)
56 unsigned int delay = dev->d3_delay;
58 if (delay < pci_pm_d3_delay)
59 delay = pci_pm_d3_delay;
64 #ifdef CONFIG_PCI_DOMAINS
65 int pci_domains_supported = 1;
68 #define DEFAULT_CARDBUS_IO_SIZE (256)
69 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
70 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
71 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
72 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
74 #define DEFAULT_HOTPLUG_IO_SIZE (256)
75 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
76 /* pci=hpmemsize=nnM,hpiosize=nn can override this */
77 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
78 unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
81 * The default CLS is used if arch didn't set CLS explicitly and not
82 * all pci devices agree on the same value. Arch can override either
83 * the dfl or actual value as it sees fit. Don't forget this is
84 * measured in 32-bit words, not bytes.
86 u8 pci_dfl_cache_line_size __devinitdata = L1_CACHE_BYTES >> 2;
87 u8 pci_cache_line_size;
90 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
91 * @bus: pointer to PCI bus structure to search
93 * Given a PCI bus, returns the highest PCI bus number present in the set
94 * including the given PCI bus and its list of child PCI buses.
96 unsigned char pci_bus_max_busnr(struct pci_bus* bus)
98 struct list_head *tmp;
101 max = bus->subordinate;
102 list_for_each(tmp, &bus->children) {
103 n = pci_bus_max_busnr(pci_bus_b(tmp));
109 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
111 #ifdef CONFIG_HAS_IOMEM
112 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
115 * Make sure the BAR is actually a memory resource, not an IO resource
117 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
121 return ioremap_nocache(pci_resource_start(pdev, bar),
122 pci_resource_len(pdev, bar));
124 EXPORT_SYMBOL_GPL(pci_ioremap_bar);
129 * pci_max_busnr - returns maximum PCI bus number
131 * Returns the highest PCI bus number present in the system global list of
134 unsigned char __devinit
137 struct pci_bus *bus = NULL;
138 unsigned char max, n;
141 while ((bus = pci_find_next_bus(bus)) != NULL) {
142 n = pci_bus_max_busnr(bus);
151 #define PCI_FIND_CAP_TTL 48
153 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
154 u8 pos, int cap, int *ttl)
159 pci_bus_read_config_byte(bus, devfn, pos, &pos);
163 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
169 pos += PCI_CAP_LIST_NEXT;
174 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
177 int ttl = PCI_FIND_CAP_TTL;
179 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
182 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
184 return __pci_find_next_cap(dev->bus, dev->devfn,
185 pos + PCI_CAP_LIST_NEXT, cap);
187 EXPORT_SYMBOL_GPL(pci_find_next_capability);
189 static int __pci_bus_find_cap_start(struct pci_bus *bus,
190 unsigned int devfn, u8 hdr_type)
194 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
195 if (!(status & PCI_STATUS_CAP_LIST))
199 case PCI_HEADER_TYPE_NORMAL:
200 case PCI_HEADER_TYPE_BRIDGE:
201 return PCI_CAPABILITY_LIST;
202 case PCI_HEADER_TYPE_CARDBUS:
203 return PCI_CB_CAPABILITY_LIST;
212 * pci_find_capability - query for devices' capabilities
213 * @dev: PCI device to query
214 * @cap: capability code
216 * Tell if a device supports a given PCI capability.
217 * Returns the address of the requested capability structure within the
218 * device's PCI configuration space or 0 in case the device does not
219 * support it. Possible values for @cap:
221 * %PCI_CAP_ID_PM Power Management
222 * %PCI_CAP_ID_AGP Accelerated Graphics Port
223 * %PCI_CAP_ID_VPD Vital Product Data
224 * %PCI_CAP_ID_SLOTID Slot Identification
225 * %PCI_CAP_ID_MSI Message Signalled Interrupts
226 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
227 * %PCI_CAP_ID_PCIX PCI-X
228 * %PCI_CAP_ID_EXP PCI Express
230 int pci_find_capability(struct pci_dev *dev, int cap)
234 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
236 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
242 * pci_bus_find_capability - query for devices' capabilities
243 * @bus: the PCI bus to query
244 * @devfn: PCI device to query
245 * @cap: capability code
247 * Like pci_find_capability() but works for pci devices that do not have a
248 * pci_dev structure set up yet.
250 * Returns the address of the requested capability structure within the
251 * device's PCI configuration space or 0 in case the device does not
254 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
259 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
261 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
263 pos = __pci_find_next_cap(bus, devfn, pos, cap);
269 * pci_find_ext_capability - Find an extended capability
270 * @dev: PCI device to query
271 * @cap: capability code
273 * Returns the address of the requested extended capability structure
274 * within the device's PCI configuration space or 0 if the device does
275 * not support it. Possible values for @cap:
277 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
278 * %PCI_EXT_CAP_ID_VC Virtual Channel
279 * %PCI_EXT_CAP_ID_DSN Device Serial Number
280 * %PCI_EXT_CAP_ID_PWR Power Budgeting
282 int pci_find_ext_capability(struct pci_dev *dev, int cap)
286 int pos = PCI_CFG_SPACE_SIZE;
288 /* minimum 8 bytes per capability */
289 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
291 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
294 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
298 * If we have no capabilities, this is indicated by cap ID,
299 * cap version and next pointer all being 0.
305 if (PCI_EXT_CAP_ID(header) == cap)
308 pos = PCI_EXT_CAP_NEXT(header);
309 if (pos < PCI_CFG_SPACE_SIZE)
312 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
318 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
321 * pci_bus_find_ext_capability - find an extended capability
322 * @bus: the PCI bus to query
323 * @devfn: PCI device to query
324 * @cap: capability code
326 * Like pci_find_ext_capability() but works for pci devices that do not have a
327 * pci_dev structure set up yet.
329 * Returns the address of the requested capability structure within the
330 * device's PCI configuration space or 0 in case the device does not
333 int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn,
338 int pos = PCI_CFG_SPACE_SIZE;
340 /* minimum 8 bytes per capability */
341 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
343 if (!pci_bus_read_config_dword(bus, devfn, pos, &header))
345 if (header == 0xffffffff || header == 0)
349 if (PCI_EXT_CAP_ID(header) == cap)
352 pos = PCI_EXT_CAP_NEXT(header);
353 if (pos < PCI_CFG_SPACE_SIZE)
356 if (!pci_bus_read_config_dword(bus, devfn, pos, &header))
363 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
365 int rc, ttl = PCI_FIND_CAP_TTL;
368 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
369 mask = HT_3BIT_CAP_MASK;
371 mask = HT_5BIT_CAP_MASK;
373 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
374 PCI_CAP_ID_HT, &ttl);
376 rc = pci_read_config_byte(dev, pos + 3, &cap);
377 if (rc != PCIBIOS_SUCCESSFUL)
380 if ((cap & mask) == ht_cap)
383 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
384 pos + PCI_CAP_LIST_NEXT,
385 PCI_CAP_ID_HT, &ttl);
391 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
392 * @dev: PCI device to query
393 * @pos: Position from which to continue searching
394 * @ht_cap: Hypertransport capability code
396 * To be used in conjunction with pci_find_ht_capability() to search for
397 * all capabilities matching @ht_cap. @pos should always be a value returned
398 * from pci_find_ht_capability().
400 * NB. To be 100% safe against broken PCI devices, the caller should take
401 * steps to avoid an infinite loop.
403 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
405 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
407 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
410 * pci_find_ht_capability - query a device's Hypertransport capabilities
411 * @dev: PCI device to query
412 * @ht_cap: Hypertransport capability code
414 * Tell if a device supports a given Hypertransport capability.
415 * Returns an address within the device's PCI configuration space
416 * or 0 in case the device does not support the request capability.
417 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
418 * which has a Hypertransport capability matching @ht_cap.
420 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
424 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
426 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
430 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
433 * pci_find_parent_resource - return resource region of parent bus of given region
434 * @dev: PCI device structure contains resources to be searched
435 * @res: child resource record for which parent is sought
437 * For given resource region of given device, return the resource
438 * region of parent bus the given region is contained in or where
439 * it should be allocated from.
442 pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
444 const struct pci_bus *bus = dev->bus;
446 struct resource *best = NULL, *r;
448 pci_bus_for_each_resource(bus, r, i) {
451 if (res->start && !(res->start >= r->start && res->end <= r->end))
452 continue; /* Not contained */
453 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
454 continue; /* Wrong type */
455 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
456 return r; /* Exact match */
457 /* We can't insert a non-prefetch resource inside a prefetchable parent .. */
458 if (r->flags & IORESOURCE_PREFETCH)
460 /* .. but we can put a prefetchable resource inside a non-prefetchable one */
468 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
469 * @dev: PCI device to have its BARs restored
471 * Restore the BAR values for a given device, so as to make it
472 * accessible by its driver.
475 pci_restore_bars(struct pci_dev *dev)
479 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
480 pci_update_resource(dev, i);
483 static struct pci_platform_pm_ops *pci_platform_pm;
485 int pci_set_platform_pm(struct pci_platform_pm_ops *ops)
487 if (!ops->is_manageable || !ops->set_state || !ops->choose_state
488 || !ops->sleep_wake || !ops->can_wakeup)
490 pci_platform_pm = ops;
494 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
496 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
499 static inline int platform_pci_set_power_state(struct pci_dev *dev,
502 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
505 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
507 return pci_platform_pm ?
508 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
511 static inline bool platform_pci_can_wakeup(struct pci_dev *dev)
513 return pci_platform_pm ? pci_platform_pm->can_wakeup(dev) : false;
516 static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
518 return pci_platform_pm ?
519 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
522 static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable)
524 return pci_platform_pm ?
525 pci_platform_pm->run_wake(dev, enable) : -ENODEV;
529 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
531 * @dev: PCI device to handle.
532 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
535 * -EINVAL if the requested state is invalid.
536 * -EIO if device does not support PCI PM or its PM capabilities register has a
537 * wrong version, or device doesn't support the requested state.
538 * 0 if device already is in the requested state.
539 * 0 if device's power state has been successfully changed.
541 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
544 bool need_restore = false;
546 /* Check if we're already there */
547 if (dev->current_state == state)
553 if (state < PCI_D0 || state > PCI_D3hot)
556 /* Validate current state:
557 * Can enter D0 from any state, but if we can only go deeper
558 * to sleep if we're already in a low power state
560 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
561 && dev->current_state > state) {
562 dev_err(&dev->dev, "invalid power transition "
563 "(from state %d to %d)\n", dev->current_state, state);
567 /* check if this device supports the desired state */
568 if ((state == PCI_D1 && !dev->d1_support)
569 || (state == PCI_D2 && !dev->d2_support))
572 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
574 /* If we're (effectively) in D3, force entire word to 0.
575 * This doesn't affect PME_Status, disables PME_En, and
576 * sets PowerState to 0.
578 switch (dev->current_state) {
582 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
587 case PCI_UNKNOWN: /* Boot-up */
588 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
589 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
591 /* Fall-through: force to D0 */
597 /* enter specified state */
598 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
600 /* Mandatory power management transition delays */
601 /* see PCI PM 1.1 5.6.1 table 18 */
602 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
603 pci_dev_d3_sleep(dev);
604 else if (state == PCI_D2 || dev->current_state == PCI_D2)
605 udelay(PCI_PM_D2_DELAY);
607 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
608 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
609 if (dev->current_state != state && printk_ratelimit())
610 dev_info(&dev->dev, "Refused to change power state, "
611 "currently in D%d\n", dev->current_state);
613 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
614 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
615 * from D3hot to D0 _may_ perform an internal reset, thereby
616 * going to "D0 Uninitialized" rather than "D0 Initialized".
617 * For example, at least some versions of the 3c905B and the
618 * 3c556B exhibit this behaviour.
620 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
621 * devices in a D3hot state at boot. Consequently, we need to
622 * restore at least the BARs so that the device will be
623 * accessible to its driver.
626 pci_restore_bars(dev);
629 pcie_aspm_pm_state_change(dev->bus->self);
635 * pci_update_current_state - Read PCI power state of given device from its
636 * PCI PM registers and cache it
637 * @dev: PCI device to handle.
638 * @state: State to cache in case the device doesn't have the PM capability
640 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
645 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
646 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
648 dev->current_state = state;
653 * pci_platform_power_transition - Use platform to change device power state
654 * @dev: PCI device to handle.
655 * @state: State to put the device into.
657 static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
661 if (platform_pci_power_manageable(dev)) {
662 error = platform_pci_set_power_state(dev, state);
664 pci_update_current_state(dev, state);
667 /* Fall back to PCI_D0 if native PM is not supported */
669 dev->current_state = PCI_D0;
676 * __pci_start_power_transition - Start power transition of a PCI device
677 * @dev: PCI device to handle.
678 * @state: State to put the device into.
680 static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
683 pci_platform_power_transition(dev, PCI_D0);
687 * __pci_complete_power_transition - Complete power transition of a PCI device
688 * @dev: PCI device to handle.
689 * @state: State to put the device into.
691 * This function should not be called directly by device drivers.
693 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
695 return state >= PCI_D0 ?
696 pci_platform_power_transition(dev, state) : -EINVAL;
698 EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
701 * pci_set_power_state - Set the power state of a PCI device
702 * @dev: PCI device to handle.
703 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
705 * Transition a device to a new power state, using the platform firmware and/or
706 * the device's PCI PM registers.
709 * -EINVAL if the requested state is invalid.
710 * -EIO if device does not support PCI PM or its PM capabilities register has a
711 * wrong version, or device doesn't support the requested state.
712 * 0 if device already is in the requested state.
713 * 0 if device's power state has been successfully changed.
715 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
719 /* bound the state we're entering */
720 if (state > PCI_D3hot)
722 else if (state < PCI_D0)
724 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
726 * If the device or the parent bridge do not support PCI PM,
727 * ignore the request if we're doing anything other than putting
728 * it into D0 (which would only happen on boot).
732 __pci_start_power_transition(dev, state);
734 /* This device is quirked not to be put into D3, so
735 don't put it in D3 */
736 if (state == PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
739 error = pci_raw_set_power_state(dev, state);
741 if (!__pci_complete_power_transition(dev, state))
744 * When aspm_policy is "powersave" this call ensures
745 * that ASPM is configured.
747 if (!error && dev->bus->self)
748 pcie_aspm_powersave_config_link(dev->bus->self);
754 * pci_choose_state - Choose the power state of a PCI device
755 * @dev: PCI device to be suspended
756 * @state: target sleep state for the whole system. This is the value
757 * that is passed to suspend() function.
759 * Returns PCI power state suitable for given device and given system
763 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
767 if (!pci_find_capability(dev, PCI_CAP_ID_PM))
770 ret = platform_pci_choose_state(dev);
771 if (ret != PCI_POWER_ERROR)
774 switch (state.event) {
777 case PM_EVENT_FREEZE:
778 case PM_EVENT_PRETHAW:
779 /* REVISIT both freeze and pre-thaw "should" use D0 */
780 case PM_EVENT_SUSPEND:
781 case PM_EVENT_HIBERNATE:
784 dev_info(&dev->dev, "unrecognized suspend event %d\n",
791 EXPORT_SYMBOL(pci_choose_state);
793 #define PCI_EXP_SAVE_REGS 7
795 #define pcie_cap_has_devctl(type, flags) 1
796 #define pcie_cap_has_lnkctl(type, flags) \
797 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
798 (type == PCI_EXP_TYPE_ROOT_PORT || \
799 type == PCI_EXP_TYPE_ENDPOINT || \
800 type == PCI_EXP_TYPE_LEG_END))
801 #define pcie_cap_has_sltctl(type, flags) \
802 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
803 ((type == PCI_EXP_TYPE_ROOT_PORT) || \
804 (type == PCI_EXP_TYPE_DOWNSTREAM && \
805 (flags & PCI_EXP_FLAGS_SLOT))))
806 #define pcie_cap_has_rtctl(type, flags) \
807 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
808 (type == PCI_EXP_TYPE_ROOT_PORT || \
809 type == PCI_EXP_TYPE_RC_EC))
810 #define pcie_cap_has_devctl2(type, flags) \
811 ((flags & PCI_EXP_FLAGS_VERS) > 1)
812 #define pcie_cap_has_lnkctl2(type, flags) \
813 ((flags & PCI_EXP_FLAGS_VERS) > 1)
814 #define pcie_cap_has_sltctl2(type, flags) \
815 ((flags & PCI_EXP_FLAGS_VERS) > 1)
817 static int pci_save_pcie_state(struct pci_dev *dev)
820 struct pci_cap_saved_state *save_state;
824 pos = pci_pcie_cap(dev);
828 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
830 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
833 cap = (u16 *)&save_state->data[0];
835 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
837 if (pcie_cap_has_devctl(dev->pcie_type, flags))
838 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]);
839 if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
840 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
841 if (pcie_cap_has_sltctl(dev->pcie_type, flags))
842 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
843 if (pcie_cap_has_rtctl(dev->pcie_type, flags))
844 pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
845 if (pcie_cap_has_devctl2(dev->pcie_type, flags))
846 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &cap[i++]);
847 if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
848 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL2, &cap[i++]);
849 if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
850 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL2, &cap[i++]);
855 static void pci_restore_pcie_state(struct pci_dev *dev)
858 struct pci_cap_saved_state *save_state;
862 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
863 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
864 if (!save_state || pos <= 0)
866 cap = (u16 *)&save_state->data[0];
868 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
870 if (pcie_cap_has_devctl(dev->pcie_type, flags))
871 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
872 if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
873 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
874 if (pcie_cap_has_sltctl(dev->pcie_type, flags))
875 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
876 if (pcie_cap_has_rtctl(dev->pcie_type, flags))
877 pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
878 if (pcie_cap_has_devctl2(dev->pcie_type, flags))
879 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, cap[i++]);
880 if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
881 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL2, cap[i++]);
882 if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
883 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL2, cap[i++]);
887 static int pci_save_pcix_state(struct pci_dev *dev)
890 struct pci_cap_saved_state *save_state;
892 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
896 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
898 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
902 pci_read_config_word(dev, pos + PCI_X_CMD, (u16 *)save_state->data);
907 static void pci_restore_pcix_state(struct pci_dev *dev)
910 struct pci_cap_saved_state *save_state;
913 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
914 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
915 if (!save_state || pos <= 0)
917 cap = (u16 *)&save_state->data[0];
919 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
924 * pci_save_state - save the PCI configuration space of a device before suspending
925 * @dev: - PCI device that we're dealing with
928 pci_save_state(struct pci_dev *dev)
931 /* XXX: 100% dword access ok here? */
932 for (i = 0; i < 16; i++)
933 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
934 dev->state_saved = true;
935 if ((i = pci_save_pcie_state(dev)) != 0)
937 if ((i = pci_save_pcix_state(dev)) != 0)
943 * pci_restore_state - Restore the saved state of a PCI device
944 * @dev: - PCI device that we're dealing with
946 void pci_restore_state(struct pci_dev *dev)
951 if (!dev->state_saved)
954 /* PCI Express register must be restored first */
955 pci_restore_pcie_state(dev);
958 * The Base Address register should be programmed before the command
961 for (i = 15; i >= 0; i--) {
962 pci_read_config_dword(dev, i * 4, &val);
963 if (val != dev->saved_config_space[i]) {
964 dev_printk(KERN_DEBUG, &dev->dev, "restoring config "
965 "space at offset %#x (was %#x, writing %#x)\n",
966 i, val, (int)dev->saved_config_space[i]);
967 pci_write_config_dword(dev,i * 4,
968 dev->saved_config_space[i]);
971 pci_restore_pcix_state(dev);
972 pci_restore_msi_state(dev);
973 pci_restore_iov_state(dev);
975 dev->state_saved = false;
978 static int do_pci_enable_device(struct pci_dev *dev, int bars)
982 err = pci_set_power_state(dev, PCI_D0);
983 if (err < 0 && err != -EIO)
985 err = pcibios_enable_device(dev, bars);
988 pci_fixup_device(pci_fixup_enable, dev);
994 * pci_reenable_device - Resume abandoned device
995 * @dev: PCI device to be resumed
997 * Note this function is a backend of pci_default_resume and is not supposed
998 * to be called by normal code, write proper resume handler and use it instead.
1000 int pci_reenable_device(struct pci_dev *dev)
1002 if (pci_is_enabled(dev))
1003 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1007 static int __pci_enable_device_flags(struct pci_dev *dev,
1008 resource_size_t flags)
1014 * Power state could be unknown at this point, either due to a fresh
1015 * boot or a device removal call. So get the current power state
1016 * so that things like MSI message writing will behave as expected
1017 * (e.g. if the device really is in D0 at enable time).
1021 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1022 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1025 if (atomic_add_return(1, &dev->enable_cnt) > 1)
1026 return 0; /* already enabled */
1028 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1029 if (dev->resource[i].flags & flags)
1032 err = do_pci_enable_device(dev, bars);
1034 atomic_dec(&dev->enable_cnt);
1039 * pci_enable_device_io - Initialize a device for use with IO space
1040 * @dev: PCI device to be initialized
1042 * Initialize device before it's used by a driver. Ask low-level code
1043 * to enable I/O resources. Wake up the device if it was suspended.
1044 * Beware, this function can fail.
1046 int pci_enable_device_io(struct pci_dev *dev)
1048 return __pci_enable_device_flags(dev, IORESOURCE_IO);
1052 * pci_enable_device_mem - Initialize a device for use with Memory space
1053 * @dev: PCI device to be initialized
1055 * Initialize device before it's used by a driver. Ask low-level code
1056 * to enable Memory resources. Wake up the device if it was suspended.
1057 * Beware, this function can fail.
1059 int pci_enable_device_mem(struct pci_dev *dev)
1061 return __pci_enable_device_flags(dev, IORESOURCE_MEM);
1065 * pci_enable_device - Initialize device before it's used by a driver.
1066 * @dev: PCI device to be initialized
1068 * Initialize device before it's used by a driver. Ask low-level code
1069 * to enable I/O and memory. Wake up the device if it was suspended.
1070 * Beware, this function can fail.
1072 * Note we don't actually enable the device many times if we call
1073 * this function repeatedly (we just increment the count).
1075 int pci_enable_device(struct pci_dev *dev)
1077 return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
1081 * Managed PCI resources. This manages device on/off, intx/msi/msix
1082 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1083 * there's no need to track it separately. pci_devres is initialized
1084 * when a device is enabled using managed PCI device enable interface.
1087 unsigned int enabled:1;
1088 unsigned int pinned:1;
1089 unsigned int orig_intx:1;
1090 unsigned int restore_intx:1;
1094 static void pcim_release(struct device *gendev, void *res)
1096 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
1097 struct pci_devres *this = res;
1100 if (dev->msi_enabled)
1101 pci_disable_msi(dev);
1102 if (dev->msix_enabled)
1103 pci_disable_msix(dev);
1105 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1106 if (this->region_mask & (1 << i))
1107 pci_release_region(dev, i);
1109 if (this->restore_intx)
1110 pci_intx(dev, this->orig_intx);
1112 if (this->enabled && !this->pinned)
1113 pci_disable_device(dev);
1116 static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
1118 struct pci_devres *dr, *new_dr;
1120 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1124 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1127 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1130 static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
1132 if (pci_is_managed(pdev))
1133 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1138 * pcim_enable_device - Managed pci_enable_device()
1139 * @pdev: PCI device to be initialized
1141 * Managed pci_enable_device().
1143 int pcim_enable_device(struct pci_dev *pdev)
1145 struct pci_devres *dr;
1148 dr = get_pci_dr(pdev);
1154 rc = pci_enable_device(pdev);
1156 pdev->is_managed = 1;
1163 * pcim_pin_device - Pin managed PCI device
1164 * @pdev: PCI device to pin
1166 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1167 * driver detach. @pdev must have been enabled with
1168 * pcim_enable_device().
1170 void pcim_pin_device(struct pci_dev *pdev)
1172 struct pci_devres *dr;
1174 dr = find_pci_dr(pdev);
1175 WARN_ON(!dr || !dr->enabled);
1181 * pcibios_disable_device - disable arch specific PCI resources for device dev
1182 * @dev: the PCI device to disable
1184 * Disables architecture specific PCI resources for the device. This
1185 * is the default implementation. Architecture implementations can
1188 void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
1190 static void do_pci_disable_device(struct pci_dev *dev)
1194 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1195 if (pci_command & PCI_COMMAND_MASTER) {
1196 pci_command &= ~PCI_COMMAND_MASTER;
1197 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1200 pcibios_disable_device(dev);
1204 * pci_disable_enabled_device - Disable device without updating enable_cnt
1205 * @dev: PCI device to disable
1207 * NOTE: This function is a backend of PCI power management routines and is
1208 * not supposed to be called drivers.
1210 void pci_disable_enabled_device(struct pci_dev *dev)
1212 if (pci_is_enabled(dev))
1213 do_pci_disable_device(dev);
1217 * pci_disable_device - Disable PCI device after use
1218 * @dev: PCI device to be disabled
1220 * Signal to the system that the PCI device is not in use by the system
1221 * anymore. This only involves disabling PCI bus-mastering, if active.
1223 * Note we don't actually disable the device until all callers of
1224 * pci_enable_device() have called pci_disable_device().
1227 pci_disable_device(struct pci_dev *dev)
1229 struct pci_devres *dr;
1231 dr = find_pci_dr(dev);
1235 if (atomic_sub_return(1, &dev->enable_cnt) != 0)
1238 do_pci_disable_device(dev);
1240 dev->is_busmaster = 0;
1244 * pcibios_set_pcie_reset_state - set reset state for device dev
1245 * @dev: the PCIe device reset
1246 * @state: Reset state to enter into
1249 * Sets the PCIe reset state for the device. This is the default
1250 * implementation. Architecture implementations can override this.
1252 int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev,
1253 enum pcie_reset_state state)
1259 * pci_set_pcie_reset_state - set reset state for device dev
1260 * @dev: the PCIe device reset
1261 * @state: Reset state to enter into
1264 * Sets the PCI reset state for the device.
1266 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1268 return pcibios_set_pcie_reset_state(dev, state);
1272 * pci_check_pme_status - Check if given device has generated PME.
1273 * @dev: Device to check.
1275 * Check the PME status of the device and if set, clear it and clear PME enable
1276 * (if set). Return 'true' if PME status and PME enable were both set or
1277 * 'false' otherwise.
1279 bool pci_check_pme_status(struct pci_dev *dev)
1288 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
1289 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
1290 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
1293 /* Clear PME status. */
1294 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1295 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
1296 /* Disable PME to avoid interrupt flood. */
1297 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1301 pci_write_config_word(dev, pmcsr_pos, pmcsr);
1307 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1308 * @dev: Device to handle.
1311 * Check if @dev has generated PME and queue a resume request for it in that
1314 static int pci_pme_wakeup(struct pci_dev *dev, void *ign)
1316 if (pci_check_pme_status(dev)) {
1317 pci_wakeup_event(dev);
1318 pm_request_resume(&dev->dev);
1324 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1325 * @bus: Top bus of the subtree to walk.
1327 void pci_pme_wakeup_bus(struct pci_bus *bus)
1330 pci_walk_bus(bus, pci_pme_wakeup, NULL);
1334 * pci_pme_capable - check the capability of PCI device to generate PME#
1335 * @dev: PCI device to handle.
1336 * @state: PCI state from which device will issue PME#.
1338 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
1343 return !!(dev->pme_support & (1 << state));
1346 static void pci_pme_list_scan(struct work_struct *work)
1348 struct pci_pme_device *pme_dev;
1350 mutex_lock(&pci_pme_list_mutex);
1351 if (!list_empty(&pci_pme_list)) {
1352 list_for_each_entry(pme_dev, &pci_pme_list, list)
1353 pci_pme_wakeup(pme_dev->dev, NULL);
1354 schedule_delayed_work(&pci_pme_work, msecs_to_jiffies(PME_TIMEOUT));
1356 mutex_unlock(&pci_pme_list_mutex);
1360 * pci_external_pme - is a device an external PCI PME source?
1361 * @dev: PCI device to check
1365 static bool pci_external_pme(struct pci_dev *dev)
1367 if (pci_is_pcie(dev) || dev->bus->number == 0)
1373 * pci_pme_active - enable or disable PCI device's PME# function
1374 * @dev: PCI device to handle.
1375 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1377 * The caller must verify that the device is capable of generating PME# before
1378 * calling this function with @enable equal to 'true'.
1380 void pci_pme_active(struct pci_dev *dev, bool enable)
1387 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1388 /* Clear PME_Status by writing 1 to it and enable PME# */
1389 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1391 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1393 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1395 /* PCI (as opposed to PCIe) PME requires that the device have
1396 its PME# line hooked up correctly. Not all hardware vendors
1397 do this, so the PME never gets delivered and the device
1398 remains asleep. The easiest way around this is to
1399 periodically walk the list of suspended devices and check
1400 whether any have their PME flag set. The assumption is that
1401 we'll wake up often enough anyway that this won't be a huge
1402 hit, and the power savings from the devices will still be a
1405 if (pci_external_pme(dev)) {
1406 struct pci_pme_device *pme_dev;
1408 pme_dev = kmalloc(sizeof(struct pci_pme_device),
1413 mutex_lock(&pci_pme_list_mutex);
1414 list_add(&pme_dev->list, &pci_pme_list);
1415 if (list_is_singular(&pci_pme_list))
1416 schedule_delayed_work(&pci_pme_work,
1417 msecs_to_jiffies(PME_TIMEOUT));
1418 mutex_unlock(&pci_pme_list_mutex);
1420 mutex_lock(&pci_pme_list_mutex);
1421 list_for_each_entry(pme_dev, &pci_pme_list, list) {
1422 if (pme_dev->dev == dev) {
1423 list_del(&pme_dev->list);
1428 mutex_unlock(&pci_pme_list_mutex);
1433 dev_printk(KERN_DEBUG, &dev->dev, "PME# %s\n",
1434 enable ? "enabled" : "disabled");
1438 * __pci_enable_wake - enable PCI device as wakeup event source
1439 * @dev: PCI device affected
1440 * @state: PCI state from which device will issue wakeup events
1441 * @runtime: True if the events are to be generated at run time
1442 * @enable: True to enable event generation; false to disable
1444 * This enables the device as a wakeup event source, or disables it.
1445 * When such events involves platform-specific hooks, those hooks are
1446 * called automatically by this routine.
1448 * Devices with legacy power management (no standard PCI PM capabilities)
1449 * always require such platform hooks.
1452 * 0 is returned on success
1453 * -EINVAL is returned if device is not supposed to wake up the system
1454 * Error code depending on the platform is returned if both the platform and
1455 * the native mechanism fail to enable the generation of wake-up events
1457 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1458 bool runtime, bool enable)
1462 if (enable && !runtime && !device_may_wakeup(&dev->dev))
1465 /* Don't do the same thing twice in a row for one device. */
1466 if (!!enable == !!dev->wakeup_prepared)
1470 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1471 * Anderson we should be doing PME# wake enable followed by ACPI wake
1472 * enable. To disable wake-up we call the platform first, for symmetry.
1478 if (pci_pme_capable(dev, state))
1479 pci_pme_active(dev, true);
1482 error = runtime ? platform_pci_run_wake(dev, true) :
1483 platform_pci_sleep_wake(dev, true);
1487 dev->wakeup_prepared = true;
1490 platform_pci_run_wake(dev, false);
1492 platform_pci_sleep_wake(dev, false);
1493 pci_pme_active(dev, false);
1494 dev->wakeup_prepared = false;
1499 EXPORT_SYMBOL(__pci_enable_wake);
1502 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1503 * @dev: PCI device to prepare
1504 * @enable: True to enable wake-up event generation; false to disable
1506 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1507 * and this function allows them to set that up cleanly - pci_enable_wake()
1508 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1509 * ordering constraints.
1511 * This function only returns error code if the device is not capable of
1512 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1513 * enable wake-up power for it.
1515 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1517 return pci_pme_capable(dev, PCI_D3cold) ?
1518 pci_enable_wake(dev, PCI_D3cold, enable) :
1519 pci_enable_wake(dev, PCI_D3hot, enable);
1523 * pci_target_state - find an appropriate low power state for a given PCI dev
1526 * Use underlying platform code to find a supported low power state for @dev.
1527 * If the platform can't manage @dev, return the deepest state from which it
1528 * can generate wake events, based on any available PME info.
1530 pci_power_t pci_target_state(struct pci_dev *dev)
1532 pci_power_t target_state = PCI_D3hot;
1534 if (platform_pci_power_manageable(dev)) {
1536 * Call the platform to choose the target state of the device
1537 * and enable wake-up from this state if supported.
1539 pci_power_t state = platform_pci_choose_state(dev);
1542 case PCI_POWER_ERROR:
1547 if (pci_no_d1d2(dev))
1550 target_state = state;
1552 } else if (!dev->pm_cap) {
1553 target_state = PCI_D0;
1554 } else if (device_may_wakeup(&dev->dev)) {
1556 * Find the deepest state from which the device can generate
1557 * wake-up events, make it the target state and enable device
1560 if (dev->pme_support) {
1562 && !(dev->pme_support & (1 << target_state)))
1567 return target_state;
1571 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1572 * @dev: Device to handle.
1574 * Choose the power state appropriate for the device depending on whether
1575 * it can wake up the system and/or is power manageable by the platform
1576 * (PCI_D3hot is the default) and put the device into that state.
1578 int pci_prepare_to_sleep(struct pci_dev *dev)
1580 pci_power_t target_state = pci_target_state(dev);
1583 if (target_state == PCI_POWER_ERROR)
1586 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
1588 error = pci_set_power_state(dev, target_state);
1591 pci_enable_wake(dev, target_state, false);
1597 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
1598 * @dev: Device to handle.
1600 * Disable device's system wake-up capability and put it into D0.
1602 int pci_back_from_sleep(struct pci_dev *dev)
1604 pci_enable_wake(dev, PCI_D0, false);
1605 return pci_set_power_state(dev, PCI_D0);
1609 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
1610 * @dev: PCI device being suspended.
1612 * Prepare @dev to generate wake-up events at run time and put it into a low
1615 int pci_finish_runtime_suspend(struct pci_dev *dev)
1617 pci_power_t target_state = pci_target_state(dev);
1620 if (target_state == PCI_POWER_ERROR)
1623 __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev));
1625 error = pci_set_power_state(dev, target_state);
1628 __pci_enable_wake(dev, target_state, true, false);
1634 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
1635 * @dev: Device to check.
1637 * Return true if the device itself is cabable of generating wake-up events
1638 * (through the platform or using the native PCIe PME) or if the device supports
1639 * PME and one of its upstream bridges can generate wake-up events.
1641 bool pci_dev_run_wake(struct pci_dev *dev)
1643 struct pci_bus *bus = dev->bus;
1645 if (device_run_wake(&dev->dev))
1648 if (!dev->pme_support)
1651 while (bus->parent) {
1652 struct pci_dev *bridge = bus->self;
1654 if (device_run_wake(&bridge->dev))
1660 /* We have reached the root bus. */
1662 return device_run_wake(bus->bridge);
1666 EXPORT_SYMBOL_GPL(pci_dev_run_wake);
1669 * pci_pm_init - Initialize PM functions of given PCI device
1670 * @dev: PCI device to handle.
1672 void pci_pm_init(struct pci_dev *dev)
1677 pm_runtime_forbid(&dev->dev);
1678 device_enable_async_suspend(&dev->dev);
1679 dev->wakeup_prepared = false;
1683 /* find PCI PM capability in list */
1684 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1687 /* Check device's ability to generate PME# */
1688 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
1690 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
1691 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
1692 pmc & PCI_PM_CAP_VER_MASK);
1697 dev->d3_delay = PCI_PM_D3_WAIT;
1699 dev->d1_support = false;
1700 dev->d2_support = false;
1701 if (!pci_no_d1d2(dev)) {
1702 if (pmc & PCI_PM_CAP_D1)
1703 dev->d1_support = true;
1704 if (pmc & PCI_PM_CAP_D2)
1705 dev->d2_support = true;
1707 if (dev->d1_support || dev->d2_support)
1708 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
1709 dev->d1_support ? " D1" : "",
1710 dev->d2_support ? " D2" : "");
1713 pmc &= PCI_PM_CAP_PME_MASK;
1715 dev_printk(KERN_DEBUG, &dev->dev,
1716 "PME# supported from%s%s%s%s%s\n",
1717 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
1718 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
1719 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
1720 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
1721 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
1722 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
1724 * Make device's PM flags reflect the wake-up capability, but
1725 * let the user space enable it to wake up the system as needed.
1727 device_set_wakeup_capable(&dev->dev, true);
1728 /* Disable the PME# generation functionality */
1729 pci_pme_active(dev, false);
1731 dev->pme_support = 0;
1736 * platform_pci_wakeup_init - init platform wakeup if present
1739 * Some devices don't have PCI PM caps but can still generate wakeup
1740 * events through platform methods (like ACPI events). If @dev supports
1741 * platform wakeup events, set the device flag to indicate as much. This
1742 * may be redundant if the device also supports PCI PM caps, but double
1743 * initialization should be safe in that case.
1745 void platform_pci_wakeup_init(struct pci_dev *dev)
1747 if (!platform_pci_can_wakeup(dev))
1750 device_set_wakeup_capable(&dev->dev, true);
1751 platform_pci_sleep_wake(dev, false);
1755 * pci_add_save_buffer - allocate buffer for saving given capability registers
1756 * @dev: the PCI device
1757 * @cap: the capability to allocate the buffer for
1758 * @size: requested size of the buffer
1760 static int pci_add_cap_save_buffer(
1761 struct pci_dev *dev, char cap, unsigned int size)
1764 struct pci_cap_saved_state *save_state;
1766 pos = pci_find_capability(dev, cap);
1770 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
1774 save_state->cap_nr = cap;
1775 pci_add_saved_cap(dev, save_state);
1781 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
1782 * @dev: the PCI device
1784 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
1788 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
1789 PCI_EXP_SAVE_REGS * sizeof(u16));
1792 "unable to preallocate PCI Express save buffer\n");
1794 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
1797 "unable to preallocate PCI-X save buffer\n");
1801 * pci_enable_ari - enable ARI forwarding if hardware support it
1802 * @dev: the PCI device
1804 void pci_enable_ari(struct pci_dev *dev)
1809 struct pci_dev *bridge;
1811 if (!pci_is_pcie(dev) || dev->devfn)
1814 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1818 bridge = dev->bus->self;
1819 if (!bridge || !pci_is_pcie(bridge))
1822 pos = pci_pcie_cap(bridge);
1826 pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap);
1827 if (!(cap & PCI_EXP_DEVCAP2_ARI))
1830 pci_read_config_word(bridge, pos + PCI_EXP_DEVCTL2, &ctrl);
1831 ctrl |= PCI_EXP_DEVCTL2_ARI;
1832 pci_write_config_word(bridge, pos + PCI_EXP_DEVCTL2, ctrl);
1834 bridge->ari_enabled = 1;
1838 * pci_enable_ido - enable ID-based ordering on a device
1839 * @dev: the PCI device
1840 * @type: which types of IDO to enable
1842 * Enable ID-based ordering on @dev. @type can contain the bits
1843 * %PCI_EXP_IDO_REQUEST and/or %PCI_EXP_IDO_COMPLETION to indicate
1844 * which types of transactions are allowed to be re-ordered.
1846 void pci_enable_ido(struct pci_dev *dev, unsigned long type)
1851 pos = pci_pcie_cap(dev);
1855 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
1856 if (type & PCI_EXP_IDO_REQUEST)
1857 ctrl |= PCI_EXP_IDO_REQ_EN;
1858 if (type & PCI_EXP_IDO_COMPLETION)
1859 ctrl |= PCI_EXP_IDO_CMP_EN;
1860 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
1862 EXPORT_SYMBOL(pci_enable_ido);
1865 * pci_disable_ido - disable ID-based ordering on a device
1866 * @dev: the PCI device
1867 * @type: which types of IDO to disable
1869 void pci_disable_ido(struct pci_dev *dev, unsigned long type)
1874 if (!pci_is_pcie(dev))
1877 pos = pci_pcie_cap(dev);
1881 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
1882 if (type & PCI_EXP_IDO_REQUEST)
1883 ctrl &= ~PCI_EXP_IDO_REQ_EN;
1884 if (type & PCI_EXP_IDO_COMPLETION)
1885 ctrl &= ~PCI_EXP_IDO_CMP_EN;
1886 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
1888 EXPORT_SYMBOL(pci_disable_ido);
1890 static int pci_acs_enable;
1893 * pci_request_acs - ask for ACS to be enabled if supported
1895 void pci_request_acs(void)
1901 * pci_enable_acs - enable ACS if hardware support it
1902 * @dev: the PCI device
1904 void pci_enable_acs(struct pci_dev *dev)
1910 if (!pci_acs_enable)
1913 if (!pci_is_pcie(dev))
1916 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
1920 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
1921 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
1923 /* Source Validation */
1924 ctrl |= (cap & PCI_ACS_SV);
1926 /* P2P Request Redirect */
1927 ctrl |= (cap & PCI_ACS_RR);
1929 /* P2P Completion Redirect */
1930 ctrl |= (cap & PCI_ACS_CR);
1932 /* Upstream Forwarding */
1933 ctrl |= (cap & PCI_ACS_UF);
1935 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
1939 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
1940 * @dev: the PCI device
1941 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD)
1943 * Perform INTx swizzling for a device behind one level of bridge. This is
1944 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
1945 * behind bridges on add-in cards. For devices with ARI enabled, the slot
1946 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
1947 * the PCI Express Base Specification, Revision 2.1)
1949 u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin)
1953 if (pci_ari_enabled(dev->bus))
1956 slot = PCI_SLOT(dev->devfn);
1958 return (((pin - 1) + slot) % 4) + 1;
1962 pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
1970 while (!pci_is_root_bus(dev->bus)) {
1971 pin = pci_swizzle_interrupt_pin(dev, pin);
1972 dev = dev->bus->self;
1979 * pci_common_swizzle - swizzle INTx all the way to root bridge
1980 * @dev: the PCI device
1981 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
1983 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
1984 * bridges all the way up to a PCI root bus.
1986 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
1990 while (!pci_is_root_bus(dev->bus)) {
1991 pin = pci_swizzle_interrupt_pin(dev, pin);
1992 dev = dev->bus->self;
1995 return PCI_SLOT(dev->devfn);
1999 * pci_release_region - Release a PCI bar
2000 * @pdev: PCI device whose resources were previously reserved by pci_request_region
2001 * @bar: BAR to release
2003 * Releases the PCI I/O and memory resources previously reserved by a
2004 * successful call to pci_request_region. Call this function only
2005 * after all use of the PCI regions has ceased.
2007 void pci_release_region(struct pci_dev *pdev, int bar)
2009 struct pci_devres *dr;
2011 if (pci_resource_len(pdev, bar) == 0)
2013 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
2014 release_region(pci_resource_start(pdev, bar),
2015 pci_resource_len(pdev, bar));
2016 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
2017 release_mem_region(pci_resource_start(pdev, bar),
2018 pci_resource_len(pdev, bar));
2020 dr = find_pci_dr(pdev);
2022 dr->region_mask &= ~(1 << bar);
2026 * __pci_request_region - Reserved PCI I/O and memory resource
2027 * @pdev: PCI device whose resources are to be reserved
2028 * @bar: BAR to be reserved
2029 * @res_name: Name to be associated with resource.
2030 * @exclusive: whether the region access is exclusive or not
2032 * Mark the PCI region associated with PCI device @pdev BR @bar as
2033 * being reserved by owner @res_name. Do not access any
2034 * address inside the PCI regions unless this call returns
2037 * If @exclusive is set, then the region is marked so that userspace
2038 * is explicitly not allowed to map the resource via /dev/mem or
2039 * sysfs MMIO access.
2041 * Returns 0 on success, or %EBUSY on error. A warning
2042 * message is also printed on failure.
2044 static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name,
2047 struct pci_devres *dr;
2049 if (pci_resource_len(pdev, bar) == 0)
2052 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
2053 if (!request_region(pci_resource_start(pdev, bar),
2054 pci_resource_len(pdev, bar), res_name))
2057 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
2058 if (!__request_mem_region(pci_resource_start(pdev, bar),
2059 pci_resource_len(pdev, bar), res_name,
2064 dr = find_pci_dr(pdev);
2066 dr->region_mask |= 1 << bar;
2071 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar,
2072 &pdev->resource[bar]);
2077 * pci_request_region - Reserve PCI I/O and memory resource
2078 * @pdev: PCI device whose resources are to be reserved
2079 * @bar: BAR to be reserved
2080 * @res_name: Name to be associated with resource
2082 * Mark the PCI region associated with PCI device @pdev BAR @bar as
2083 * being reserved by owner @res_name. Do not access any
2084 * address inside the PCI regions unless this call returns
2087 * Returns 0 on success, or %EBUSY on error. A warning
2088 * message is also printed on failure.
2090 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
2092 return __pci_request_region(pdev, bar, res_name, 0);
2096 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
2097 * @pdev: PCI device whose resources are to be reserved
2098 * @bar: BAR to be reserved
2099 * @res_name: Name to be associated with resource.
2101 * Mark the PCI region associated with PCI device @pdev BR @bar as
2102 * being reserved by owner @res_name. Do not access any
2103 * address inside the PCI regions unless this call returns
2106 * Returns 0 on success, or %EBUSY on error. A warning
2107 * message is also printed on failure.
2109 * The key difference that _exclusive makes it that userspace is
2110 * explicitly not allowed to map the resource via /dev/mem or
2113 int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name)
2115 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
2118 * pci_release_selected_regions - Release selected PCI I/O and memory resources
2119 * @pdev: PCI device whose resources were previously reserved
2120 * @bars: Bitmask of BARs to be released
2122 * Release selected PCI I/O and memory resources previously reserved.
2123 * Call this function only after all use of the PCI regions has ceased.
2125 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
2129 for (i = 0; i < 6; i++)
2130 if (bars & (1 << i))
2131 pci_release_region(pdev, i);
2134 int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
2135 const char *res_name, int excl)
2139 for (i = 0; i < 6; i++)
2140 if (bars & (1 << i))
2141 if (__pci_request_region(pdev, i, res_name, excl))
2147 if (bars & (1 << i))
2148 pci_release_region(pdev, i);
2155 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
2156 * @pdev: PCI device whose resources are to be reserved
2157 * @bars: Bitmask of BARs to be requested
2158 * @res_name: Name to be associated with resource
2160 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
2161 const char *res_name)
2163 return __pci_request_selected_regions(pdev, bars, res_name, 0);
2166 int pci_request_selected_regions_exclusive(struct pci_dev *pdev,
2167 int bars, const char *res_name)
2169 return __pci_request_selected_regions(pdev, bars, res_name,
2170 IORESOURCE_EXCLUSIVE);
2174 * pci_release_regions - Release reserved PCI I/O and memory resources
2175 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
2177 * Releases all PCI I/O and memory resources previously reserved by a
2178 * successful call to pci_request_regions. Call this function only
2179 * after all use of the PCI regions has ceased.
2182 void pci_release_regions(struct pci_dev *pdev)
2184 pci_release_selected_regions(pdev, (1 << 6) - 1);
2188 * pci_request_regions - Reserved PCI I/O and memory resources
2189 * @pdev: PCI device whose resources are to be reserved
2190 * @res_name: Name to be associated with resource.
2192 * Mark all PCI regions associated with PCI device @pdev as
2193 * being reserved by owner @res_name. Do not access any
2194 * address inside the PCI regions unless this call returns
2197 * Returns 0 on success, or %EBUSY on error. A warning
2198 * message is also printed on failure.
2200 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
2202 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
2206 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
2207 * @pdev: PCI device whose resources are to be reserved
2208 * @res_name: Name to be associated with resource.
2210 * Mark all PCI regions associated with PCI device @pdev as
2211 * being reserved by owner @res_name. Do not access any
2212 * address inside the PCI regions unless this call returns
2215 * pci_request_regions_exclusive() will mark the region so that
2216 * /dev/mem and the sysfs MMIO access will not be allowed.
2218 * Returns 0 on success, or %EBUSY on error. A warning
2219 * message is also printed on failure.
2221 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
2223 return pci_request_selected_regions_exclusive(pdev,
2224 ((1 << 6) - 1), res_name);
2227 static void __pci_set_master(struct pci_dev *dev, bool enable)
2231 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
2233 cmd = old_cmd | PCI_COMMAND_MASTER;
2235 cmd = old_cmd & ~PCI_COMMAND_MASTER;
2236 if (cmd != old_cmd) {
2237 dev_dbg(&dev->dev, "%s bus mastering\n",
2238 enable ? "enabling" : "disabling");
2239 pci_write_config_word(dev, PCI_COMMAND, cmd);
2241 dev->is_busmaster = enable;
2245 * pci_set_master - enables bus-mastering for device dev
2246 * @dev: the PCI device to enable
2248 * Enables bus-mastering on the device and calls pcibios_set_master()
2249 * to do the needed arch specific settings.
2251 void pci_set_master(struct pci_dev *dev)
2253 __pci_set_master(dev, true);
2254 pcibios_set_master(dev);
2258 * pci_clear_master - disables bus-mastering for device dev
2259 * @dev: the PCI device to disable
2261 void pci_clear_master(struct pci_dev *dev)
2263 __pci_set_master(dev, false);
2267 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
2268 * @dev: the PCI device for which MWI is to be enabled
2270 * Helper function for pci_set_mwi.
2271 * Originally copied from drivers/net/acenic.c.
2272 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
2274 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2276 int pci_set_cacheline_size(struct pci_dev *dev)
2280 if (!pci_cache_line_size)
2283 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
2284 equal to or multiple of the right value. */
2285 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2286 if (cacheline_size >= pci_cache_line_size &&
2287 (cacheline_size % pci_cache_line_size) == 0)
2290 /* Write the correct value. */
2291 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
2293 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2294 if (cacheline_size == pci_cache_line_size)
2297 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not "
2298 "supported\n", pci_cache_line_size << 2);
2302 EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
2304 #ifdef PCI_DISABLE_MWI
2305 int pci_set_mwi(struct pci_dev *dev)
2310 int pci_try_set_mwi(struct pci_dev *dev)
2315 void pci_clear_mwi(struct pci_dev *dev)
2322 * pci_set_mwi - enables memory-write-invalidate PCI transaction
2323 * @dev: the PCI device for which MWI is enabled
2325 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2327 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2330 pci_set_mwi(struct pci_dev *dev)
2335 rc = pci_set_cacheline_size(dev);
2339 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2340 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
2341 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
2342 cmd |= PCI_COMMAND_INVALIDATE;
2343 pci_write_config_word(dev, PCI_COMMAND, cmd);
2350 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
2351 * @dev: the PCI device for which MWI is enabled
2353 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2354 * Callers are not required to check the return value.
2356 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2358 int pci_try_set_mwi(struct pci_dev *dev)
2360 int rc = pci_set_mwi(dev);
2365 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
2366 * @dev: the PCI device to disable
2368 * Disables PCI Memory-Write-Invalidate transaction on the device
2371 pci_clear_mwi(struct pci_dev *dev)
2375 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2376 if (cmd & PCI_COMMAND_INVALIDATE) {
2377 cmd &= ~PCI_COMMAND_INVALIDATE;
2378 pci_write_config_word(dev, PCI_COMMAND, cmd);
2381 #endif /* ! PCI_DISABLE_MWI */
2384 * pci_intx - enables/disables PCI INTx for device dev
2385 * @pdev: the PCI device to operate on
2386 * @enable: boolean: whether to enable or disable PCI INTx
2388 * Enables/disables PCI INTx for device dev
2391 pci_intx(struct pci_dev *pdev, int enable)
2393 u16 pci_command, new;
2395 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
2398 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
2400 new = pci_command | PCI_COMMAND_INTX_DISABLE;
2403 if (new != pci_command) {
2404 struct pci_devres *dr;
2406 pci_write_config_word(pdev, PCI_COMMAND, new);
2408 dr = find_pci_dr(pdev);
2409 if (dr && !dr->restore_intx) {
2410 dr->restore_intx = 1;
2411 dr->orig_intx = !enable;
2417 * pci_msi_off - disables any msi or msix capabilities
2418 * @dev: the PCI device to operate on
2420 * If you want to use msi see pci_enable_msi and friends.
2421 * This is a lower level primitive that allows us to disable
2422 * msi operation at the device level.
2424 void pci_msi_off(struct pci_dev *dev)
2429 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
2431 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
2432 control &= ~PCI_MSI_FLAGS_ENABLE;
2433 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
2435 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
2437 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
2438 control &= ~PCI_MSIX_FLAGS_ENABLE;
2439 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
2442 EXPORT_SYMBOL_GPL(pci_msi_off);
2444 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
2446 return dma_set_max_seg_size(&dev->dev, size);
2448 EXPORT_SYMBOL(pci_set_dma_max_seg_size);
2450 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
2452 return dma_set_seg_boundary(&dev->dev, mask);
2454 EXPORT_SYMBOL(pci_set_dma_seg_boundary);
2456 static int pcie_flr(struct pci_dev *dev, int probe)
2461 u16 status, control;
2463 pos = pci_pcie_cap(dev);
2467 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP, &cap);
2468 if (!(cap & PCI_EXP_DEVCAP_FLR))
2474 /* Wait for Transaction Pending bit clean */
2475 for (i = 0; i < 4; i++) {
2477 msleep((1 << (i - 1)) * 100);
2479 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
2480 if (!(status & PCI_EXP_DEVSTA_TRPND))
2484 dev_err(&dev->dev, "transaction is not cleared; "
2485 "proceeding with reset anyway\n");
2488 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &control);
2489 control |= PCI_EXP_DEVCTL_BCR_FLR;
2490 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, control);
2497 static int pci_af_flr(struct pci_dev *dev, int probe)
2504 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
2508 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
2509 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
2515 /* Wait for Transaction Pending bit clean */
2516 for (i = 0; i < 4; i++) {
2518 msleep((1 << (i - 1)) * 100);
2520 pci_read_config_byte(dev, pos + PCI_AF_STATUS, &status);
2521 if (!(status & PCI_AF_STATUS_TP))
2525 dev_err(&dev->dev, "transaction is not cleared; "
2526 "proceeding with reset anyway\n");
2529 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
2536 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
2537 * @dev: Device to reset.
2538 * @probe: If set, only check if the device can be reset this way.
2540 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
2541 * unset, it will be reinitialized internally when going from PCI_D3hot to
2542 * PCI_D0. If that's the case and the device is not in a low-power state
2543 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
2545 * NOTE: This causes the caller to sleep for twice the device power transition
2546 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
2547 * by devault (i.e. unless the @dev's d3_delay field has a different value).
2548 * Moreover, only devices in D0 can be reset by this function.
2550 static int pci_pm_reset(struct pci_dev *dev, int probe)
2557 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
2558 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
2564 if (dev->current_state != PCI_D0)
2567 csr &= ~PCI_PM_CTRL_STATE_MASK;
2569 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
2570 pci_dev_d3_sleep(dev);
2572 csr &= ~PCI_PM_CTRL_STATE_MASK;
2574 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
2575 pci_dev_d3_sleep(dev);
2580 static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
2583 struct pci_dev *pdev;
2585 if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self)
2588 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
2595 pci_read_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, &ctrl);
2596 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
2597 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
2600 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
2601 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
2607 static int pci_dev_reset(struct pci_dev *dev, int probe)
2614 pci_block_user_cfg_access(dev);
2615 /* block PM suspend, driver probe, etc. */
2616 device_lock(&dev->dev);
2619 rc = pci_dev_specific_reset(dev, probe);
2623 rc = pcie_flr(dev, probe);
2627 rc = pci_af_flr(dev, probe);
2631 rc = pci_pm_reset(dev, probe);
2635 rc = pci_parent_bus_reset(dev, probe);
2638 device_unlock(&dev->dev);
2639 pci_unblock_user_cfg_access(dev);
2646 * __pci_reset_function - reset a PCI device function
2647 * @dev: PCI device to reset
2649 * Some devices allow an individual function to be reset without affecting
2650 * other functions in the same device. The PCI device must be responsive
2651 * to PCI config space in order to use this function.
2653 * The device function is presumed to be unused when this function is called.
2654 * Resetting the device will make the contents of PCI configuration space
2655 * random, so any caller of this must be prepared to reinitialise the
2656 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
2659 * Returns 0 if the device function was successfully reset or negative if the
2660 * device doesn't support resetting a single function.
2662 int __pci_reset_function(struct pci_dev *dev)
2664 return pci_dev_reset(dev, 0);
2666 EXPORT_SYMBOL_GPL(__pci_reset_function);
2669 * pci_probe_reset_function - check whether the device can be safely reset
2670 * @dev: PCI device to reset
2672 * Some devices allow an individual function to be reset without affecting
2673 * other functions in the same device. The PCI device must be responsive
2674 * to PCI config space in order to use this function.
2676 * Returns 0 if the device function can be reset or negative if the
2677 * device doesn't support resetting a single function.
2679 int pci_probe_reset_function(struct pci_dev *dev)
2681 return pci_dev_reset(dev, 1);
2685 * pci_reset_function - quiesce and reset a PCI device function
2686 * @dev: PCI device to reset
2688 * Some devices allow an individual function to be reset without affecting
2689 * other functions in the same device. The PCI device must be responsive
2690 * to PCI config space in order to use this function.
2692 * This function does not just reset the PCI portion of a device, but
2693 * clears all the state associated with the device. This function differs
2694 * from __pci_reset_function in that it saves and restores device state
2697 * Returns 0 if the device function was successfully reset or negative if the
2698 * device doesn't support resetting a single function.
2700 int pci_reset_function(struct pci_dev *dev)
2704 rc = pci_dev_reset(dev, 1);
2708 pci_save_state(dev);
2711 * both INTx and MSI are disabled after the Interrupt Disable bit
2712 * is set and the Bus Master bit is cleared.
2714 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
2716 rc = pci_dev_reset(dev, 0);
2718 pci_restore_state(dev);
2722 EXPORT_SYMBOL_GPL(pci_reset_function);
2725 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
2726 * @dev: PCI device to query
2728 * Returns mmrbc: maximum designed memory read count in bytes
2729 * or appropriate error value.
2731 int pcix_get_max_mmrbc(struct pci_dev *dev)
2736 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
2740 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
2743 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
2745 EXPORT_SYMBOL(pcix_get_max_mmrbc);
2748 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
2749 * @dev: PCI device to query
2751 * Returns mmrbc: maximum memory read count in bytes
2752 * or appropriate error value.
2754 int pcix_get_mmrbc(struct pci_dev *dev)
2759 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
2763 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
2766 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
2768 EXPORT_SYMBOL(pcix_get_mmrbc);
2771 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
2772 * @dev: PCI device to query
2773 * @mmrbc: maximum memory read count in bytes
2774 * valid values are 512, 1024, 2048, 4096
2776 * If possible sets maximum memory read byte count, some bridges have erratas
2777 * that prevent this.
2779 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
2785 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
2788 v = ffs(mmrbc) - 10;
2790 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
2794 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
2797 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
2800 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
2803 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
2805 if (v > o && dev->bus &&
2806 (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
2809 cmd &= ~PCI_X_CMD_MAX_READ;
2811 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
2816 EXPORT_SYMBOL(pcix_set_mmrbc);
2819 * pcie_get_readrq - get PCI Express read request size
2820 * @dev: PCI device to query
2822 * Returns maximum memory read request in bytes
2823 * or appropriate error value.
2825 int pcie_get_readrq(struct pci_dev *dev)
2830 cap = pci_pcie_cap(dev);
2834 ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
2836 ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
2840 EXPORT_SYMBOL(pcie_get_readrq);
2843 * pcie_set_readrq - set PCI Express maximum memory read request
2844 * @dev: PCI device to query
2845 * @rq: maximum memory read count in bytes
2846 * valid values are 128, 256, 512, 1024, 2048, 4096
2848 * If possible sets maximum read byte count
2850 int pcie_set_readrq(struct pci_dev *dev, int rq)
2852 int cap, err = -EINVAL;
2855 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
2858 v = (ffs(rq) - 8) << 12;
2860 cap = pci_pcie_cap(dev);
2864 err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
2868 if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) {
2869 ctl &= ~PCI_EXP_DEVCTL_READRQ;
2871 err = pci_write_config_dword(dev, cap + PCI_EXP_DEVCTL, ctl);
2877 EXPORT_SYMBOL(pcie_set_readrq);
2880 * pci_select_bars - Make BAR mask from the type of resource
2881 * @dev: the PCI device for which BAR mask is made
2882 * @flags: resource type mask to be selected
2884 * This helper routine makes bar mask from the type of resource.
2886 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
2889 for (i = 0; i < PCI_NUM_RESOURCES; i++)
2890 if (pci_resource_flags(dev, i) & flags)
2896 * pci_resource_bar - get position of the BAR associated with a resource
2897 * @dev: the PCI device
2898 * @resno: the resource number
2899 * @type: the BAR type to be filled in
2901 * Returns BAR position in config space, or 0 if the BAR is invalid.
2903 int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type)
2907 if (resno < PCI_ROM_RESOURCE) {
2908 *type = pci_bar_unknown;
2909 return PCI_BASE_ADDRESS_0 + 4 * resno;
2910 } else if (resno == PCI_ROM_RESOURCE) {
2911 *type = pci_bar_mem32;
2912 return dev->rom_base_reg;
2913 } else if (resno < PCI_BRIDGE_RESOURCES) {
2914 /* device specific resource */
2915 reg = pci_iov_resource_bar(dev, resno, type);
2920 dev_err(&dev->dev, "BAR %d: invalid resource\n", resno);
2924 /* Some architectures require additional programming to enable VGA */
2925 static arch_set_vga_state_t arch_set_vga_state;
2927 void __init pci_register_set_vga_state(arch_set_vga_state_t func)
2929 arch_set_vga_state = func; /* NULL disables */
2932 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
2933 unsigned int command_bits, bool change_bridge)
2935 if (arch_set_vga_state)
2936 return arch_set_vga_state(dev, decode, command_bits,
2942 * pci_set_vga_state - set VGA decode state on device and parents if requested
2943 * @dev: the PCI device
2944 * @decode: true = enable decoding, false = disable decoding
2945 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
2946 * @change_bridge: traverse ancestors and change bridges
2948 int pci_set_vga_state(struct pci_dev *dev, bool decode,
2949 unsigned int command_bits, bool change_bridge)
2951 struct pci_bus *bus;
2952 struct pci_dev *bridge;
2956 WARN_ON(command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY));
2958 /* ARCH specific VGA enables */
2959 rc = pci_set_vga_state_arch(dev, decode, command_bits, change_bridge);
2963 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2965 cmd |= command_bits;
2967 cmd &= ~command_bits;
2968 pci_write_config_word(dev, PCI_COMMAND, cmd);
2970 if (change_bridge == false)
2977 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
2980 cmd |= PCI_BRIDGE_CTL_VGA;
2982 cmd &= ~PCI_BRIDGE_CTL_VGA;
2983 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
2991 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
2992 static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
2993 static DEFINE_SPINLOCK(resource_alignment_lock);
2996 * pci_specified_resource_alignment - get resource alignment specified by user.
2997 * @dev: the PCI device to get
2999 * RETURNS: Resource alignment if it is specified.
3000 * Zero if it is not specified.
3002 resource_size_t pci_specified_resource_alignment(struct pci_dev *dev)
3004 int seg, bus, slot, func, align_order, count;
3005 resource_size_t align = 0;
3008 spin_lock(&resource_alignment_lock);
3009 p = resource_alignment_param;
3012 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
3018 if (sscanf(p, "%x:%x:%x.%x%n",
3019 &seg, &bus, &slot, &func, &count) != 4) {
3021 if (sscanf(p, "%x:%x.%x%n",
3022 &bus, &slot, &func, &count) != 3) {
3023 /* Invalid format */
3024 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
3030 if (seg == pci_domain_nr(dev->bus) &&
3031 bus == dev->bus->number &&
3032 slot == PCI_SLOT(dev->devfn) &&
3033 func == PCI_FUNC(dev->devfn)) {
3034 if (align_order == -1) {
3037 align = 1 << align_order;
3042 if (*p != ';' && *p != ',') {
3043 /* End of param or invalid format */
3048 spin_unlock(&resource_alignment_lock);
3053 * pci_is_reassigndev - check if specified PCI is target device to reassign
3054 * @dev: the PCI device to check
3056 * RETURNS: non-zero for PCI device is a target device to reassign,
3059 int pci_is_reassigndev(struct pci_dev *dev)
3061 return (pci_specified_resource_alignment(dev) != 0);
3064 ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
3066 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
3067 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
3068 spin_lock(&resource_alignment_lock);
3069 strncpy(resource_alignment_param, buf, count);
3070 resource_alignment_param[count] = '\0';
3071 spin_unlock(&resource_alignment_lock);
3075 ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
3078 spin_lock(&resource_alignment_lock);
3079 count = snprintf(buf, size, "%s", resource_alignment_param);
3080 spin_unlock(&resource_alignment_lock);
3084 static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
3086 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
3089 static ssize_t pci_resource_alignment_store(struct bus_type *bus,
3090 const char *buf, size_t count)
3092 return pci_set_resource_alignment_param(buf, count);
3095 BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
3096 pci_resource_alignment_store);
3098 static int __init pci_resource_alignment_sysfs_init(void)
3100 return bus_create_file(&pci_bus_type,
3101 &bus_attr_resource_alignment);
3104 late_initcall(pci_resource_alignment_sysfs_init);
3106 static void __devinit pci_no_domains(void)
3108 #ifdef CONFIG_PCI_DOMAINS
3109 pci_domains_supported = 0;
3114 * pci_ext_cfg_enabled - can we access extended PCI config space?
3115 * @dev: The PCI device of the root bridge.
3117 * Returns 1 if we can access PCI extended config space (offsets
3118 * greater than 0xff). This is the default implementation. Architecture
3119 * implementations can override this.
3121 int __attribute__ ((weak)) pci_ext_cfg_avail(struct pci_dev *dev)
3126 void __weak pci_fixup_cardbus(struct pci_bus *bus)
3129 EXPORT_SYMBOL(pci_fixup_cardbus);
3131 static int __init pci_setup(char *str)
3134 char *k = strchr(str, ',');
3137 if (*str && (str = pcibios_setup(str)) && *str) {
3138 if (!strcmp(str, "nomsi")) {
3140 } else if (!strcmp(str, "noaer")) {
3142 } else if (!strcmp(str, "nodomains")) {
3144 } else if (!strncmp(str, "cbiosize=", 9)) {
3145 pci_cardbus_io_size = memparse(str + 9, &str);
3146 } else if (!strncmp(str, "cbmemsize=", 10)) {
3147 pci_cardbus_mem_size = memparse(str + 10, &str);
3148 } else if (!strncmp(str, "resource_alignment=", 19)) {
3149 pci_set_resource_alignment_param(str + 19,
3151 } else if (!strncmp(str, "ecrc=", 5)) {
3152 pcie_ecrc_get_policy(str + 5);
3153 } else if (!strncmp(str, "hpiosize=", 9)) {
3154 pci_hotplug_io_size = memparse(str + 9, &str);
3155 } else if (!strncmp(str, "hpmemsize=", 10)) {
3156 pci_hotplug_mem_size = memparse(str + 10, &str);
3158 printk(KERN_ERR "PCI: Unknown option `%s'\n",
3166 early_param("pci", pci_setup);
3168 EXPORT_SYMBOL(pci_reenable_device);
3169 EXPORT_SYMBOL(pci_enable_device_io);
3170 EXPORT_SYMBOL(pci_enable_device_mem);
3171 EXPORT_SYMBOL(pci_enable_device);
3172 EXPORT_SYMBOL(pcim_enable_device);
3173 EXPORT_SYMBOL(pcim_pin_device);
3174 EXPORT_SYMBOL(pci_disable_device);
3175 EXPORT_SYMBOL(pci_find_capability);
3176 EXPORT_SYMBOL(pci_bus_find_capability);
3177 EXPORT_SYMBOL(pci_release_regions);
3178 EXPORT_SYMBOL(pci_request_regions);
3179 EXPORT_SYMBOL(pci_request_regions_exclusive);
3180 EXPORT_SYMBOL(pci_release_region);
3181 EXPORT_SYMBOL(pci_request_region);
3182 EXPORT_SYMBOL(pci_request_region_exclusive);
3183 EXPORT_SYMBOL(pci_release_selected_regions);
3184 EXPORT_SYMBOL(pci_request_selected_regions);
3185 EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
3186 EXPORT_SYMBOL(pci_set_master);
3187 EXPORT_SYMBOL(pci_clear_master);
3188 EXPORT_SYMBOL(pci_set_mwi);
3189 EXPORT_SYMBOL(pci_try_set_mwi);
3190 EXPORT_SYMBOL(pci_clear_mwi);
3191 EXPORT_SYMBOL_GPL(pci_intx);
3192 EXPORT_SYMBOL(pci_assign_resource);
3193 EXPORT_SYMBOL(pci_find_parent_resource);
3194 EXPORT_SYMBOL(pci_select_bars);
3196 EXPORT_SYMBOL(pci_set_power_state);
3197 EXPORT_SYMBOL(pci_save_state);
3198 EXPORT_SYMBOL(pci_restore_state);
3199 EXPORT_SYMBOL(pci_pme_capable);
3200 EXPORT_SYMBOL(pci_pme_active);
3201 EXPORT_SYMBOL(pci_wake_from_d3);
3202 EXPORT_SYMBOL(pci_target_state);
3203 EXPORT_SYMBOL(pci_prepare_to_sleep);
3204 EXPORT_SYMBOL(pci_back_from_sleep);
3205 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);