2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/pci.h>
15 #include <linux/slab.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <linux/string.h>
19 #include <linux/log2.h>
20 #include <linux/pci-aspm.h>
21 #include <linux/pm_wakeup.h>
22 #include <linux/interrupt.h>
23 #include <linux/device.h>
24 #include <linux/pm_runtime.h>
25 #include <asm/setup.h>
28 const char *pci_power_names[] = {
29 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
31 EXPORT_SYMBOL_GPL(pci_power_names);
33 int isa_dma_bridge_buggy;
34 EXPORT_SYMBOL(isa_dma_bridge_buggy);
37 EXPORT_SYMBOL(pci_pci_problems);
39 unsigned int pci_pm_d3_delay;
41 static void pci_dev_d3_sleep(struct pci_dev *dev)
43 unsigned int delay = dev->d3_delay;
45 if (delay < pci_pm_d3_delay)
46 delay = pci_pm_d3_delay;
51 #ifdef CONFIG_PCI_DOMAINS
52 int pci_domains_supported = 1;
55 #define DEFAULT_CARDBUS_IO_SIZE (256)
56 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
57 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
58 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
59 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
61 #define DEFAULT_HOTPLUG_IO_SIZE (256)
62 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
63 /* pci=hpmemsize=nnM,hpiosize=nn can override this */
64 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
65 unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
68 * The default CLS is used if arch didn't set CLS explicitly and not
69 * all pci devices agree on the same value. Arch can override either
70 * the dfl or actual value as it sees fit. Don't forget this is
71 * measured in 32-bit words, not bytes.
73 u8 pci_dfl_cache_line_size __devinitdata = L1_CACHE_BYTES >> 2;
74 u8 pci_cache_line_size;
77 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
78 * @bus: pointer to PCI bus structure to search
80 * Given a PCI bus, returns the highest PCI bus number present in the set
81 * including the given PCI bus and its list of child PCI buses.
83 unsigned char pci_bus_max_busnr(struct pci_bus* bus)
85 struct list_head *tmp;
88 max = bus->subordinate;
89 list_for_each(tmp, &bus->children) {
90 n = pci_bus_max_busnr(pci_bus_b(tmp));
96 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
98 #ifdef CONFIG_HAS_IOMEM
99 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
102 * Make sure the BAR is actually a memory resource, not an IO resource
104 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
108 return ioremap_nocache(pci_resource_start(pdev, bar),
109 pci_resource_len(pdev, bar));
111 EXPORT_SYMBOL_GPL(pci_ioremap_bar);
116 * pci_max_busnr - returns maximum PCI bus number
118 * Returns the highest PCI bus number present in the system global list of
121 unsigned char __devinit
124 struct pci_bus *bus = NULL;
125 unsigned char max, n;
128 while ((bus = pci_find_next_bus(bus)) != NULL) {
129 n = pci_bus_max_busnr(bus);
138 #define PCI_FIND_CAP_TTL 48
140 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
141 u8 pos, int cap, int *ttl)
146 pci_bus_read_config_byte(bus, devfn, pos, &pos);
150 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
156 pos += PCI_CAP_LIST_NEXT;
161 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
164 int ttl = PCI_FIND_CAP_TTL;
166 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
169 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
171 return __pci_find_next_cap(dev->bus, dev->devfn,
172 pos + PCI_CAP_LIST_NEXT, cap);
174 EXPORT_SYMBOL_GPL(pci_find_next_capability);
176 static int __pci_bus_find_cap_start(struct pci_bus *bus,
177 unsigned int devfn, u8 hdr_type)
181 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
182 if (!(status & PCI_STATUS_CAP_LIST))
186 case PCI_HEADER_TYPE_NORMAL:
187 case PCI_HEADER_TYPE_BRIDGE:
188 return PCI_CAPABILITY_LIST;
189 case PCI_HEADER_TYPE_CARDBUS:
190 return PCI_CB_CAPABILITY_LIST;
199 * pci_find_capability - query for devices' capabilities
200 * @dev: PCI device to query
201 * @cap: capability code
203 * Tell if a device supports a given PCI capability.
204 * Returns the address of the requested capability structure within the
205 * device's PCI configuration space or 0 in case the device does not
206 * support it. Possible values for @cap:
208 * %PCI_CAP_ID_PM Power Management
209 * %PCI_CAP_ID_AGP Accelerated Graphics Port
210 * %PCI_CAP_ID_VPD Vital Product Data
211 * %PCI_CAP_ID_SLOTID Slot Identification
212 * %PCI_CAP_ID_MSI Message Signalled Interrupts
213 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
214 * %PCI_CAP_ID_PCIX PCI-X
215 * %PCI_CAP_ID_EXP PCI Express
217 int pci_find_capability(struct pci_dev *dev, int cap)
221 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
223 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
229 * pci_bus_find_capability - query for devices' capabilities
230 * @bus: the PCI bus to query
231 * @devfn: PCI device to query
232 * @cap: capability code
234 * Like pci_find_capability() but works for pci devices that do not have a
235 * pci_dev structure set up yet.
237 * Returns the address of the requested capability structure within the
238 * device's PCI configuration space or 0 in case the device does not
241 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
246 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
248 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
250 pos = __pci_find_next_cap(bus, devfn, pos, cap);
256 * pci_find_ext_capability - Find an extended capability
257 * @dev: PCI device to query
258 * @cap: capability code
260 * Returns the address of the requested extended capability structure
261 * within the device's PCI configuration space or 0 if the device does
262 * not support it. Possible values for @cap:
264 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
265 * %PCI_EXT_CAP_ID_VC Virtual Channel
266 * %PCI_EXT_CAP_ID_DSN Device Serial Number
267 * %PCI_EXT_CAP_ID_PWR Power Budgeting
269 int pci_find_ext_capability(struct pci_dev *dev, int cap)
273 int pos = PCI_CFG_SPACE_SIZE;
275 /* minimum 8 bytes per capability */
276 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
278 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
281 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
285 * If we have no capabilities, this is indicated by cap ID,
286 * cap version and next pointer all being 0.
292 if (PCI_EXT_CAP_ID(header) == cap)
295 pos = PCI_EXT_CAP_NEXT(header);
296 if (pos < PCI_CFG_SPACE_SIZE)
299 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
305 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
308 * pci_bus_find_ext_capability - find an extended capability
309 * @bus: the PCI bus to query
310 * @devfn: PCI device to query
311 * @cap: capability code
313 * Like pci_find_ext_capability() but works for pci devices that do not have a
314 * pci_dev structure set up yet.
316 * Returns the address of the requested capability structure within the
317 * device's PCI configuration space or 0 in case the device does not
320 int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn,
325 int pos = PCI_CFG_SPACE_SIZE;
327 /* minimum 8 bytes per capability */
328 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
330 if (!pci_bus_read_config_dword(bus, devfn, pos, &header))
332 if (header == 0xffffffff || header == 0)
336 if (PCI_EXT_CAP_ID(header) == cap)
339 pos = PCI_EXT_CAP_NEXT(header);
340 if (pos < PCI_CFG_SPACE_SIZE)
343 if (!pci_bus_read_config_dword(bus, devfn, pos, &header))
350 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
352 int rc, ttl = PCI_FIND_CAP_TTL;
355 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
356 mask = HT_3BIT_CAP_MASK;
358 mask = HT_5BIT_CAP_MASK;
360 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
361 PCI_CAP_ID_HT, &ttl);
363 rc = pci_read_config_byte(dev, pos + 3, &cap);
364 if (rc != PCIBIOS_SUCCESSFUL)
367 if ((cap & mask) == ht_cap)
370 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
371 pos + PCI_CAP_LIST_NEXT,
372 PCI_CAP_ID_HT, &ttl);
378 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
379 * @dev: PCI device to query
380 * @pos: Position from which to continue searching
381 * @ht_cap: Hypertransport capability code
383 * To be used in conjunction with pci_find_ht_capability() to search for
384 * all capabilities matching @ht_cap. @pos should always be a value returned
385 * from pci_find_ht_capability().
387 * NB. To be 100% safe against broken PCI devices, the caller should take
388 * steps to avoid an infinite loop.
390 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
392 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
394 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
397 * pci_find_ht_capability - query a device's Hypertransport capabilities
398 * @dev: PCI device to query
399 * @ht_cap: Hypertransport capability code
401 * Tell if a device supports a given Hypertransport capability.
402 * Returns an address within the device's PCI configuration space
403 * or 0 in case the device does not support the request capability.
404 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
405 * which has a Hypertransport capability matching @ht_cap.
407 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
411 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
413 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
417 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
420 * pci_find_parent_resource - return resource region of parent bus of given region
421 * @dev: PCI device structure contains resources to be searched
422 * @res: child resource record for which parent is sought
424 * For given resource region of given device, return the resource
425 * region of parent bus the given region is contained in or where
426 * it should be allocated from.
429 pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
431 const struct pci_bus *bus = dev->bus;
433 struct resource *best = NULL, *r;
435 pci_bus_for_each_resource(bus, r, i) {
438 if (res->start && !(res->start >= r->start && res->end <= r->end))
439 continue; /* Not contained */
440 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
441 continue; /* Wrong type */
442 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
443 return r; /* Exact match */
444 /* We can't insert a non-prefetch resource inside a prefetchable parent .. */
445 if (r->flags & IORESOURCE_PREFETCH)
447 /* .. but we can put a prefetchable resource inside a non-prefetchable one */
455 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
456 * @dev: PCI device to have its BARs restored
458 * Restore the BAR values for a given device, so as to make it
459 * accessible by its driver.
462 pci_restore_bars(struct pci_dev *dev)
466 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
467 pci_update_resource(dev, i);
470 static struct pci_platform_pm_ops *pci_platform_pm;
472 int pci_set_platform_pm(struct pci_platform_pm_ops *ops)
474 if (!ops->is_manageable || !ops->set_state || !ops->choose_state
475 || !ops->sleep_wake || !ops->can_wakeup)
477 pci_platform_pm = ops;
481 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
483 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
486 static inline int platform_pci_set_power_state(struct pci_dev *dev,
489 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
492 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
494 return pci_platform_pm ?
495 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
498 static inline bool platform_pci_can_wakeup(struct pci_dev *dev)
500 return pci_platform_pm ? pci_platform_pm->can_wakeup(dev) : false;
503 static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
505 return pci_platform_pm ?
506 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
509 static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable)
511 return pci_platform_pm ?
512 pci_platform_pm->run_wake(dev, enable) : -ENODEV;
516 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
518 * @dev: PCI device to handle.
519 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
522 * -EINVAL if the requested state is invalid.
523 * -EIO if device does not support PCI PM or its PM capabilities register has a
524 * wrong version, or device doesn't support the requested state.
525 * 0 if device already is in the requested state.
526 * 0 if device's power state has been successfully changed.
528 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
531 bool need_restore = false;
533 /* Check if we're already there */
534 if (dev->current_state == state)
540 if (state < PCI_D0 || state > PCI_D3hot)
543 /* Validate current state:
544 * Can enter D0 from any state, but if we can only go deeper
545 * to sleep if we're already in a low power state
547 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
548 && dev->current_state > state) {
549 dev_err(&dev->dev, "invalid power transition "
550 "(from state %d to %d)\n", dev->current_state, state);
554 /* check if this device supports the desired state */
555 if ((state == PCI_D1 && !dev->d1_support)
556 || (state == PCI_D2 && !dev->d2_support))
559 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
561 /* If we're (effectively) in D3, force entire word to 0.
562 * This doesn't affect PME_Status, disables PME_En, and
563 * sets PowerState to 0.
565 switch (dev->current_state) {
569 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
574 case PCI_UNKNOWN: /* Boot-up */
575 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
576 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
578 /* Fall-through: force to D0 */
584 /* enter specified state */
585 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
587 /* Mandatory power management transition delays */
588 /* see PCI PM 1.1 5.6.1 table 18 */
589 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
590 pci_dev_d3_sleep(dev);
591 else if (state == PCI_D2 || dev->current_state == PCI_D2)
592 udelay(PCI_PM_D2_DELAY);
594 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
595 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
596 if (dev->current_state != state && printk_ratelimit())
597 dev_info(&dev->dev, "Refused to change power state, "
598 "currently in D%d\n", dev->current_state);
600 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
601 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
602 * from D3hot to D0 _may_ perform an internal reset, thereby
603 * going to "D0 Uninitialized" rather than "D0 Initialized".
604 * For example, at least some versions of the 3c905B and the
605 * 3c556B exhibit this behaviour.
607 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
608 * devices in a D3hot state at boot. Consequently, we need to
609 * restore at least the BARs so that the device will be
610 * accessible to its driver.
613 pci_restore_bars(dev);
616 pcie_aspm_pm_state_change(dev->bus->self);
622 * pci_update_current_state - Read PCI power state of given device from its
623 * PCI PM registers and cache it
624 * @dev: PCI device to handle.
625 * @state: State to cache in case the device doesn't have the PM capability
627 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
632 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
633 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
635 dev->current_state = state;
640 * pci_platform_power_transition - Use platform to change device power state
641 * @dev: PCI device to handle.
642 * @state: State to put the device into.
644 static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
648 if (platform_pci_power_manageable(dev)) {
649 error = platform_pci_set_power_state(dev, state);
651 pci_update_current_state(dev, state);
654 /* Fall back to PCI_D0 if native PM is not supported */
656 dev->current_state = PCI_D0;
663 * __pci_start_power_transition - Start power transition of a PCI device
664 * @dev: PCI device to handle.
665 * @state: State to put the device into.
667 static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
670 pci_platform_power_transition(dev, PCI_D0);
674 * __pci_complete_power_transition - Complete power transition of a PCI device
675 * @dev: PCI device to handle.
676 * @state: State to put the device into.
678 * This function should not be called directly by device drivers.
680 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
682 return state > PCI_D0 ?
683 pci_platform_power_transition(dev, state) : -EINVAL;
685 EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
688 * pci_set_power_state - Set the power state of a PCI device
689 * @dev: PCI device to handle.
690 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
692 * Transition a device to a new power state, using the platform firmware and/or
693 * the device's PCI PM registers.
696 * -EINVAL if the requested state is invalid.
697 * -EIO if device does not support PCI PM or its PM capabilities register has a
698 * wrong version, or device doesn't support the requested state.
699 * 0 if device already is in the requested state.
700 * 0 if device's power state has been successfully changed.
702 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
706 /* bound the state we're entering */
707 if (state > PCI_D3hot)
709 else if (state < PCI_D0)
711 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
713 * If the device or the parent bridge do not support PCI PM,
714 * ignore the request if we're doing anything other than putting
715 * it into D0 (which would only happen on boot).
719 /* Check if we're already there */
720 if (dev->current_state == state)
723 __pci_start_power_transition(dev, state);
725 /* This device is quirked not to be put into D3, so
726 don't put it in D3 */
727 if (state == PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
730 error = pci_raw_set_power_state(dev, state);
732 if (!__pci_complete_power_transition(dev, state))
739 * pci_choose_state - Choose the power state of a PCI device
740 * @dev: PCI device to be suspended
741 * @state: target sleep state for the whole system. This is the value
742 * that is passed to suspend() function.
744 * Returns PCI power state suitable for given device and given system
748 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
752 if (!pci_find_capability(dev, PCI_CAP_ID_PM))
755 ret = platform_pci_choose_state(dev);
756 if (ret != PCI_POWER_ERROR)
759 switch (state.event) {
762 case PM_EVENT_FREEZE:
763 case PM_EVENT_PRETHAW:
764 /* REVISIT both freeze and pre-thaw "should" use D0 */
765 case PM_EVENT_SUSPEND:
766 case PM_EVENT_HIBERNATE:
769 dev_info(&dev->dev, "unrecognized suspend event %d\n",
776 EXPORT_SYMBOL(pci_choose_state);
778 #define PCI_EXP_SAVE_REGS 7
780 #define pcie_cap_has_devctl(type, flags) 1
781 #define pcie_cap_has_lnkctl(type, flags) \
782 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
783 (type == PCI_EXP_TYPE_ROOT_PORT || \
784 type == PCI_EXP_TYPE_ENDPOINT || \
785 type == PCI_EXP_TYPE_LEG_END))
786 #define pcie_cap_has_sltctl(type, flags) \
787 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
788 ((type == PCI_EXP_TYPE_ROOT_PORT) || \
789 (type == PCI_EXP_TYPE_DOWNSTREAM && \
790 (flags & PCI_EXP_FLAGS_SLOT))))
791 #define pcie_cap_has_rtctl(type, flags) \
792 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
793 (type == PCI_EXP_TYPE_ROOT_PORT || \
794 type == PCI_EXP_TYPE_RC_EC))
795 #define pcie_cap_has_devctl2(type, flags) \
796 ((flags & PCI_EXP_FLAGS_VERS) > 1)
797 #define pcie_cap_has_lnkctl2(type, flags) \
798 ((flags & PCI_EXP_FLAGS_VERS) > 1)
799 #define pcie_cap_has_sltctl2(type, flags) \
800 ((flags & PCI_EXP_FLAGS_VERS) > 1)
802 static int pci_save_pcie_state(struct pci_dev *dev)
805 struct pci_cap_saved_state *save_state;
809 pos = pci_pcie_cap(dev);
813 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
815 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
818 cap = (u16 *)&save_state->data[0];
820 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
822 if (pcie_cap_has_devctl(dev->pcie_type, flags))
823 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]);
824 if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
825 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
826 if (pcie_cap_has_sltctl(dev->pcie_type, flags))
827 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
828 if (pcie_cap_has_rtctl(dev->pcie_type, flags))
829 pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
830 if (pcie_cap_has_devctl2(dev->pcie_type, flags))
831 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &cap[i++]);
832 if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
833 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL2, &cap[i++]);
834 if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
835 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL2, &cap[i++]);
840 static void pci_restore_pcie_state(struct pci_dev *dev)
843 struct pci_cap_saved_state *save_state;
847 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
848 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
849 if (!save_state || pos <= 0)
851 cap = (u16 *)&save_state->data[0];
853 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
855 if (pcie_cap_has_devctl(dev->pcie_type, flags))
856 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
857 if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
858 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
859 if (pcie_cap_has_sltctl(dev->pcie_type, flags))
860 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
861 if (pcie_cap_has_rtctl(dev->pcie_type, flags))
862 pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
863 if (pcie_cap_has_devctl2(dev->pcie_type, flags))
864 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, cap[i++]);
865 if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
866 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL2, cap[i++]);
867 if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
868 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL2, cap[i++]);
872 static int pci_save_pcix_state(struct pci_dev *dev)
875 struct pci_cap_saved_state *save_state;
877 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
881 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
883 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
887 pci_read_config_word(dev, pos + PCI_X_CMD, (u16 *)save_state->data);
892 static void pci_restore_pcix_state(struct pci_dev *dev)
895 struct pci_cap_saved_state *save_state;
898 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
899 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
900 if (!save_state || pos <= 0)
902 cap = (u16 *)&save_state->data[0];
904 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
909 * pci_save_state - save the PCI configuration space of a device before suspending
910 * @dev: - PCI device that we're dealing with
913 pci_save_state(struct pci_dev *dev)
916 /* XXX: 100% dword access ok here? */
917 for (i = 0; i < 16; i++)
918 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
919 dev->state_saved = true;
920 if ((i = pci_save_pcie_state(dev)) != 0)
922 if ((i = pci_save_pcix_state(dev)) != 0)
928 * pci_restore_state - Restore the saved state of a PCI device
929 * @dev: - PCI device that we're dealing with
932 pci_restore_state(struct pci_dev *dev)
937 if (!dev->state_saved)
940 /* PCI Express register must be restored first */
941 pci_restore_pcie_state(dev);
944 * The Base Address register should be programmed before the command
947 for (i = 15; i >= 0; i--) {
948 pci_read_config_dword(dev, i * 4, &val);
949 if (val != dev->saved_config_space[i]) {
950 dev_printk(KERN_DEBUG, &dev->dev, "restoring config "
951 "space at offset %#x (was %#x, writing %#x)\n",
952 i, val, (int)dev->saved_config_space[i]);
953 pci_write_config_dword(dev,i * 4,
954 dev->saved_config_space[i]);
957 pci_restore_pcix_state(dev);
958 pci_restore_msi_state(dev);
959 pci_restore_iov_state(dev);
961 dev->state_saved = false;
966 static int do_pci_enable_device(struct pci_dev *dev, int bars)
970 err = pci_set_power_state(dev, PCI_D0);
971 if (err < 0 && err != -EIO)
973 err = pcibios_enable_device(dev, bars);
976 pci_fixup_device(pci_fixup_enable, dev);
982 * pci_reenable_device - Resume abandoned device
983 * @dev: PCI device to be resumed
985 * Note this function is a backend of pci_default_resume and is not supposed
986 * to be called by normal code, write proper resume handler and use it instead.
988 int pci_reenable_device(struct pci_dev *dev)
990 if (pci_is_enabled(dev))
991 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
995 static int __pci_enable_device_flags(struct pci_dev *dev,
996 resource_size_t flags)
1001 if (atomic_add_return(1, &dev->enable_cnt) > 1)
1002 return 0; /* already enabled */
1004 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1005 if (dev->resource[i].flags & flags)
1008 err = do_pci_enable_device(dev, bars);
1010 atomic_dec(&dev->enable_cnt);
1015 * pci_enable_device_io - Initialize a device for use with IO space
1016 * @dev: PCI device to be initialized
1018 * Initialize device before it's used by a driver. Ask low-level code
1019 * to enable I/O resources. Wake up the device if it was suspended.
1020 * Beware, this function can fail.
1022 int pci_enable_device_io(struct pci_dev *dev)
1024 return __pci_enable_device_flags(dev, IORESOURCE_IO);
1028 * pci_enable_device_mem - Initialize a device for use with Memory space
1029 * @dev: PCI device to be initialized
1031 * Initialize device before it's used by a driver. Ask low-level code
1032 * to enable Memory resources. Wake up the device if it was suspended.
1033 * Beware, this function can fail.
1035 int pci_enable_device_mem(struct pci_dev *dev)
1037 return __pci_enable_device_flags(dev, IORESOURCE_MEM);
1041 * pci_enable_device - Initialize device before it's used by a driver.
1042 * @dev: PCI device to be initialized
1044 * Initialize device before it's used by a driver. Ask low-level code
1045 * to enable I/O and memory. Wake up the device if it was suspended.
1046 * Beware, this function can fail.
1048 * Note we don't actually enable the device many times if we call
1049 * this function repeatedly (we just increment the count).
1051 int pci_enable_device(struct pci_dev *dev)
1053 return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
1057 * Managed PCI resources. This manages device on/off, intx/msi/msix
1058 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1059 * there's no need to track it separately. pci_devres is initialized
1060 * when a device is enabled using managed PCI device enable interface.
1063 unsigned int enabled:1;
1064 unsigned int pinned:1;
1065 unsigned int orig_intx:1;
1066 unsigned int restore_intx:1;
1070 static void pcim_release(struct device *gendev, void *res)
1072 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
1073 struct pci_devres *this = res;
1076 if (dev->msi_enabled)
1077 pci_disable_msi(dev);
1078 if (dev->msix_enabled)
1079 pci_disable_msix(dev);
1081 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1082 if (this->region_mask & (1 << i))
1083 pci_release_region(dev, i);
1085 if (this->restore_intx)
1086 pci_intx(dev, this->orig_intx);
1088 if (this->enabled && !this->pinned)
1089 pci_disable_device(dev);
1092 static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
1094 struct pci_devres *dr, *new_dr;
1096 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1100 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1103 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1106 static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
1108 if (pci_is_managed(pdev))
1109 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1114 * pcim_enable_device - Managed pci_enable_device()
1115 * @pdev: PCI device to be initialized
1117 * Managed pci_enable_device().
1119 int pcim_enable_device(struct pci_dev *pdev)
1121 struct pci_devres *dr;
1124 dr = get_pci_dr(pdev);
1130 rc = pci_enable_device(pdev);
1132 pdev->is_managed = 1;
1139 * pcim_pin_device - Pin managed PCI device
1140 * @pdev: PCI device to pin
1142 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1143 * driver detach. @pdev must have been enabled with
1144 * pcim_enable_device().
1146 void pcim_pin_device(struct pci_dev *pdev)
1148 struct pci_devres *dr;
1150 dr = find_pci_dr(pdev);
1151 WARN_ON(!dr || !dr->enabled);
1157 * pcibios_disable_device - disable arch specific PCI resources for device dev
1158 * @dev: the PCI device to disable
1160 * Disables architecture specific PCI resources for the device. This
1161 * is the default implementation. Architecture implementations can
1164 void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
1166 static void do_pci_disable_device(struct pci_dev *dev)
1170 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1171 if (pci_command & PCI_COMMAND_MASTER) {
1172 pci_command &= ~PCI_COMMAND_MASTER;
1173 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1176 pcibios_disable_device(dev);
1180 * pci_disable_enabled_device - Disable device without updating enable_cnt
1181 * @dev: PCI device to disable
1183 * NOTE: This function is a backend of PCI power management routines and is
1184 * not supposed to be called drivers.
1186 void pci_disable_enabled_device(struct pci_dev *dev)
1188 if (pci_is_enabled(dev))
1189 do_pci_disable_device(dev);
1193 * pci_disable_device - Disable PCI device after use
1194 * @dev: PCI device to be disabled
1196 * Signal to the system that the PCI device is not in use by the system
1197 * anymore. This only involves disabling PCI bus-mastering, if active.
1199 * Note we don't actually disable the device until all callers of
1200 * pci_device_enable() have called pci_device_disable().
1203 pci_disable_device(struct pci_dev *dev)
1205 struct pci_devres *dr;
1207 dr = find_pci_dr(dev);
1211 if (atomic_sub_return(1, &dev->enable_cnt) != 0)
1214 do_pci_disable_device(dev);
1216 dev->is_busmaster = 0;
1220 * pcibios_set_pcie_reset_state - set reset state for device dev
1221 * @dev: the PCIe device reset
1222 * @state: Reset state to enter into
1225 * Sets the PCIe reset state for the device. This is the default
1226 * implementation. Architecture implementations can override this.
1228 int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev,
1229 enum pcie_reset_state state)
1235 * pci_set_pcie_reset_state - set reset state for device dev
1236 * @dev: the PCIe device reset
1237 * @state: Reset state to enter into
1240 * Sets the PCI reset state for the device.
1242 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1244 return pcibios_set_pcie_reset_state(dev, state);
1248 * pci_check_pme_status - Check if given device has generated PME.
1249 * @dev: Device to check.
1251 * Check the PME status of the device and if set, clear it and clear PME enable
1252 * (if set). Return 'true' if PME status and PME enable were both set or
1253 * 'false' otherwise.
1255 bool pci_check_pme_status(struct pci_dev *dev)
1264 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
1265 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
1266 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
1269 /* Clear PME status. */
1270 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1271 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
1272 /* Disable PME to avoid interrupt flood. */
1273 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1277 pci_write_config_word(dev, pmcsr_pos, pmcsr);
1283 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1284 * @dev: Device to handle.
1287 * Check if @dev has generated PME and queue a resume request for it in that
1290 static int pci_pme_wakeup(struct pci_dev *dev, void *ign)
1292 if (pci_check_pme_status(dev))
1293 pm_request_resume(&dev->dev);
1298 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1299 * @bus: Top bus of the subtree to walk.
1301 void pci_pme_wakeup_bus(struct pci_bus *bus)
1304 pci_walk_bus(bus, pci_pme_wakeup, NULL);
1308 * pci_pme_capable - check the capability of PCI device to generate PME#
1309 * @dev: PCI device to handle.
1310 * @state: PCI state from which device will issue PME#.
1312 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
1317 return !!(dev->pme_support & (1 << state));
1321 * pci_pme_active - enable or disable PCI device's PME# function
1322 * @dev: PCI device to handle.
1323 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1325 * The caller must verify that the device is capable of generating PME# before
1326 * calling this function with @enable equal to 'true'.
1328 void pci_pme_active(struct pci_dev *dev, bool enable)
1335 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1336 /* Clear PME_Status by writing 1 to it and enable PME# */
1337 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1339 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1341 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1343 dev_printk(KERN_DEBUG, &dev->dev, "PME# %s\n",
1344 enable ? "enabled" : "disabled");
1348 * __pci_enable_wake - enable PCI device as wakeup event source
1349 * @dev: PCI device affected
1350 * @state: PCI state from which device will issue wakeup events
1351 * @runtime: True if the events are to be generated at run time
1352 * @enable: True to enable event generation; false to disable
1354 * This enables the device as a wakeup event source, or disables it.
1355 * When such events involves platform-specific hooks, those hooks are
1356 * called automatically by this routine.
1358 * Devices with legacy power management (no standard PCI PM capabilities)
1359 * always require such platform hooks.
1362 * 0 is returned on success
1363 * -EINVAL is returned if device is not supposed to wake up the system
1364 * Error code depending on the platform is returned if both the platform and
1365 * the native mechanism fail to enable the generation of wake-up events
1367 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1368 bool runtime, bool enable)
1372 if (enable && !runtime && !device_may_wakeup(&dev->dev))
1375 /* Don't do the same thing twice in a row for one device. */
1376 if (!!enable == !!dev->wakeup_prepared)
1380 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1381 * Anderson we should be doing PME# wake enable followed by ACPI wake
1382 * enable. To disable wake-up we call the platform first, for symmetry.
1388 if (pci_pme_capable(dev, state))
1389 pci_pme_active(dev, true);
1392 error = runtime ? platform_pci_run_wake(dev, true) :
1393 platform_pci_sleep_wake(dev, true);
1397 dev->wakeup_prepared = true;
1400 platform_pci_run_wake(dev, false);
1402 platform_pci_sleep_wake(dev, false);
1403 pci_pme_active(dev, false);
1404 dev->wakeup_prepared = false;
1409 EXPORT_SYMBOL(__pci_enable_wake);
1412 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1413 * @dev: PCI device to prepare
1414 * @enable: True to enable wake-up event generation; false to disable
1416 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1417 * and this function allows them to set that up cleanly - pci_enable_wake()
1418 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1419 * ordering constraints.
1421 * This function only returns error code if the device is not capable of
1422 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1423 * enable wake-up power for it.
1425 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1427 return pci_pme_capable(dev, PCI_D3cold) ?
1428 pci_enable_wake(dev, PCI_D3cold, enable) :
1429 pci_enable_wake(dev, PCI_D3hot, enable);
1433 * pci_target_state - find an appropriate low power state for a given PCI dev
1436 * Use underlying platform code to find a supported low power state for @dev.
1437 * If the platform can't manage @dev, return the deepest state from which it
1438 * can generate wake events, based on any available PME info.
1440 pci_power_t pci_target_state(struct pci_dev *dev)
1442 pci_power_t target_state = PCI_D3hot;
1444 if (platform_pci_power_manageable(dev)) {
1446 * Call the platform to choose the target state of the device
1447 * and enable wake-up from this state if supported.
1449 pci_power_t state = platform_pci_choose_state(dev);
1452 case PCI_POWER_ERROR:
1457 if (pci_no_d1d2(dev))
1460 target_state = state;
1462 } else if (!dev->pm_cap) {
1463 target_state = PCI_D0;
1464 } else if (device_may_wakeup(&dev->dev)) {
1466 * Find the deepest state from which the device can generate
1467 * wake-up events, make it the target state and enable device
1470 if (dev->pme_support) {
1472 && !(dev->pme_support & (1 << target_state)))
1477 return target_state;
1481 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1482 * @dev: Device to handle.
1484 * Choose the power state appropriate for the device depending on whether
1485 * it can wake up the system and/or is power manageable by the platform
1486 * (PCI_D3hot is the default) and put the device into that state.
1488 int pci_prepare_to_sleep(struct pci_dev *dev)
1490 pci_power_t target_state = pci_target_state(dev);
1493 if (target_state == PCI_POWER_ERROR)
1496 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
1498 error = pci_set_power_state(dev, target_state);
1501 pci_enable_wake(dev, target_state, false);
1507 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
1508 * @dev: Device to handle.
1510 * Disable device's sytem wake-up capability and put it into D0.
1512 int pci_back_from_sleep(struct pci_dev *dev)
1514 pci_enable_wake(dev, PCI_D0, false);
1515 return pci_set_power_state(dev, PCI_D0);
1519 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
1520 * @dev: PCI device being suspended.
1522 * Prepare @dev to generate wake-up events at run time and put it into a low
1525 int pci_finish_runtime_suspend(struct pci_dev *dev)
1527 pci_power_t target_state = pci_target_state(dev);
1530 if (target_state == PCI_POWER_ERROR)
1533 __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev));
1535 error = pci_set_power_state(dev, target_state);
1538 __pci_enable_wake(dev, target_state, true, false);
1544 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
1545 * @dev: Device to check.
1547 * Return true if the device itself is cabable of generating wake-up events
1548 * (through the platform or using the native PCIe PME) or if the device supports
1549 * PME and one of its upstream bridges can generate wake-up events.
1551 bool pci_dev_run_wake(struct pci_dev *dev)
1553 struct pci_bus *bus = dev->bus;
1555 if (device_run_wake(&dev->dev))
1558 if (!dev->pme_support)
1561 while (bus->parent) {
1562 struct pci_dev *bridge = bus->self;
1564 if (device_run_wake(&bridge->dev))
1570 /* We have reached the root bus. */
1572 return device_run_wake(bus->bridge);
1576 EXPORT_SYMBOL_GPL(pci_dev_run_wake);
1579 * pci_pm_init - Initialize PM functions of given PCI device
1580 * @dev: PCI device to handle.
1582 void pci_pm_init(struct pci_dev *dev)
1587 pm_runtime_forbid(&dev->dev);
1588 device_enable_async_suspend(&dev->dev);
1589 dev->wakeup_prepared = false;
1593 /* find PCI PM capability in list */
1594 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1597 /* Check device's ability to generate PME# */
1598 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
1600 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
1601 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
1602 pmc & PCI_PM_CAP_VER_MASK);
1607 dev->d3_delay = PCI_PM_D3_WAIT;
1609 dev->d1_support = false;
1610 dev->d2_support = false;
1611 if (!pci_no_d1d2(dev)) {
1612 if (pmc & PCI_PM_CAP_D1)
1613 dev->d1_support = true;
1614 if (pmc & PCI_PM_CAP_D2)
1615 dev->d2_support = true;
1617 if (dev->d1_support || dev->d2_support)
1618 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
1619 dev->d1_support ? " D1" : "",
1620 dev->d2_support ? " D2" : "");
1623 pmc &= PCI_PM_CAP_PME_MASK;
1625 dev_printk(KERN_DEBUG, &dev->dev,
1626 "PME# supported from%s%s%s%s%s\n",
1627 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
1628 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
1629 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
1630 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
1631 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
1632 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
1634 * Make device's PM flags reflect the wake-up capability, but
1635 * let the user space enable it to wake up the system as needed.
1637 device_set_wakeup_capable(&dev->dev, true);
1638 device_set_wakeup_enable(&dev->dev, false);
1639 /* Disable the PME# generation functionality */
1640 pci_pme_active(dev, false);
1642 dev->pme_support = 0;
1647 * platform_pci_wakeup_init - init platform wakeup if present
1650 * Some devices don't have PCI PM caps but can still generate wakeup
1651 * events through platform methods (like ACPI events). If @dev supports
1652 * platform wakeup events, set the device flag to indicate as much. This
1653 * may be redundant if the device also supports PCI PM caps, but double
1654 * initialization should be safe in that case.
1656 void platform_pci_wakeup_init(struct pci_dev *dev)
1658 if (!platform_pci_can_wakeup(dev))
1661 device_set_wakeup_capable(&dev->dev, true);
1662 device_set_wakeup_enable(&dev->dev, false);
1663 platform_pci_sleep_wake(dev, false);
1667 * pci_add_save_buffer - allocate buffer for saving given capability registers
1668 * @dev: the PCI device
1669 * @cap: the capability to allocate the buffer for
1670 * @size: requested size of the buffer
1672 static int pci_add_cap_save_buffer(
1673 struct pci_dev *dev, char cap, unsigned int size)
1676 struct pci_cap_saved_state *save_state;
1678 pos = pci_find_capability(dev, cap);
1682 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
1686 save_state->cap_nr = cap;
1687 pci_add_saved_cap(dev, save_state);
1693 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
1694 * @dev: the PCI device
1696 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
1700 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
1701 PCI_EXP_SAVE_REGS * sizeof(u16));
1704 "unable to preallocate PCI Express save buffer\n");
1706 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
1709 "unable to preallocate PCI-X save buffer\n");
1713 * pci_enable_ari - enable ARI forwarding if hardware support it
1714 * @dev: the PCI device
1716 void pci_enable_ari(struct pci_dev *dev)
1721 struct pci_dev *bridge;
1723 if (!pci_is_pcie(dev) || dev->devfn)
1726 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1730 bridge = dev->bus->self;
1731 if (!bridge || !pci_is_pcie(bridge))
1734 pos = pci_pcie_cap(bridge);
1738 pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap);
1739 if (!(cap & PCI_EXP_DEVCAP2_ARI))
1742 pci_read_config_word(bridge, pos + PCI_EXP_DEVCTL2, &ctrl);
1743 ctrl |= PCI_EXP_DEVCTL2_ARI;
1744 pci_write_config_word(bridge, pos + PCI_EXP_DEVCTL2, ctrl);
1746 bridge->ari_enabled = 1;
1749 static int pci_acs_enable;
1752 * pci_request_acs - ask for ACS to be enabled if supported
1754 void pci_request_acs(void)
1760 * pci_enable_acs - enable ACS if hardware support it
1761 * @dev: the PCI device
1763 void pci_enable_acs(struct pci_dev *dev)
1769 if (!pci_acs_enable)
1772 if (!pci_is_pcie(dev))
1775 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
1779 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
1780 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
1782 /* Source Validation */
1783 ctrl |= (cap & PCI_ACS_SV);
1785 /* P2P Request Redirect */
1786 ctrl |= (cap & PCI_ACS_RR);
1788 /* P2P Completion Redirect */
1789 ctrl |= (cap & PCI_ACS_CR);
1791 /* Upstream Forwarding */
1792 ctrl |= (cap & PCI_ACS_UF);
1794 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
1798 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
1799 * @dev: the PCI device
1800 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD)
1802 * Perform INTx swizzling for a device behind one level of bridge. This is
1803 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
1804 * behind bridges on add-in cards. For devices with ARI enabled, the slot
1805 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
1806 * the PCI Express Base Specification, Revision 2.1)
1808 u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin)
1812 if (pci_ari_enabled(dev->bus))
1815 slot = PCI_SLOT(dev->devfn);
1817 return (((pin - 1) + slot) % 4) + 1;
1821 pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
1829 while (!pci_is_root_bus(dev->bus)) {
1830 pin = pci_swizzle_interrupt_pin(dev, pin);
1831 dev = dev->bus->self;
1838 * pci_common_swizzle - swizzle INTx all the way to root bridge
1839 * @dev: the PCI device
1840 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
1842 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
1843 * bridges all the way up to a PCI root bus.
1845 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
1849 while (!pci_is_root_bus(dev->bus)) {
1850 pin = pci_swizzle_interrupt_pin(dev, pin);
1851 dev = dev->bus->self;
1854 return PCI_SLOT(dev->devfn);
1858 * pci_release_region - Release a PCI bar
1859 * @pdev: PCI device whose resources were previously reserved by pci_request_region
1860 * @bar: BAR to release
1862 * Releases the PCI I/O and memory resources previously reserved by a
1863 * successful call to pci_request_region. Call this function only
1864 * after all use of the PCI regions has ceased.
1866 void pci_release_region(struct pci_dev *pdev, int bar)
1868 struct pci_devres *dr;
1870 if (pci_resource_len(pdev, bar) == 0)
1872 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
1873 release_region(pci_resource_start(pdev, bar),
1874 pci_resource_len(pdev, bar));
1875 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
1876 release_mem_region(pci_resource_start(pdev, bar),
1877 pci_resource_len(pdev, bar));
1879 dr = find_pci_dr(pdev);
1881 dr->region_mask &= ~(1 << bar);
1885 * __pci_request_region - Reserved PCI I/O and memory resource
1886 * @pdev: PCI device whose resources are to be reserved
1887 * @bar: BAR to be reserved
1888 * @res_name: Name to be associated with resource.
1889 * @exclusive: whether the region access is exclusive or not
1891 * Mark the PCI region associated with PCI device @pdev BR @bar as
1892 * being reserved by owner @res_name. Do not access any
1893 * address inside the PCI regions unless this call returns
1896 * If @exclusive is set, then the region is marked so that userspace
1897 * is explicitly not allowed to map the resource via /dev/mem or
1898 * sysfs MMIO access.
1900 * Returns 0 on success, or %EBUSY on error. A warning
1901 * message is also printed on failure.
1903 static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name,
1906 struct pci_devres *dr;
1908 if (pci_resource_len(pdev, bar) == 0)
1911 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
1912 if (!request_region(pci_resource_start(pdev, bar),
1913 pci_resource_len(pdev, bar), res_name))
1916 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
1917 if (!__request_mem_region(pci_resource_start(pdev, bar),
1918 pci_resource_len(pdev, bar), res_name,
1923 dr = find_pci_dr(pdev);
1925 dr->region_mask |= 1 << bar;
1930 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar,
1931 &pdev->resource[bar]);
1936 * pci_request_region - Reserve PCI I/O and memory resource
1937 * @pdev: PCI device whose resources are to be reserved
1938 * @bar: BAR to be reserved
1939 * @res_name: Name to be associated with resource
1941 * Mark the PCI region associated with PCI device @pdev BAR @bar as
1942 * being reserved by owner @res_name. Do not access any
1943 * address inside the PCI regions unless this call returns
1946 * Returns 0 on success, or %EBUSY on error. A warning
1947 * message is also printed on failure.
1949 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
1951 return __pci_request_region(pdev, bar, res_name, 0);
1955 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
1956 * @pdev: PCI device whose resources are to be reserved
1957 * @bar: BAR to be reserved
1958 * @res_name: Name to be associated with resource.
1960 * Mark the PCI region associated with PCI device @pdev BR @bar as
1961 * being reserved by owner @res_name. Do not access any
1962 * address inside the PCI regions unless this call returns
1965 * Returns 0 on success, or %EBUSY on error. A warning
1966 * message is also printed on failure.
1968 * The key difference that _exclusive makes it that userspace is
1969 * explicitly not allowed to map the resource via /dev/mem or
1972 int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name)
1974 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
1977 * pci_release_selected_regions - Release selected PCI I/O and memory resources
1978 * @pdev: PCI device whose resources were previously reserved
1979 * @bars: Bitmask of BARs to be released
1981 * Release selected PCI I/O and memory resources previously reserved.
1982 * Call this function only after all use of the PCI regions has ceased.
1984 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
1988 for (i = 0; i < 6; i++)
1989 if (bars & (1 << i))
1990 pci_release_region(pdev, i);
1993 int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
1994 const char *res_name, int excl)
1998 for (i = 0; i < 6; i++)
1999 if (bars & (1 << i))
2000 if (__pci_request_region(pdev, i, res_name, excl))
2006 if (bars & (1 << i))
2007 pci_release_region(pdev, i);
2014 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
2015 * @pdev: PCI device whose resources are to be reserved
2016 * @bars: Bitmask of BARs to be requested
2017 * @res_name: Name to be associated with resource
2019 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
2020 const char *res_name)
2022 return __pci_request_selected_regions(pdev, bars, res_name, 0);
2025 int pci_request_selected_regions_exclusive(struct pci_dev *pdev,
2026 int bars, const char *res_name)
2028 return __pci_request_selected_regions(pdev, bars, res_name,
2029 IORESOURCE_EXCLUSIVE);
2033 * pci_release_regions - Release reserved PCI I/O and memory resources
2034 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
2036 * Releases all PCI I/O and memory resources previously reserved by a
2037 * successful call to pci_request_regions. Call this function only
2038 * after all use of the PCI regions has ceased.
2041 void pci_release_regions(struct pci_dev *pdev)
2043 pci_release_selected_regions(pdev, (1 << 6) - 1);
2047 * pci_request_regions - Reserved PCI I/O and memory resources
2048 * @pdev: PCI device whose resources are to be reserved
2049 * @res_name: Name to be associated with resource.
2051 * Mark all PCI regions associated with PCI device @pdev as
2052 * being reserved by owner @res_name. Do not access any
2053 * address inside the PCI regions unless this call returns
2056 * Returns 0 on success, or %EBUSY on error. A warning
2057 * message is also printed on failure.
2059 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
2061 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
2065 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
2066 * @pdev: PCI device whose resources are to be reserved
2067 * @res_name: Name to be associated with resource.
2069 * Mark all PCI regions associated with PCI device @pdev as
2070 * being reserved by owner @res_name. Do not access any
2071 * address inside the PCI regions unless this call returns
2074 * pci_request_regions_exclusive() will mark the region so that
2075 * /dev/mem and the sysfs MMIO access will not be allowed.
2077 * Returns 0 on success, or %EBUSY on error. A warning
2078 * message is also printed on failure.
2080 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
2082 return pci_request_selected_regions_exclusive(pdev,
2083 ((1 << 6) - 1), res_name);
2086 static void __pci_set_master(struct pci_dev *dev, bool enable)
2090 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
2092 cmd = old_cmd | PCI_COMMAND_MASTER;
2094 cmd = old_cmd & ~PCI_COMMAND_MASTER;
2095 if (cmd != old_cmd) {
2096 dev_dbg(&dev->dev, "%s bus mastering\n",
2097 enable ? "enabling" : "disabling");
2098 pci_write_config_word(dev, PCI_COMMAND, cmd);
2100 dev->is_busmaster = enable;
2104 * pci_set_master - enables bus-mastering for device dev
2105 * @dev: the PCI device to enable
2107 * Enables bus-mastering on the device and calls pcibios_set_master()
2108 * to do the needed arch specific settings.
2110 void pci_set_master(struct pci_dev *dev)
2112 __pci_set_master(dev, true);
2113 pcibios_set_master(dev);
2117 * pci_clear_master - disables bus-mastering for device dev
2118 * @dev: the PCI device to disable
2120 void pci_clear_master(struct pci_dev *dev)
2122 __pci_set_master(dev, false);
2126 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
2127 * @dev: the PCI device for which MWI is to be enabled
2129 * Helper function for pci_set_mwi.
2130 * Originally copied from drivers/net/acenic.c.
2131 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
2133 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2135 int pci_set_cacheline_size(struct pci_dev *dev)
2139 if (!pci_cache_line_size)
2142 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
2143 equal to or multiple of the right value. */
2144 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2145 if (cacheline_size >= pci_cache_line_size &&
2146 (cacheline_size % pci_cache_line_size) == 0)
2149 /* Write the correct value. */
2150 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
2152 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2153 if (cacheline_size == pci_cache_line_size)
2156 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not "
2157 "supported\n", pci_cache_line_size << 2);
2161 EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
2163 #ifdef PCI_DISABLE_MWI
2164 int pci_set_mwi(struct pci_dev *dev)
2169 int pci_try_set_mwi(struct pci_dev *dev)
2174 void pci_clear_mwi(struct pci_dev *dev)
2181 * pci_set_mwi - enables memory-write-invalidate PCI transaction
2182 * @dev: the PCI device for which MWI is enabled
2184 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2186 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2189 pci_set_mwi(struct pci_dev *dev)
2194 rc = pci_set_cacheline_size(dev);
2198 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2199 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
2200 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
2201 cmd |= PCI_COMMAND_INVALIDATE;
2202 pci_write_config_word(dev, PCI_COMMAND, cmd);
2209 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
2210 * @dev: the PCI device for which MWI is enabled
2212 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2213 * Callers are not required to check the return value.
2215 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2217 int pci_try_set_mwi(struct pci_dev *dev)
2219 int rc = pci_set_mwi(dev);
2224 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
2225 * @dev: the PCI device to disable
2227 * Disables PCI Memory-Write-Invalidate transaction on the device
2230 pci_clear_mwi(struct pci_dev *dev)
2234 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2235 if (cmd & PCI_COMMAND_INVALIDATE) {
2236 cmd &= ~PCI_COMMAND_INVALIDATE;
2237 pci_write_config_word(dev, PCI_COMMAND, cmd);
2240 #endif /* ! PCI_DISABLE_MWI */
2243 * pci_intx - enables/disables PCI INTx for device dev
2244 * @pdev: the PCI device to operate on
2245 * @enable: boolean: whether to enable or disable PCI INTx
2247 * Enables/disables PCI INTx for device dev
2250 pci_intx(struct pci_dev *pdev, int enable)
2252 u16 pci_command, new;
2254 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
2257 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
2259 new = pci_command | PCI_COMMAND_INTX_DISABLE;
2262 if (new != pci_command) {
2263 struct pci_devres *dr;
2265 pci_write_config_word(pdev, PCI_COMMAND, new);
2267 dr = find_pci_dr(pdev);
2268 if (dr && !dr->restore_intx) {
2269 dr->restore_intx = 1;
2270 dr->orig_intx = !enable;
2276 * pci_msi_off - disables any msi or msix capabilities
2277 * @dev: the PCI device to operate on
2279 * If you want to use msi see pci_enable_msi and friends.
2280 * This is a lower level primitive that allows us to disable
2281 * msi operation at the device level.
2283 void pci_msi_off(struct pci_dev *dev)
2288 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
2290 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
2291 control &= ~PCI_MSI_FLAGS_ENABLE;
2292 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
2294 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
2296 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
2297 control &= ~PCI_MSIX_FLAGS_ENABLE;
2298 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
2302 #ifndef HAVE_ARCH_PCI_SET_DMA_MAX_SEGMENT_SIZE
2303 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
2305 return dma_set_max_seg_size(&dev->dev, size);
2307 EXPORT_SYMBOL(pci_set_dma_max_seg_size);
2310 #ifndef HAVE_ARCH_PCI_SET_DMA_SEGMENT_BOUNDARY
2311 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
2313 return dma_set_seg_boundary(&dev->dev, mask);
2315 EXPORT_SYMBOL(pci_set_dma_seg_boundary);
2318 static int pcie_flr(struct pci_dev *dev, int probe)
2323 u16 status, control;
2325 pos = pci_pcie_cap(dev);
2329 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP, &cap);
2330 if (!(cap & PCI_EXP_DEVCAP_FLR))
2336 /* Wait for Transaction Pending bit clean */
2337 for (i = 0; i < 4; i++) {
2339 msleep((1 << (i - 1)) * 100);
2341 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
2342 if (!(status & PCI_EXP_DEVSTA_TRPND))
2346 dev_err(&dev->dev, "transaction is not cleared; "
2347 "proceeding with reset anyway\n");
2350 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &control);
2351 control |= PCI_EXP_DEVCTL_BCR_FLR;
2352 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, control);
2359 static int pci_af_flr(struct pci_dev *dev, int probe)
2366 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
2370 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
2371 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
2377 /* Wait for Transaction Pending bit clean */
2378 for (i = 0; i < 4; i++) {
2380 msleep((1 << (i - 1)) * 100);
2382 pci_read_config_byte(dev, pos + PCI_AF_STATUS, &status);
2383 if (!(status & PCI_AF_STATUS_TP))
2387 dev_err(&dev->dev, "transaction is not cleared; "
2388 "proceeding with reset anyway\n");
2391 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
2397 static int pci_pm_reset(struct pci_dev *dev, int probe)
2404 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
2405 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
2411 if (dev->current_state != PCI_D0)
2414 csr &= ~PCI_PM_CTRL_STATE_MASK;
2416 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
2417 pci_dev_d3_sleep(dev);
2419 csr &= ~PCI_PM_CTRL_STATE_MASK;
2421 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
2422 pci_dev_d3_sleep(dev);
2427 static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
2430 struct pci_dev *pdev;
2432 if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self)
2435 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
2442 pci_read_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, &ctrl);
2443 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
2444 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
2447 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
2448 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
2454 static int pci_dev_reset(struct pci_dev *dev, int probe)
2461 pci_block_user_cfg_access(dev);
2462 /* block PM suspend, driver probe, etc. */
2463 device_lock(&dev->dev);
2466 rc = pci_dev_specific_reset(dev, probe);
2470 rc = pcie_flr(dev, probe);
2474 rc = pci_af_flr(dev, probe);
2478 rc = pci_pm_reset(dev, probe);
2482 rc = pci_parent_bus_reset(dev, probe);
2485 device_unlock(&dev->dev);
2486 pci_unblock_user_cfg_access(dev);
2493 * __pci_reset_function - reset a PCI device function
2494 * @dev: PCI device to reset
2496 * Some devices allow an individual function to be reset without affecting
2497 * other functions in the same device. The PCI device must be responsive
2498 * to PCI config space in order to use this function.
2500 * The device function is presumed to be unused when this function is called.
2501 * Resetting the device will make the contents of PCI configuration space
2502 * random, so any caller of this must be prepared to reinitialise the
2503 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
2506 * Returns 0 if the device function was successfully reset or negative if the
2507 * device doesn't support resetting a single function.
2509 int __pci_reset_function(struct pci_dev *dev)
2511 return pci_dev_reset(dev, 0);
2513 EXPORT_SYMBOL_GPL(__pci_reset_function);
2516 * pci_probe_reset_function - check whether the device can be safely reset
2517 * @dev: PCI device to reset
2519 * Some devices allow an individual function to be reset without affecting
2520 * other functions in the same device. The PCI device must be responsive
2521 * to PCI config space in order to use this function.
2523 * Returns 0 if the device function can be reset or negative if the
2524 * device doesn't support resetting a single function.
2526 int pci_probe_reset_function(struct pci_dev *dev)
2528 return pci_dev_reset(dev, 1);
2532 * pci_reset_function - quiesce and reset a PCI device function
2533 * @dev: PCI device to reset
2535 * Some devices allow an individual function to be reset without affecting
2536 * other functions in the same device. The PCI device must be responsive
2537 * to PCI config space in order to use this function.
2539 * This function does not just reset the PCI portion of a device, but
2540 * clears all the state associated with the device. This function differs
2541 * from __pci_reset_function in that it saves and restores device state
2544 * Returns 0 if the device function was successfully reset or negative if the
2545 * device doesn't support resetting a single function.
2547 int pci_reset_function(struct pci_dev *dev)
2551 rc = pci_dev_reset(dev, 1);
2555 pci_save_state(dev);
2558 * both INTx and MSI are disabled after the Interrupt Disable bit
2559 * is set and the Bus Master bit is cleared.
2561 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
2563 rc = pci_dev_reset(dev, 0);
2565 pci_restore_state(dev);
2569 EXPORT_SYMBOL_GPL(pci_reset_function);
2572 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
2573 * @dev: PCI device to query
2575 * Returns mmrbc: maximum designed memory read count in bytes
2576 * or appropriate error value.
2578 int pcix_get_max_mmrbc(struct pci_dev *dev)
2583 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
2587 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
2590 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
2592 EXPORT_SYMBOL(pcix_get_max_mmrbc);
2595 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
2596 * @dev: PCI device to query
2598 * Returns mmrbc: maximum memory read count in bytes
2599 * or appropriate error value.
2601 int pcix_get_mmrbc(struct pci_dev *dev)
2606 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
2610 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
2613 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
2615 EXPORT_SYMBOL(pcix_get_mmrbc);
2618 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
2619 * @dev: PCI device to query
2620 * @mmrbc: maximum memory read count in bytes
2621 * valid values are 512, 1024, 2048, 4096
2623 * If possible sets maximum memory read byte count, some bridges have erratas
2624 * that prevent this.
2626 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
2632 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
2635 v = ffs(mmrbc) - 10;
2637 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
2641 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
2644 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
2647 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
2650 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
2652 if (v > o && dev->bus &&
2653 (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
2656 cmd &= ~PCI_X_CMD_MAX_READ;
2658 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
2663 EXPORT_SYMBOL(pcix_set_mmrbc);
2666 * pcie_get_readrq - get PCI Express read request size
2667 * @dev: PCI device to query
2669 * Returns maximum memory read request in bytes
2670 * or appropriate error value.
2672 int pcie_get_readrq(struct pci_dev *dev)
2677 cap = pci_pcie_cap(dev);
2681 ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
2683 ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
2687 EXPORT_SYMBOL(pcie_get_readrq);
2690 * pcie_set_readrq - set PCI Express maximum memory read request
2691 * @dev: PCI device to query
2692 * @rq: maximum memory read count in bytes
2693 * valid values are 128, 256, 512, 1024, 2048, 4096
2695 * If possible sets maximum read byte count
2697 int pcie_set_readrq(struct pci_dev *dev, int rq)
2699 int cap, err = -EINVAL;
2702 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
2705 v = (ffs(rq) - 8) << 12;
2707 cap = pci_pcie_cap(dev);
2711 err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
2715 if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) {
2716 ctl &= ~PCI_EXP_DEVCTL_READRQ;
2718 err = pci_write_config_dword(dev, cap + PCI_EXP_DEVCTL, ctl);
2724 EXPORT_SYMBOL(pcie_set_readrq);
2727 * pci_select_bars - Make BAR mask from the type of resource
2728 * @dev: the PCI device for which BAR mask is made
2729 * @flags: resource type mask to be selected
2731 * This helper routine makes bar mask from the type of resource.
2733 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
2736 for (i = 0; i < PCI_NUM_RESOURCES; i++)
2737 if (pci_resource_flags(dev, i) & flags)
2743 * pci_resource_bar - get position of the BAR associated with a resource
2744 * @dev: the PCI device
2745 * @resno: the resource number
2746 * @type: the BAR type to be filled in
2748 * Returns BAR position in config space, or 0 if the BAR is invalid.
2750 int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type)
2754 if (resno < PCI_ROM_RESOURCE) {
2755 *type = pci_bar_unknown;
2756 return PCI_BASE_ADDRESS_0 + 4 * resno;
2757 } else if (resno == PCI_ROM_RESOURCE) {
2758 *type = pci_bar_mem32;
2759 return dev->rom_base_reg;
2760 } else if (resno < PCI_BRIDGE_RESOURCES) {
2761 /* device specific resource */
2762 reg = pci_iov_resource_bar(dev, resno, type);
2767 dev_err(&dev->dev, "BAR %d: invalid resource\n", resno);
2771 /* Some architectures require additional programming to enable VGA */
2772 static arch_set_vga_state_t arch_set_vga_state;
2774 void __init pci_register_set_vga_state(arch_set_vga_state_t func)
2776 arch_set_vga_state = func; /* NULL disables */
2779 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
2780 unsigned int command_bits, bool change_bridge)
2782 if (arch_set_vga_state)
2783 return arch_set_vga_state(dev, decode, command_bits,
2789 * pci_set_vga_state - set VGA decode state on device and parents if requested
2790 * @dev: the PCI device
2791 * @decode: true = enable decoding, false = disable decoding
2792 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
2793 * @change_bridge: traverse ancestors and change bridges
2795 int pci_set_vga_state(struct pci_dev *dev, bool decode,
2796 unsigned int command_bits, bool change_bridge)
2798 struct pci_bus *bus;
2799 struct pci_dev *bridge;
2803 WARN_ON(command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY));
2805 /* ARCH specific VGA enables */
2806 rc = pci_set_vga_state_arch(dev, decode, command_bits, change_bridge);
2810 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2812 cmd |= command_bits;
2814 cmd &= ~command_bits;
2815 pci_write_config_word(dev, PCI_COMMAND, cmd);
2817 if (change_bridge == false)
2824 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
2827 cmd |= PCI_BRIDGE_CTL_VGA;
2829 cmd &= ~PCI_BRIDGE_CTL_VGA;
2830 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
2838 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
2839 static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
2840 static DEFINE_SPINLOCK(resource_alignment_lock);
2843 * pci_specified_resource_alignment - get resource alignment specified by user.
2844 * @dev: the PCI device to get
2846 * RETURNS: Resource alignment if it is specified.
2847 * Zero if it is not specified.
2849 resource_size_t pci_specified_resource_alignment(struct pci_dev *dev)
2851 int seg, bus, slot, func, align_order, count;
2852 resource_size_t align = 0;
2855 spin_lock(&resource_alignment_lock);
2856 p = resource_alignment_param;
2859 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
2865 if (sscanf(p, "%x:%x:%x.%x%n",
2866 &seg, &bus, &slot, &func, &count) != 4) {
2868 if (sscanf(p, "%x:%x.%x%n",
2869 &bus, &slot, &func, &count) != 3) {
2870 /* Invalid format */
2871 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
2877 if (seg == pci_domain_nr(dev->bus) &&
2878 bus == dev->bus->number &&
2879 slot == PCI_SLOT(dev->devfn) &&
2880 func == PCI_FUNC(dev->devfn)) {
2881 if (align_order == -1) {
2884 align = 1 << align_order;
2889 if (*p != ';' && *p != ',') {
2890 /* End of param or invalid format */
2895 spin_unlock(&resource_alignment_lock);
2900 * pci_is_reassigndev - check if specified PCI is target device to reassign
2901 * @dev: the PCI device to check
2903 * RETURNS: non-zero for PCI device is a target device to reassign,
2906 int pci_is_reassigndev(struct pci_dev *dev)
2908 return (pci_specified_resource_alignment(dev) != 0);
2911 ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
2913 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
2914 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
2915 spin_lock(&resource_alignment_lock);
2916 strncpy(resource_alignment_param, buf, count);
2917 resource_alignment_param[count] = '\0';
2918 spin_unlock(&resource_alignment_lock);
2922 ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
2925 spin_lock(&resource_alignment_lock);
2926 count = snprintf(buf, size, "%s", resource_alignment_param);
2927 spin_unlock(&resource_alignment_lock);
2931 static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
2933 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
2936 static ssize_t pci_resource_alignment_store(struct bus_type *bus,
2937 const char *buf, size_t count)
2939 return pci_set_resource_alignment_param(buf, count);
2942 BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
2943 pci_resource_alignment_store);
2945 static int __init pci_resource_alignment_sysfs_init(void)
2947 return bus_create_file(&pci_bus_type,
2948 &bus_attr_resource_alignment);
2951 late_initcall(pci_resource_alignment_sysfs_init);
2953 static void __devinit pci_no_domains(void)
2955 #ifdef CONFIG_PCI_DOMAINS
2956 pci_domains_supported = 0;
2961 * pci_ext_cfg_enabled - can we access extended PCI config space?
2962 * @dev: The PCI device of the root bridge.
2964 * Returns 1 if we can access PCI extended config space (offsets
2965 * greater than 0xff). This is the default implementation. Architecture
2966 * implementations can override this.
2968 int __attribute__ ((weak)) pci_ext_cfg_avail(struct pci_dev *dev)
2973 void __weak pci_fixup_cardbus(struct pci_bus *bus)
2976 EXPORT_SYMBOL(pci_fixup_cardbus);
2978 static int __init pci_setup(char *str)
2981 char *k = strchr(str, ',');
2984 if (*str && (str = pcibios_setup(str)) && *str) {
2985 if (!strcmp(str, "nomsi")) {
2987 } else if (!strcmp(str, "noaer")) {
2989 } else if (!strcmp(str, "nodomains")) {
2991 } else if (!strncmp(str, "cbiosize=", 9)) {
2992 pci_cardbus_io_size = memparse(str + 9, &str);
2993 } else if (!strncmp(str, "cbmemsize=", 10)) {
2994 pci_cardbus_mem_size = memparse(str + 10, &str);
2995 } else if (!strncmp(str, "resource_alignment=", 19)) {
2996 pci_set_resource_alignment_param(str + 19,
2998 } else if (!strncmp(str, "ecrc=", 5)) {
2999 pcie_ecrc_get_policy(str + 5);
3000 } else if (!strncmp(str, "hpiosize=", 9)) {
3001 pci_hotplug_io_size = memparse(str + 9, &str);
3002 } else if (!strncmp(str, "hpmemsize=", 10)) {
3003 pci_hotplug_mem_size = memparse(str + 10, &str);
3005 printk(KERN_ERR "PCI: Unknown option `%s'\n",
3013 early_param("pci", pci_setup);
3015 EXPORT_SYMBOL(pci_reenable_device);
3016 EXPORT_SYMBOL(pci_enable_device_io);
3017 EXPORT_SYMBOL(pci_enable_device_mem);
3018 EXPORT_SYMBOL(pci_enable_device);
3019 EXPORT_SYMBOL(pcim_enable_device);
3020 EXPORT_SYMBOL(pcim_pin_device);
3021 EXPORT_SYMBOL(pci_disable_device);
3022 EXPORT_SYMBOL(pci_find_capability);
3023 EXPORT_SYMBOL(pci_bus_find_capability);
3024 EXPORT_SYMBOL(pci_release_regions);
3025 EXPORT_SYMBOL(pci_request_regions);
3026 EXPORT_SYMBOL(pci_request_regions_exclusive);
3027 EXPORT_SYMBOL(pci_release_region);
3028 EXPORT_SYMBOL(pci_request_region);
3029 EXPORT_SYMBOL(pci_request_region_exclusive);
3030 EXPORT_SYMBOL(pci_release_selected_regions);
3031 EXPORT_SYMBOL(pci_request_selected_regions);
3032 EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
3033 EXPORT_SYMBOL(pci_set_master);
3034 EXPORT_SYMBOL(pci_clear_master);
3035 EXPORT_SYMBOL(pci_set_mwi);
3036 EXPORT_SYMBOL(pci_try_set_mwi);
3037 EXPORT_SYMBOL(pci_clear_mwi);
3038 EXPORT_SYMBOL_GPL(pci_intx);
3039 EXPORT_SYMBOL(pci_assign_resource);
3040 EXPORT_SYMBOL(pci_find_parent_resource);
3041 EXPORT_SYMBOL(pci_select_bars);
3043 EXPORT_SYMBOL(pci_set_power_state);
3044 EXPORT_SYMBOL(pci_save_state);
3045 EXPORT_SYMBOL(pci_restore_state);
3046 EXPORT_SYMBOL(pci_pme_capable);
3047 EXPORT_SYMBOL(pci_pme_active);
3048 EXPORT_SYMBOL(pci_wake_from_d3);
3049 EXPORT_SYMBOL(pci_target_state);
3050 EXPORT_SYMBOL(pci_prepare_to_sleep);
3051 EXPORT_SYMBOL(pci_back_from_sleep);
3052 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);