2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/pci.h>
15 #include <linux/slab.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <linux/string.h>
19 #include <linux/log2.h>
20 #include <linux/pci-aspm.h>
21 #include <linux/pm_wakeup.h>
22 #include <linux/interrupt.h>
23 #include <linux/device.h>
24 #include <linux/pm_runtime.h>
25 #include <asm/setup.h>
28 const char *pci_power_names[] = {
29 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
31 EXPORT_SYMBOL_GPL(pci_power_names);
33 int isa_dma_bridge_buggy;
34 EXPORT_SYMBOL(isa_dma_bridge_buggy);
37 EXPORT_SYMBOL(pci_pci_problems);
39 unsigned int pci_pm_d3_delay;
41 static void pci_pme_list_scan(struct work_struct *work);
43 static LIST_HEAD(pci_pme_list);
44 static DEFINE_MUTEX(pci_pme_list_mutex);
45 static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
47 struct pci_pme_device {
48 struct list_head list;
52 #define PME_TIMEOUT 1000 /* How long between PME checks */
54 static void pci_dev_d3_sleep(struct pci_dev *dev)
56 unsigned int delay = dev->d3_delay;
58 if (delay < pci_pm_d3_delay)
59 delay = pci_pm_d3_delay;
64 #ifdef CONFIG_PCI_DOMAINS
65 int pci_domains_supported = 1;
68 #define DEFAULT_CARDBUS_IO_SIZE (256)
69 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
70 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
71 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
72 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
74 #define DEFAULT_HOTPLUG_IO_SIZE (256)
75 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
76 /* pci=hpmemsize=nnM,hpiosize=nn can override this */
77 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
78 unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
80 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF;
83 * The default CLS is used if arch didn't set CLS explicitly and not
84 * all pci devices agree on the same value. Arch can override either
85 * the dfl or actual value as it sees fit. Don't forget this is
86 * measured in 32-bit words, not bytes.
88 u8 pci_dfl_cache_line_size __devinitdata = L1_CACHE_BYTES >> 2;
89 u8 pci_cache_line_size;
92 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
93 * @bus: pointer to PCI bus structure to search
95 * Given a PCI bus, returns the highest PCI bus number present in the set
96 * including the given PCI bus and its list of child PCI buses.
98 unsigned char pci_bus_max_busnr(struct pci_bus* bus)
100 struct list_head *tmp;
101 unsigned char max, n;
103 max = bus->subordinate;
104 list_for_each(tmp, &bus->children) {
105 n = pci_bus_max_busnr(pci_bus_b(tmp));
111 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
113 #ifdef CONFIG_HAS_IOMEM
114 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
117 * Make sure the BAR is actually a memory resource, not an IO resource
119 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
123 return ioremap_nocache(pci_resource_start(pdev, bar),
124 pci_resource_len(pdev, bar));
126 EXPORT_SYMBOL_GPL(pci_ioremap_bar);
131 * pci_max_busnr - returns maximum PCI bus number
133 * Returns the highest PCI bus number present in the system global list of
136 unsigned char __devinit
139 struct pci_bus *bus = NULL;
140 unsigned char max, n;
143 while ((bus = pci_find_next_bus(bus)) != NULL) {
144 n = pci_bus_max_busnr(bus);
153 #define PCI_FIND_CAP_TTL 48
155 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
156 u8 pos, int cap, int *ttl)
161 pci_bus_read_config_byte(bus, devfn, pos, &pos);
165 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
171 pos += PCI_CAP_LIST_NEXT;
176 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
179 int ttl = PCI_FIND_CAP_TTL;
181 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
184 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
186 return __pci_find_next_cap(dev->bus, dev->devfn,
187 pos + PCI_CAP_LIST_NEXT, cap);
189 EXPORT_SYMBOL_GPL(pci_find_next_capability);
191 static int __pci_bus_find_cap_start(struct pci_bus *bus,
192 unsigned int devfn, u8 hdr_type)
196 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
197 if (!(status & PCI_STATUS_CAP_LIST))
201 case PCI_HEADER_TYPE_NORMAL:
202 case PCI_HEADER_TYPE_BRIDGE:
203 return PCI_CAPABILITY_LIST;
204 case PCI_HEADER_TYPE_CARDBUS:
205 return PCI_CB_CAPABILITY_LIST;
214 * pci_find_capability - query for devices' capabilities
215 * @dev: PCI device to query
216 * @cap: capability code
218 * Tell if a device supports a given PCI capability.
219 * Returns the address of the requested capability structure within the
220 * device's PCI configuration space or 0 in case the device does not
221 * support it. Possible values for @cap:
223 * %PCI_CAP_ID_PM Power Management
224 * %PCI_CAP_ID_AGP Accelerated Graphics Port
225 * %PCI_CAP_ID_VPD Vital Product Data
226 * %PCI_CAP_ID_SLOTID Slot Identification
227 * %PCI_CAP_ID_MSI Message Signalled Interrupts
228 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
229 * %PCI_CAP_ID_PCIX PCI-X
230 * %PCI_CAP_ID_EXP PCI Express
232 int pci_find_capability(struct pci_dev *dev, int cap)
236 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
238 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
244 * pci_bus_find_capability - query for devices' capabilities
245 * @bus: the PCI bus to query
246 * @devfn: PCI device to query
247 * @cap: capability code
249 * Like pci_find_capability() but works for pci devices that do not have a
250 * pci_dev structure set up yet.
252 * Returns the address of the requested capability structure within the
253 * device's PCI configuration space or 0 in case the device does not
256 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
261 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
263 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
265 pos = __pci_find_next_cap(bus, devfn, pos, cap);
271 * pci_find_ext_capability - Find an extended capability
272 * @dev: PCI device to query
273 * @cap: capability code
275 * Returns the address of the requested extended capability structure
276 * within the device's PCI configuration space or 0 if the device does
277 * not support it. Possible values for @cap:
279 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
280 * %PCI_EXT_CAP_ID_VC Virtual Channel
281 * %PCI_EXT_CAP_ID_DSN Device Serial Number
282 * %PCI_EXT_CAP_ID_PWR Power Budgeting
284 int pci_find_ext_capability(struct pci_dev *dev, int cap)
288 int pos = PCI_CFG_SPACE_SIZE;
290 /* minimum 8 bytes per capability */
291 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
293 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
296 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
300 * If we have no capabilities, this is indicated by cap ID,
301 * cap version and next pointer all being 0.
307 if (PCI_EXT_CAP_ID(header) == cap)
310 pos = PCI_EXT_CAP_NEXT(header);
311 if (pos < PCI_CFG_SPACE_SIZE)
314 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
320 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
323 * pci_bus_find_ext_capability - find an extended capability
324 * @bus: the PCI bus to query
325 * @devfn: PCI device to query
326 * @cap: capability code
328 * Like pci_find_ext_capability() but works for pci devices that do not have a
329 * pci_dev structure set up yet.
331 * Returns the address of the requested capability structure within the
332 * device's PCI configuration space or 0 in case the device does not
335 int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn,
340 int pos = PCI_CFG_SPACE_SIZE;
342 /* minimum 8 bytes per capability */
343 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
345 if (!pci_bus_read_config_dword(bus, devfn, pos, &header))
347 if (header == 0xffffffff || header == 0)
351 if (PCI_EXT_CAP_ID(header) == cap)
354 pos = PCI_EXT_CAP_NEXT(header);
355 if (pos < PCI_CFG_SPACE_SIZE)
358 if (!pci_bus_read_config_dword(bus, devfn, pos, &header))
365 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
367 int rc, ttl = PCI_FIND_CAP_TTL;
370 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
371 mask = HT_3BIT_CAP_MASK;
373 mask = HT_5BIT_CAP_MASK;
375 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
376 PCI_CAP_ID_HT, &ttl);
378 rc = pci_read_config_byte(dev, pos + 3, &cap);
379 if (rc != PCIBIOS_SUCCESSFUL)
382 if ((cap & mask) == ht_cap)
385 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
386 pos + PCI_CAP_LIST_NEXT,
387 PCI_CAP_ID_HT, &ttl);
393 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
394 * @dev: PCI device to query
395 * @pos: Position from which to continue searching
396 * @ht_cap: Hypertransport capability code
398 * To be used in conjunction with pci_find_ht_capability() to search for
399 * all capabilities matching @ht_cap. @pos should always be a value returned
400 * from pci_find_ht_capability().
402 * NB. To be 100% safe against broken PCI devices, the caller should take
403 * steps to avoid an infinite loop.
405 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
407 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
409 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
412 * pci_find_ht_capability - query a device's Hypertransport capabilities
413 * @dev: PCI device to query
414 * @ht_cap: Hypertransport capability code
416 * Tell if a device supports a given Hypertransport capability.
417 * Returns an address within the device's PCI configuration space
418 * or 0 in case the device does not support the request capability.
419 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
420 * which has a Hypertransport capability matching @ht_cap.
422 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
426 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
428 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
432 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
435 * pci_find_parent_resource - return resource region of parent bus of given region
436 * @dev: PCI device structure contains resources to be searched
437 * @res: child resource record for which parent is sought
439 * For given resource region of given device, return the resource
440 * region of parent bus the given region is contained in or where
441 * it should be allocated from.
444 pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
446 const struct pci_bus *bus = dev->bus;
448 struct resource *best = NULL, *r;
450 pci_bus_for_each_resource(bus, r, i) {
453 if (res->start && !(res->start >= r->start && res->end <= r->end))
454 continue; /* Not contained */
455 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
456 continue; /* Wrong type */
457 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
458 return r; /* Exact match */
459 /* We can't insert a non-prefetch resource inside a prefetchable parent .. */
460 if (r->flags & IORESOURCE_PREFETCH)
462 /* .. but we can put a prefetchable resource inside a non-prefetchable one */
470 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
471 * @dev: PCI device to have its BARs restored
473 * Restore the BAR values for a given device, so as to make it
474 * accessible by its driver.
477 pci_restore_bars(struct pci_dev *dev)
481 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
482 pci_update_resource(dev, i);
485 static struct pci_platform_pm_ops *pci_platform_pm;
487 int pci_set_platform_pm(struct pci_platform_pm_ops *ops)
489 if (!ops->is_manageable || !ops->set_state || !ops->choose_state
490 || !ops->sleep_wake || !ops->can_wakeup)
492 pci_platform_pm = ops;
496 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
498 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
501 static inline int platform_pci_set_power_state(struct pci_dev *dev,
504 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
507 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
509 return pci_platform_pm ?
510 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
513 static inline bool platform_pci_can_wakeup(struct pci_dev *dev)
515 return pci_platform_pm ? pci_platform_pm->can_wakeup(dev) : false;
518 static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
520 return pci_platform_pm ?
521 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
524 static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable)
526 return pci_platform_pm ?
527 pci_platform_pm->run_wake(dev, enable) : -ENODEV;
531 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
533 * @dev: PCI device to handle.
534 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
537 * -EINVAL if the requested state is invalid.
538 * -EIO if device does not support PCI PM or its PM capabilities register has a
539 * wrong version, or device doesn't support the requested state.
540 * 0 if device already is in the requested state.
541 * 0 if device's power state has been successfully changed.
543 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
546 bool need_restore = false;
548 /* Check if we're already there */
549 if (dev->current_state == state)
555 if (state < PCI_D0 || state > PCI_D3hot)
558 /* Validate current state:
559 * Can enter D0 from any state, but if we can only go deeper
560 * to sleep if we're already in a low power state
562 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
563 && dev->current_state > state) {
564 dev_err(&dev->dev, "invalid power transition "
565 "(from state %d to %d)\n", dev->current_state, state);
569 /* check if this device supports the desired state */
570 if ((state == PCI_D1 && !dev->d1_support)
571 || (state == PCI_D2 && !dev->d2_support))
574 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
576 /* If we're (effectively) in D3, force entire word to 0.
577 * This doesn't affect PME_Status, disables PME_En, and
578 * sets PowerState to 0.
580 switch (dev->current_state) {
584 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
589 case PCI_UNKNOWN: /* Boot-up */
590 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
591 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
593 /* Fall-through: force to D0 */
599 /* enter specified state */
600 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
602 /* Mandatory power management transition delays */
603 /* see PCI PM 1.1 5.6.1 table 18 */
604 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
605 pci_dev_d3_sleep(dev);
606 else if (state == PCI_D2 || dev->current_state == PCI_D2)
607 udelay(PCI_PM_D2_DELAY);
609 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
610 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
611 if (dev->current_state != state && printk_ratelimit())
612 dev_info(&dev->dev, "Refused to change power state, "
613 "currently in D%d\n", dev->current_state);
615 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
616 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
617 * from D3hot to D0 _may_ perform an internal reset, thereby
618 * going to "D0 Uninitialized" rather than "D0 Initialized".
619 * For example, at least some versions of the 3c905B and the
620 * 3c556B exhibit this behaviour.
622 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
623 * devices in a D3hot state at boot. Consequently, we need to
624 * restore at least the BARs so that the device will be
625 * accessible to its driver.
628 pci_restore_bars(dev);
631 pcie_aspm_pm_state_change(dev->bus->self);
637 * pci_update_current_state - Read PCI power state of given device from its
638 * PCI PM registers and cache it
639 * @dev: PCI device to handle.
640 * @state: State to cache in case the device doesn't have the PM capability
642 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
647 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
648 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
650 dev->current_state = state;
655 * pci_platform_power_transition - Use platform to change device power state
656 * @dev: PCI device to handle.
657 * @state: State to put the device into.
659 static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
663 if (platform_pci_power_manageable(dev)) {
664 error = platform_pci_set_power_state(dev, state);
666 pci_update_current_state(dev, state);
670 if (error && !dev->pm_cap) /* Fall back to PCI_D0 */
671 dev->current_state = PCI_D0;
677 * __pci_start_power_transition - Start power transition of a PCI device
678 * @dev: PCI device to handle.
679 * @state: State to put the device into.
681 static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
684 pci_platform_power_transition(dev, PCI_D0);
688 * __pci_complete_power_transition - Complete power transition of a PCI device
689 * @dev: PCI device to handle.
690 * @state: State to put the device into.
692 * This function should not be called directly by device drivers.
694 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
696 return state >= PCI_D0 ?
697 pci_platform_power_transition(dev, state) : -EINVAL;
699 EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
702 * pci_set_power_state - Set the power state of a PCI device
703 * @dev: PCI device to handle.
704 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
706 * Transition a device to a new power state, using the platform firmware and/or
707 * the device's PCI PM registers.
710 * -EINVAL if the requested state is invalid.
711 * -EIO if device does not support PCI PM or its PM capabilities register has a
712 * wrong version, or device doesn't support the requested state.
713 * 0 if device already is in the requested state.
714 * 0 if device's power state has been successfully changed.
716 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
720 /* bound the state we're entering */
721 if (state > PCI_D3hot)
723 else if (state < PCI_D0)
725 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
727 * If the device or the parent bridge do not support PCI PM,
728 * ignore the request if we're doing anything other than putting
729 * it into D0 (which would only happen on boot).
733 __pci_start_power_transition(dev, state);
735 /* This device is quirked not to be put into D3, so
736 don't put it in D3 */
737 if (state == PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
740 error = pci_raw_set_power_state(dev, state);
742 if (!__pci_complete_power_transition(dev, state))
745 * When aspm_policy is "powersave" this call ensures
746 * that ASPM is configured.
748 if (!error && dev->bus->self)
749 pcie_aspm_powersave_config_link(dev->bus->self);
755 * pci_choose_state - Choose the power state of a PCI device
756 * @dev: PCI device to be suspended
757 * @state: target sleep state for the whole system. This is the value
758 * that is passed to suspend() function.
760 * Returns PCI power state suitable for given device and given system
764 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
768 if (!pci_find_capability(dev, PCI_CAP_ID_PM))
771 ret = platform_pci_choose_state(dev);
772 if (ret != PCI_POWER_ERROR)
775 switch (state.event) {
778 case PM_EVENT_FREEZE:
779 case PM_EVENT_PRETHAW:
780 /* REVISIT both freeze and pre-thaw "should" use D0 */
781 case PM_EVENT_SUSPEND:
782 case PM_EVENT_HIBERNATE:
785 dev_info(&dev->dev, "unrecognized suspend event %d\n",
792 EXPORT_SYMBOL(pci_choose_state);
794 #define PCI_EXP_SAVE_REGS 7
796 #define pcie_cap_has_devctl(type, flags) 1
797 #define pcie_cap_has_lnkctl(type, flags) \
798 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
799 (type == PCI_EXP_TYPE_ROOT_PORT || \
800 type == PCI_EXP_TYPE_ENDPOINT || \
801 type == PCI_EXP_TYPE_LEG_END))
802 #define pcie_cap_has_sltctl(type, flags) \
803 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
804 ((type == PCI_EXP_TYPE_ROOT_PORT) || \
805 (type == PCI_EXP_TYPE_DOWNSTREAM && \
806 (flags & PCI_EXP_FLAGS_SLOT))))
807 #define pcie_cap_has_rtctl(type, flags) \
808 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
809 (type == PCI_EXP_TYPE_ROOT_PORT || \
810 type == PCI_EXP_TYPE_RC_EC))
811 #define pcie_cap_has_devctl2(type, flags) \
812 ((flags & PCI_EXP_FLAGS_VERS) > 1)
813 #define pcie_cap_has_lnkctl2(type, flags) \
814 ((flags & PCI_EXP_FLAGS_VERS) > 1)
815 #define pcie_cap_has_sltctl2(type, flags) \
816 ((flags & PCI_EXP_FLAGS_VERS) > 1)
818 static int pci_save_pcie_state(struct pci_dev *dev)
821 struct pci_cap_saved_state *save_state;
825 pos = pci_pcie_cap(dev);
829 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
831 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
834 cap = (u16 *)&save_state->cap.data[0];
836 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
838 if (pcie_cap_has_devctl(dev->pcie_type, flags))
839 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]);
840 if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
841 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
842 if (pcie_cap_has_sltctl(dev->pcie_type, flags))
843 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
844 if (pcie_cap_has_rtctl(dev->pcie_type, flags))
845 pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
846 if (pcie_cap_has_devctl2(dev->pcie_type, flags))
847 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &cap[i++]);
848 if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
849 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL2, &cap[i++]);
850 if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
851 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL2, &cap[i++]);
856 static void pci_restore_pcie_state(struct pci_dev *dev)
859 struct pci_cap_saved_state *save_state;
863 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
864 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
865 if (!save_state || pos <= 0)
867 cap = (u16 *)&save_state->cap.data[0];
869 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
871 if (pcie_cap_has_devctl(dev->pcie_type, flags))
872 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
873 if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
874 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
875 if (pcie_cap_has_sltctl(dev->pcie_type, flags))
876 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
877 if (pcie_cap_has_rtctl(dev->pcie_type, flags))
878 pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
879 if (pcie_cap_has_devctl2(dev->pcie_type, flags))
880 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, cap[i++]);
881 if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
882 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL2, cap[i++]);
883 if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
884 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL2, cap[i++]);
888 static int pci_save_pcix_state(struct pci_dev *dev)
891 struct pci_cap_saved_state *save_state;
893 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
897 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
899 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
903 pci_read_config_word(dev, pos + PCI_X_CMD,
904 (u16 *)save_state->cap.data);
909 static void pci_restore_pcix_state(struct pci_dev *dev)
912 struct pci_cap_saved_state *save_state;
915 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
916 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
917 if (!save_state || pos <= 0)
919 cap = (u16 *)&save_state->cap.data[0];
921 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
926 * pci_save_state - save the PCI configuration space of a device before suspending
927 * @dev: - PCI device that we're dealing with
930 pci_save_state(struct pci_dev *dev)
933 /* XXX: 100% dword access ok here? */
934 for (i = 0; i < 16; i++)
935 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
936 dev->state_saved = true;
937 if ((i = pci_save_pcie_state(dev)) != 0)
939 if ((i = pci_save_pcix_state(dev)) != 0)
945 * pci_restore_state - Restore the saved state of a PCI device
946 * @dev: - PCI device that we're dealing with
948 void pci_restore_state(struct pci_dev *dev)
953 if (!dev->state_saved)
956 /* PCI Express register must be restored first */
957 pci_restore_pcie_state(dev);
960 * The Base Address register should be programmed before the command
963 for (i = 15; i >= 0; i--) {
964 pci_read_config_dword(dev, i * 4, &val);
965 if (val != dev->saved_config_space[i]) {
966 dev_printk(KERN_DEBUG, &dev->dev, "restoring config "
967 "space at offset %#x (was %#x, writing %#x)\n",
968 i, val, (int)dev->saved_config_space[i]);
969 pci_write_config_dword(dev,i * 4,
970 dev->saved_config_space[i]);
973 pci_restore_pcix_state(dev);
974 pci_restore_msi_state(dev);
975 pci_restore_iov_state(dev);
977 dev->state_saved = false;
980 struct pci_saved_state {
981 u32 config_space[16];
982 struct pci_cap_saved_data cap[0];
986 * pci_store_saved_state - Allocate and return an opaque struct containing
987 * the device saved state.
988 * @dev: PCI device that we're dealing with
990 * Rerturn NULL if no state or error.
992 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
994 struct pci_saved_state *state;
995 struct pci_cap_saved_state *tmp;
996 struct pci_cap_saved_data *cap;
997 struct hlist_node *pos;
1000 if (!dev->state_saved)
1003 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1005 hlist_for_each_entry(tmp, pos, &dev->saved_cap_space, next)
1006 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1008 state = kzalloc(size, GFP_KERNEL);
1012 memcpy(state->config_space, dev->saved_config_space,
1013 sizeof(state->config_space));
1016 hlist_for_each_entry(tmp, pos, &dev->saved_cap_space, next) {
1017 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1018 memcpy(cap, &tmp->cap, len);
1019 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1021 /* Empty cap_save terminates list */
1025 EXPORT_SYMBOL_GPL(pci_store_saved_state);
1028 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1029 * @dev: PCI device that we're dealing with
1030 * @state: Saved state returned from pci_store_saved_state()
1032 int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state)
1034 struct pci_cap_saved_data *cap;
1036 dev->state_saved = false;
1041 memcpy(dev->saved_config_space, state->config_space,
1042 sizeof(state->config_space));
1046 struct pci_cap_saved_state *tmp;
1048 tmp = pci_find_saved_cap(dev, cap->cap_nr);
1049 if (!tmp || tmp->cap.size != cap->size)
1052 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1053 cap = (struct pci_cap_saved_data *)((u8 *)cap +
1054 sizeof(struct pci_cap_saved_data) + cap->size);
1057 dev->state_saved = true;
1060 EXPORT_SYMBOL_GPL(pci_load_saved_state);
1063 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1064 * and free the memory allocated for it.
1065 * @dev: PCI device that we're dealing with
1066 * @state: Pointer to saved state returned from pci_store_saved_state()
1068 int pci_load_and_free_saved_state(struct pci_dev *dev,
1069 struct pci_saved_state **state)
1071 int ret = pci_load_saved_state(dev, *state);
1076 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1078 static int do_pci_enable_device(struct pci_dev *dev, int bars)
1082 err = pci_set_power_state(dev, PCI_D0);
1083 if (err < 0 && err != -EIO)
1085 err = pcibios_enable_device(dev, bars);
1088 pci_fixup_device(pci_fixup_enable, dev);
1094 * pci_reenable_device - Resume abandoned device
1095 * @dev: PCI device to be resumed
1097 * Note this function is a backend of pci_default_resume and is not supposed
1098 * to be called by normal code, write proper resume handler and use it instead.
1100 int pci_reenable_device(struct pci_dev *dev)
1102 if (pci_is_enabled(dev))
1103 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1107 static int __pci_enable_device_flags(struct pci_dev *dev,
1108 resource_size_t flags)
1114 * Power state could be unknown at this point, either due to a fresh
1115 * boot or a device removal call. So get the current power state
1116 * so that things like MSI message writing will behave as expected
1117 * (e.g. if the device really is in D0 at enable time).
1121 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1122 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1125 if (atomic_add_return(1, &dev->enable_cnt) > 1)
1126 return 0; /* already enabled */
1128 /* only skip sriov related */
1129 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
1130 if (dev->resource[i].flags & flags)
1132 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
1133 if (dev->resource[i].flags & flags)
1136 err = do_pci_enable_device(dev, bars);
1138 atomic_dec(&dev->enable_cnt);
1143 * pci_enable_device_io - Initialize a device for use with IO space
1144 * @dev: PCI device to be initialized
1146 * Initialize device before it's used by a driver. Ask low-level code
1147 * to enable I/O resources. Wake up the device if it was suspended.
1148 * Beware, this function can fail.
1150 int pci_enable_device_io(struct pci_dev *dev)
1152 return __pci_enable_device_flags(dev, IORESOURCE_IO);
1156 * pci_enable_device_mem - Initialize a device for use with Memory space
1157 * @dev: PCI device to be initialized
1159 * Initialize device before it's used by a driver. Ask low-level code
1160 * to enable Memory resources. Wake up the device if it was suspended.
1161 * Beware, this function can fail.
1163 int pci_enable_device_mem(struct pci_dev *dev)
1165 return __pci_enable_device_flags(dev, IORESOURCE_MEM);
1169 * pci_enable_device - Initialize device before it's used by a driver.
1170 * @dev: PCI device to be initialized
1172 * Initialize device before it's used by a driver. Ask low-level code
1173 * to enable I/O and memory. Wake up the device if it was suspended.
1174 * Beware, this function can fail.
1176 * Note we don't actually enable the device many times if we call
1177 * this function repeatedly (we just increment the count).
1179 int pci_enable_device(struct pci_dev *dev)
1181 return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
1185 * Managed PCI resources. This manages device on/off, intx/msi/msix
1186 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1187 * there's no need to track it separately. pci_devres is initialized
1188 * when a device is enabled using managed PCI device enable interface.
1191 unsigned int enabled:1;
1192 unsigned int pinned:1;
1193 unsigned int orig_intx:1;
1194 unsigned int restore_intx:1;
1198 static void pcim_release(struct device *gendev, void *res)
1200 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
1201 struct pci_devres *this = res;
1204 if (dev->msi_enabled)
1205 pci_disable_msi(dev);
1206 if (dev->msix_enabled)
1207 pci_disable_msix(dev);
1209 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1210 if (this->region_mask & (1 << i))
1211 pci_release_region(dev, i);
1213 if (this->restore_intx)
1214 pci_intx(dev, this->orig_intx);
1216 if (this->enabled && !this->pinned)
1217 pci_disable_device(dev);
1220 static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
1222 struct pci_devres *dr, *new_dr;
1224 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1228 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1231 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1234 static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
1236 if (pci_is_managed(pdev))
1237 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1242 * pcim_enable_device - Managed pci_enable_device()
1243 * @pdev: PCI device to be initialized
1245 * Managed pci_enable_device().
1247 int pcim_enable_device(struct pci_dev *pdev)
1249 struct pci_devres *dr;
1252 dr = get_pci_dr(pdev);
1258 rc = pci_enable_device(pdev);
1260 pdev->is_managed = 1;
1267 * pcim_pin_device - Pin managed PCI device
1268 * @pdev: PCI device to pin
1270 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1271 * driver detach. @pdev must have been enabled with
1272 * pcim_enable_device().
1274 void pcim_pin_device(struct pci_dev *pdev)
1276 struct pci_devres *dr;
1278 dr = find_pci_dr(pdev);
1279 WARN_ON(!dr || !dr->enabled);
1285 * pcibios_disable_device - disable arch specific PCI resources for device dev
1286 * @dev: the PCI device to disable
1288 * Disables architecture specific PCI resources for the device. This
1289 * is the default implementation. Architecture implementations can
1292 void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
1294 static void do_pci_disable_device(struct pci_dev *dev)
1298 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1299 if (pci_command & PCI_COMMAND_MASTER) {
1300 pci_command &= ~PCI_COMMAND_MASTER;
1301 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1304 pcibios_disable_device(dev);
1308 * pci_disable_enabled_device - Disable device without updating enable_cnt
1309 * @dev: PCI device to disable
1311 * NOTE: This function is a backend of PCI power management routines and is
1312 * not supposed to be called drivers.
1314 void pci_disable_enabled_device(struct pci_dev *dev)
1316 if (pci_is_enabled(dev))
1317 do_pci_disable_device(dev);
1321 * pci_disable_device - Disable PCI device after use
1322 * @dev: PCI device to be disabled
1324 * Signal to the system that the PCI device is not in use by the system
1325 * anymore. This only involves disabling PCI bus-mastering, if active.
1327 * Note we don't actually disable the device until all callers of
1328 * pci_enable_device() have called pci_disable_device().
1331 pci_disable_device(struct pci_dev *dev)
1333 struct pci_devres *dr;
1335 dr = find_pci_dr(dev);
1339 if (atomic_sub_return(1, &dev->enable_cnt) != 0)
1342 do_pci_disable_device(dev);
1344 dev->is_busmaster = 0;
1348 * pcibios_set_pcie_reset_state - set reset state for device dev
1349 * @dev: the PCIe device reset
1350 * @state: Reset state to enter into
1353 * Sets the PCIe reset state for the device. This is the default
1354 * implementation. Architecture implementations can override this.
1356 int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev,
1357 enum pcie_reset_state state)
1363 * pci_set_pcie_reset_state - set reset state for device dev
1364 * @dev: the PCIe device reset
1365 * @state: Reset state to enter into
1368 * Sets the PCI reset state for the device.
1370 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1372 return pcibios_set_pcie_reset_state(dev, state);
1376 * pci_check_pme_status - Check if given device has generated PME.
1377 * @dev: Device to check.
1379 * Check the PME status of the device and if set, clear it and clear PME enable
1380 * (if set). Return 'true' if PME status and PME enable were both set or
1381 * 'false' otherwise.
1383 bool pci_check_pme_status(struct pci_dev *dev)
1392 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
1393 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
1394 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
1397 /* Clear PME status. */
1398 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1399 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
1400 /* Disable PME to avoid interrupt flood. */
1401 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1405 pci_write_config_word(dev, pmcsr_pos, pmcsr);
1411 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1412 * @dev: Device to handle.
1413 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
1415 * Check if @dev has generated PME and queue a resume request for it in that
1418 static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
1420 if (pme_poll_reset && dev->pme_poll)
1421 dev->pme_poll = false;
1423 if (pci_check_pme_status(dev)) {
1424 pci_wakeup_event(dev);
1425 pm_request_resume(&dev->dev);
1431 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1432 * @bus: Top bus of the subtree to walk.
1434 void pci_pme_wakeup_bus(struct pci_bus *bus)
1437 pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
1441 * pci_pme_capable - check the capability of PCI device to generate PME#
1442 * @dev: PCI device to handle.
1443 * @state: PCI state from which device will issue PME#.
1445 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
1450 return !!(dev->pme_support & (1 << state));
1453 static void pci_pme_list_scan(struct work_struct *work)
1455 struct pci_pme_device *pme_dev, *n;
1457 mutex_lock(&pci_pme_list_mutex);
1458 if (!list_empty(&pci_pme_list)) {
1459 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
1460 if (pme_dev->dev->pme_poll) {
1461 pci_pme_wakeup(pme_dev->dev, NULL);
1463 list_del(&pme_dev->list);
1467 if (!list_empty(&pci_pme_list))
1468 schedule_delayed_work(&pci_pme_work,
1469 msecs_to_jiffies(PME_TIMEOUT));
1471 mutex_unlock(&pci_pme_list_mutex);
1475 * pci_pme_active - enable or disable PCI device's PME# function
1476 * @dev: PCI device to handle.
1477 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1479 * The caller must verify that the device is capable of generating PME# before
1480 * calling this function with @enable equal to 'true'.
1482 void pci_pme_active(struct pci_dev *dev, bool enable)
1489 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1490 /* Clear PME_Status by writing 1 to it and enable PME# */
1491 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1493 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1495 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1497 /* PCI (as opposed to PCIe) PME requires that the device have
1498 its PME# line hooked up correctly. Not all hardware vendors
1499 do this, so the PME never gets delivered and the device
1500 remains asleep. The easiest way around this is to
1501 periodically walk the list of suspended devices and check
1502 whether any have their PME flag set. The assumption is that
1503 we'll wake up often enough anyway that this won't be a huge
1504 hit, and the power savings from the devices will still be a
1507 if (dev->pme_poll) {
1508 struct pci_pme_device *pme_dev;
1510 pme_dev = kmalloc(sizeof(struct pci_pme_device),
1515 mutex_lock(&pci_pme_list_mutex);
1516 list_add(&pme_dev->list, &pci_pme_list);
1517 if (list_is_singular(&pci_pme_list))
1518 schedule_delayed_work(&pci_pme_work,
1519 msecs_to_jiffies(PME_TIMEOUT));
1520 mutex_unlock(&pci_pme_list_mutex);
1522 mutex_lock(&pci_pme_list_mutex);
1523 list_for_each_entry(pme_dev, &pci_pme_list, list) {
1524 if (pme_dev->dev == dev) {
1525 list_del(&pme_dev->list);
1530 mutex_unlock(&pci_pme_list_mutex);
1535 dev_printk(KERN_DEBUG, &dev->dev, "PME# %s\n",
1536 enable ? "enabled" : "disabled");
1540 * __pci_enable_wake - enable PCI device as wakeup event source
1541 * @dev: PCI device affected
1542 * @state: PCI state from which device will issue wakeup events
1543 * @runtime: True if the events are to be generated at run time
1544 * @enable: True to enable event generation; false to disable
1546 * This enables the device as a wakeup event source, or disables it.
1547 * When such events involves platform-specific hooks, those hooks are
1548 * called automatically by this routine.
1550 * Devices with legacy power management (no standard PCI PM capabilities)
1551 * always require such platform hooks.
1554 * 0 is returned on success
1555 * -EINVAL is returned if device is not supposed to wake up the system
1556 * Error code depending on the platform is returned if both the platform and
1557 * the native mechanism fail to enable the generation of wake-up events
1559 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1560 bool runtime, bool enable)
1564 if (enable && !runtime && !device_may_wakeup(&dev->dev))
1567 /* Don't do the same thing twice in a row for one device. */
1568 if (!!enable == !!dev->wakeup_prepared)
1572 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1573 * Anderson we should be doing PME# wake enable followed by ACPI wake
1574 * enable. To disable wake-up we call the platform first, for symmetry.
1580 if (pci_pme_capable(dev, state))
1581 pci_pme_active(dev, true);
1584 error = runtime ? platform_pci_run_wake(dev, true) :
1585 platform_pci_sleep_wake(dev, true);
1589 dev->wakeup_prepared = true;
1592 platform_pci_run_wake(dev, false);
1594 platform_pci_sleep_wake(dev, false);
1595 pci_pme_active(dev, false);
1596 dev->wakeup_prepared = false;
1601 EXPORT_SYMBOL(__pci_enable_wake);
1604 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1605 * @dev: PCI device to prepare
1606 * @enable: True to enable wake-up event generation; false to disable
1608 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1609 * and this function allows them to set that up cleanly - pci_enable_wake()
1610 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1611 * ordering constraints.
1613 * This function only returns error code if the device is not capable of
1614 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1615 * enable wake-up power for it.
1617 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1619 return pci_pme_capable(dev, PCI_D3cold) ?
1620 pci_enable_wake(dev, PCI_D3cold, enable) :
1621 pci_enable_wake(dev, PCI_D3hot, enable);
1625 * pci_target_state - find an appropriate low power state for a given PCI dev
1628 * Use underlying platform code to find a supported low power state for @dev.
1629 * If the platform can't manage @dev, return the deepest state from which it
1630 * can generate wake events, based on any available PME info.
1632 pci_power_t pci_target_state(struct pci_dev *dev)
1634 pci_power_t target_state = PCI_D3hot;
1636 if (platform_pci_power_manageable(dev)) {
1638 * Call the platform to choose the target state of the device
1639 * and enable wake-up from this state if supported.
1641 pci_power_t state = platform_pci_choose_state(dev);
1644 case PCI_POWER_ERROR:
1649 if (pci_no_d1d2(dev))
1652 target_state = state;
1654 } else if (!dev->pm_cap) {
1655 target_state = PCI_D0;
1656 } else if (device_may_wakeup(&dev->dev)) {
1658 * Find the deepest state from which the device can generate
1659 * wake-up events, make it the target state and enable device
1662 if (dev->pme_support) {
1664 && !(dev->pme_support & (1 << target_state)))
1669 return target_state;
1673 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1674 * @dev: Device to handle.
1676 * Choose the power state appropriate for the device depending on whether
1677 * it can wake up the system and/or is power manageable by the platform
1678 * (PCI_D3hot is the default) and put the device into that state.
1680 int pci_prepare_to_sleep(struct pci_dev *dev)
1682 pci_power_t target_state = pci_target_state(dev);
1685 if (target_state == PCI_POWER_ERROR)
1688 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
1690 error = pci_set_power_state(dev, target_state);
1693 pci_enable_wake(dev, target_state, false);
1699 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
1700 * @dev: Device to handle.
1702 * Disable device's system wake-up capability and put it into D0.
1704 int pci_back_from_sleep(struct pci_dev *dev)
1706 pci_enable_wake(dev, PCI_D0, false);
1707 return pci_set_power_state(dev, PCI_D0);
1711 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
1712 * @dev: PCI device being suspended.
1714 * Prepare @dev to generate wake-up events at run time and put it into a low
1717 int pci_finish_runtime_suspend(struct pci_dev *dev)
1719 pci_power_t target_state = pci_target_state(dev);
1722 if (target_state == PCI_POWER_ERROR)
1725 __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev));
1727 error = pci_set_power_state(dev, target_state);
1730 __pci_enable_wake(dev, target_state, true, false);
1736 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
1737 * @dev: Device to check.
1739 * Return true if the device itself is cabable of generating wake-up events
1740 * (through the platform or using the native PCIe PME) or if the device supports
1741 * PME and one of its upstream bridges can generate wake-up events.
1743 bool pci_dev_run_wake(struct pci_dev *dev)
1745 struct pci_bus *bus = dev->bus;
1747 if (device_run_wake(&dev->dev))
1750 if (!dev->pme_support)
1753 while (bus->parent) {
1754 struct pci_dev *bridge = bus->self;
1756 if (device_run_wake(&bridge->dev))
1762 /* We have reached the root bus. */
1764 return device_run_wake(bus->bridge);
1768 EXPORT_SYMBOL_GPL(pci_dev_run_wake);
1771 * pci_pm_init - Initialize PM functions of given PCI device
1772 * @dev: PCI device to handle.
1774 void pci_pm_init(struct pci_dev *dev)
1779 pm_runtime_forbid(&dev->dev);
1780 device_enable_async_suspend(&dev->dev);
1781 dev->wakeup_prepared = false;
1785 /* find PCI PM capability in list */
1786 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1789 /* Check device's ability to generate PME# */
1790 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
1792 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
1793 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
1794 pmc & PCI_PM_CAP_VER_MASK);
1799 dev->d3_delay = PCI_PM_D3_WAIT;
1801 dev->d1_support = false;
1802 dev->d2_support = false;
1803 if (!pci_no_d1d2(dev)) {
1804 if (pmc & PCI_PM_CAP_D1)
1805 dev->d1_support = true;
1806 if (pmc & PCI_PM_CAP_D2)
1807 dev->d2_support = true;
1809 if (dev->d1_support || dev->d2_support)
1810 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
1811 dev->d1_support ? " D1" : "",
1812 dev->d2_support ? " D2" : "");
1815 pmc &= PCI_PM_CAP_PME_MASK;
1817 dev_printk(KERN_DEBUG, &dev->dev,
1818 "PME# supported from%s%s%s%s%s\n",
1819 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
1820 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
1821 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
1822 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
1823 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
1824 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
1825 dev->pme_poll = true;
1827 * Make device's PM flags reflect the wake-up capability, but
1828 * let the user space enable it to wake up the system as needed.
1830 device_set_wakeup_capable(&dev->dev, true);
1831 /* Disable the PME# generation functionality */
1832 pci_pme_active(dev, false);
1834 dev->pme_support = 0;
1839 * platform_pci_wakeup_init - init platform wakeup if present
1842 * Some devices don't have PCI PM caps but can still generate wakeup
1843 * events through platform methods (like ACPI events). If @dev supports
1844 * platform wakeup events, set the device flag to indicate as much. This
1845 * may be redundant if the device also supports PCI PM caps, but double
1846 * initialization should be safe in that case.
1848 void platform_pci_wakeup_init(struct pci_dev *dev)
1850 if (!platform_pci_can_wakeup(dev))
1853 device_set_wakeup_capable(&dev->dev, true);
1854 platform_pci_sleep_wake(dev, false);
1858 * pci_add_save_buffer - allocate buffer for saving given capability registers
1859 * @dev: the PCI device
1860 * @cap: the capability to allocate the buffer for
1861 * @size: requested size of the buffer
1863 static int pci_add_cap_save_buffer(
1864 struct pci_dev *dev, char cap, unsigned int size)
1867 struct pci_cap_saved_state *save_state;
1869 pos = pci_find_capability(dev, cap);
1873 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
1877 save_state->cap.cap_nr = cap;
1878 save_state->cap.size = size;
1879 pci_add_saved_cap(dev, save_state);
1885 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
1886 * @dev: the PCI device
1888 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
1892 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
1893 PCI_EXP_SAVE_REGS * sizeof(u16));
1896 "unable to preallocate PCI Express save buffer\n");
1898 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
1901 "unable to preallocate PCI-X save buffer\n");
1905 * pci_enable_ari - enable ARI forwarding if hardware support it
1906 * @dev: the PCI device
1908 void pci_enable_ari(struct pci_dev *dev)
1913 struct pci_dev *bridge;
1915 if (!pci_is_pcie(dev) || dev->devfn)
1918 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1922 bridge = dev->bus->self;
1923 if (!bridge || !pci_is_pcie(bridge))
1926 pos = pci_pcie_cap(bridge);
1930 /* ARI is a PCIe v2 feature */
1931 pci_read_config_word(bridge, pos + PCI_EXP_FLAGS, &flags);
1932 if ((flags & PCI_EXP_FLAGS_VERS) < 2)
1935 pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap);
1936 if (!(cap & PCI_EXP_DEVCAP2_ARI))
1939 pci_read_config_word(bridge, pos + PCI_EXP_DEVCTL2, &ctrl);
1940 ctrl |= PCI_EXP_DEVCTL2_ARI;
1941 pci_write_config_word(bridge, pos + PCI_EXP_DEVCTL2, ctrl);
1943 bridge->ari_enabled = 1;
1947 * pci_enable_ido - enable ID-based ordering on a device
1948 * @dev: the PCI device
1949 * @type: which types of IDO to enable
1951 * Enable ID-based ordering on @dev. @type can contain the bits
1952 * %PCI_EXP_IDO_REQUEST and/or %PCI_EXP_IDO_COMPLETION to indicate
1953 * which types of transactions are allowed to be re-ordered.
1955 void pci_enable_ido(struct pci_dev *dev, unsigned long type)
1960 pos = pci_pcie_cap(dev);
1964 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
1965 if (type & PCI_EXP_IDO_REQUEST)
1966 ctrl |= PCI_EXP_IDO_REQ_EN;
1967 if (type & PCI_EXP_IDO_COMPLETION)
1968 ctrl |= PCI_EXP_IDO_CMP_EN;
1969 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
1971 EXPORT_SYMBOL(pci_enable_ido);
1974 * pci_disable_ido - disable ID-based ordering on a device
1975 * @dev: the PCI device
1976 * @type: which types of IDO to disable
1978 void pci_disable_ido(struct pci_dev *dev, unsigned long type)
1983 if (!pci_is_pcie(dev))
1986 pos = pci_pcie_cap(dev);
1990 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
1991 if (type & PCI_EXP_IDO_REQUEST)
1992 ctrl &= ~PCI_EXP_IDO_REQ_EN;
1993 if (type & PCI_EXP_IDO_COMPLETION)
1994 ctrl &= ~PCI_EXP_IDO_CMP_EN;
1995 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
1997 EXPORT_SYMBOL(pci_disable_ido);
2000 * pci_enable_obff - enable optimized buffer flush/fill
2002 * @type: type of signaling to use
2004 * Try to enable @type OBFF signaling on @dev. It will try using WAKE#
2005 * signaling if possible, falling back to message signaling only if
2006 * WAKE# isn't supported. @type should indicate whether the PCIe link
2007 * be brought out of L0s or L1 to send the message. It should be either
2008 * %PCI_EXP_OBFF_SIGNAL_ALWAYS or %PCI_OBFF_SIGNAL_L0.
2010 * If your device can benefit from receiving all messages, even at the
2011 * power cost of bringing the link back up from a low power state, use
2012 * %PCI_EXP_OBFF_SIGNAL_ALWAYS. Otherwise, use %PCI_OBFF_SIGNAL_L0 (the
2016 * Zero on success, appropriate error number on failure.
2018 int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type)
2025 if (!pci_is_pcie(dev))
2028 pos = pci_pcie_cap(dev);
2032 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP2, &cap);
2033 if (!(cap & PCI_EXP_OBFF_MASK))
2034 return -ENOTSUPP; /* no OBFF support at all */
2036 /* Make sure the topology supports OBFF as well */
2038 ret = pci_enable_obff(dev->bus->self, type);
2043 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2044 if (cap & PCI_EXP_OBFF_WAKE)
2045 ctrl |= PCI_EXP_OBFF_WAKE_EN;
2048 case PCI_EXP_OBFF_SIGNAL_L0:
2049 if (!(ctrl & PCI_EXP_OBFF_WAKE_EN))
2050 ctrl |= PCI_EXP_OBFF_MSGA_EN;
2052 case PCI_EXP_OBFF_SIGNAL_ALWAYS:
2053 ctrl &= ~PCI_EXP_OBFF_WAKE_EN;
2054 ctrl |= PCI_EXP_OBFF_MSGB_EN;
2057 WARN(1, "bad OBFF signal type\n");
2061 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
2065 EXPORT_SYMBOL(pci_enable_obff);
2068 * pci_disable_obff - disable optimized buffer flush/fill
2071 * Disable OBFF on @dev.
2073 void pci_disable_obff(struct pci_dev *dev)
2078 if (!pci_is_pcie(dev))
2081 pos = pci_pcie_cap(dev);
2085 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2086 ctrl &= ~PCI_EXP_OBFF_WAKE_EN;
2087 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
2089 EXPORT_SYMBOL(pci_disable_obff);
2092 * pci_ltr_supported - check whether a device supports LTR
2096 * True if @dev supports latency tolerance reporting, false otherwise.
2098 bool pci_ltr_supported(struct pci_dev *dev)
2103 if (!pci_is_pcie(dev))
2106 pos = pci_pcie_cap(dev);
2110 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP2, &cap);
2112 return cap & PCI_EXP_DEVCAP2_LTR;
2114 EXPORT_SYMBOL(pci_ltr_supported);
2117 * pci_enable_ltr - enable latency tolerance reporting
2120 * Enable LTR on @dev if possible, which means enabling it first on
2124 * Zero on success, errno on failure.
2126 int pci_enable_ltr(struct pci_dev *dev)
2132 if (!pci_ltr_supported(dev))
2135 pos = pci_pcie_cap(dev);
2139 /* Only primary function can enable/disable LTR */
2140 if (PCI_FUNC(dev->devfn) != 0)
2143 /* Enable upstream ports first */
2145 ret = pci_enable_ltr(dev->bus->self);
2150 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2151 ctrl |= PCI_EXP_LTR_EN;
2152 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
2156 EXPORT_SYMBOL(pci_enable_ltr);
2159 * pci_disable_ltr - disable latency tolerance reporting
2162 void pci_disable_ltr(struct pci_dev *dev)
2167 if (!pci_ltr_supported(dev))
2170 pos = pci_pcie_cap(dev);
2174 /* Only primary function can enable/disable LTR */
2175 if (PCI_FUNC(dev->devfn) != 0)
2178 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2179 ctrl &= ~PCI_EXP_LTR_EN;
2180 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
2182 EXPORT_SYMBOL(pci_disable_ltr);
2184 static int __pci_ltr_scale(int *val)
2188 while (*val > 1023) {
2189 *val = (*val + 31) / 32;
2196 * pci_set_ltr - set LTR latency values
2198 * @snoop_lat_ns: snoop latency in nanoseconds
2199 * @nosnoop_lat_ns: nosnoop latency in nanoseconds
2201 * Figure out the scale and set the LTR values accordingly.
2203 int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns)
2205 int pos, ret, snoop_scale, nosnoop_scale;
2208 if (!pci_ltr_supported(dev))
2211 snoop_scale = __pci_ltr_scale(&snoop_lat_ns);
2212 nosnoop_scale = __pci_ltr_scale(&nosnoop_lat_ns);
2214 if (snoop_lat_ns > PCI_LTR_VALUE_MASK ||
2215 nosnoop_lat_ns > PCI_LTR_VALUE_MASK)
2218 if ((snoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)) ||
2219 (nosnoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)))
2222 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
2226 val = (snoop_scale << PCI_LTR_SCALE_SHIFT) | snoop_lat_ns;
2227 ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_SNOOP_LAT, val);
2231 val = (nosnoop_scale << PCI_LTR_SCALE_SHIFT) | nosnoop_lat_ns;
2232 ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_NOSNOOP_LAT, val);
2238 EXPORT_SYMBOL(pci_set_ltr);
2240 static int pci_acs_enable;
2243 * pci_request_acs - ask for ACS to be enabled if supported
2245 void pci_request_acs(void)
2251 * pci_enable_acs - enable ACS if hardware support it
2252 * @dev: the PCI device
2254 void pci_enable_acs(struct pci_dev *dev)
2260 if (!pci_acs_enable)
2263 if (!pci_is_pcie(dev))
2266 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
2270 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
2271 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
2273 /* Source Validation */
2274 ctrl |= (cap & PCI_ACS_SV);
2276 /* P2P Request Redirect */
2277 ctrl |= (cap & PCI_ACS_RR);
2279 /* P2P Completion Redirect */
2280 ctrl |= (cap & PCI_ACS_CR);
2282 /* Upstream Forwarding */
2283 ctrl |= (cap & PCI_ACS_UF);
2285 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
2289 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
2290 * @dev: the PCI device
2291 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2293 * Perform INTx swizzling for a device behind one level of bridge. This is
2294 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
2295 * behind bridges on add-in cards. For devices with ARI enabled, the slot
2296 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
2297 * the PCI Express Base Specification, Revision 2.1)
2299 u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin)
2303 if (pci_ari_enabled(dev->bus))
2306 slot = PCI_SLOT(dev->devfn);
2308 return (((pin - 1) + slot) % 4) + 1;
2312 pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
2320 while (!pci_is_root_bus(dev->bus)) {
2321 pin = pci_swizzle_interrupt_pin(dev, pin);
2322 dev = dev->bus->self;
2329 * pci_common_swizzle - swizzle INTx all the way to root bridge
2330 * @dev: the PCI device
2331 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2333 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
2334 * bridges all the way up to a PCI root bus.
2336 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
2340 while (!pci_is_root_bus(dev->bus)) {
2341 pin = pci_swizzle_interrupt_pin(dev, pin);
2342 dev = dev->bus->self;
2345 return PCI_SLOT(dev->devfn);
2349 * pci_release_region - Release a PCI bar
2350 * @pdev: PCI device whose resources were previously reserved by pci_request_region
2351 * @bar: BAR to release
2353 * Releases the PCI I/O and memory resources previously reserved by a
2354 * successful call to pci_request_region. Call this function only
2355 * after all use of the PCI regions has ceased.
2357 void pci_release_region(struct pci_dev *pdev, int bar)
2359 struct pci_devres *dr;
2361 if (pci_resource_len(pdev, bar) == 0)
2363 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
2364 release_region(pci_resource_start(pdev, bar),
2365 pci_resource_len(pdev, bar));
2366 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
2367 release_mem_region(pci_resource_start(pdev, bar),
2368 pci_resource_len(pdev, bar));
2370 dr = find_pci_dr(pdev);
2372 dr->region_mask &= ~(1 << bar);
2376 * __pci_request_region - Reserved PCI I/O and memory resource
2377 * @pdev: PCI device whose resources are to be reserved
2378 * @bar: BAR to be reserved
2379 * @res_name: Name to be associated with resource.
2380 * @exclusive: whether the region access is exclusive or not
2382 * Mark the PCI region associated with PCI device @pdev BR @bar as
2383 * being reserved by owner @res_name. Do not access any
2384 * address inside the PCI regions unless this call returns
2387 * If @exclusive is set, then the region is marked so that userspace
2388 * is explicitly not allowed to map the resource via /dev/mem or
2389 * sysfs MMIO access.
2391 * Returns 0 on success, or %EBUSY on error. A warning
2392 * message is also printed on failure.
2394 static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name,
2397 struct pci_devres *dr;
2399 if (pci_resource_len(pdev, bar) == 0)
2402 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
2403 if (!request_region(pci_resource_start(pdev, bar),
2404 pci_resource_len(pdev, bar), res_name))
2407 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
2408 if (!__request_mem_region(pci_resource_start(pdev, bar),
2409 pci_resource_len(pdev, bar), res_name,
2414 dr = find_pci_dr(pdev);
2416 dr->region_mask |= 1 << bar;
2421 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar,
2422 &pdev->resource[bar]);
2427 * pci_request_region - Reserve PCI I/O and memory resource
2428 * @pdev: PCI device whose resources are to be reserved
2429 * @bar: BAR to be reserved
2430 * @res_name: Name to be associated with resource
2432 * Mark the PCI region associated with PCI device @pdev BAR @bar as
2433 * being reserved by owner @res_name. Do not access any
2434 * address inside the PCI regions unless this call returns
2437 * Returns 0 on success, or %EBUSY on error. A warning
2438 * message is also printed on failure.
2440 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
2442 return __pci_request_region(pdev, bar, res_name, 0);
2446 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
2447 * @pdev: PCI device whose resources are to be reserved
2448 * @bar: BAR to be reserved
2449 * @res_name: Name to be associated with resource.
2451 * Mark the PCI region associated with PCI device @pdev BR @bar as
2452 * being reserved by owner @res_name. Do not access any
2453 * address inside the PCI regions unless this call returns
2456 * Returns 0 on success, or %EBUSY on error. A warning
2457 * message is also printed on failure.
2459 * The key difference that _exclusive makes it that userspace is
2460 * explicitly not allowed to map the resource via /dev/mem or
2463 int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name)
2465 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
2468 * pci_release_selected_regions - Release selected PCI I/O and memory resources
2469 * @pdev: PCI device whose resources were previously reserved
2470 * @bars: Bitmask of BARs to be released
2472 * Release selected PCI I/O and memory resources previously reserved.
2473 * Call this function only after all use of the PCI regions has ceased.
2475 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
2479 for (i = 0; i < 6; i++)
2480 if (bars & (1 << i))
2481 pci_release_region(pdev, i);
2484 int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
2485 const char *res_name, int excl)
2489 for (i = 0; i < 6; i++)
2490 if (bars & (1 << i))
2491 if (__pci_request_region(pdev, i, res_name, excl))
2497 if (bars & (1 << i))
2498 pci_release_region(pdev, i);
2505 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
2506 * @pdev: PCI device whose resources are to be reserved
2507 * @bars: Bitmask of BARs to be requested
2508 * @res_name: Name to be associated with resource
2510 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
2511 const char *res_name)
2513 return __pci_request_selected_regions(pdev, bars, res_name, 0);
2516 int pci_request_selected_regions_exclusive(struct pci_dev *pdev,
2517 int bars, const char *res_name)
2519 return __pci_request_selected_regions(pdev, bars, res_name,
2520 IORESOURCE_EXCLUSIVE);
2524 * pci_release_regions - Release reserved PCI I/O and memory resources
2525 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
2527 * Releases all PCI I/O and memory resources previously reserved by a
2528 * successful call to pci_request_regions. Call this function only
2529 * after all use of the PCI regions has ceased.
2532 void pci_release_regions(struct pci_dev *pdev)
2534 pci_release_selected_regions(pdev, (1 << 6) - 1);
2538 * pci_request_regions - Reserved PCI I/O and memory resources
2539 * @pdev: PCI device whose resources are to be reserved
2540 * @res_name: Name to be associated with resource.
2542 * Mark all PCI regions associated with PCI device @pdev as
2543 * being reserved by owner @res_name. Do not access any
2544 * address inside the PCI regions unless this call returns
2547 * Returns 0 on success, or %EBUSY on error. A warning
2548 * message is also printed on failure.
2550 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
2552 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
2556 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
2557 * @pdev: PCI device whose resources are to be reserved
2558 * @res_name: Name to be associated with resource.
2560 * Mark all PCI regions associated with PCI device @pdev as
2561 * being reserved by owner @res_name. Do not access any
2562 * address inside the PCI regions unless this call returns
2565 * pci_request_regions_exclusive() will mark the region so that
2566 * /dev/mem and the sysfs MMIO access will not be allowed.
2568 * Returns 0 on success, or %EBUSY on error. A warning
2569 * message is also printed on failure.
2571 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
2573 return pci_request_selected_regions_exclusive(pdev,
2574 ((1 << 6) - 1), res_name);
2577 static void __pci_set_master(struct pci_dev *dev, bool enable)
2581 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
2583 cmd = old_cmd | PCI_COMMAND_MASTER;
2585 cmd = old_cmd & ~PCI_COMMAND_MASTER;
2586 if (cmd != old_cmd) {
2587 dev_dbg(&dev->dev, "%s bus mastering\n",
2588 enable ? "enabling" : "disabling");
2589 pci_write_config_word(dev, PCI_COMMAND, cmd);
2591 dev->is_busmaster = enable;
2595 * pci_set_master - enables bus-mastering for device dev
2596 * @dev: the PCI device to enable
2598 * Enables bus-mastering on the device and calls pcibios_set_master()
2599 * to do the needed arch specific settings.
2601 void pci_set_master(struct pci_dev *dev)
2603 __pci_set_master(dev, true);
2604 pcibios_set_master(dev);
2608 * pci_clear_master - disables bus-mastering for device dev
2609 * @dev: the PCI device to disable
2611 void pci_clear_master(struct pci_dev *dev)
2613 __pci_set_master(dev, false);
2617 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
2618 * @dev: the PCI device for which MWI is to be enabled
2620 * Helper function for pci_set_mwi.
2621 * Originally copied from drivers/net/acenic.c.
2622 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
2624 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2626 int pci_set_cacheline_size(struct pci_dev *dev)
2630 if (!pci_cache_line_size)
2633 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
2634 equal to or multiple of the right value. */
2635 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2636 if (cacheline_size >= pci_cache_line_size &&
2637 (cacheline_size % pci_cache_line_size) == 0)
2640 /* Write the correct value. */
2641 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
2643 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2644 if (cacheline_size == pci_cache_line_size)
2647 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not "
2648 "supported\n", pci_cache_line_size << 2);
2652 EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
2654 #ifdef PCI_DISABLE_MWI
2655 int pci_set_mwi(struct pci_dev *dev)
2660 int pci_try_set_mwi(struct pci_dev *dev)
2665 void pci_clear_mwi(struct pci_dev *dev)
2672 * pci_set_mwi - enables memory-write-invalidate PCI transaction
2673 * @dev: the PCI device for which MWI is enabled
2675 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2677 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2680 pci_set_mwi(struct pci_dev *dev)
2685 rc = pci_set_cacheline_size(dev);
2689 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2690 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
2691 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
2692 cmd |= PCI_COMMAND_INVALIDATE;
2693 pci_write_config_word(dev, PCI_COMMAND, cmd);
2700 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
2701 * @dev: the PCI device for which MWI is enabled
2703 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2704 * Callers are not required to check the return value.
2706 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2708 int pci_try_set_mwi(struct pci_dev *dev)
2710 int rc = pci_set_mwi(dev);
2715 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
2716 * @dev: the PCI device to disable
2718 * Disables PCI Memory-Write-Invalidate transaction on the device
2721 pci_clear_mwi(struct pci_dev *dev)
2725 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2726 if (cmd & PCI_COMMAND_INVALIDATE) {
2727 cmd &= ~PCI_COMMAND_INVALIDATE;
2728 pci_write_config_word(dev, PCI_COMMAND, cmd);
2731 #endif /* ! PCI_DISABLE_MWI */
2734 * pci_intx - enables/disables PCI INTx for device dev
2735 * @pdev: the PCI device to operate on
2736 * @enable: boolean: whether to enable or disable PCI INTx
2738 * Enables/disables PCI INTx for device dev
2741 pci_intx(struct pci_dev *pdev, int enable)
2743 u16 pci_command, new;
2745 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
2748 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
2750 new = pci_command | PCI_COMMAND_INTX_DISABLE;
2753 if (new != pci_command) {
2754 struct pci_devres *dr;
2756 pci_write_config_word(pdev, PCI_COMMAND, new);
2758 dr = find_pci_dr(pdev);
2759 if (dr && !dr->restore_intx) {
2760 dr->restore_intx = 1;
2761 dr->orig_intx = !enable;
2767 * pci_msi_off - disables any msi or msix capabilities
2768 * @dev: the PCI device to operate on
2770 * If you want to use msi see pci_enable_msi and friends.
2771 * This is a lower level primitive that allows us to disable
2772 * msi operation at the device level.
2774 void pci_msi_off(struct pci_dev *dev)
2779 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
2781 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
2782 control &= ~PCI_MSI_FLAGS_ENABLE;
2783 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
2785 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
2787 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
2788 control &= ~PCI_MSIX_FLAGS_ENABLE;
2789 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
2792 EXPORT_SYMBOL_GPL(pci_msi_off);
2794 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
2796 return dma_set_max_seg_size(&dev->dev, size);
2798 EXPORT_SYMBOL(pci_set_dma_max_seg_size);
2800 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
2802 return dma_set_seg_boundary(&dev->dev, mask);
2804 EXPORT_SYMBOL(pci_set_dma_seg_boundary);
2806 static int pcie_flr(struct pci_dev *dev, int probe)
2811 u16 status, control;
2813 pos = pci_pcie_cap(dev);
2817 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP, &cap);
2818 if (!(cap & PCI_EXP_DEVCAP_FLR))
2824 /* Wait for Transaction Pending bit clean */
2825 for (i = 0; i < 4; i++) {
2827 msleep((1 << (i - 1)) * 100);
2829 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
2830 if (!(status & PCI_EXP_DEVSTA_TRPND))
2834 dev_err(&dev->dev, "transaction is not cleared; "
2835 "proceeding with reset anyway\n");
2838 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &control);
2839 control |= PCI_EXP_DEVCTL_BCR_FLR;
2840 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, control);
2847 static int pci_af_flr(struct pci_dev *dev, int probe)
2854 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
2858 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
2859 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
2865 /* Wait for Transaction Pending bit clean */
2866 for (i = 0; i < 4; i++) {
2868 msleep((1 << (i - 1)) * 100);
2870 pci_read_config_byte(dev, pos + PCI_AF_STATUS, &status);
2871 if (!(status & PCI_AF_STATUS_TP))
2875 dev_err(&dev->dev, "transaction is not cleared; "
2876 "proceeding with reset anyway\n");
2879 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
2886 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
2887 * @dev: Device to reset.
2888 * @probe: If set, only check if the device can be reset this way.
2890 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
2891 * unset, it will be reinitialized internally when going from PCI_D3hot to
2892 * PCI_D0. If that's the case and the device is not in a low-power state
2893 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
2895 * NOTE: This causes the caller to sleep for twice the device power transition
2896 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
2897 * by devault (i.e. unless the @dev's d3_delay field has a different value).
2898 * Moreover, only devices in D0 can be reset by this function.
2900 static int pci_pm_reset(struct pci_dev *dev, int probe)
2907 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
2908 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
2914 if (dev->current_state != PCI_D0)
2917 csr &= ~PCI_PM_CTRL_STATE_MASK;
2919 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
2920 pci_dev_d3_sleep(dev);
2922 csr &= ~PCI_PM_CTRL_STATE_MASK;
2924 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
2925 pci_dev_d3_sleep(dev);
2930 static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
2933 struct pci_dev *pdev;
2935 if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self)
2938 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
2945 pci_read_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, &ctrl);
2946 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
2947 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
2950 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
2951 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
2957 static int pci_dev_reset(struct pci_dev *dev, int probe)
2964 pci_block_user_cfg_access(dev);
2965 /* block PM suspend, driver probe, etc. */
2966 device_lock(&dev->dev);
2969 rc = pci_dev_specific_reset(dev, probe);
2973 rc = pcie_flr(dev, probe);
2977 rc = pci_af_flr(dev, probe);
2981 rc = pci_pm_reset(dev, probe);
2985 rc = pci_parent_bus_reset(dev, probe);
2988 device_unlock(&dev->dev);
2989 pci_unblock_user_cfg_access(dev);
2996 * __pci_reset_function - reset a PCI device function
2997 * @dev: PCI device to reset
2999 * Some devices allow an individual function to be reset without affecting
3000 * other functions in the same device. The PCI device must be responsive
3001 * to PCI config space in order to use this function.
3003 * The device function is presumed to be unused when this function is called.
3004 * Resetting the device will make the contents of PCI configuration space
3005 * random, so any caller of this must be prepared to reinitialise the
3006 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3009 * Returns 0 if the device function was successfully reset or negative if the
3010 * device doesn't support resetting a single function.
3012 int __pci_reset_function(struct pci_dev *dev)
3014 return pci_dev_reset(dev, 0);
3016 EXPORT_SYMBOL_GPL(__pci_reset_function);
3019 * pci_probe_reset_function - check whether the device can be safely reset
3020 * @dev: PCI device to reset
3022 * Some devices allow an individual function to be reset without affecting
3023 * other functions in the same device. The PCI device must be responsive
3024 * to PCI config space in order to use this function.
3026 * Returns 0 if the device function can be reset or negative if the
3027 * device doesn't support resetting a single function.
3029 int pci_probe_reset_function(struct pci_dev *dev)
3031 return pci_dev_reset(dev, 1);
3035 * pci_reset_function - quiesce and reset a PCI device function
3036 * @dev: PCI device to reset
3038 * Some devices allow an individual function to be reset without affecting
3039 * other functions in the same device. The PCI device must be responsive
3040 * to PCI config space in order to use this function.
3042 * This function does not just reset the PCI portion of a device, but
3043 * clears all the state associated with the device. This function differs
3044 * from __pci_reset_function in that it saves and restores device state
3047 * Returns 0 if the device function was successfully reset or negative if the
3048 * device doesn't support resetting a single function.
3050 int pci_reset_function(struct pci_dev *dev)
3054 rc = pci_dev_reset(dev, 1);
3058 pci_save_state(dev);
3061 * both INTx and MSI are disabled after the Interrupt Disable bit
3062 * is set and the Bus Master bit is cleared.
3064 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
3066 rc = pci_dev_reset(dev, 0);
3068 pci_restore_state(dev);
3072 EXPORT_SYMBOL_GPL(pci_reset_function);
3075 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
3076 * @dev: PCI device to query
3078 * Returns mmrbc: maximum designed memory read count in bytes
3079 * or appropriate error value.
3081 int pcix_get_max_mmrbc(struct pci_dev *dev)
3086 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3090 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
3093 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
3095 EXPORT_SYMBOL(pcix_get_max_mmrbc);
3098 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
3099 * @dev: PCI device to query
3101 * Returns mmrbc: maximum memory read count in bytes
3102 * or appropriate error value.
3104 int pcix_get_mmrbc(struct pci_dev *dev)
3109 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3113 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
3116 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
3118 EXPORT_SYMBOL(pcix_get_mmrbc);
3121 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
3122 * @dev: PCI device to query
3123 * @mmrbc: maximum memory read count in bytes
3124 * valid values are 512, 1024, 2048, 4096
3126 * If possible sets maximum memory read byte count, some bridges have erratas
3127 * that prevent this.
3129 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
3135 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
3138 v = ffs(mmrbc) - 10;
3140 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3144 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
3147 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
3150 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
3153 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
3155 if (v > o && dev->bus &&
3156 (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
3159 cmd &= ~PCI_X_CMD_MAX_READ;
3161 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
3166 EXPORT_SYMBOL(pcix_set_mmrbc);
3169 * pcie_get_readrq - get PCI Express read request size
3170 * @dev: PCI device to query
3172 * Returns maximum memory read request in bytes
3173 * or appropriate error value.
3175 int pcie_get_readrq(struct pci_dev *dev)
3180 cap = pci_pcie_cap(dev);
3184 ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
3186 ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
3190 EXPORT_SYMBOL(pcie_get_readrq);
3193 * pcie_set_readrq - set PCI Express maximum memory read request
3194 * @dev: PCI device to query
3195 * @rq: maximum memory read count in bytes
3196 * valid values are 128, 256, 512, 1024, 2048, 4096
3198 * If possible sets maximum memory read request in bytes
3200 int pcie_set_readrq(struct pci_dev *dev, int rq)
3202 int cap, err = -EINVAL;
3205 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
3208 cap = pci_pcie_cap(dev);
3212 err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
3216 * If using the "performance" PCIe config, we clamp the
3217 * read rq size to the max packet size to prevent the
3218 * host bridge generating requests larger than we can
3221 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
3222 int mps = pcie_get_mps(dev);
3230 v = (ffs(rq) - 8) << 12;
3232 if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) {
3233 ctl &= ~PCI_EXP_DEVCTL_READRQ;
3235 err = pci_write_config_word(dev, cap + PCI_EXP_DEVCTL, ctl);
3241 EXPORT_SYMBOL(pcie_set_readrq);
3244 * pcie_get_mps - get PCI Express maximum payload size
3245 * @dev: PCI device to query
3247 * Returns maximum payload size in bytes
3248 * or appropriate error value.
3250 int pcie_get_mps(struct pci_dev *dev)
3255 cap = pci_pcie_cap(dev);
3259 ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
3261 ret = 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
3267 * pcie_set_mps - set PCI Express maximum payload size
3268 * @dev: PCI device to query
3269 * @mps: maximum payload size in bytes
3270 * valid values are 128, 256, 512, 1024, 2048, 4096
3272 * If possible sets maximum payload size
3274 int pcie_set_mps(struct pci_dev *dev, int mps)
3276 int cap, err = -EINVAL;
3279 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
3283 if (v > dev->pcie_mpss)
3287 cap = pci_pcie_cap(dev);
3291 err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
3295 if ((ctl & PCI_EXP_DEVCTL_PAYLOAD) != v) {
3296 ctl &= ~PCI_EXP_DEVCTL_PAYLOAD;
3298 err = pci_write_config_word(dev, cap + PCI_EXP_DEVCTL, ctl);
3305 * pci_select_bars - Make BAR mask from the type of resource
3306 * @dev: the PCI device for which BAR mask is made
3307 * @flags: resource type mask to be selected
3309 * This helper routine makes bar mask from the type of resource.
3311 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
3314 for (i = 0; i < PCI_NUM_RESOURCES; i++)
3315 if (pci_resource_flags(dev, i) & flags)
3321 * pci_resource_bar - get position of the BAR associated with a resource
3322 * @dev: the PCI device
3323 * @resno: the resource number
3324 * @type: the BAR type to be filled in
3326 * Returns BAR position in config space, or 0 if the BAR is invalid.
3328 int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type)
3332 if (resno < PCI_ROM_RESOURCE) {
3333 *type = pci_bar_unknown;
3334 return PCI_BASE_ADDRESS_0 + 4 * resno;
3335 } else if (resno == PCI_ROM_RESOURCE) {
3336 *type = pci_bar_mem32;
3337 return dev->rom_base_reg;
3338 } else if (resno < PCI_BRIDGE_RESOURCES) {
3339 /* device specific resource */
3340 reg = pci_iov_resource_bar(dev, resno, type);
3345 dev_err(&dev->dev, "BAR %d: invalid resource\n", resno);
3349 /* Some architectures require additional programming to enable VGA */
3350 static arch_set_vga_state_t arch_set_vga_state;
3352 void __init pci_register_set_vga_state(arch_set_vga_state_t func)
3354 arch_set_vga_state = func; /* NULL disables */
3357 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
3358 unsigned int command_bits, u32 flags)
3360 if (arch_set_vga_state)
3361 return arch_set_vga_state(dev, decode, command_bits,
3367 * pci_set_vga_state - set VGA decode state on device and parents if requested
3368 * @dev: the PCI device
3369 * @decode: true = enable decoding, false = disable decoding
3370 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
3371 * @flags: traverse ancestors and change bridges
3372 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
3374 int pci_set_vga_state(struct pci_dev *dev, bool decode,
3375 unsigned int command_bits, u32 flags)
3377 struct pci_bus *bus;
3378 struct pci_dev *bridge;
3382 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) & (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
3384 /* ARCH specific VGA enables */
3385 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
3389 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
3390 pci_read_config_word(dev, PCI_COMMAND, &cmd);
3392 cmd |= command_bits;
3394 cmd &= ~command_bits;
3395 pci_write_config_word(dev, PCI_COMMAND, cmd);
3398 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
3405 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
3408 cmd |= PCI_BRIDGE_CTL_VGA;
3410 cmd &= ~PCI_BRIDGE_CTL_VGA;
3411 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
3419 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
3420 static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
3421 static DEFINE_SPINLOCK(resource_alignment_lock);
3424 * pci_specified_resource_alignment - get resource alignment specified by user.
3425 * @dev: the PCI device to get
3427 * RETURNS: Resource alignment if it is specified.
3428 * Zero if it is not specified.
3430 resource_size_t pci_specified_resource_alignment(struct pci_dev *dev)
3432 int seg, bus, slot, func, align_order, count;
3433 resource_size_t align = 0;
3436 spin_lock(&resource_alignment_lock);
3437 p = resource_alignment_param;
3440 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
3446 if (sscanf(p, "%x:%x:%x.%x%n",
3447 &seg, &bus, &slot, &func, &count) != 4) {
3449 if (sscanf(p, "%x:%x.%x%n",
3450 &bus, &slot, &func, &count) != 3) {
3451 /* Invalid format */
3452 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
3458 if (seg == pci_domain_nr(dev->bus) &&
3459 bus == dev->bus->number &&
3460 slot == PCI_SLOT(dev->devfn) &&
3461 func == PCI_FUNC(dev->devfn)) {
3462 if (align_order == -1) {
3465 align = 1 << align_order;
3470 if (*p != ';' && *p != ',') {
3471 /* End of param or invalid format */
3476 spin_unlock(&resource_alignment_lock);
3481 * pci_is_reassigndev - check if specified PCI is target device to reassign
3482 * @dev: the PCI device to check
3484 * RETURNS: non-zero for PCI device is a target device to reassign,
3487 int pci_is_reassigndev(struct pci_dev *dev)
3489 return (pci_specified_resource_alignment(dev) != 0);
3492 ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
3494 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
3495 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
3496 spin_lock(&resource_alignment_lock);
3497 strncpy(resource_alignment_param, buf, count);
3498 resource_alignment_param[count] = '\0';
3499 spin_unlock(&resource_alignment_lock);
3503 ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
3506 spin_lock(&resource_alignment_lock);
3507 count = snprintf(buf, size, "%s", resource_alignment_param);
3508 spin_unlock(&resource_alignment_lock);
3512 static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
3514 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
3517 static ssize_t pci_resource_alignment_store(struct bus_type *bus,
3518 const char *buf, size_t count)
3520 return pci_set_resource_alignment_param(buf, count);
3523 BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
3524 pci_resource_alignment_store);
3526 static int __init pci_resource_alignment_sysfs_init(void)
3528 return bus_create_file(&pci_bus_type,
3529 &bus_attr_resource_alignment);
3532 late_initcall(pci_resource_alignment_sysfs_init);
3534 static void __devinit pci_no_domains(void)
3536 #ifdef CONFIG_PCI_DOMAINS
3537 pci_domains_supported = 0;
3542 * pci_ext_cfg_enabled - can we access extended PCI config space?
3543 * @dev: The PCI device of the root bridge.
3545 * Returns 1 if we can access PCI extended config space (offsets
3546 * greater than 0xff). This is the default implementation. Architecture
3547 * implementations can override this.
3549 int __attribute__ ((weak)) pci_ext_cfg_avail(struct pci_dev *dev)
3554 void __weak pci_fixup_cardbus(struct pci_bus *bus)
3557 EXPORT_SYMBOL(pci_fixup_cardbus);
3559 static int __init pci_setup(char *str)
3562 char *k = strchr(str, ',');
3565 if (*str && (str = pcibios_setup(str)) && *str) {
3566 if (!strcmp(str, "nomsi")) {
3568 } else if (!strcmp(str, "noaer")) {
3570 } else if (!strncmp(str, "realloc", 7)) {
3572 } else if (!strcmp(str, "nodomains")) {
3574 } else if (!strncmp(str, "cbiosize=", 9)) {
3575 pci_cardbus_io_size = memparse(str + 9, &str);
3576 } else if (!strncmp(str, "cbmemsize=", 10)) {
3577 pci_cardbus_mem_size = memparse(str + 10, &str);
3578 } else if (!strncmp(str, "resource_alignment=", 19)) {
3579 pci_set_resource_alignment_param(str + 19,
3581 } else if (!strncmp(str, "ecrc=", 5)) {
3582 pcie_ecrc_get_policy(str + 5);
3583 } else if (!strncmp(str, "hpiosize=", 9)) {
3584 pci_hotplug_io_size = memparse(str + 9, &str);
3585 } else if (!strncmp(str, "hpmemsize=", 10)) {
3586 pci_hotplug_mem_size = memparse(str + 10, &str);
3587 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
3588 pcie_bus_config = PCIE_BUS_TUNE_OFF;
3589 } else if (!strncmp(str, "pcie_bus_safe", 13)) {
3590 pcie_bus_config = PCIE_BUS_SAFE;
3591 } else if (!strncmp(str, "pcie_bus_perf", 13)) {
3592 pcie_bus_config = PCIE_BUS_PERFORMANCE;
3593 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
3594 pcie_bus_config = PCIE_BUS_PEER2PEER;
3596 printk(KERN_ERR "PCI: Unknown option `%s'\n",
3604 early_param("pci", pci_setup);
3606 EXPORT_SYMBOL(pci_reenable_device);
3607 EXPORT_SYMBOL(pci_enable_device_io);
3608 EXPORT_SYMBOL(pci_enable_device_mem);
3609 EXPORT_SYMBOL(pci_enable_device);
3610 EXPORT_SYMBOL(pcim_enable_device);
3611 EXPORT_SYMBOL(pcim_pin_device);
3612 EXPORT_SYMBOL(pci_disable_device);
3613 EXPORT_SYMBOL(pci_find_capability);
3614 EXPORT_SYMBOL(pci_bus_find_capability);
3615 EXPORT_SYMBOL(pci_release_regions);
3616 EXPORT_SYMBOL(pci_request_regions);
3617 EXPORT_SYMBOL(pci_request_regions_exclusive);
3618 EXPORT_SYMBOL(pci_release_region);
3619 EXPORT_SYMBOL(pci_request_region);
3620 EXPORT_SYMBOL(pci_request_region_exclusive);
3621 EXPORT_SYMBOL(pci_release_selected_regions);
3622 EXPORT_SYMBOL(pci_request_selected_regions);
3623 EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
3624 EXPORT_SYMBOL(pci_set_master);
3625 EXPORT_SYMBOL(pci_clear_master);
3626 EXPORT_SYMBOL(pci_set_mwi);
3627 EXPORT_SYMBOL(pci_try_set_mwi);
3628 EXPORT_SYMBOL(pci_clear_mwi);
3629 EXPORT_SYMBOL_GPL(pci_intx);
3630 EXPORT_SYMBOL(pci_assign_resource);
3631 EXPORT_SYMBOL(pci_find_parent_resource);
3632 EXPORT_SYMBOL(pci_select_bars);
3634 EXPORT_SYMBOL(pci_set_power_state);
3635 EXPORT_SYMBOL(pci_save_state);
3636 EXPORT_SYMBOL(pci_restore_state);
3637 EXPORT_SYMBOL(pci_pme_capable);
3638 EXPORT_SYMBOL(pci_pme_active);
3639 EXPORT_SYMBOL(pci_wake_from_d3);
3640 EXPORT_SYMBOL(pci_target_state);
3641 EXPORT_SYMBOL(pci_prepare_to_sleep);
3642 EXPORT_SYMBOL(pci_back_from_sleep);
3643 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);