1 #include <linux/interrupt.h>
2 #include <linux/dmar.h>
3 #include <linux/spinlock.h>
4 #include <linux/slab.h>
5 #include <linux/jiffies.h>
6 #include <linux/hpet.h>
9 #include <asm/io_apic.h>
12 #include <linux/intel-iommu.h>
13 #include "intr_remapping.h"
14 #include <acpi/acpi.h>
15 #include <asm/pci-direct.h>
18 static struct ioapic_scope ir_ioapic[MAX_IO_APICS];
19 static struct hpet_scope ir_hpet[MAX_HPET_TBS];
20 static int ir_ioapic_num, ir_hpet_num;
21 int intr_remapping_enabled;
23 static int disable_intremap;
24 static int disable_sourceid_checking;
26 static __init int setup_nointremap(char *str)
31 early_param("nointremap", setup_nointremap);
33 static __init int setup_intremap(char *str)
38 if (!strncmp(str, "on", 2))
40 else if (!strncmp(str, "off", 3))
42 else if (!strncmp(str, "nosid", 5))
43 disable_sourceid_checking = 1;
47 early_param("intremap", setup_intremap);
50 struct intel_iommu *iommu;
56 #ifdef CONFIG_GENERIC_HARDIRQS
57 static struct irq_2_iommu *get_one_free_irq_2_iommu(int node)
59 struct irq_2_iommu *iommu;
61 iommu = kzalloc_node(sizeof(*iommu), GFP_ATOMIC, node);
62 printk(KERN_DEBUG "alloc irq_2_iommu on node %d\n", node);
67 static struct irq_2_iommu *irq_2_iommu(unsigned int irq)
69 struct irq_desc *desc;
71 desc = irq_to_desc(irq);
73 if (WARN_ON_ONCE(!desc))
76 return desc->irq_2_iommu;
79 static struct irq_2_iommu *irq_2_iommu_alloc(unsigned int irq)
81 struct irq_desc *desc;
82 struct irq_2_iommu *irq_iommu;
84 desc = irq_to_desc(irq);
86 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
90 irq_iommu = desc->irq_2_iommu;
93 desc->irq_2_iommu = get_one_free_irq_2_iommu(irq_node(irq));
95 return desc->irq_2_iommu;
98 #else /* !CONFIG_SPARSE_IRQ */
100 static struct irq_2_iommu irq_2_iommuX[NR_IRQS];
102 static struct irq_2_iommu *irq_2_iommu(unsigned int irq)
105 return &irq_2_iommuX[irq];
109 static struct irq_2_iommu *irq_2_iommu_alloc(unsigned int irq)
111 return irq_2_iommu(irq);
115 static DEFINE_SPINLOCK(irq_2_ir_lock);
117 static struct irq_2_iommu *valid_irq_2_iommu(unsigned int irq)
119 struct irq_2_iommu *irq_iommu;
121 irq_iommu = irq_2_iommu(irq);
126 if (!irq_iommu->iommu)
132 int irq_remapped(int irq)
134 return valid_irq_2_iommu(irq) != NULL;
137 int get_irte(int irq, struct irte *entry)
140 struct irq_2_iommu *irq_iommu;
146 spin_lock_irqsave(&irq_2_ir_lock, flags);
147 irq_iommu = valid_irq_2_iommu(irq);
149 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
153 index = irq_iommu->irte_index + irq_iommu->sub_handle;
154 *entry = *(irq_iommu->iommu->ir_table->base + index);
156 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
160 int alloc_irte(struct intel_iommu *iommu, int irq, u16 count)
162 struct ir_table *table = iommu->ir_table;
163 struct irq_2_iommu *irq_iommu;
164 u16 index, start_index;
165 unsigned int mask = 0;
172 #ifndef CONFIG_SPARSE_IRQ
173 /* protect irq_2_iommu_alloc later */
179 * start the IRTE search from index 0.
181 index = start_index = 0;
184 count = __roundup_pow_of_two(count);
188 if (mask > ecap_max_handle_mask(iommu->ecap)) {
190 "Requested mask %x exceeds the max invalidation handle"
191 " mask value %Lx\n", mask,
192 ecap_max_handle_mask(iommu->ecap));
196 spin_lock_irqsave(&irq_2_ir_lock, flags);
198 for (i = index; i < index + count; i++)
199 if (table->base[i].present)
201 /* empty index found */
202 if (i == index + count)
205 index = (index + count) % INTR_REMAP_TABLE_ENTRIES;
207 if (index == start_index) {
208 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
209 printk(KERN_ERR "can't allocate an IRTE\n");
214 for (i = index; i < index + count; i++)
215 table->base[i].present = 1;
217 irq_iommu = irq_2_iommu_alloc(irq);
219 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
220 printk(KERN_ERR "can't allocate irq_2_iommu\n");
224 irq_iommu->iommu = iommu;
225 irq_iommu->irte_index = index;
226 irq_iommu->sub_handle = 0;
227 irq_iommu->irte_mask = mask;
229 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
234 static int qi_flush_iec(struct intel_iommu *iommu, int index, int mask)
238 desc.low = QI_IEC_IIDEX(index) | QI_IEC_TYPE | QI_IEC_IM(mask)
242 return qi_submit_sync(&desc, iommu);
245 int map_irq_to_irte_handle(int irq, u16 *sub_handle)
248 struct irq_2_iommu *irq_iommu;
251 spin_lock_irqsave(&irq_2_ir_lock, flags);
252 irq_iommu = valid_irq_2_iommu(irq);
254 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
258 *sub_handle = irq_iommu->sub_handle;
259 index = irq_iommu->irte_index;
260 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
264 int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index, u16 subhandle)
266 struct irq_2_iommu *irq_iommu;
269 spin_lock_irqsave(&irq_2_ir_lock, flags);
271 irq_iommu = irq_2_iommu_alloc(irq);
274 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
275 printk(KERN_ERR "can't allocate irq_2_iommu\n");
279 irq_iommu->iommu = iommu;
280 irq_iommu->irte_index = index;
281 irq_iommu->sub_handle = subhandle;
282 irq_iommu->irte_mask = 0;
284 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
289 int clear_irte_irq(int irq, struct intel_iommu *iommu, u16 index)
291 struct irq_2_iommu *irq_iommu;
294 spin_lock_irqsave(&irq_2_ir_lock, flags);
295 irq_iommu = valid_irq_2_iommu(irq);
297 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
301 irq_iommu->iommu = NULL;
302 irq_iommu->irte_index = 0;
303 irq_iommu->sub_handle = 0;
304 irq_2_iommu(irq)->irte_mask = 0;
306 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
311 int modify_irte(int irq, struct irte *irte_modified)
316 struct intel_iommu *iommu;
317 struct irq_2_iommu *irq_iommu;
320 spin_lock_irqsave(&irq_2_ir_lock, flags);
321 irq_iommu = valid_irq_2_iommu(irq);
323 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
327 iommu = irq_iommu->iommu;
329 index = irq_iommu->irte_index + irq_iommu->sub_handle;
330 irte = &iommu->ir_table->base[index];
332 set_64bit(&irte->low, irte_modified->low);
333 set_64bit(&irte->high, irte_modified->high);
334 __iommu_flush_cache(iommu, irte, sizeof(*irte));
336 rc = qi_flush_iec(iommu, index, 0);
337 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
342 int flush_irte(int irq)
346 struct intel_iommu *iommu;
347 struct irq_2_iommu *irq_iommu;
350 spin_lock_irqsave(&irq_2_ir_lock, flags);
351 irq_iommu = valid_irq_2_iommu(irq);
353 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
357 iommu = irq_iommu->iommu;
359 index = irq_iommu->irte_index + irq_iommu->sub_handle;
361 rc = qi_flush_iec(iommu, index, irq_iommu->irte_mask);
362 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
367 struct intel_iommu *map_hpet_to_ir(u8 hpet_id)
371 for (i = 0; i < MAX_HPET_TBS; i++)
372 if (ir_hpet[i].id == hpet_id)
373 return ir_hpet[i].iommu;
377 struct intel_iommu *map_ioapic_to_ir(int apic)
381 for (i = 0; i < MAX_IO_APICS; i++)
382 if (ir_ioapic[i].id == apic)
383 return ir_ioapic[i].iommu;
387 struct intel_iommu *map_dev_to_ir(struct pci_dev *dev)
389 struct dmar_drhd_unit *drhd;
391 drhd = dmar_find_matched_drhd_unit(dev);
398 static int clear_entries(struct irq_2_iommu *irq_iommu)
400 struct irte *start, *entry, *end;
401 struct intel_iommu *iommu;
404 if (irq_iommu->sub_handle)
407 iommu = irq_iommu->iommu;
408 index = irq_iommu->irte_index + irq_iommu->sub_handle;
410 start = iommu->ir_table->base + index;
411 end = start + (1 << irq_iommu->irte_mask);
413 for (entry = start; entry < end; entry++) {
414 set_64bit(&entry->low, 0);
415 set_64bit(&entry->high, 0);
418 return qi_flush_iec(iommu, index, irq_iommu->irte_mask);
421 int free_irte(int irq)
424 struct irq_2_iommu *irq_iommu;
427 spin_lock_irqsave(&irq_2_ir_lock, flags);
428 irq_iommu = valid_irq_2_iommu(irq);
430 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
434 rc = clear_entries(irq_iommu);
436 irq_iommu->iommu = NULL;
437 irq_iommu->irte_index = 0;
438 irq_iommu->sub_handle = 0;
439 irq_iommu->irte_mask = 0;
441 spin_unlock_irqrestore(&irq_2_ir_lock, flags);
447 * source validation type
449 #define SVT_NO_VERIFY 0x0 /* no verification is required */
450 #define SVT_VERIFY_SID_SQ 0x1 /* verify using SID and SQ fiels */
451 #define SVT_VERIFY_BUS 0x2 /* verify bus of request-id */
454 * source-id qualifier
456 #define SQ_ALL_16 0x0 /* verify all 16 bits of request-id */
457 #define SQ_13_IGNORE_1 0x1 /* verify most significant 13 bits, ignore
458 * the third least significant bit
460 #define SQ_13_IGNORE_2 0x2 /* verify most significant 13 bits, ignore
461 * the second and third least significant bits
463 #define SQ_13_IGNORE_3 0x3 /* verify most significant 13 bits, ignore
464 * the least three significant bits
468 * set SVT, SQ and SID fields of irte to verify
469 * source ids of interrupt requests
471 static void set_irte_sid(struct irte *irte, unsigned int svt,
472 unsigned int sq, unsigned int sid)
474 if (disable_sourceid_checking)
481 int set_ioapic_sid(struct irte *irte, int apic)
489 for (i = 0; i < MAX_IO_APICS; i++) {
490 if (ir_ioapic[i].id == apic) {
491 sid = (ir_ioapic[i].bus << 8) | ir_ioapic[i].devfn;
497 pr_warning("Failed to set source-id of IOAPIC (%d)\n", apic);
501 set_irte_sid(irte, 1, 0, sid);
506 int set_hpet_sid(struct irte *irte, u8 id)
514 for (i = 0; i < MAX_HPET_TBS; i++) {
515 if (ir_hpet[i].id == id) {
516 sid = (ir_hpet[i].bus << 8) | ir_hpet[i].devfn;
522 pr_warning("Failed to set source-id of HPET block (%d)\n", id);
527 * Should really use SQ_ALL_16. Some platforms are broken.
528 * While we figure out the right quirks for these broken platforms, use
529 * SQ_13_IGNORE_3 for now.
531 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_13_IGNORE_3, sid);
536 int set_msi_sid(struct irte *irte, struct pci_dev *dev)
538 struct pci_dev *bridge;
543 /* PCIe device or Root Complex integrated PCI device */
544 if (pci_is_pcie(dev) || !dev->bus->parent) {
545 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16,
546 (dev->bus->number << 8) | dev->devfn);
550 bridge = pci_find_upstream_pcie_bridge(dev);
552 if (pci_is_pcie(bridge))/* this is a PCIe-to-PCI/PCIX bridge */
553 set_irte_sid(irte, SVT_VERIFY_BUS, SQ_ALL_16,
554 (bridge->bus->number << 8) | dev->bus->number);
555 else /* this is a legacy PCI bridge */
556 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16,
557 (bridge->bus->number << 8) | bridge->devfn);
563 static void iommu_set_intr_remapping(struct intel_iommu *iommu, int mode)
569 addr = virt_to_phys((void *)iommu->ir_table->base);
571 spin_lock_irqsave(&iommu->register_lock, flags);
573 dmar_writeq(iommu->reg + DMAR_IRTA_REG,
574 (addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE);
576 /* Set interrupt-remapping table pointer */
577 iommu->gcmd |= DMA_GCMD_SIRTP;
578 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
580 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
581 readl, (sts & DMA_GSTS_IRTPS), sts);
582 spin_unlock_irqrestore(&iommu->register_lock, flags);
585 * global invalidation of interrupt entry cache before enabling
586 * interrupt-remapping.
588 qi_global_iec(iommu);
590 spin_lock_irqsave(&iommu->register_lock, flags);
592 /* Enable interrupt-remapping */
593 iommu->gcmd |= DMA_GCMD_IRE;
594 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
596 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
597 readl, (sts & DMA_GSTS_IRES), sts);
599 spin_unlock_irqrestore(&iommu->register_lock, flags);
603 static int setup_intr_remapping(struct intel_iommu *iommu, int mode)
605 struct ir_table *ir_table;
608 ir_table = iommu->ir_table = kzalloc(sizeof(struct ir_table),
611 if (!iommu->ir_table)
614 pages = alloc_pages_node(iommu->node, GFP_ATOMIC | __GFP_ZERO,
615 INTR_REMAP_PAGE_ORDER);
618 printk(KERN_ERR "failed to allocate pages of order %d\n",
619 INTR_REMAP_PAGE_ORDER);
620 kfree(iommu->ir_table);
624 ir_table->base = page_address(pages);
626 iommu_set_intr_remapping(iommu, mode);
631 * Disable Interrupt Remapping.
633 static void iommu_disable_intr_remapping(struct intel_iommu *iommu)
638 if (!ecap_ir_support(iommu->ecap))
642 * global invalidation of interrupt entry cache before disabling
643 * interrupt-remapping.
645 qi_global_iec(iommu);
647 spin_lock_irqsave(&iommu->register_lock, flags);
649 sts = dmar_readq(iommu->reg + DMAR_GSTS_REG);
650 if (!(sts & DMA_GSTS_IRES))
653 iommu->gcmd &= ~DMA_GCMD_IRE;
654 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
656 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
657 readl, !(sts & DMA_GSTS_IRES), sts);
660 spin_unlock_irqrestore(&iommu->register_lock, flags);
663 int __init intr_remapping_supported(void)
665 struct dmar_drhd_unit *drhd;
667 if (disable_intremap)
670 if (!dmar_ir_support())
673 for_each_drhd_unit(drhd) {
674 struct intel_iommu *iommu = drhd->iommu;
676 if (!ecap_ir_support(iommu->ecap))
683 int __init enable_intr_remapping(int eim)
685 struct dmar_drhd_unit *drhd;
688 if (parse_ioapics_under_ir() != 1) {
689 printk(KERN_INFO "Not enable interrupt remapping\n");
693 for_each_drhd_unit(drhd) {
694 struct intel_iommu *iommu = drhd->iommu;
697 * If the queued invalidation is already initialized,
698 * shouldn't disable it.
704 * Clear previous faults.
706 dmar_fault(-1, iommu);
709 * Disable intr remapping and queued invalidation, if already
710 * enabled prior to OS handover.
712 iommu_disable_intr_remapping(iommu);
714 dmar_disable_qi(iommu);
718 * check for the Interrupt-remapping support
720 for_each_drhd_unit(drhd) {
721 struct intel_iommu *iommu = drhd->iommu;
723 if (!ecap_ir_support(iommu->ecap))
726 if (eim && !ecap_eim_support(iommu->ecap)) {
727 printk(KERN_INFO "DRHD %Lx: EIM not supported by DRHD, "
728 " ecap %Lx\n", drhd->reg_base_addr, iommu->ecap);
734 * Enable queued invalidation for all the DRHD's.
736 for_each_drhd_unit(drhd) {
738 struct intel_iommu *iommu = drhd->iommu;
739 ret = dmar_enable_qi(iommu);
742 printk(KERN_ERR "DRHD %Lx: failed to enable queued, "
743 " invalidation, ecap %Lx, ret %d\n",
744 drhd->reg_base_addr, iommu->ecap, ret);
750 * Setup Interrupt-remapping for all the DRHD's now.
752 for_each_drhd_unit(drhd) {
753 struct intel_iommu *iommu = drhd->iommu;
755 if (!ecap_ir_support(iommu->ecap))
758 if (setup_intr_remapping(iommu, eim))
767 intr_remapping_enabled = 1;
773 * handle error condition gracefully here!
778 static void ir_parse_one_hpet_scope(struct acpi_dmar_device_scope *scope,
779 struct intel_iommu *iommu)
781 struct acpi_dmar_pci_path *path;
786 path = (struct acpi_dmar_pci_path *)(scope + 1);
787 count = (scope->length - sizeof(struct acpi_dmar_device_scope))
788 / sizeof(struct acpi_dmar_pci_path);
790 while (--count > 0) {
792 * Access PCI directly due to the PCI
793 * subsystem isn't initialized yet.
795 bus = read_pci_config_byte(bus, path->dev, path->fn,
799 ir_hpet[ir_hpet_num].bus = bus;
800 ir_hpet[ir_hpet_num].devfn = PCI_DEVFN(path->dev, path->fn);
801 ir_hpet[ir_hpet_num].iommu = iommu;
802 ir_hpet[ir_hpet_num].id = scope->enumeration_id;
806 static void ir_parse_one_ioapic_scope(struct acpi_dmar_device_scope *scope,
807 struct intel_iommu *iommu)
809 struct acpi_dmar_pci_path *path;
814 path = (struct acpi_dmar_pci_path *)(scope + 1);
815 count = (scope->length - sizeof(struct acpi_dmar_device_scope))
816 / sizeof(struct acpi_dmar_pci_path);
818 while (--count > 0) {
820 * Access PCI directly due to the PCI
821 * subsystem isn't initialized yet.
823 bus = read_pci_config_byte(bus, path->dev, path->fn,
828 ir_ioapic[ir_ioapic_num].bus = bus;
829 ir_ioapic[ir_ioapic_num].devfn = PCI_DEVFN(path->dev, path->fn);
830 ir_ioapic[ir_ioapic_num].iommu = iommu;
831 ir_ioapic[ir_ioapic_num].id = scope->enumeration_id;
835 static int ir_parse_ioapic_hpet_scope(struct acpi_dmar_header *header,
836 struct intel_iommu *iommu)
838 struct acpi_dmar_hardware_unit *drhd;
839 struct acpi_dmar_device_scope *scope;
842 drhd = (struct acpi_dmar_hardware_unit *)header;
844 start = (void *)(drhd + 1);
845 end = ((void *)drhd) + header->length;
847 while (start < end) {
849 if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC) {
850 if (ir_ioapic_num == MAX_IO_APICS) {
851 printk(KERN_WARNING "Exceeded Max IO APICS\n");
855 printk(KERN_INFO "IOAPIC id %d under DRHD base "
856 " 0x%Lx IOMMU %d\n", scope->enumeration_id,
857 drhd->address, iommu->seq_id);
859 ir_parse_one_ioapic_scope(scope, iommu);
860 } else if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_HPET) {
861 if (ir_hpet_num == MAX_HPET_TBS) {
862 printk(KERN_WARNING "Exceeded Max HPET blocks\n");
866 printk(KERN_INFO "HPET id %d under DRHD base"
867 " 0x%Lx\n", scope->enumeration_id,
870 ir_parse_one_hpet_scope(scope, iommu);
872 start += scope->length;
879 * Finds the assocaition between IOAPIC's and its Interrupt-remapping
882 int __init parse_ioapics_under_ir(void)
884 struct dmar_drhd_unit *drhd;
885 int ir_supported = 0;
887 for_each_drhd_unit(drhd) {
888 struct intel_iommu *iommu = drhd->iommu;
890 if (ecap_ir_support(iommu->ecap)) {
891 if (ir_parse_ioapic_hpet_scope(drhd->hdr, iommu))
898 if (ir_supported && ir_ioapic_num != nr_ioapics) {
900 "Not all IO-APIC's listed under remapping hardware\n");
907 void disable_intr_remapping(void)
909 struct dmar_drhd_unit *drhd;
910 struct intel_iommu *iommu = NULL;
913 * Disable Interrupt-remapping for all the DRHD's now.
915 for_each_iommu(iommu, drhd) {
916 if (!ecap_ir_support(iommu->ecap))
919 iommu_disable_intr_remapping(iommu);
923 int reenable_intr_remapping(int eim)
925 struct dmar_drhd_unit *drhd;
927 struct intel_iommu *iommu = NULL;
929 for_each_iommu(iommu, drhd)
931 dmar_reenable_qi(iommu);
934 * Setup Interrupt-remapping for all the DRHD's now.
936 for_each_iommu(iommu, drhd) {
937 if (!ecap_ir_support(iommu->ecap))
940 /* Set up interrupt remapping for iommu.*/
941 iommu_set_intr_remapping(iommu, eim);
952 * handle error condition gracefully here!