2 * Copyright (c) 2006, Intel Corporation.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
15 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 * Copyright (C) 2006-2008 Intel Corporation
18 * Author: Ashok Raj <ashok.raj@intel.com>
19 * Author: Shaohua Li <shaohua.li@intel.com>
20 * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
21 * Author: Fenghua Yu <fenghua.yu@intel.com>
24 #include <linux/init.h>
25 #include <linux/bitmap.h>
26 #include <linux/debugfs.h>
27 #include <linux/slab.h>
28 #include <linux/irq.h>
29 #include <linux/interrupt.h>
30 #include <linux/spinlock.h>
31 #include <linux/pci.h>
32 #include <linux/dmar.h>
33 #include <linux/dma-mapping.h>
34 #include <linux/mempool.h>
35 #include <linux/timer.h>
36 #include <linux/iova.h>
37 #include <linux/iommu.h>
38 #include <linux/intel-iommu.h>
39 #include <linux/sysdev.h>
40 #include <asm/cacheflush.h>
41 #include <asm/iommu.h>
44 #define ROOT_SIZE VTD_PAGE_SIZE
45 #define CONTEXT_SIZE VTD_PAGE_SIZE
47 #define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
48 #define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
50 #define IOAPIC_RANGE_START (0xfee00000)
51 #define IOAPIC_RANGE_END (0xfeefffff)
52 #define IOVA_START_ADDR (0x1000)
54 #define DEFAULT_DOMAIN_ADDRESS_WIDTH 48
56 #define MAX_AGAW_WIDTH 64
58 #define DOMAIN_MAX_ADDR(gaw) ((((u64)1) << gaw) - 1)
60 #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
61 #define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32))
62 #define DMA_64BIT_PFN IOVA_PFN(DMA_BIT_MASK(64))
64 /* global iommu list, set NULL for ignored DMAR units */
65 static struct intel_iommu **g_iommus;
67 static int rwbf_quirk;
72 * 12-63: Context Ptr (12 - (haw-1))
79 #define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry))
80 static inline bool root_present(struct root_entry *root)
82 return (root->val & 1);
84 static inline void set_root_present(struct root_entry *root)
88 static inline void set_root_value(struct root_entry *root, unsigned long value)
90 root->val |= value & VTD_PAGE_MASK;
93 static inline struct context_entry *
94 get_context_addr_from_root(struct root_entry *root)
96 return (struct context_entry *)
97 (root_present(root)?phys_to_virt(
98 root->val & VTD_PAGE_MASK) :
105 * 1: fault processing disable
106 * 2-3: translation type
107 * 12-63: address space root
113 struct context_entry {
118 static inline bool context_present(struct context_entry *context)
120 return (context->lo & 1);
122 static inline void context_set_present(struct context_entry *context)
127 static inline void context_set_fault_enable(struct context_entry *context)
129 context->lo &= (((u64)-1) << 2) | 1;
132 static inline void context_set_translation_type(struct context_entry *context,
135 context->lo &= (((u64)-1) << 4) | 3;
136 context->lo |= (value & 3) << 2;
139 static inline void context_set_address_root(struct context_entry *context,
142 context->lo |= value & VTD_PAGE_MASK;
145 static inline void context_set_address_width(struct context_entry *context,
148 context->hi |= value & 7;
151 static inline void context_set_domain_id(struct context_entry *context,
154 context->hi |= (value & ((1 << 16) - 1)) << 8;
157 static inline void context_clear_entry(struct context_entry *context)
170 * 12-63: Host physcial address
176 static inline void dma_clear_pte(struct dma_pte *pte)
181 static inline void dma_set_pte_readable(struct dma_pte *pte)
183 pte->val |= DMA_PTE_READ;
186 static inline void dma_set_pte_writable(struct dma_pte *pte)
188 pte->val |= DMA_PTE_WRITE;
191 static inline void dma_set_pte_snp(struct dma_pte *pte)
193 pte->val |= DMA_PTE_SNP;
196 static inline void dma_set_pte_prot(struct dma_pte *pte, unsigned long prot)
198 pte->val = (pte->val & ~3) | (prot & 3);
201 static inline u64 dma_pte_addr(struct dma_pte *pte)
203 return (pte->val & VTD_PAGE_MASK);
206 static inline void dma_set_pte_addr(struct dma_pte *pte, u64 addr)
208 pte->val |= (addr & VTD_PAGE_MASK);
211 static inline bool dma_pte_present(struct dma_pte *pte)
213 return (pte->val & 3) != 0;
216 /* devices under the same p2p bridge are owned in one domain */
217 #define DOMAIN_FLAG_P2P_MULTIPLE_DEVICES (1 << 0)
219 /* domain represents a virtual machine, more than one devices
220 * across iommus may be owned in one domain, e.g. kvm guest.
222 #define DOMAIN_FLAG_VIRTUAL_MACHINE (1 << 1)
225 int id; /* domain id */
226 unsigned long iommu_bmp; /* bitmap of iommus this domain uses*/
228 struct list_head devices; /* all devices' list */
229 struct iova_domain iovad; /* iova's that belong to this domain */
231 struct dma_pte *pgd; /* virtual address */
232 spinlock_t mapping_lock; /* page table lock */
233 int gaw; /* max guest address width */
235 /* adjusted guest address width, 0 is level 2 30-bit */
238 int flags; /* flags to find out type of domain */
240 int iommu_coherency;/* indicate coherency of iommu access */
241 int iommu_snooping; /* indicate snooping control feature*/
242 int iommu_count; /* reference count of iommu */
243 spinlock_t iommu_lock; /* protect iommu set in domain */
244 u64 max_addr; /* maximum mapped address */
247 /* PCI domain-device relationship */
248 struct device_domain_info {
249 struct list_head link; /* link to domain siblings */
250 struct list_head global; /* link to global list */
251 int segment; /* PCI domain */
252 u8 bus; /* PCI bus number */
253 u8 devfn; /* PCI devfn number */
254 struct pci_dev *dev; /* it's NULL for PCIE-to-PCI bridge */
255 struct dmar_domain *domain; /* pointer to domain */
258 static void flush_unmaps_timeout(unsigned long data);
260 DEFINE_TIMER(unmap_timer, flush_unmaps_timeout, 0, 0);
262 #define HIGH_WATER_MARK 250
263 struct deferred_flush_tables {
265 struct iova *iova[HIGH_WATER_MARK];
266 struct dmar_domain *domain[HIGH_WATER_MARK];
269 static struct deferred_flush_tables *deferred_flush;
271 /* bitmap for indexing intel_iommus */
272 static int g_num_of_iommus;
274 static DEFINE_SPINLOCK(async_umap_flush_lock);
275 static LIST_HEAD(unmaps_to_do);
278 static long list_size;
280 static void domain_remove_dev_info(struct dmar_domain *domain);
282 #ifdef CONFIG_DMAR_DEFAULT_ON
283 int dmar_disabled = 0;
285 int dmar_disabled = 1;
286 #endif /*CONFIG_DMAR_DEFAULT_ON*/
288 static int __initdata dmar_map_gfx = 1;
289 static int dmar_forcedac;
290 static int intel_iommu_strict;
291 int iommu_pass_through;
293 #define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1))
294 static DEFINE_SPINLOCK(device_domain_lock);
295 static LIST_HEAD(device_domain_list);
297 static struct iommu_ops intel_iommu_ops;
299 static int __init intel_iommu_setup(char *str)
304 if (!strncmp(str, "on", 2)) {
306 printk(KERN_INFO "Intel-IOMMU: enabled\n");
307 } else if (!strncmp(str, "off", 3)) {
309 printk(KERN_INFO "Intel-IOMMU: disabled\n");
310 } else if (!strncmp(str, "igfx_off", 8)) {
313 "Intel-IOMMU: disable GFX device mapping\n");
314 } else if (!strncmp(str, "forcedac", 8)) {
316 "Intel-IOMMU: Forcing DAC for PCI devices\n");
318 } else if (!strncmp(str, "strict", 6)) {
320 "Intel-IOMMU: disable batched IOTLB flush\n");
321 intel_iommu_strict = 1;
324 str += strcspn(str, ",");
330 __setup("intel_iommu=", intel_iommu_setup);
332 static struct kmem_cache *iommu_domain_cache;
333 static struct kmem_cache *iommu_devinfo_cache;
334 static struct kmem_cache *iommu_iova_cache;
336 static inline void *iommu_kmem_cache_alloc(struct kmem_cache *cachep)
341 /* trying to avoid low memory issues */
342 flags = current->flags & PF_MEMALLOC;
343 current->flags |= PF_MEMALLOC;
344 vaddr = kmem_cache_alloc(cachep, GFP_ATOMIC);
345 current->flags &= (~PF_MEMALLOC | flags);
350 static inline void *alloc_pgtable_page(void)
355 /* trying to avoid low memory issues */
356 flags = current->flags & PF_MEMALLOC;
357 current->flags |= PF_MEMALLOC;
358 vaddr = (void *)get_zeroed_page(GFP_ATOMIC);
359 current->flags &= (~PF_MEMALLOC | flags);
363 static inline void free_pgtable_page(void *vaddr)
365 free_page((unsigned long)vaddr);
368 static inline void *alloc_domain_mem(void)
370 return iommu_kmem_cache_alloc(iommu_domain_cache);
373 static void free_domain_mem(void *vaddr)
375 kmem_cache_free(iommu_domain_cache, vaddr);
378 static inline void * alloc_devinfo_mem(void)
380 return iommu_kmem_cache_alloc(iommu_devinfo_cache);
383 static inline void free_devinfo_mem(void *vaddr)
385 kmem_cache_free(iommu_devinfo_cache, vaddr);
388 struct iova *alloc_iova_mem(void)
390 return iommu_kmem_cache_alloc(iommu_iova_cache);
393 void free_iova_mem(struct iova *iova)
395 kmem_cache_free(iommu_iova_cache, iova);
399 static inline int width_to_agaw(int width);
401 static int __iommu_calculate_agaw(struct intel_iommu *iommu, int max_gaw)
406 sagaw = cap_sagaw(iommu->cap);
407 for (agaw = width_to_agaw(max_gaw);
409 if (test_bit(agaw, &sagaw))
417 * Calculate max SAGAW for each iommu.
419 int iommu_calculate_max_sagaw(struct intel_iommu *iommu)
421 return __iommu_calculate_agaw(iommu, MAX_AGAW_WIDTH);
425 * calculate agaw for each iommu.
426 * "SAGAW" may be different across iommus, use a default agaw, and
427 * get a supported less agaw for iommus that don't support the default agaw.
429 int iommu_calculate_agaw(struct intel_iommu *iommu)
431 return __iommu_calculate_agaw(iommu, DEFAULT_DOMAIN_ADDRESS_WIDTH);
434 /* in native case, each domain is related to only one iommu */
435 static struct intel_iommu *domain_get_iommu(struct dmar_domain *domain)
439 BUG_ON(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE);
441 iommu_id = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
442 if (iommu_id < 0 || iommu_id >= g_num_of_iommus)
445 return g_iommus[iommu_id];
448 static void domain_update_iommu_coherency(struct dmar_domain *domain)
452 domain->iommu_coherency = 1;
454 i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
455 for (; i < g_num_of_iommus; ) {
456 if (!ecap_coherent(g_iommus[i]->ecap)) {
457 domain->iommu_coherency = 0;
460 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
464 static void domain_update_iommu_snooping(struct dmar_domain *domain)
468 domain->iommu_snooping = 1;
470 i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
471 for (; i < g_num_of_iommus; ) {
472 if (!ecap_sc_support(g_iommus[i]->ecap)) {
473 domain->iommu_snooping = 0;
476 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
480 /* Some capabilities may be different across iommus */
481 static void domain_update_iommu_cap(struct dmar_domain *domain)
483 domain_update_iommu_coherency(domain);
484 domain_update_iommu_snooping(domain);
487 static struct intel_iommu *device_to_iommu(int segment, u8 bus, u8 devfn)
489 struct dmar_drhd_unit *drhd = NULL;
492 for_each_drhd_unit(drhd) {
495 if (segment != drhd->segment)
498 for (i = 0; i < drhd->devices_cnt; i++) {
499 if (drhd->devices[i] &&
500 drhd->devices[i]->bus->number == bus &&
501 drhd->devices[i]->devfn == devfn)
503 if (drhd->devices[i] &&
504 drhd->devices[i]->subordinate &&
505 drhd->devices[i]->subordinate->number <= bus &&
506 drhd->devices[i]->subordinate->subordinate >= bus)
510 if (drhd->include_all)
517 static void domain_flush_cache(struct dmar_domain *domain,
518 void *addr, int size)
520 if (!domain->iommu_coherency)
521 clflush_cache_range(addr, size);
524 /* Gets context entry for a given bus and devfn */
525 static struct context_entry * device_to_context_entry(struct intel_iommu *iommu,
528 struct root_entry *root;
529 struct context_entry *context;
530 unsigned long phy_addr;
533 spin_lock_irqsave(&iommu->lock, flags);
534 root = &iommu->root_entry[bus];
535 context = get_context_addr_from_root(root);
537 context = (struct context_entry *)alloc_pgtable_page();
539 spin_unlock_irqrestore(&iommu->lock, flags);
542 __iommu_flush_cache(iommu, (void *)context, CONTEXT_SIZE);
543 phy_addr = virt_to_phys((void *)context);
544 set_root_value(root, phy_addr);
545 set_root_present(root);
546 __iommu_flush_cache(iommu, root, sizeof(*root));
548 spin_unlock_irqrestore(&iommu->lock, flags);
549 return &context[devfn];
552 static int device_context_mapped(struct intel_iommu *iommu, u8 bus, u8 devfn)
554 struct root_entry *root;
555 struct context_entry *context;
559 spin_lock_irqsave(&iommu->lock, flags);
560 root = &iommu->root_entry[bus];
561 context = get_context_addr_from_root(root);
566 ret = context_present(&context[devfn]);
568 spin_unlock_irqrestore(&iommu->lock, flags);
572 static void clear_context_table(struct intel_iommu *iommu, u8 bus, u8 devfn)
574 struct root_entry *root;
575 struct context_entry *context;
578 spin_lock_irqsave(&iommu->lock, flags);
579 root = &iommu->root_entry[bus];
580 context = get_context_addr_from_root(root);
582 context_clear_entry(&context[devfn]);
583 __iommu_flush_cache(iommu, &context[devfn], \
586 spin_unlock_irqrestore(&iommu->lock, flags);
589 static void free_context_table(struct intel_iommu *iommu)
591 struct root_entry *root;
594 struct context_entry *context;
596 spin_lock_irqsave(&iommu->lock, flags);
597 if (!iommu->root_entry) {
600 for (i = 0; i < ROOT_ENTRY_NR; i++) {
601 root = &iommu->root_entry[i];
602 context = get_context_addr_from_root(root);
604 free_pgtable_page(context);
606 free_pgtable_page(iommu->root_entry);
607 iommu->root_entry = NULL;
609 spin_unlock_irqrestore(&iommu->lock, flags);
612 /* page table handling */
613 #define LEVEL_STRIDE (9)
614 #define LEVEL_MASK (((u64)1 << LEVEL_STRIDE) - 1)
616 static inline int agaw_to_level(int agaw)
621 static inline int agaw_to_width(int agaw)
623 return 30 + agaw * LEVEL_STRIDE;
627 static inline int width_to_agaw(int width)
629 return (width - 30) / LEVEL_STRIDE;
632 static inline unsigned int level_to_offset_bits(int level)
634 return (12 + (level - 1) * LEVEL_STRIDE);
637 static inline int address_level_offset(u64 addr, int level)
639 return ((addr >> level_to_offset_bits(level)) & LEVEL_MASK);
642 static inline u64 level_mask(int level)
644 return ((u64)-1 << level_to_offset_bits(level));
647 static inline u64 level_size(int level)
649 return ((u64)1 << level_to_offset_bits(level));
652 static inline u64 align_to_level(u64 addr, int level)
654 return ((addr + level_size(level) - 1) & level_mask(level));
657 static struct dma_pte * addr_to_dma_pte(struct dmar_domain *domain, u64 addr)
659 int addr_width = agaw_to_width(domain->agaw);
660 struct dma_pte *parent, *pte = NULL;
661 int level = agaw_to_level(domain->agaw);
665 BUG_ON(!domain->pgd);
667 addr &= (((u64)1) << addr_width) - 1;
668 parent = domain->pgd;
670 spin_lock_irqsave(&domain->mapping_lock, flags);
674 offset = address_level_offset(addr, level);
675 pte = &parent[offset];
679 if (!dma_pte_present(pte)) {
680 tmp_page = alloc_pgtable_page();
683 spin_unlock_irqrestore(&domain->mapping_lock,
687 domain_flush_cache(domain, tmp_page, PAGE_SIZE);
688 dma_set_pte_addr(pte, virt_to_phys(tmp_page));
690 * high level table always sets r/w, last level page
691 * table control read/write
693 dma_set_pte_readable(pte);
694 dma_set_pte_writable(pte);
695 domain_flush_cache(domain, pte, sizeof(*pte));
697 parent = phys_to_virt(dma_pte_addr(pte));
701 spin_unlock_irqrestore(&domain->mapping_lock, flags);
705 /* return address's pte at specific level */
706 static struct dma_pte *dma_addr_level_pte(struct dmar_domain *domain, u64 addr,
709 struct dma_pte *parent, *pte = NULL;
710 int total = agaw_to_level(domain->agaw);
713 parent = domain->pgd;
714 while (level <= total) {
715 offset = address_level_offset(addr, total);
716 pte = &parent[offset];
720 if (!dma_pte_present(pte))
722 parent = phys_to_virt(dma_pte_addr(pte));
728 /* clear one page's page table */
729 static void dma_pte_clear_one(struct dmar_domain *domain, u64 addr)
731 struct dma_pte *pte = NULL;
733 /* get last level pte */
734 pte = dma_addr_level_pte(domain, addr, 1);
738 domain_flush_cache(domain, pte, sizeof(*pte));
742 /* clear last level pte, a tlb flush should be followed */
743 static void dma_pte_clear_range(struct dmar_domain *domain, u64 start, u64 end)
745 int addr_width = agaw_to_width(domain->agaw);
748 start &= (((u64)1) << addr_width) - 1;
749 end &= (((u64)1) << addr_width) - 1;
750 /* in case it's partial page */
752 end = PAGE_ALIGN(end);
753 npages = (end - start) / VTD_PAGE_SIZE;
755 /* we don't need lock here, nobody else touches the iova range */
757 dma_pte_clear_one(domain, start);
758 start += VTD_PAGE_SIZE;
762 /* free page table pages. last level pte should already be cleared */
763 static void dma_pte_free_pagetable(struct dmar_domain *domain,
766 int addr_width = agaw_to_width(domain->agaw);
768 int total = agaw_to_level(domain->agaw);
772 start &= (((u64)1) << addr_width) - 1;
773 end &= (((u64)1) << addr_width) - 1;
775 /* we don't need lock here, nobody else touches the iova range */
777 while (level <= total) {
778 tmp = align_to_level(start, level);
779 if (tmp >= end || (tmp + level_size(level) > end))
783 pte = dma_addr_level_pte(domain, tmp, level);
786 phys_to_virt(dma_pte_addr(pte)));
788 domain_flush_cache(domain, pte, sizeof(*pte));
790 tmp += level_size(level);
795 if (start == 0 && end >= ((((u64)1) << addr_width) - 1)) {
796 free_pgtable_page(domain->pgd);
802 static int iommu_alloc_root_entry(struct intel_iommu *iommu)
804 struct root_entry *root;
807 root = (struct root_entry *)alloc_pgtable_page();
811 __iommu_flush_cache(iommu, root, ROOT_SIZE);
813 spin_lock_irqsave(&iommu->lock, flags);
814 iommu->root_entry = root;
815 spin_unlock_irqrestore(&iommu->lock, flags);
820 static void iommu_set_root_entry(struct intel_iommu *iommu)
826 addr = iommu->root_entry;
828 spin_lock_irqsave(&iommu->register_lock, flag);
829 dmar_writeq(iommu->reg + DMAR_RTADDR_REG, virt_to_phys(addr));
831 cmd = iommu->gcmd | DMA_GCMD_SRTP;
832 writel(cmd, iommu->reg + DMAR_GCMD_REG);
834 /* Make sure hardware complete it */
835 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
836 readl, (sts & DMA_GSTS_RTPS), sts);
838 spin_unlock_irqrestore(&iommu->register_lock, flag);
841 static void iommu_flush_write_buffer(struct intel_iommu *iommu)
846 if (!rwbf_quirk && !cap_rwbf(iommu->cap))
848 val = iommu->gcmd | DMA_GCMD_WBF;
850 spin_lock_irqsave(&iommu->register_lock, flag);
851 writel(val, iommu->reg + DMAR_GCMD_REG);
853 /* Make sure hardware complete it */
854 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
855 readl, (!(val & DMA_GSTS_WBFS)), val);
857 spin_unlock_irqrestore(&iommu->register_lock, flag);
860 /* return value determine if we need a write buffer flush */
861 static int __iommu_flush_context(struct intel_iommu *iommu,
862 u16 did, u16 source_id, u8 function_mask, u64 type,
863 int non_present_entry_flush)
869 * In the non-present entry flush case, if hardware doesn't cache
870 * non-present entry we do nothing and if hardware cache non-present
871 * entry, we flush entries of domain 0 (the domain id is used to cache
872 * any non-present entries)
874 if (non_present_entry_flush) {
875 if (!cap_caching_mode(iommu->cap))
882 case DMA_CCMD_GLOBAL_INVL:
883 val = DMA_CCMD_GLOBAL_INVL;
885 case DMA_CCMD_DOMAIN_INVL:
886 val = DMA_CCMD_DOMAIN_INVL|DMA_CCMD_DID(did);
888 case DMA_CCMD_DEVICE_INVL:
889 val = DMA_CCMD_DEVICE_INVL|DMA_CCMD_DID(did)
890 | DMA_CCMD_SID(source_id) | DMA_CCMD_FM(function_mask);
897 spin_lock_irqsave(&iommu->register_lock, flag);
898 dmar_writeq(iommu->reg + DMAR_CCMD_REG, val);
900 /* Make sure hardware complete it */
901 IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG,
902 dmar_readq, (!(val & DMA_CCMD_ICC)), val);
904 spin_unlock_irqrestore(&iommu->register_lock, flag);
906 /* flush context entry will implicitly flush write buffer */
910 /* return value determine if we need a write buffer flush */
911 static int __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did,
912 u64 addr, unsigned int size_order, u64 type,
913 int non_present_entry_flush)
915 int tlb_offset = ecap_iotlb_offset(iommu->ecap);
916 u64 val = 0, val_iva = 0;
920 * In the non-present entry flush case, if hardware doesn't cache
921 * non-present entry we do nothing and if hardware cache non-present
922 * entry, we flush entries of domain 0 (the domain id is used to cache
923 * any non-present entries)
925 if (non_present_entry_flush) {
926 if (!cap_caching_mode(iommu->cap))
933 case DMA_TLB_GLOBAL_FLUSH:
934 /* global flush doesn't need set IVA_REG */
935 val = DMA_TLB_GLOBAL_FLUSH|DMA_TLB_IVT;
937 case DMA_TLB_DSI_FLUSH:
938 val = DMA_TLB_DSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
940 case DMA_TLB_PSI_FLUSH:
941 val = DMA_TLB_PSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
942 /* Note: always flush non-leaf currently */
943 val_iva = size_order | addr;
948 /* Note: set drain read/write */
951 * This is probably to be super secure.. Looks like we can
952 * ignore it without any impact.
954 if (cap_read_drain(iommu->cap))
955 val |= DMA_TLB_READ_DRAIN;
957 if (cap_write_drain(iommu->cap))
958 val |= DMA_TLB_WRITE_DRAIN;
960 spin_lock_irqsave(&iommu->register_lock, flag);
961 /* Note: Only uses first TLB reg currently */
963 dmar_writeq(iommu->reg + tlb_offset, val_iva);
964 dmar_writeq(iommu->reg + tlb_offset + 8, val);
966 /* Make sure hardware complete it */
967 IOMMU_WAIT_OP(iommu, tlb_offset + 8,
968 dmar_readq, (!(val & DMA_TLB_IVT)), val);
970 spin_unlock_irqrestore(&iommu->register_lock, flag);
972 /* check IOTLB invalidation granularity */
973 if (DMA_TLB_IAIG(val) == 0)
974 printk(KERN_ERR"IOMMU: flush IOTLB failed\n");
975 if (DMA_TLB_IAIG(val) != DMA_TLB_IIRG(type))
976 pr_debug("IOMMU: tlb flush request %Lx, actual %Lx\n",
977 (unsigned long long)DMA_TLB_IIRG(type),
978 (unsigned long long)DMA_TLB_IAIG(val));
979 /* flush iotlb entry will implicitly flush write buffer */
983 static int iommu_flush_iotlb_psi(struct intel_iommu *iommu, u16 did,
984 u64 addr, unsigned int pages, int non_present_entry_flush)
988 BUG_ON(addr & (~VTD_PAGE_MASK));
991 /* Fallback to domain selective flush if no PSI support */
992 if (!cap_pgsel_inv(iommu->cap))
993 return iommu->flush.flush_iotlb(iommu, did, 0, 0,
995 non_present_entry_flush);
998 * PSI requires page size to be 2 ^ x, and the base address is naturally
999 * aligned to the size
1001 mask = ilog2(__roundup_pow_of_two(pages));
1002 /* Fallback to domain selective flush if size is too big */
1003 if (mask > cap_max_amask_val(iommu->cap))
1004 return iommu->flush.flush_iotlb(iommu, did, 0, 0,
1005 DMA_TLB_DSI_FLUSH, non_present_entry_flush);
1007 return iommu->flush.flush_iotlb(iommu, did, addr, mask,
1009 non_present_entry_flush);
1012 static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu)
1015 unsigned long flags;
1017 spin_lock_irqsave(&iommu->register_lock, flags);
1018 pmen = readl(iommu->reg + DMAR_PMEN_REG);
1019 pmen &= ~DMA_PMEN_EPM;
1020 writel(pmen, iommu->reg + DMAR_PMEN_REG);
1022 /* wait for the protected region status bit to clear */
1023 IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG,
1024 readl, !(pmen & DMA_PMEN_PRS), pmen);
1026 spin_unlock_irqrestore(&iommu->register_lock, flags);
1029 static int iommu_enable_translation(struct intel_iommu *iommu)
1032 unsigned long flags;
1034 spin_lock_irqsave(&iommu->register_lock, flags);
1035 writel(iommu->gcmd|DMA_GCMD_TE, iommu->reg + DMAR_GCMD_REG);
1037 /* Make sure hardware complete it */
1038 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1039 readl, (sts & DMA_GSTS_TES), sts);
1041 iommu->gcmd |= DMA_GCMD_TE;
1042 spin_unlock_irqrestore(&iommu->register_lock, flags);
1046 static int iommu_disable_translation(struct intel_iommu *iommu)
1051 spin_lock_irqsave(&iommu->register_lock, flag);
1052 iommu->gcmd &= ~DMA_GCMD_TE;
1053 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1055 /* Make sure hardware complete it */
1056 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1057 readl, (!(sts & DMA_GSTS_TES)), sts);
1059 spin_unlock_irqrestore(&iommu->register_lock, flag);
1064 static int iommu_init_domains(struct intel_iommu *iommu)
1066 unsigned long ndomains;
1067 unsigned long nlongs;
1069 ndomains = cap_ndoms(iommu->cap);
1070 pr_debug("Number of Domains supportd <%ld>\n", ndomains);
1071 nlongs = BITS_TO_LONGS(ndomains);
1073 /* TBD: there might be 64K domains,
1074 * consider other allocation for future chip
1076 iommu->domain_ids = kcalloc(nlongs, sizeof(unsigned long), GFP_KERNEL);
1077 if (!iommu->domain_ids) {
1078 printk(KERN_ERR "Allocating domain id array failed\n");
1081 iommu->domains = kcalloc(ndomains, sizeof(struct dmar_domain *),
1083 if (!iommu->domains) {
1084 printk(KERN_ERR "Allocating domain array failed\n");
1085 kfree(iommu->domain_ids);
1089 spin_lock_init(&iommu->lock);
1092 * if Caching mode is set, then invalid translations are tagged
1093 * with domainid 0. Hence we need to pre-allocate it.
1095 if (cap_caching_mode(iommu->cap))
1096 set_bit(0, iommu->domain_ids);
1101 static void domain_exit(struct dmar_domain *domain);
1102 static void vm_domain_exit(struct dmar_domain *domain);
1104 void free_dmar_iommu(struct intel_iommu *iommu)
1106 struct dmar_domain *domain;
1108 unsigned long flags;
1110 i = find_first_bit(iommu->domain_ids, cap_ndoms(iommu->cap));
1111 for (; i < cap_ndoms(iommu->cap); ) {
1112 domain = iommu->domains[i];
1113 clear_bit(i, iommu->domain_ids);
1115 spin_lock_irqsave(&domain->iommu_lock, flags);
1116 if (--domain->iommu_count == 0) {
1117 if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE)
1118 vm_domain_exit(domain);
1120 domain_exit(domain);
1122 spin_unlock_irqrestore(&domain->iommu_lock, flags);
1124 i = find_next_bit(iommu->domain_ids,
1125 cap_ndoms(iommu->cap), i+1);
1128 if (iommu->gcmd & DMA_GCMD_TE)
1129 iommu_disable_translation(iommu);
1132 set_irq_data(iommu->irq, NULL);
1133 /* This will mask the irq */
1134 free_irq(iommu->irq, iommu);
1135 destroy_irq(iommu->irq);
1138 kfree(iommu->domains);
1139 kfree(iommu->domain_ids);
1141 g_iommus[iommu->seq_id] = NULL;
1143 /* if all iommus are freed, free g_iommus */
1144 for (i = 0; i < g_num_of_iommus; i++) {
1149 if (i == g_num_of_iommus)
1152 /* free context mapping */
1153 free_context_table(iommu);
1156 static struct dmar_domain * iommu_alloc_domain(struct intel_iommu *iommu)
1159 unsigned long ndomains;
1160 struct dmar_domain *domain;
1161 unsigned long flags;
1163 domain = alloc_domain_mem();
1167 ndomains = cap_ndoms(iommu->cap);
1169 spin_lock_irqsave(&iommu->lock, flags);
1170 num = find_first_zero_bit(iommu->domain_ids, ndomains);
1171 if (num >= ndomains) {
1172 spin_unlock_irqrestore(&iommu->lock, flags);
1173 free_domain_mem(domain);
1174 printk(KERN_ERR "IOMMU: no free domain ids\n");
1178 set_bit(num, iommu->domain_ids);
1180 memset(&domain->iommu_bmp, 0, sizeof(unsigned long));
1181 set_bit(iommu->seq_id, &domain->iommu_bmp);
1183 iommu->domains[num] = domain;
1184 spin_unlock_irqrestore(&iommu->lock, flags);
1189 static void iommu_free_domain(struct dmar_domain *domain)
1191 unsigned long flags;
1192 struct intel_iommu *iommu;
1194 iommu = domain_get_iommu(domain);
1196 spin_lock_irqsave(&iommu->lock, flags);
1197 clear_bit(domain->id, iommu->domain_ids);
1198 spin_unlock_irqrestore(&iommu->lock, flags);
1201 static struct iova_domain reserved_iova_list;
1202 static struct lock_class_key reserved_alloc_key;
1203 static struct lock_class_key reserved_rbtree_key;
1205 static void dmar_init_reserved_ranges(void)
1207 struct pci_dev *pdev = NULL;
1212 init_iova_domain(&reserved_iova_list, DMA_32BIT_PFN);
1214 lockdep_set_class(&reserved_iova_list.iova_alloc_lock,
1215 &reserved_alloc_key);
1216 lockdep_set_class(&reserved_iova_list.iova_rbtree_lock,
1217 &reserved_rbtree_key);
1219 /* IOAPIC ranges shouldn't be accessed by DMA */
1220 iova = reserve_iova(&reserved_iova_list, IOVA_PFN(IOAPIC_RANGE_START),
1221 IOVA_PFN(IOAPIC_RANGE_END));
1223 printk(KERN_ERR "Reserve IOAPIC range failed\n");
1225 /* Reserve all PCI MMIO to avoid peer-to-peer access */
1226 for_each_pci_dev(pdev) {
1229 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1230 r = &pdev->resource[i];
1231 if (!r->flags || !(r->flags & IORESOURCE_MEM))
1235 size = r->end - addr;
1236 size = PAGE_ALIGN(size);
1237 iova = reserve_iova(&reserved_iova_list, IOVA_PFN(addr),
1238 IOVA_PFN(size + addr) - 1);
1240 printk(KERN_ERR "Reserve iova failed\n");
1246 static void domain_reserve_special_ranges(struct dmar_domain *domain)
1248 copy_reserved_iova(&reserved_iova_list, &domain->iovad);
1251 static inline int guestwidth_to_adjustwidth(int gaw)
1254 int r = (gaw - 12) % 9;
1265 static int domain_init(struct dmar_domain *domain, int guest_width)
1267 struct intel_iommu *iommu;
1268 int adjust_width, agaw;
1269 unsigned long sagaw;
1271 init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
1272 spin_lock_init(&domain->mapping_lock);
1273 spin_lock_init(&domain->iommu_lock);
1275 domain_reserve_special_ranges(domain);
1277 /* calculate AGAW */
1278 iommu = domain_get_iommu(domain);
1279 if (guest_width > cap_mgaw(iommu->cap))
1280 guest_width = cap_mgaw(iommu->cap);
1281 domain->gaw = guest_width;
1282 adjust_width = guestwidth_to_adjustwidth(guest_width);
1283 agaw = width_to_agaw(adjust_width);
1284 sagaw = cap_sagaw(iommu->cap);
1285 if (!test_bit(agaw, &sagaw)) {
1286 /* hardware doesn't support it, choose a bigger one */
1287 pr_debug("IOMMU: hardware doesn't support agaw %d\n", agaw);
1288 agaw = find_next_bit(&sagaw, 5, agaw);
1292 domain->agaw = agaw;
1293 INIT_LIST_HEAD(&domain->devices);
1295 if (ecap_coherent(iommu->ecap))
1296 domain->iommu_coherency = 1;
1298 domain->iommu_coherency = 0;
1300 if (ecap_sc_support(iommu->ecap))
1301 domain->iommu_snooping = 1;
1303 domain->iommu_snooping = 0;
1305 domain->iommu_count = 1;
1307 /* always allocate the top pgd */
1308 domain->pgd = (struct dma_pte *)alloc_pgtable_page();
1311 __iommu_flush_cache(iommu, domain->pgd, PAGE_SIZE);
1315 static void domain_exit(struct dmar_domain *domain)
1319 /* Domain 0 is reserved, so dont process it */
1323 domain_remove_dev_info(domain);
1325 put_iova_domain(&domain->iovad);
1326 end = DOMAIN_MAX_ADDR(domain->gaw);
1327 end = end & (~PAGE_MASK);
1330 dma_pte_clear_range(domain, 0, end);
1332 /* free page tables */
1333 dma_pte_free_pagetable(domain, 0, end);
1335 iommu_free_domain(domain);
1336 free_domain_mem(domain);
1339 static int domain_context_mapping_one(struct dmar_domain *domain, int segment,
1340 u8 bus, u8 devfn, int translation)
1342 struct context_entry *context;
1343 unsigned long flags;
1344 struct intel_iommu *iommu;
1345 struct dma_pte *pgd;
1347 unsigned long ndomains;
1351 pr_debug("Set context mapping for %02x:%02x.%d\n",
1352 bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
1354 BUG_ON(!domain->pgd);
1355 BUG_ON(translation != CONTEXT_TT_PASS_THROUGH &&
1356 translation != CONTEXT_TT_MULTI_LEVEL);
1358 iommu = device_to_iommu(segment, bus, devfn);
1362 context = device_to_context_entry(iommu, bus, devfn);
1365 spin_lock_irqsave(&iommu->lock, flags);
1366 if (context_present(context)) {
1367 spin_unlock_irqrestore(&iommu->lock, flags);
1374 if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE) {
1377 /* find an available domain id for this device in iommu */
1378 ndomains = cap_ndoms(iommu->cap);
1379 num = find_first_bit(iommu->domain_ids, ndomains);
1380 for (; num < ndomains; ) {
1381 if (iommu->domains[num] == domain) {
1386 num = find_next_bit(iommu->domain_ids,
1387 cap_ndoms(iommu->cap), num+1);
1391 num = find_first_zero_bit(iommu->domain_ids, ndomains);
1392 if (num >= ndomains) {
1393 spin_unlock_irqrestore(&iommu->lock, flags);
1394 printk(KERN_ERR "IOMMU: no free domain ids\n");
1398 set_bit(num, iommu->domain_ids);
1399 iommu->domains[num] = domain;
1403 /* Skip top levels of page tables for
1404 * iommu which has less agaw than default.
1406 for (agaw = domain->agaw; agaw != iommu->agaw; agaw--) {
1407 pgd = phys_to_virt(dma_pte_addr(pgd));
1408 if (!dma_pte_present(pgd)) {
1409 spin_unlock_irqrestore(&iommu->lock, flags);
1415 context_set_domain_id(context, id);
1418 * In pass through mode, AW must be programmed to indicate the largest
1419 * AGAW value supported by hardware. And ASR is ignored by hardware.
1421 if (likely(translation == CONTEXT_TT_MULTI_LEVEL)) {
1422 context_set_address_width(context, iommu->agaw);
1423 context_set_address_root(context, virt_to_phys(pgd));
1425 context_set_address_width(context, iommu->msagaw);
1427 context_set_translation_type(context, translation);
1428 context_set_fault_enable(context);
1429 context_set_present(context);
1430 domain_flush_cache(domain, context, sizeof(*context));
1432 /* it's a non-present to present mapping */
1433 if (iommu->flush.flush_context(iommu, domain->id,
1434 (((u16)bus) << 8) | devfn, DMA_CCMD_MASK_NOBIT,
1435 DMA_CCMD_DEVICE_INVL, 1))
1436 iommu_flush_write_buffer(iommu);
1438 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_DSI_FLUSH, 0);
1440 spin_unlock_irqrestore(&iommu->lock, flags);
1442 spin_lock_irqsave(&domain->iommu_lock, flags);
1443 if (!test_and_set_bit(iommu->seq_id, &domain->iommu_bmp)) {
1444 domain->iommu_count++;
1445 domain_update_iommu_cap(domain);
1447 spin_unlock_irqrestore(&domain->iommu_lock, flags);
1452 domain_context_mapping(struct dmar_domain *domain, struct pci_dev *pdev,
1456 struct pci_dev *tmp, *parent;
1458 ret = domain_context_mapping_one(domain, pci_domain_nr(pdev->bus),
1459 pdev->bus->number, pdev->devfn,
1464 /* dependent device mapping */
1465 tmp = pci_find_upstream_pcie_bridge(pdev);
1468 /* Secondary interface's bus number and devfn 0 */
1469 parent = pdev->bus->self;
1470 while (parent != tmp) {
1471 ret = domain_context_mapping_one(domain,
1472 pci_domain_nr(parent->bus),
1473 parent->bus->number,
1474 parent->devfn, translation);
1477 parent = parent->bus->self;
1479 if (tmp->is_pcie) /* this is a PCIE-to-PCI bridge */
1480 return domain_context_mapping_one(domain,
1481 pci_domain_nr(tmp->subordinate),
1482 tmp->subordinate->number, 0,
1484 else /* this is a legacy PCI bridge */
1485 return domain_context_mapping_one(domain,
1486 pci_domain_nr(tmp->bus),
1492 static int domain_context_mapped(struct pci_dev *pdev)
1495 struct pci_dev *tmp, *parent;
1496 struct intel_iommu *iommu;
1498 iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
1503 ret = device_context_mapped(iommu, pdev->bus->number, pdev->devfn);
1506 /* dependent device mapping */
1507 tmp = pci_find_upstream_pcie_bridge(pdev);
1510 /* Secondary interface's bus number and devfn 0 */
1511 parent = pdev->bus->self;
1512 while (parent != tmp) {
1513 ret = device_context_mapped(iommu, parent->bus->number,
1517 parent = parent->bus->self;
1520 return device_context_mapped(iommu, tmp->subordinate->number,
1523 return device_context_mapped(iommu, tmp->bus->number,
1528 domain_page_mapping(struct dmar_domain *domain, dma_addr_t iova,
1529 u64 hpa, size_t size, int prot)
1531 u64 start_pfn, end_pfn;
1532 struct dma_pte *pte;
1534 int addr_width = agaw_to_width(domain->agaw);
1536 hpa &= (((u64)1) << addr_width) - 1;
1538 if ((prot & (DMA_PTE_READ|DMA_PTE_WRITE)) == 0)
1541 start_pfn = ((u64)hpa) >> VTD_PAGE_SHIFT;
1542 end_pfn = (VTD_PAGE_ALIGN(((u64)hpa) + size)) >> VTD_PAGE_SHIFT;
1544 while (start_pfn < end_pfn) {
1545 pte = addr_to_dma_pte(domain, iova + VTD_PAGE_SIZE * index);
1548 /* We don't need lock here, nobody else
1549 * touches the iova range
1551 BUG_ON(dma_pte_addr(pte));
1552 dma_set_pte_addr(pte, start_pfn << VTD_PAGE_SHIFT);
1553 dma_set_pte_prot(pte, prot);
1554 if (prot & DMA_PTE_SNP)
1555 dma_set_pte_snp(pte);
1556 domain_flush_cache(domain, pte, sizeof(*pte));
1563 static void iommu_detach_dev(struct intel_iommu *iommu, u8 bus, u8 devfn)
1568 clear_context_table(iommu, bus, devfn);
1569 iommu->flush.flush_context(iommu, 0, 0, 0,
1570 DMA_CCMD_GLOBAL_INVL, 0);
1571 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
1572 DMA_TLB_GLOBAL_FLUSH, 0);
1575 static void domain_remove_dev_info(struct dmar_domain *domain)
1577 struct device_domain_info *info;
1578 unsigned long flags;
1579 struct intel_iommu *iommu;
1581 spin_lock_irqsave(&device_domain_lock, flags);
1582 while (!list_empty(&domain->devices)) {
1583 info = list_entry(domain->devices.next,
1584 struct device_domain_info, link);
1585 list_del(&info->link);
1586 list_del(&info->global);
1588 info->dev->dev.archdata.iommu = NULL;
1589 spin_unlock_irqrestore(&device_domain_lock, flags);
1591 iommu = device_to_iommu(info->segment, info->bus, info->devfn);
1592 iommu_detach_dev(iommu, info->bus, info->devfn);
1593 free_devinfo_mem(info);
1595 spin_lock_irqsave(&device_domain_lock, flags);
1597 spin_unlock_irqrestore(&device_domain_lock, flags);
1602 * Note: we use struct pci_dev->dev.archdata.iommu stores the info
1604 static struct dmar_domain *
1605 find_domain(struct pci_dev *pdev)
1607 struct device_domain_info *info;
1609 /* No lock here, assumes no domain exit in normal case */
1610 info = pdev->dev.archdata.iommu;
1612 return info->domain;
1616 /* domain is initialized */
1617 static struct dmar_domain *get_domain_for_dev(struct pci_dev *pdev, int gaw)
1619 struct dmar_domain *domain, *found = NULL;
1620 struct intel_iommu *iommu;
1621 struct dmar_drhd_unit *drhd;
1622 struct device_domain_info *info, *tmp;
1623 struct pci_dev *dev_tmp;
1624 unsigned long flags;
1625 int bus = 0, devfn = 0;
1628 domain = find_domain(pdev);
1632 segment = pci_domain_nr(pdev->bus);
1634 dev_tmp = pci_find_upstream_pcie_bridge(pdev);
1636 if (dev_tmp->is_pcie) {
1637 bus = dev_tmp->subordinate->number;
1640 bus = dev_tmp->bus->number;
1641 devfn = dev_tmp->devfn;
1643 spin_lock_irqsave(&device_domain_lock, flags);
1644 list_for_each_entry(info, &device_domain_list, global) {
1645 if (info->segment == segment &&
1646 info->bus == bus && info->devfn == devfn) {
1647 found = info->domain;
1651 spin_unlock_irqrestore(&device_domain_lock, flags);
1652 /* pcie-pci bridge already has a domain, uses it */
1659 /* Allocate new domain for the device */
1660 drhd = dmar_find_matched_drhd_unit(pdev);
1662 printk(KERN_ERR "IOMMU: can't find DMAR for device %s\n",
1666 iommu = drhd->iommu;
1668 domain = iommu_alloc_domain(iommu);
1672 if (domain_init(domain, gaw)) {
1673 domain_exit(domain);
1677 /* register pcie-to-pci device */
1679 info = alloc_devinfo_mem();
1681 domain_exit(domain);
1684 info->segment = segment;
1686 info->devfn = devfn;
1688 info->domain = domain;
1689 /* This domain is shared by devices under p2p bridge */
1690 domain->flags |= DOMAIN_FLAG_P2P_MULTIPLE_DEVICES;
1692 /* pcie-to-pci bridge already has a domain, uses it */
1694 spin_lock_irqsave(&device_domain_lock, flags);
1695 list_for_each_entry(tmp, &device_domain_list, global) {
1696 if (tmp->segment == segment &&
1697 tmp->bus == bus && tmp->devfn == devfn) {
1698 found = tmp->domain;
1703 free_devinfo_mem(info);
1704 domain_exit(domain);
1707 list_add(&info->link, &domain->devices);
1708 list_add(&info->global, &device_domain_list);
1710 spin_unlock_irqrestore(&device_domain_lock, flags);
1714 info = alloc_devinfo_mem();
1717 info->segment = segment;
1718 info->bus = pdev->bus->number;
1719 info->devfn = pdev->devfn;
1721 info->domain = domain;
1722 spin_lock_irqsave(&device_domain_lock, flags);
1723 /* somebody is fast */
1724 found = find_domain(pdev);
1725 if (found != NULL) {
1726 spin_unlock_irqrestore(&device_domain_lock, flags);
1727 if (found != domain) {
1728 domain_exit(domain);
1731 free_devinfo_mem(info);
1734 list_add(&info->link, &domain->devices);
1735 list_add(&info->global, &device_domain_list);
1736 pdev->dev.archdata.iommu = info;
1737 spin_unlock_irqrestore(&device_domain_lock, flags);
1740 /* recheck it here, maybe others set it */
1741 return find_domain(pdev);
1744 static int iommu_prepare_identity_map(struct pci_dev *pdev,
1745 unsigned long long start,
1746 unsigned long long end)
1748 struct dmar_domain *domain;
1750 unsigned long long base;
1754 "IOMMU: Setting identity map for device %s [0x%Lx - 0x%Lx]\n",
1755 pci_name(pdev), start, end);
1756 /* page table init */
1757 domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
1761 /* The address might not be aligned */
1762 base = start & PAGE_MASK;
1764 size = PAGE_ALIGN(size);
1765 if (!reserve_iova(&domain->iovad, IOVA_PFN(base),
1766 IOVA_PFN(base + size) - 1)) {
1767 printk(KERN_ERR "IOMMU: reserve iova failed\n");
1772 pr_debug("Mapping reserved region %lx@%llx for %s\n",
1773 size, base, pci_name(pdev));
1775 * RMRR range might have overlap with physical memory range,
1778 dma_pte_clear_range(domain, base, base + size);
1780 ret = domain_page_mapping(domain, base, base, size,
1781 DMA_PTE_READ|DMA_PTE_WRITE);
1785 /* context entry init */
1786 ret = domain_context_mapping(domain, pdev, CONTEXT_TT_MULTI_LEVEL);
1790 domain_exit(domain);
1795 static inline int iommu_prepare_rmrr_dev(struct dmar_rmrr_unit *rmrr,
1796 struct pci_dev *pdev)
1798 if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO)
1800 return iommu_prepare_identity_map(pdev, rmrr->base_address,
1801 rmrr->end_address + 1);
1804 #ifdef CONFIG_DMAR_GFX_WA
1805 struct iommu_prepare_data {
1806 struct pci_dev *pdev;
1810 static int __init iommu_prepare_work_fn(unsigned long start_pfn,
1811 unsigned long end_pfn, void *datax)
1813 struct iommu_prepare_data *data;
1815 data = (struct iommu_prepare_data *)datax;
1817 data->ret = iommu_prepare_identity_map(data->pdev,
1818 start_pfn<<PAGE_SHIFT, end_pfn<<PAGE_SHIFT);
1823 static int __init iommu_prepare_with_active_regions(struct pci_dev *pdev)
1826 struct iommu_prepare_data data;
1831 for_each_online_node(nid) {
1832 work_with_active_regions(nid, iommu_prepare_work_fn, &data);
1839 static void __init iommu_prepare_gfx_mapping(void)
1841 struct pci_dev *pdev = NULL;
1844 for_each_pci_dev(pdev) {
1845 if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO ||
1846 !IS_GFX_DEVICE(pdev))
1848 printk(KERN_INFO "IOMMU: gfx device %s 1-1 mapping\n",
1850 ret = iommu_prepare_with_active_regions(pdev);
1852 printk(KERN_ERR "IOMMU: mapping reserved region failed\n");
1855 #else /* !CONFIG_DMAR_GFX_WA */
1856 static inline void iommu_prepare_gfx_mapping(void)
1862 #ifdef CONFIG_DMAR_FLOPPY_WA
1863 static inline void iommu_prepare_isa(void)
1865 struct pci_dev *pdev;
1868 pdev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
1872 printk(KERN_INFO "IOMMU: Prepare 0-16M unity mapping for LPC\n");
1873 ret = iommu_prepare_identity_map(pdev, 0, 16*1024*1024);
1876 printk(KERN_ERR "IOMMU: Failed to create 0-64M identity map, "
1877 "floppy might not work\n");
1881 static inline void iommu_prepare_isa(void)
1885 #endif /* !CONFIG_DMAR_FLPY_WA */
1887 /* Initialize each context entry as pass through.*/
1888 static int __init init_context_pass_through(void)
1890 struct pci_dev *pdev = NULL;
1891 struct dmar_domain *domain;
1894 for_each_pci_dev(pdev) {
1895 domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
1896 ret = domain_context_mapping(domain, pdev,
1897 CONTEXT_TT_PASS_THROUGH);
1904 static int __init init_dmars(void)
1906 struct dmar_drhd_unit *drhd;
1907 struct dmar_rmrr_unit *rmrr;
1908 struct pci_dev *pdev;
1909 struct intel_iommu *iommu;
1911 int pass_through = 1;
1916 * initialize and program root entry to not present
1919 for_each_drhd_unit(drhd) {
1922 * lock not needed as this is only incremented in the single
1923 * threaded kernel __init code path all other access are read
1928 g_iommus = kcalloc(g_num_of_iommus, sizeof(struct intel_iommu *),
1931 printk(KERN_ERR "Allocating global iommu array failed\n");
1936 deferred_flush = kzalloc(g_num_of_iommus *
1937 sizeof(struct deferred_flush_tables), GFP_KERNEL);
1938 if (!deferred_flush) {
1944 for_each_drhd_unit(drhd) {
1948 iommu = drhd->iommu;
1949 g_iommus[iommu->seq_id] = iommu;
1951 ret = iommu_init_domains(iommu);
1957 * we could share the same root & context tables
1958 * amoung all IOMMU's. Need to Split it later.
1960 ret = iommu_alloc_root_entry(iommu);
1962 printk(KERN_ERR "IOMMU: allocate root entry failed\n");
1965 if (!ecap_pass_through(iommu->ecap))
1968 if (iommu_pass_through)
1969 if (!pass_through) {
1971 "Pass Through is not supported by hardware.\n");
1972 iommu_pass_through = 0;
1976 * Start from the sane iommu hardware state.
1978 for_each_drhd_unit(drhd) {
1982 iommu = drhd->iommu;
1985 * If the queued invalidation is already initialized by us
1986 * (for example, while enabling interrupt-remapping) then
1987 * we got the things already rolling from a sane state.
1993 * Clear any previous faults.
1995 dmar_fault(-1, iommu);
1997 * Disable queued invalidation if supported and already enabled
1998 * before OS handover.
2000 dmar_disable_qi(iommu);
2003 for_each_drhd_unit(drhd) {
2007 iommu = drhd->iommu;
2009 if (dmar_enable_qi(iommu)) {
2011 * Queued Invalidate not enabled, use Register Based
2014 iommu->flush.flush_context = __iommu_flush_context;
2015 iommu->flush.flush_iotlb = __iommu_flush_iotlb;
2016 printk(KERN_INFO "IOMMU 0x%Lx: using Register based "
2018 (unsigned long long)drhd->reg_base_addr);
2020 iommu->flush.flush_context = qi_flush_context;
2021 iommu->flush.flush_iotlb = qi_flush_iotlb;
2022 printk(KERN_INFO "IOMMU 0x%Lx: using Queued "
2024 (unsigned long long)drhd->reg_base_addr);
2028 #ifdef CONFIG_INTR_REMAP
2029 if (!intr_remapping_enabled) {
2030 ret = enable_intr_remapping(0);
2033 "IOMMU: enable interrupt remapping failed\n");
2037 * If pass through is set and enabled, context entries of all pci
2038 * devices are intialized by pass through translation type.
2040 if (iommu_pass_through) {
2041 ret = init_context_pass_through();
2043 printk(KERN_ERR "IOMMU: Pass through init failed.\n");
2044 iommu_pass_through = 0;
2049 * If pass through is not set or not enabled, setup context entries for
2050 * identity mappings for rmrr, gfx, and isa.
2052 if (!iommu_pass_through) {
2055 * for each dev attached to rmrr
2057 * locate drhd for dev, alloc domain for dev
2058 * allocate free domain
2059 * allocate page table entries for rmrr
2060 * if context not allocated for bus
2061 * allocate and init context
2062 * set present in root table for this bus
2063 * init context with domain, translation etc
2067 for_each_rmrr_units(rmrr) {
2068 for (i = 0; i < rmrr->devices_cnt; i++) {
2069 pdev = rmrr->devices[i];
2071 * some BIOS lists non-exist devices in DMAR
2076 ret = iommu_prepare_rmrr_dev(rmrr, pdev);
2079 "IOMMU: mapping reserved region failed\n");
2083 iommu_prepare_gfx_mapping();
2085 iommu_prepare_isa();
2091 * global invalidate context cache
2092 * global invalidate iotlb
2093 * enable translation
2095 for_each_drhd_unit(drhd) {
2098 iommu = drhd->iommu;
2100 iommu_flush_write_buffer(iommu);
2102 ret = dmar_set_interrupt(iommu);
2106 iommu_set_root_entry(iommu);
2108 iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL,
2110 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH,
2112 iommu_disable_protect_mem_regions(iommu);
2114 ret = iommu_enable_translation(iommu);
2121 for_each_drhd_unit(drhd) {
2124 iommu = drhd->iommu;
2131 static inline u64 aligned_size(u64 host_addr, size_t size)
2134 addr = (host_addr & (~PAGE_MASK)) + size;
2135 return PAGE_ALIGN(addr);
2139 iommu_alloc_iova(struct dmar_domain *domain, size_t size, u64 end)
2143 /* Make sure it's in range */
2144 end = min_t(u64, DOMAIN_MAX_ADDR(domain->gaw), end);
2145 if (!size || (IOVA_START_ADDR + size > end))
2148 piova = alloc_iova(&domain->iovad,
2149 size >> PAGE_SHIFT, IOVA_PFN(end), 1);
2153 static struct iova *
2154 __intel_alloc_iova(struct device *dev, struct dmar_domain *domain,
2155 size_t size, u64 dma_mask)
2157 struct pci_dev *pdev = to_pci_dev(dev);
2158 struct iova *iova = NULL;
2160 if (dma_mask <= DMA_BIT_MASK(32) || dmar_forcedac)
2161 iova = iommu_alloc_iova(domain, size, dma_mask);
2164 * First try to allocate an io virtual address in
2165 * DMA_BIT_MASK(32) and if that fails then try allocating
2168 iova = iommu_alloc_iova(domain, size, DMA_BIT_MASK(32));
2170 iova = iommu_alloc_iova(domain, size, dma_mask);
2174 printk(KERN_ERR"Allocating iova for %s failed", pci_name(pdev));
2181 static struct dmar_domain *
2182 get_valid_domain_for_dev(struct pci_dev *pdev)
2184 struct dmar_domain *domain;
2187 domain = get_domain_for_dev(pdev,
2188 DEFAULT_DOMAIN_ADDRESS_WIDTH);
2191 "Allocating domain for %s failed", pci_name(pdev));
2195 /* make sure context mapping is ok */
2196 if (unlikely(!domain_context_mapped(pdev))) {
2197 ret = domain_context_mapping(domain, pdev,
2198 CONTEXT_TT_MULTI_LEVEL);
2201 "Domain context map for %s failed",
2210 static dma_addr_t __intel_map_single(struct device *hwdev, phys_addr_t paddr,
2211 size_t size, int dir, u64 dma_mask)
2213 struct pci_dev *pdev = to_pci_dev(hwdev);
2214 struct dmar_domain *domain;
2215 phys_addr_t start_paddr;
2219 struct intel_iommu *iommu;
2221 BUG_ON(dir == DMA_NONE);
2222 if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO)
2225 domain = get_valid_domain_for_dev(pdev);
2229 iommu = domain_get_iommu(domain);
2230 size = aligned_size((u64)paddr, size);
2232 iova = __intel_alloc_iova(hwdev, domain, size, pdev->dma_mask);
2236 start_paddr = (phys_addr_t)iova->pfn_lo << PAGE_SHIFT;
2239 * Check if DMAR supports zero-length reads on write only
2242 if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
2243 !cap_zlr(iommu->cap))
2244 prot |= DMA_PTE_READ;
2245 if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
2246 prot |= DMA_PTE_WRITE;
2248 * paddr - (paddr + size) might be partial page, we should map the whole
2249 * page. Note: if two part of one page are separately mapped, we
2250 * might have two guest_addr mapping to the same host paddr, but this
2251 * is not a big problem
2253 ret = domain_page_mapping(domain, start_paddr,
2254 ((u64)paddr) & PAGE_MASK, size, prot);
2258 /* it's a non-present to present mapping */
2259 ret = iommu_flush_iotlb_psi(iommu, domain->id,
2260 start_paddr, size >> VTD_PAGE_SHIFT, 1);
2262 iommu_flush_write_buffer(iommu);
2264 return start_paddr + ((u64)paddr & (~PAGE_MASK));
2268 __free_iova(&domain->iovad, iova);
2269 printk(KERN_ERR"Device %s request: %zx@%llx dir %d --- failed\n",
2270 pci_name(pdev), size, (unsigned long long)paddr, dir);
2274 static dma_addr_t intel_map_page(struct device *dev, struct page *page,
2275 unsigned long offset, size_t size,
2276 enum dma_data_direction dir,
2277 struct dma_attrs *attrs)
2279 return __intel_map_single(dev, page_to_phys(page) + offset, size,
2280 dir, to_pci_dev(dev)->dma_mask);
2283 static void flush_unmaps(void)
2289 /* just flush them all */
2290 for (i = 0; i < g_num_of_iommus; i++) {
2291 struct intel_iommu *iommu = g_iommus[i];
2295 if (deferred_flush[i].next) {
2296 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
2297 DMA_TLB_GLOBAL_FLUSH, 0);
2298 for (j = 0; j < deferred_flush[i].next; j++) {
2299 __free_iova(&deferred_flush[i].domain[j]->iovad,
2300 deferred_flush[i].iova[j]);
2302 deferred_flush[i].next = 0;
2309 static void flush_unmaps_timeout(unsigned long data)
2311 unsigned long flags;
2313 spin_lock_irqsave(&async_umap_flush_lock, flags);
2315 spin_unlock_irqrestore(&async_umap_flush_lock, flags);
2318 static void add_unmap(struct dmar_domain *dom, struct iova *iova)
2320 unsigned long flags;
2322 struct intel_iommu *iommu;
2324 spin_lock_irqsave(&async_umap_flush_lock, flags);
2325 if (list_size == HIGH_WATER_MARK)
2328 iommu = domain_get_iommu(dom);
2329 iommu_id = iommu->seq_id;
2331 next = deferred_flush[iommu_id].next;
2332 deferred_flush[iommu_id].domain[next] = dom;
2333 deferred_flush[iommu_id].iova[next] = iova;
2334 deferred_flush[iommu_id].next++;
2337 mod_timer(&unmap_timer, jiffies + msecs_to_jiffies(10));
2341 spin_unlock_irqrestore(&async_umap_flush_lock, flags);
2344 static void intel_unmap_page(struct device *dev, dma_addr_t dev_addr,
2345 size_t size, enum dma_data_direction dir,
2346 struct dma_attrs *attrs)
2348 struct pci_dev *pdev = to_pci_dev(dev);
2349 struct dmar_domain *domain;
2350 unsigned long start_addr;
2352 struct intel_iommu *iommu;
2354 if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO)
2356 domain = find_domain(pdev);
2359 iommu = domain_get_iommu(domain);
2361 iova = find_iova(&domain->iovad, IOVA_PFN(dev_addr));
2365 start_addr = iova->pfn_lo << PAGE_SHIFT;
2366 size = aligned_size((u64)dev_addr, size);
2368 pr_debug("Device %s unmapping: %zx@%llx\n",
2369 pci_name(pdev), size, (unsigned long long)start_addr);
2371 /* clear the whole page */
2372 dma_pte_clear_range(domain, start_addr, start_addr + size);
2373 /* free page tables */
2374 dma_pte_free_pagetable(domain, start_addr, start_addr + size);
2375 if (intel_iommu_strict) {
2376 if (iommu_flush_iotlb_psi(iommu,
2377 domain->id, start_addr, size >> VTD_PAGE_SHIFT, 0))
2378 iommu_flush_write_buffer(iommu);
2380 __free_iova(&domain->iovad, iova);
2382 add_unmap(domain, iova);
2384 * queue up the release of the unmap to save the 1/6th of the
2385 * cpu used up by the iotlb flush operation...
2390 static void intel_unmap_single(struct device *dev, dma_addr_t dev_addr, size_t size,
2393 intel_unmap_page(dev, dev_addr, size, dir, NULL);
2396 static void *intel_alloc_coherent(struct device *hwdev, size_t size,
2397 dma_addr_t *dma_handle, gfp_t flags)
2402 size = PAGE_ALIGN(size);
2403 order = get_order(size);
2404 flags &= ~(GFP_DMA | GFP_DMA32);
2406 vaddr = (void *)__get_free_pages(flags, order);
2409 memset(vaddr, 0, size);
2411 *dma_handle = __intel_map_single(hwdev, virt_to_bus(vaddr), size,
2413 hwdev->coherent_dma_mask);
2416 free_pages((unsigned long)vaddr, order);
2420 static void intel_free_coherent(struct device *hwdev, size_t size, void *vaddr,
2421 dma_addr_t dma_handle)
2425 size = PAGE_ALIGN(size);
2426 order = get_order(size);
2428 intel_unmap_single(hwdev, dma_handle, size, DMA_BIDIRECTIONAL);
2429 free_pages((unsigned long)vaddr, order);
2432 static void intel_unmap_sg(struct device *hwdev, struct scatterlist *sglist,
2433 int nelems, enum dma_data_direction dir,
2434 struct dma_attrs *attrs)
2437 struct pci_dev *pdev = to_pci_dev(hwdev);
2438 struct dmar_domain *domain;
2439 unsigned long start_addr;
2443 struct scatterlist *sg;
2444 struct intel_iommu *iommu;
2446 if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO)
2449 domain = find_domain(pdev);
2452 iommu = domain_get_iommu(domain);
2454 iova = find_iova(&domain->iovad, IOVA_PFN(sglist[0].dma_address));
2457 for_each_sg(sglist, sg, nelems, i) {
2458 addr = page_to_phys(sg_page(sg)) + sg->offset;
2459 size += aligned_size((u64)addr, sg->length);
2462 start_addr = iova->pfn_lo << PAGE_SHIFT;
2464 /* clear the whole page */
2465 dma_pte_clear_range(domain, start_addr, start_addr + size);
2466 /* free page tables */
2467 dma_pte_free_pagetable(domain, start_addr, start_addr + size);
2469 if (iommu_flush_iotlb_psi(iommu, domain->id, start_addr,
2470 size >> VTD_PAGE_SHIFT, 0))
2471 iommu_flush_write_buffer(iommu);
2474 __free_iova(&domain->iovad, iova);
2477 static int intel_nontranslate_map_sg(struct device *hddev,
2478 struct scatterlist *sglist, int nelems, int dir)
2481 struct scatterlist *sg;
2483 for_each_sg(sglist, sg, nelems, i) {
2484 BUG_ON(!sg_page(sg));
2485 sg->dma_address = page_to_phys(sg_page(sg)) + sg->offset;
2486 sg->dma_length = sg->length;
2491 static int intel_map_sg(struct device *hwdev, struct scatterlist *sglist, int nelems,
2492 enum dma_data_direction dir, struct dma_attrs *attrs)
2496 struct pci_dev *pdev = to_pci_dev(hwdev);
2497 struct dmar_domain *domain;
2501 struct iova *iova = NULL;
2503 struct scatterlist *sg;
2504 unsigned long start_addr;
2505 struct intel_iommu *iommu;
2507 BUG_ON(dir == DMA_NONE);
2508 if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO)
2509 return intel_nontranslate_map_sg(hwdev, sglist, nelems, dir);
2511 domain = get_valid_domain_for_dev(pdev);
2515 iommu = domain_get_iommu(domain);
2517 for_each_sg(sglist, sg, nelems, i) {
2518 addr = page_to_phys(sg_page(sg)) + sg->offset;
2519 size += aligned_size((u64)addr, sg->length);
2522 iova = __intel_alloc_iova(hwdev, domain, size, pdev->dma_mask);
2524 sglist->dma_length = 0;
2529 * Check if DMAR supports zero-length reads on write only
2532 if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
2533 !cap_zlr(iommu->cap))
2534 prot |= DMA_PTE_READ;
2535 if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
2536 prot |= DMA_PTE_WRITE;
2538 start_addr = iova->pfn_lo << PAGE_SHIFT;
2540 for_each_sg(sglist, sg, nelems, i) {
2541 addr = page_to_phys(sg_page(sg)) + sg->offset;
2542 size = aligned_size((u64)addr, sg->length);
2543 ret = domain_page_mapping(domain, start_addr + offset,
2544 ((u64)addr) & PAGE_MASK,
2547 /* clear the page */
2548 dma_pte_clear_range(domain, start_addr,
2549 start_addr + offset);
2550 /* free page tables */
2551 dma_pte_free_pagetable(domain, start_addr,
2552 start_addr + offset);
2554 __free_iova(&domain->iovad, iova);
2557 sg->dma_address = start_addr + offset +
2558 ((u64)addr & (~PAGE_MASK));
2559 sg->dma_length = sg->length;
2563 /* it's a non-present to present mapping */
2564 if (iommu_flush_iotlb_psi(iommu, domain->id,
2565 start_addr, offset >> VTD_PAGE_SHIFT, 1))
2566 iommu_flush_write_buffer(iommu);
2570 static int intel_mapping_error(struct device *dev, dma_addr_t dma_addr)
2575 struct dma_map_ops intel_dma_ops = {
2576 .alloc_coherent = intel_alloc_coherent,
2577 .free_coherent = intel_free_coherent,
2578 .map_sg = intel_map_sg,
2579 .unmap_sg = intel_unmap_sg,
2580 .map_page = intel_map_page,
2581 .unmap_page = intel_unmap_page,
2582 .mapping_error = intel_mapping_error,
2585 static inline int iommu_domain_cache_init(void)
2589 iommu_domain_cache = kmem_cache_create("iommu_domain",
2590 sizeof(struct dmar_domain),
2595 if (!iommu_domain_cache) {
2596 printk(KERN_ERR "Couldn't create iommu_domain cache\n");
2603 static inline int iommu_devinfo_cache_init(void)
2607 iommu_devinfo_cache = kmem_cache_create("iommu_devinfo",
2608 sizeof(struct device_domain_info),
2612 if (!iommu_devinfo_cache) {
2613 printk(KERN_ERR "Couldn't create devinfo cache\n");
2620 static inline int iommu_iova_cache_init(void)
2624 iommu_iova_cache = kmem_cache_create("iommu_iova",
2625 sizeof(struct iova),
2629 if (!iommu_iova_cache) {
2630 printk(KERN_ERR "Couldn't create iova cache\n");
2637 static int __init iommu_init_mempool(void)
2640 ret = iommu_iova_cache_init();
2644 ret = iommu_domain_cache_init();
2648 ret = iommu_devinfo_cache_init();
2652 kmem_cache_destroy(iommu_domain_cache);
2654 kmem_cache_destroy(iommu_iova_cache);
2659 static void __init iommu_exit_mempool(void)
2661 kmem_cache_destroy(iommu_devinfo_cache);
2662 kmem_cache_destroy(iommu_domain_cache);
2663 kmem_cache_destroy(iommu_iova_cache);
2667 static void __init init_no_remapping_devices(void)
2669 struct dmar_drhd_unit *drhd;
2671 for_each_drhd_unit(drhd) {
2672 if (!drhd->include_all) {
2674 for (i = 0; i < drhd->devices_cnt; i++)
2675 if (drhd->devices[i] != NULL)
2677 /* ignore DMAR unit if no pci devices exist */
2678 if (i == drhd->devices_cnt)
2686 for_each_drhd_unit(drhd) {
2688 if (drhd->ignored || drhd->include_all)
2691 for (i = 0; i < drhd->devices_cnt; i++)
2692 if (drhd->devices[i] &&
2693 !IS_GFX_DEVICE(drhd->devices[i]))
2696 if (i < drhd->devices_cnt)
2699 /* bypass IOMMU if it is just for gfx devices */
2701 for (i = 0; i < drhd->devices_cnt; i++) {
2702 if (!drhd->devices[i])
2704 drhd->devices[i]->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
2709 #ifdef CONFIG_SUSPEND
2710 static int init_iommu_hw(void)
2712 struct dmar_drhd_unit *drhd;
2713 struct intel_iommu *iommu = NULL;
2715 for_each_active_iommu(iommu, drhd)
2717 dmar_reenable_qi(iommu);
2719 for_each_active_iommu(iommu, drhd) {
2720 iommu_flush_write_buffer(iommu);
2722 iommu_set_root_entry(iommu);
2724 iommu->flush.flush_context(iommu, 0, 0, 0,
2725 DMA_CCMD_GLOBAL_INVL, 0);
2726 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
2727 DMA_TLB_GLOBAL_FLUSH, 0);
2728 iommu_disable_protect_mem_regions(iommu);
2729 iommu_enable_translation(iommu);
2735 static void iommu_flush_all(void)
2737 struct dmar_drhd_unit *drhd;
2738 struct intel_iommu *iommu;
2740 for_each_active_iommu(iommu, drhd) {
2741 iommu->flush.flush_context(iommu, 0, 0, 0,
2742 DMA_CCMD_GLOBAL_INVL, 0);
2743 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
2744 DMA_TLB_GLOBAL_FLUSH, 0);
2748 static int iommu_suspend(struct sys_device *dev, pm_message_t state)
2750 struct dmar_drhd_unit *drhd;
2751 struct intel_iommu *iommu = NULL;
2754 for_each_active_iommu(iommu, drhd) {
2755 iommu->iommu_state = kzalloc(sizeof(u32) * MAX_SR_DMAR_REGS,
2757 if (!iommu->iommu_state)
2763 for_each_active_iommu(iommu, drhd) {
2764 iommu_disable_translation(iommu);
2766 spin_lock_irqsave(&iommu->register_lock, flag);
2768 iommu->iommu_state[SR_DMAR_FECTL_REG] =
2769 readl(iommu->reg + DMAR_FECTL_REG);
2770 iommu->iommu_state[SR_DMAR_FEDATA_REG] =
2771 readl(iommu->reg + DMAR_FEDATA_REG);
2772 iommu->iommu_state[SR_DMAR_FEADDR_REG] =
2773 readl(iommu->reg + DMAR_FEADDR_REG);
2774 iommu->iommu_state[SR_DMAR_FEUADDR_REG] =
2775 readl(iommu->reg + DMAR_FEUADDR_REG);
2777 spin_unlock_irqrestore(&iommu->register_lock, flag);
2782 for_each_active_iommu(iommu, drhd)
2783 kfree(iommu->iommu_state);
2788 static int iommu_resume(struct sys_device *dev)
2790 struct dmar_drhd_unit *drhd;
2791 struct intel_iommu *iommu = NULL;
2794 if (init_iommu_hw()) {
2795 WARN(1, "IOMMU setup failed, DMAR can not resume!\n");
2799 for_each_active_iommu(iommu, drhd) {
2801 spin_lock_irqsave(&iommu->register_lock, flag);
2803 writel(iommu->iommu_state[SR_DMAR_FECTL_REG],
2804 iommu->reg + DMAR_FECTL_REG);
2805 writel(iommu->iommu_state[SR_DMAR_FEDATA_REG],
2806 iommu->reg + DMAR_FEDATA_REG);
2807 writel(iommu->iommu_state[SR_DMAR_FEADDR_REG],
2808 iommu->reg + DMAR_FEADDR_REG);
2809 writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG],
2810 iommu->reg + DMAR_FEUADDR_REG);
2812 spin_unlock_irqrestore(&iommu->register_lock, flag);
2815 for_each_active_iommu(iommu, drhd)
2816 kfree(iommu->iommu_state);
2821 static struct sysdev_class iommu_sysclass = {
2823 .resume = iommu_resume,
2824 .suspend = iommu_suspend,
2827 static struct sys_device device_iommu = {
2828 .cls = &iommu_sysclass,
2831 static int __init init_iommu_sysfs(void)
2835 error = sysdev_class_register(&iommu_sysclass);
2839 error = sysdev_register(&device_iommu);
2841 sysdev_class_unregister(&iommu_sysclass);
2847 static int __init init_iommu_sysfs(void)
2851 #endif /* CONFIG_PM */
2853 int __init intel_iommu_init(void)
2857 if (dmar_table_init())
2860 if (dmar_dev_scope_init())
2864 * Check the need for DMA-remapping initialization now.
2865 * Above initialization will also be used by Interrupt-remapping.
2867 if (no_iommu || (swiotlb && !iommu_pass_through) || dmar_disabled)
2870 iommu_init_mempool();
2871 dmar_init_reserved_ranges();
2873 init_no_remapping_devices();
2877 printk(KERN_ERR "IOMMU: dmar init failed\n");
2878 put_iova_domain(&reserved_iova_list);
2879 iommu_exit_mempool();
2883 "PCI-DMA: Intel(R) Virtualization Technology for Directed I/O\n");
2885 init_timer(&unmap_timer);
2888 if (!iommu_pass_through) {
2890 "Multi-level page-table translation for DMAR.\n");
2891 dma_ops = &intel_dma_ops;
2894 "DMAR: Pass through translation for DMAR.\n");
2898 register_iommu(&intel_iommu_ops);
2903 static int vm_domain_add_dev_info(struct dmar_domain *domain,
2904 struct pci_dev *pdev)
2906 struct device_domain_info *info;
2907 unsigned long flags;
2909 info = alloc_devinfo_mem();
2913 info->segment = pci_domain_nr(pdev->bus);
2914 info->bus = pdev->bus->number;
2915 info->devfn = pdev->devfn;
2917 info->domain = domain;
2919 spin_lock_irqsave(&device_domain_lock, flags);
2920 list_add(&info->link, &domain->devices);
2921 list_add(&info->global, &device_domain_list);
2922 pdev->dev.archdata.iommu = info;
2923 spin_unlock_irqrestore(&device_domain_lock, flags);
2928 static void iommu_detach_dependent_devices(struct intel_iommu *iommu,
2929 struct pci_dev *pdev)
2931 struct pci_dev *tmp, *parent;
2933 if (!iommu || !pdev)
2936 /* dependent device detach */
2937 tmp = pci_find_upstream_pcie_bridge(pdev);
2938 /* Secondary interface's bus number and devfn 0 */
2940 parent = pdev->bus->self;
2941 while (parent != tmp) {
2942 iommu_detach_dev(iommu, parent->bus->number,
2944 parent = parent->bus->self;
2946 if (tmp->is_pcie) /* this is a PCIE-to-PCI bridge */
2947 iommu_detach_dev(iommu,
2948 tmp->subordinate->number, 0);
2949 else /* this is a legacy PCI bridge */
2950 iommu_detach_dev(iommu, tmp->bus->number,
2955 static void vm_domain_remove_one_dev_info(struct dmar_domain *domain,
2956 struct pci_dev *pdev)
2958 struct device_domain_info *info;
2959 struct intel_iommu *iommu;
2960 unsigned long flags;
2962 struct list_head *entry, *tmp;
2964 iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
2969 spin_lock_irqsave(&device_domain_lock, flags);
2970 list_for_each_safe(entry, tmp, &domain->devices) {
2971 info = list_entry(entry, struct device_domain_info, link);
2972 /* No need to compare PCI domain; it has to be the same */
2973 if (info->bus == pdev->bus->number &&
2974 info->devfn == pdev->devfn) {
2975 list_del(&info->link);
2976 list_del(&info->global);
2978 info->dev->dev.archdata.iommu = NULL;
2979 spin_unlock_irqrestore(&device_domain_lock, flags);
2981 iommu_detach_dev(iommu, info->bus, info->devfn);
2982 iommu_detach_dependent_devices(iommu, pdev);
2983 free_devinfo_mem(info);
2985 spin_lock_irqsave(&device_domain_lock, flags);
2993 /* if there is no other devices under the same iommu
2994 * owned by this domain, clear this iommu in iommu_bmp
2995 * update iommu count and coherency
2997 if (iommu == device_to_iommu(info->segment, info->bus,
3003 unsigned long tmp_flags;
3004 spin_lock_irqsave(&domain->iommu_lock, tmp_flags);
3005 clear_bit(iommu->seq_id, &domain->iommu_bmp);
3006 domain->iommu_count--;
3007 domain_update_iommu_cap(domain);
3008 spin_unlock_irqrestore(&domain->iommu_lock, tmp_flags);
3011 spin_unlock_irqrestore(&device_domain_lock, flags);
3014 static void vm_domain_remove_all_dev_info(struct dmar_domain *domain)
3016 struct device_domain_info *info;
3017 struct intel_iommu *iommu;
3018 unsigned long flags1, flags2;
3020 spin_lock_irqsave(&device_domain_lock, flags1);
3021 while (!list_empty(&domain->devices)) {
3022 info = list_entry(domain->devices.next,
3023 struct device_domain_info, link);
3024 list_del(&info->link);
3025 list_del(&info->global);
3027 info->dev->dev.archdata.iommu = NULL;
3029 spin_unlock_irqrestore(&device_domain_lock, flags1);
3031 iommu = device_to_iommu(info->segment, info->bus, info->devfn);
3032 iommu_detach_dev(iommu, info->bus, info->devfn);
3033 iommu_detach_dependent_devices(iommu, info->dev);
3035 /* clear this iommu in iommu_bmp, update iommu count
3038 spin_lock_irqsave(&domain->iommu_lock, flags2);
3039 if (test_and_clear_bit(iommu->seq_id,
3040 &domain->iommu_bmp)) {
3041 domain->iommu_count--;
3042 domain_update_iommu_cap(domain);
3044 spin_unlock_irqrestore(&domain->iommu_lock, flags2);
3046 free_devinfo_mem(info);
3047 spin_lock_irqsave(&device_domain_lock, flags1);
3049 spin_unlock_irqrestore(&device_domain_lock, flags1);
3052 /* domain id for virtual machine, it won't be set in context */
3053 static unsigned long vm_domid;
3055 static int vm_domain_min_agaw(struct dmar_domain *domain)
3058 int min_agaw = domain->agaw;
3060 i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
3061 for (; i < g_num_of_iommus; ) {
3062 if (min_agaw > g_iommus[i]->agaw)
3063 min_agaw = g_iommus[i]->agaw;
3065 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
3071 static struct dmar_domain *iommu_alloc_vm_domain(void)
3073 struct dmar_domain *domain;
3075 domain = alloc_domain_mem();
3079 domain->id = vm_domid++;
3080 memset(&domain->iommu_bmp, 0, sizeof(unsigned long));
3081 domain->flags = DOMAIN_FLAG_VIRTUAL_MACHINE;
3086 static int vm_domain_init(struct dmar_domain *domain, int guest_width)
3090 init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
3091 spin_lock_init(&domain->mapping_lock);
3092 spin_lock_init(&domain->iommu_lock);
3094 domain_reserve_special_ranges(domain);
3096 /* calculate AGAW */
3097 domain->gaw = guest_width;
3098 adjust_width = guestwidth_to_adjustwidth(guest_width);
3099 domain->agaw = width_to_agaw(adjust_width);
3101 INIT_LIST_HEAD(&domain->devices);
3103 domain->iommu_count = 0;
3104 domain->iommu_coherency = 0;
3105 domain->max_addr = 0;
3107 /* always allocate the top pgd */
3108 domain->pgd = (struct dma_pte *)alloc_pgtable_page();
3111 domain_flush_cache(domain, domain->pgd, PAGE_SIZE);
3115 static void iommu_free_vm_domain(struct dmar_domain *domain)
3117 unsigned long flags;
3118 struct dmar_drhd_unit *drhd;
3119 struct intel_iommu *iommu;
3121 unsigned long ndomains;
3123 for_each_drhd_unit(drhd) {
3126 iommu = drhd->iommu;
3128 ndomains = cap_ndoms(iommu->cap);
3129 i = find_first_bit(iommu->domain_ids, ndomains);
3130 for (; i < ndomains; ) {
3131 if (iommu->domains[i] == domain) {
3132 spin_lock_irqsave(&iommu->lock, flags);
3133 clear_bit(i, iommu->domain_ids);
3134 iommu->domains[i] = NULL;
3135 spin_unlock_irqrestore(&iommu->lock, flags);
3138 i = find_next_bit(iommu->domain_ids, ndomains, i+1);
3143 static void vm_domain_exit(struct dmar_domain *domain)
3147 /* Domain 0 is reserved, so dont process it */
3151 vm_domain_remove_all_dev_info(domain);
3153 put_iova_domain(&domain->iovad);
3154 end = DOMAIN_MAX_ADDR(domain->gaw);
3155 end = end & (~VTD_PAGE_MASK);
3158 dma_pte_clear_range(domain, 0, end);
3160 /* free page tables */
3161 dma_pte_free_pagetable(domain, 0, end);
3163 iommu_free_vm_domain(domain);
3164 free_domain_mem(domain);
3167 static int intel_iommu_domain_init(struct iommu_domain *domain)
3169 struct dmar_domain *dmar_domain;
3171 dmar_domain = iommu_alloc_vm_domain();
3174 "intel_iommu_domain_init: dmar_domain == NULL\n");
3177 if (vm_domain_init(dmar_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
3179 "intel_iommu_domain_init() failed\n");
3180 vm_domain_exit(dmar_domain);
3183 domain->priv = dmar_domain;
3188 static void intel_iommu_domain_destroy(struct iommu_domain *domain)
3190 struct dmar_domain *dmar_domain = domain->priv;
3192 domain->priv = NULL;
3193 vm_domain_exit(dmar_domain);
3196 static int intel_iommu_attach_device(struct iommu_domain *domain,
3199 struct dmar_domain *dmar_domain = domain->priv;
3200 struct pci_dev *pdev = to_pci_dev(dev);
3201 struct intel_iommu *iommu;
3206 /* normally pdev is not mapped */
3207 if (unlikely(domain_context_mapped(pdev))) {
3208 struct dmar_domain *old_domain;
3210 old_domain = find_domain(pdev);
3212 if (dmar_domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE)
3213 vm_domain_remove_one_dev_info(old_domain, pdev);
3215 domain_remove_dev_info(old_domain);
3219 iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
3224 /* check if this iommu agaw is sufficient for max mapped address */
3225 addr_width = agaw_to_width(iommu->agaw);
3226 end = DOMAIN_MAX_ADDR(addr_width);
3227 end = end & VTD_PAGE_MASK;
3228 if (end < dmar_domain->max_addr) {
3229 printk(KERN_ERR "%s: iommu agaw (%d) is not "
3230 "sufficient for the mapped address (%llx)\n",
3231 __func__, iommu->agaw, dmar_domain->max_addr);
3235 ret = domain_context_mapping(dmar_domain, pdev, CONTEXT_TT_MULTI_LEVEL);
3239 ret = vm_domain_add_dev_info(dmar_domain, pdev);
3243 static void intel_iommu_detach_device(struct iommu_domain *domain,
3246 struct dmar_domain *dmar_domain = domain->priv;
3247 struct pci_dev *pdev = to_pci_dev(dev);
3249 vm_domain_remove_one_dev_info(dmar_domain, pdev);
3252 static int intel_iommu_map_range(struct iommu_domain *domain,
3253 unsigned long iova, phys_addr_t hpa,
3254 size_t size, int iommu_prot)
3256 struct dmar_domain *dmar_domain = domain->priv;
3262 if (iommu_prot & IOMMU_READ)
3263 prot |= DMA_PTE_READ;
3264 if (iommu_prot & IOMMU_WRITE)
3265 prot |= DMA_PTE_WRITE;
3266 if ((iommu_prot & IOMMU_CACHE) && dmar_domain->iommu_snooping)
3267 prot |= DMA_PTE_SNP;
3269 max_addr = (iova & VTD_PAGE_MASK) + VTD_PAGE_ALIGN(size);
3270 if (dmar_domain->max_addr < max_addr) {
3274 /* check if minimum agaw is sufficient for mapped address */
3275 min_agaw = vm_domain_min_agaw(dmar_domain);
3276 addr_width = agaw_to_width(min_agaw);
3277 end = DOMAIN_MAX_ADDR(addr_width);
3278 end = end & VTD_PAGE_MASK;
3279 if (end < max_addr) {
3280 printk(KERN_ERR "%s: iommu agaw (%d) is not "
3281 "sufficient for the mapped address (%llx)\n",
3282 __func__, min_agaw, max_addr);
3285 dmar_domain->max_addr = max_addr;
3288 ret = domain_page_mapping(dmar_domain, iova, hpa, size, prot);
3292 static void intel_iommu_unmap_range(struct iommu_domain *domain,
3293 unsigned long iova, size_t size)
3295 struct dmar_domain *dmar_domain = domain->priv;
3298 /* The address might not be aligned */
3299 base = iova & VTD_PAGE_MASK;
3300 size = VTD_PAGE_ALIGN(size);
3301 dma_pte_clear_range(dmar_domain, base, base + size);
3303 if (dmar_domain->max_addr == base + size)
3304 dmar_domain->max_addr = base;
3307 static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain,
3310 struct dmar_domain *dmar_domain = domain->priv;
3311 struct dma_pte *pte;
3314 pte = addr_to_dma_pte(dmar_domain, iova);
3316 phys = dma_pte_addr(pte);
3321 static int intel_iommu_domain_has_cap(struct iommu_domain *domain,
3324 struct dmar_domain *dmar_domain = domain->priv;
3326 if (cap == IOMMU_CAP_CACHE_COHERENCY)
3327 return dmar_domain->iommu_snooping;
3332 static struct iommu_ops intel_iommu_ops = {
3333 .domain_init = intel_iommu_domain_init,
3334 .domain_destroy = intel_iommu_domain_destroy,
3335 .attach_dev = intel_iommu_attach_device,
3336 .detach_dev = intel_iommu_detach_device,
3337 .map = intel_iommu_map_range,
3338 .unmap = intel_iommu_unmap_range,
3339 .iova_to_phys = intel_iommu_iova_to_phys,
3340 .domain_has_cap = intel_iommu_domain_has_cap,
3343 static void __devinit quirk_iommu_rwbf(struct pci_dev *dev)
3346 * Mobile 4 Series Chipset neglects to set RWBF capability,
3349 printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n");
3353 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf);