2 * PCI Express PCI Hot Plug Driver
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/types.h>
33 #include <linux/signal.h>
34 #include <linux/jiffies.h>
35 #include <linux/timer.h>
36 #include <linux/pci.h>
37 #include <linux/interrupt.h>
38 #include <linux/time.h>
43 static atomic_t pciehp_num_controllers = ATOMIC_INIT(0);
45 static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value)
47 struct pci_dev *dev = ctrl->pcie->port;
48 return pci_read_config_word(dev, pci_pcie_cap(dev) + reg, value);
51 static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value)
53 struct pci_dev *dev = ctrl->pcie->port;
54 return pci_read_config_dword(dev, pci_pcie_cap(dev) + reg, value);
57 static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value)
59 struct pci_dev *dev = ctrl->pcie->port;
60 return pci_write_config_word(dev, pci_pcie_cap(dev) + reg, value);
63 static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value)
65 struct pci_dev *dev = ctrl->pcie->port;
66 return pci_write_config_dword(dev, pci_pcie_cap(dev) + reg, value);
69 /* Power Control Command */
71 #define POWER_OFF PCI_EXP_SLTCTL_PCC
73 static irqreturn_t pcie_isr(int irq, void *dev_id);
74 static void start_int_poll_timer(struct controller *ctrl, int sec);
76 /* This is the interrupt polling timeout function. */
77 static void int_poll_timeout(unsigned long data)
79 struct controller *ctrl = (struct controller *)data;
81 /* Poll for interrupt events. regs == NULL => polling */
84 init_timer(&ctrl->poll_timer);
85 if (!pciehp_poll_time)
86 pciehp_poll_time = 2; /* default polling interval is 2 sec */
88 start_int_poll_timer(ctrl, pciehp_poll_time);
91 /* This function starts the interrupt polling timer. */
92 static void start_int_poll_timer(struct controller *ctrl, int sec)
94 /* Clamp to sane value */
95 if ((sec <= 0) || (sec > 60))
98 ctrl->poll_timer.function = &int_poll_timeout;
99 ctrl->poll_timer.data = (unsigned long)ctrl;
100 ctrl->poll_timer.expires = jiffies + sec * HZ;
101 add_timer(&ctrl->poll_timer);
104 static inline int pciehp_request_irq(struct controller *ctrl)
106 int retval, irq = ctrl->pcie->irq;
108 /* Install interrupt polling timer. Start with 10 sec delay */
109 if (pciehp_poll_mode) {
110 init_timer(&ctrl->poll_timer);
111 start_int_poll_timer(ctrl, 10);
115 /* Installs the interrupt handler */
116 retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl);
118 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n",
123 static inline void pciehp_free_irq(struct controller *ctrl)
125 if (pciehp_poll_mode)
126 del_timer_sync(&ctrl->poll_timer);
128 free_irq(ctrl->pcie->irq, ctrl);
131 static int pcie_poll_cmd(struct controller *ctrl)
134 int err, timeout = 1000;
136 err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
137 if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) {
138 pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC);
141 while (timeout > 0) {
144 err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
145 if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) {
146 pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC);
150 return 0; /* timeout */
153 static void pcie_wait_cmd(struct controller *ctrl, int poll)
155 unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
156 unsigned long timeout = msecs_to_jiffies(msecs);
160 rc = pcie_poll_cmd(ctrl);
162 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
164 ctrl_dbg(ctrl, "Command not completed in 1000 msec\n");
168 * pcie_write_cmd - Issue controller command
169 * @ctrl: controller to which the command is issued
170 * @cmd: command value written to slot control register
171 * @mask: bitmask of slot control register to be modified
173 static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
179 mutex_lock(&ctrl->ctrl_lock);
181 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
183 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
188 if (slot_status & PCI_EXP_SLTSTA_CC) {
189 if (!ctrl->no_cmd_complete) {
191 * After 1 sec and CMD_COMPLETED still not set, just
192 * proceed forward to issue the next command according
193 * to spec. Just print out the error message.
195 ctrl_dbg(ctrl, "CMD_COMPLETED not clear after 1 sec\n");
196 } else if (!NO_CMD_CMPL(ctrl)) {
198 * This controller semms to notify of command completed
199 * event even though it supports none of power
200 * controller, attention led, power led and EMI.
202 ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Need to "
203 "wait for command completed event.\n");
204 ctrl->no_cmd_complete = 0;
206 ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Maybe "
207 "the controller is broken.\n");
211 retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl);
213 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
218 slot_ctrl |= (cmd & mask);
221 retval = pciehp_writew(ctrl, PCI_EXP_SLTCTL, slot_ctrl);
223 ctrl_err(ctrl, "Cannot write to SLOTCTRL register\n");
226 * Wait for command completion.
228 if (!retval && !ctrl->no_cmd_complete) {
231 * if hotplug interrupt is not enabled or command
232 * completed interrupt is not enabled, we need to poll
233 * command completed event.
235 if (!(slot_ctrl & PCI_EXP_SLTCTL_HPIE) ||
236 !(slot_ctrl & PCI_EXP_SLTCTL_CCIE))
238 pcie_wait_cmd(ctrl, poll);
241 mutex_unlock(&ctrl->ctrl_lock);
245 static inline int check_link_active(struct controller *ctrl)
249 if (pciehp_readw(ctrl, PCI_EXP_LNKSTA, &link_status))
251 return !!(link_status & PCI_EXP_LNKSTA_DLLLA);
254 static void pcie_wait_link_active(struct controller *ctrl)
258 if (check_link_active(ctrl))
260 while (timeout > 0) {
263 if (check_link_active(ctrl))
266 ctrl_dbg(ctrl, "Data Link Layer Link Active not set in 1000 msec\n");
269 int pciehp_check_link_status(struct controller *ctrl)
275 * Data Link Layer Link Active Reporting must be capable for
276 * hot-plug capable downstream port. But old controller might
277 * not implement it. In this case, we wait for 1000 ms.
279 if (ctrl->link_active_reporting){
280 /* Wait for Data Link Layer Link Active bit to be set */
281 pcie_wait_link_active(ctrl);
283 * We must wait for 100 ms after the Data Link Layer
284 * Link Active bit reads 1b before initiating a
285 * configuration access to the hot added device.
291 retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
293 ctrl_err(ctrl, "Cannot read LNKSTATUS register\n");
297 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
298 if ((lnk_status & PCI_EXP_LNKSTA_LT) ||
299 !(lnk_status & PCI_EXP_LNKSTA_NLW)) {
300 ctrl_err(ctrl, "Link Training Error occurs \n");
308 int pciehp_get_attention_status(struct slot *slot, u8 *status)
310 struct controller *ctrl = slot->ctrl;
315 retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl);
317 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
321 ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__,
322 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
324 atten_led_state = (slot_ctrl & PCI_EXP_SLTCTL_AIC) >> 6;
326 switch (atten_led_state) {
328 *status = 0xFF; /* Reserved */
331 *status = 1; /* On */
334 *status = 2; /* Blink */
337 *status = 0; /* Off */
347 int pciehp_get_power_status(struct slot *slot, u8 *status)
349 struct controller *ctrl = slot->ctrl;
354 retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl);
356 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
359 ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__,
360 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
362 pwr_state = (slot_ctrl & PCI_EXP_SLTCTL_PCC) >> 10;
379 int pciehp_get_latch_status(struct slot *slot, u8 *status)
381 struct controller *ctrl = slot->ctrl;
385 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
387 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
391 *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS);
395 int pciehp_get_adapter_status(struct slot *slot, u8 *status)
397 struct controller *ctrl = slot->ctrl;
401 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
403 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
407 *status = !!(slot_status & PCI_EXP_SLTSTA_PDS);
411 int pciehp_query_power_fault(struct slot *slot)
413 struct controller *ctrl = slot->ctrl;
417 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
419 ctrl_err(ctrl, "Cannot check for power fault\n");
422 return !!(slot_status & PCI_EXP_SLTSTA_PFD);
425 int pciehp_set_attention_status(struct slot *slot, u8 value)
427 struct controller *ctrl = slot->ctrl;
431 cmd_mask = PCI_EXP_SLTCTL_AIC;
433 case 0 : /* turn off */
436 case 1: /* turn on */
439 case 2: /* turn blink */
445 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
446 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
447 return pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
450 void pciehp_green_led_on(struct slot *slot)
452 struct controller *ctrl = slot->ctrl;
457 cmd_mask = PCI_EXP_SLTCTL_PIC;
458 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
459 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
460 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
463 void pciehp_green_led_off(struct slot *slot)
465 struct controller *ctrl = slot->ctrl;
470 cmd_mask = PCI_EXP_SLTCTL_PIC;
471 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
472 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
473 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
476 void pciehp_green_led_blink(struct slot *slot)
478 struct controller *ctrl = slot->ctrl;
483 cmd_mask = PCI_EXP_SLTCTL_PIC;
484 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
485 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
486 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
489 int pciehp_power_on_slot(struct slot * slot)
491 struct controller *ctrl = slot->ctrl;
497 /* Clear sticky power-fault bit from previous power failures */
498 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
500 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
504 slot_status &= PCI_EXP_SLTSTA_PFD;
506 retval = pciehp_writew(ctrl, PCI_EXP_SLTSTA, slot_status);
509 "%s: Cannot write to SLOTSTATUS register\n",
514 ctrl->power_fault_detected = 0;
517 cmd_mask = PCI_EXP_SLTCTL_PCC;
518 retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
520 ctrl_err(ctrl, "Write %x command failed!\n", slot_cmd);
523 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
524 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
529 int pciehp_power_off_slot(struct slot * slot)
531 struct controller *ctrl = slot->ctrl;
536 slot_cmd = POWER_OFF;
537 cmd_mask = PCI_EXP_SLTCTL_PCC;
538 retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
540 ctrl_err(ctrl, "Write command failed!\n");
543 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
544 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
548 static irqreturn_t pcie_isr(int irq, void *dev_id)
550 struct controller *ctrl = (struct controller *)dev_id;
551 struct slot *slot = ctrl->slot;
552 u16 detected, intr_loc;
555 * In order to guarantee that all interrupt events are
556 * serviced, we need to re-inspect Slot Status register after
557 * clearing what is presumed to be the last pending interrupt.
561 if (pciehp_readw(ctrl, PCI_EXP_SLTSTA, &detected)) {
562 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS\n",
567 detected &= (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
568 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
570 detected &= ~intr_loc;
571 intr_loc |= detected;
574 if (detected && pciehp_writew(ctrl, PCI_EXP_SLTSTA, intr_loc)) {
575 ctrl_err(ctrl, "%s: Cannot write to SLOTSTATUS\n",
581 ctrl_dbg(ctrl, "%s: intr_loc %x\n", __func__, intr_loc);
583 /* Check Command Complete Interrupt Pending */
584 if (intr_loc & PCI_EXP_SLTSTA_CC) {
587 wake_up(&ctrl->queue);
590 if (!(intr_loc & ~PCI_EXP_SLTSTA_CC))
593 /* Check MRL Sensor Changed */
594 if (intr_loc & PCI_EXP_SLTSTA_MRLSC)
595 pciehp_handle_switch_change(slot);
597 /* Check Attention Button Pressed */
598 if (intr_loc & PCI_EXP_SLTSTA_ABP)
599 pciehp_handle_attention_button(slot);
601 /* Check Presence Detect Changed */
602 if (intr_loc & PCI_EXP_SLTSTA_PDC)
603 pciehp_handle_presence_change(slot);
605 /* Check Power Fault Detected */
606 if ((intr_loc & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) {
607 ctrl->power_fault_detected = 1;
608 pciehp_handle_power_fault(slot);
613 int pciehp_get_max_link_speed(struct slot *slot, enum pci_bus_speed *value)
615 struct controller *ctrl = slot->ctrl;
616 enum pcie_link_speed lnk_speed;
620 retval = pciehp_readl(ctrl, PCI_EXP_LNKCAP, &lnk_cap);
622 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__);
626 switch (lnk_cap & 0x000F) {
628 lnk_speed = PCIE_2_5GB;
631 lnk_speed = PCIE_5_0GB;
634 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
639 ctrl_dbg(ctrl, "Max link speed = %d\n", lnk_speed);
644 int pciehp_get_max_lnk_width(struct slot *slot,
645 enum pcie_link_width *value)
647 struct controller *ctrl = slot->ctrl;
648 enum pcie_link_width lnk_wdth;
652 retval = pciehp_readl(ctrl, PCI_EXP_LNKCAP, &lnk_cap);
654 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__);
658 switch ((lnk_cap & PCI_EXP_LNKSTA_NLW) >> 4){
660 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
663 lnk_wdth = PCIE_LNK_X1;
666 lnk_wdth = PCIE_LNK_X2;
669 lnk_wdth = PCIE_LNK_X4;
672 lnk_wdth = PCIE_LNK_X8;
675 lnk_wdth = PCIE_LNK_X12;
678 lnk_wdth = PCIE_LNK_X16;
681 lnk_wdth = PCIE_LNK_X32;
684 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
689 ctrl_dbg(ctrl, "Max link width = %d\n", lnk_wdth);
694 int pciehp_get_cur_link_speed(struct slot *slot, enum pci_bus_speed *value)
696 struct controller *ctrl = slot->ctrl;
697 enum pcie_link_speed lnk_speed = PCI_SPEED_UNKNOWN;
701 retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
703 ctrl_err(ctrl, "%s: Cannot read LNKSTATUS register\n",
708 switch (lnk_status & PCI_EXP_LNKSTA_CLS) {
710 lnk_speed = PCIE_2_5GB;
713 lnk_speed = PCIE_5_0GB;
716 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
721 ctrl_dbg(ctrl, "Current link speed = %d\n", lnk_speed);
726 int pciehp_get_cur_lnk_width(struct slot *slot,
727 enum pcie_link_width *value)
729 struct controller *ctrl = slot->ctrl;
730 enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
734 retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
736 ctrl_err(ctrl, "%s: Cannot read LNKSTATUS register\n",
741 switch ((lnk_status & PCI_EXP_LNKSTA_NLW) >> 4){
743 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
746 lnk_wdth = PCIE_LNK_X1;
749 lnk_wdth = PCIE_LNK_X2;
752 lnk_wdth = PCIE_LNK_X4;
755 lnk_wdth = PCIE_LNK_X8;
758 lnk_wdth = PCIE_LNK_X12;
761 lnk_wdth = PCIE_LNK_X16;
764 lnk_wdth = PCIE_LNK_X32;
767 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
772 ctrl_dbg(ctrl, "Current link width = %d\n", lnk_wdth);
777 int pcie_enable_notification(struct controller *ctrl)
782 * TBD: Power fault detected software notification support.
784 * Power fault detected software notification is not enabled
785 * now, because it caused power fault detected interrupt storm
786 * on some machines. On those machines, power fault detected
787 * bit in the slot status register was set again immediately
788 * when it is cleared in the interrupt service routine, and
789 * next power fault detected interrupt was notified again.
791 cmd = PCI_EXP_SLTCTL_PDCE;
792 if (ATTN_BUTTN(ctrl))
793 cmd |= PCI_EXP_SLTCTL_ABPE;
795 cmd |= PCI_EXP_SLTCTL_MRLSCE;
796 if (!pciehp_poll_mode)
797 cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE;
799 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
800 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
801 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE);
803 if (pcie_write_cmd(ctrl, cmd, mask)) {
804 ctrl_err(ctrl, "Cannot enable software notification\n");
810 static void pcie_disable_notification(struct controller *ctrl)
813 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
814 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
815 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
816 PCI_EXP_SLTCTL_DLLSCE);
817 if (pcie_write_cmd(ctrl, 0, mask))
818 ctrl_warn(ctrl, "Cannot disable software notification\n");
821 int pcie_init_notification(struct controller *ctrl)
823 if (pciehp_request_irq(ctrl))
825 if (pcie_enable_notification(ctrl)) {
826 pciehp_free_irq(ctrl);
829 ctrl->notification_enabled = 1;
833 static void pcie_shutdown_notification(struct controller *ctrl)
835 if (ctrl->notification_enabled) {
836 pcie_disable_notification(ctrl);
837 pciehp_free_irq(ctrl);
838 ctrl->notification_enabled = 0;
842 static int pcie_init_slot(struct controller *ctrl)
846 slot = kzalloc(sizeof(*slot), GFP_KERNEL);
851 mutex_init(&slot->lock);
852 INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work);
857 static void pcie_cleanup_slot(struct controller *ctrl)
859 struct slot *slot = ctrl->slot;
860 cancel_delayed_work(&slot->work);
861 flush_scheduled_work();
862 flush_workqueue(pciehp_wq);
866 static inline void dbg_ctrl(struct controller *ctrl)
870 struct pci_dev *pdev = ctrl->pcie->port;
875 ctrl_info(ctrl, "Hotplug Controller:\n");
876 ctrl_info(ctrl, " Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n",
877 pci_name(pdev), pdev->irq);
878 ctrl_info(ctrl, " Vendor ID : 0x%04x\n", pdev->vendor);
879 ctrl_info(ctrl, " Device ID : 0x%04x\n", pdev->device);
880 ctrl_info(ctrl, " Subsystem ID : 0x%04x\n",
881 pdev->subsystem_device);
882 ctrl_info(ctrl, " Subsystem Vendor ID : 0x%04x\n",
883 pdev->subsystem_vendor);
884 ctrl_info(ctrl, " PCIe Cap offset : 0x%02x\n",
886 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
887 if (!pci_resource_len(pdev, i))
889 ctrl_info(ctrl, " PCI resource [%d] : 0x%llx@0x%llx\n",
890 i, (unsigned long long)pci_resource_len(pdev, i),
891 (unsigned long long)pci_resource_start(pdev, i));
893 ctrl_info(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap);
894 ctrl_info(ctrl, " Physical Slot Number : %d\n", PSN(ctrl));
895 ctrl_info(ctrl, " Attention Button : %3s\n",
896 ATTN_BUTTN(ctrl) ? "yes" : "no");
897 ctrl_info(ctrl, " Power Controller : %3s\n",
898 POWER_CTRL(ctrl) ? "yes" : "no");
899 ctrl_info(ctrl, " MRL Sensor : %3s\n",
900 MRL_SENS(ctrl) ? "yes" : "no");
901 ctrl_info(ctrl, " Attention Indicator : %3s\n",
902 ATTN_LED(ctrl) ? "yes" : "no");
903 ctrl_info(ctrl, " Power Indicator : %3s\n",
904 PWR_LED(ctrl) ? "yes" : "no");
905 ctrl_info(ctrl, " Hot-Plug Surprise : %3s\n",
906 HP_SUPR_RM(ctrl) ? "yes" : "no");
907 ctrl_info(ctrl, " EMI Present : %3s\n",
908 EMI(ctrl) ? "yes" : "no");
909 ctrl_info(ctrl, " Command Completed : %3s\n",
910 NO_CMD_CMPL(ctrl) ? "no" : "yes");
911 pciehp_readw(ctrl, PCI_EXP_SLTSTA, ®16);
912 ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16);
913 pciehp_readw(ctrl, PCI_EXP_SLTCTL, ®16);
914 ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16);
917 struct controller *pcie_init(struct pcie_device *dev)
919 struct controller *ctrl;
920 u32 slot_cap, link_cap;
921 struct pci_dev *pdev = dev->port;
923 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
925 dev_err(&dev->device, "%s: Out of memory\n", __func__);
929 if (!pci_pcie_cap(pdev)) {
930 ctrl_err(ctrl, "Cannot find PCI Express capability\n");
933 if (pciehp_readl(ctrl, PCI_EXP_SLTCAP, &slot_cap)) {
934 ctrl_err(ctrl, "Cannot read SLOTCAP register\n");
938 ctrl->slot_cap = slot_cap;
939 mutex_init(&ctrl->ctrl_lock);
940 init_waitqueue_head(&ctrl->queue);
943 * Controller doesn't notify of command completion if the "No
944 * Command Completed Support" bit is set in Slot Capability
945 * register or the controller supports none of power
946 * controller, attention led, power led and EMI.
948 if (NO_CMD_CMPL(ctrl) ||
949 !(POWER_CTRL(ctrl) | ATTN_LED(ctrl) | PWR_LED(ctrl) | EMI(ctrl)))
950 ctrl->no_cmd_complete = 1;
952 /* Check if Data Link Layer Link Active Reporting is implemented */
953 if (pciehp_readl(ctrl, PCI_EXP_LNKCAP, &link_cap)) {
954 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__);
957 if (link_cap & PCI_EXP_LNKCAP_DLLLARC) {
958 ctrl_dbg(ctrl, "Link Active Reporting supported\n");
959 ctrl->link_active_reporting = 1;
962 /* Clear all remaining event bits in Slot Status register */
963 if (pciehp_writew(ctrl, PCI_EXP_SLTSTA, 0x1f))
966 /* Disable sotfware notification */
967 pcie_disable_notification(ctrl);
970 * If this is the first controller to be initialized,
971 * initialize the pciehp work queue
973 if (atomic_add_return(1, &pciehp_num_controllers) == 1) {
974 pciehp_wq = create_singlethread_workqueue("pciehpd");
979 ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n",
980 pdev->vendor, pdev->device, pdev->subsystem_vendor,
981 pdev->subsystem_device);
983 if (pcie_init_slot(ctrl))
994 void pciehp_release_ctrl(struct controller *ctrl)
996 pcie_shutdown_notification(ctrl);
997 pcie_cleanup_slot(ctrl);
999 * If this is the last controller to be released, destroy the
1002 if (atomic_dec_and_test(&pciehp_num_controllers))
1003 destroy_workqueue(pciehp_wq);