2 * PCI Express PCI Hot Plug Driver
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/types.h>
33 #include <linux/signal.h>
34 #include <linux/jiffies.h>
35 #include <linux/timer.h>
36 #include <linux/pci.h>
37 #include <linux/interrupt.h>
42 #define DBG_K_TRACE_ENTRY ((unsigned int)0x00000001) /* On function entry */
43 #define DBG_K_TRACE_EXIT ((unsigned int)0x00000002) /* On function exit */
44 #define DBG_K_INFO ((unsigned int)0x00000004) /* Info messages */
45 #define DBG_K_ERROR ((unsigned int)0x00000008) /* Error messages */
46 #define DBG_K_TRACE (DBG_K_TRACE_ENTRY|DBG_K_TRACE_EXIT)
47 #define DBG_K_STANDARD (DBG_K_INFO|DBG_K_ERROR|DBG_K_TRACE)
48 /* Redefine this flagword to set debug level */
49 #define DEBUG_LEVEL DBG_K_STANDARD
51 #define DEFINE_DBG_BUFFER char __dbg_str_buf[256];
53 #define DBG_PRINT( dbg_flags, args... ) \
55 if ( DEBUG_LEVEL & ( dbg_flags ) ) \
58 len = sprintf( __dbg_str_buf, "%s:%d: %s: ", \
59 __FILE__, __LINE__, __FUNCTION__ ); \
60 sprintf( __dbg_str_buf + len, args ); \
61 printk( KERN_NOTICE "%s\n", __dbg_str_buf ); \
65 #define DBG_ENTER_ROUTINE DBG_PRINT (DBG_K_TRACE_ENTRY, "%s", "[Entry]");
66 #define DBG_LEAVE_ROUTINE DBG_PRINT (DBG_K_TRACE_EXIT, "%s", "[Exit]");
68 #define DEFINE_DBG_BUFFER
69 #define DBG_ENTER_ROUTINE
70 #define DBG_LEAVE_ROUTINE
89 } __attribute__ ((packed));
91 /* offsets to the controller registers based on the above structure layout */
93 PCIECAPID = offsetof(struct ctrl_reg, cap_id),
94 NXTCAPPTR = offsetof(struct ctrl_reg, nxt_ptr),
95 CAPREG = offsetof(struct ctrl_reg, cap_reg),
96 DEVCAP = offsetof(struct ctrl_reg, dev_cap),
97 DEVCTRL = offsetof(struct ctrl_reg, dev_ctrl),
98 DEVSTATUS = offsetof(struct ctrl_reg, dev_status),
99 LNKCAP = offsetof(struct ctrl_reg, lnk_cap),
100 LNKCTRL = offsetof(struct ctrl_reg, lnk_ctrl),
101 LNKSTATUS = offsetof(struct ctrl_reg, lnk_status),
102 SLOTCAP = offsetof(struct ctrl_reg, slot_cap),
103 SLOTCTRL = offsetof(struct ctrl_reg, slot_ctrl),
104 SLOTSTATUS = offsetof(struct ctrl_reg, slot_status),
105 ROOTCTRL = offsetof(struct ctrl_reg, root_ctrl),
106 ROOTSTATUS = offsetof(struct ctrl_reg, root_status),
108 static int pcie_cap_base = 0; /* Base of the PCI Express capability item structure */
110 #define PCIE_CAP_ID(cb) ( cb + PCIECAPID )
111 #define NXT_CAP_PTR(cb) ( cb + NXTCAPPTR )
112 #define CAP_REG(cb) ( cb + CAPREG )
113 #define DEV_CAP(cb) ( cb + DEVCAP )
114 #define DEV_CTRL(cb) ( cb + DEVCTRL )
115 #define DEV_STATUS(cb) ( cb + DEVSTATUS )
116 #define LNK_CAP(cb) ( cb + LNKCAP )
117 #define LNK_CTRL(cb) ( cb + LNKCTRL )
118 #define LNK_STATUS(cb) ( cb + LNKSTATUS )
119 #define SLOT_CAP(cb) ( cb + SLOTCAP )
120 #define SLOT_CTRL(cb) ( cb + SLOTCTRL )
121 #define SLOT_STATUS(cb) ( cb + SLOTSTATUS )
122 #define ROOT_CTRL(cb) ( cb + ROOTCTRL )
123 #define ROOT_STATUS(cb) ( cb + ROOTSTATUS )
125 #define hp_register_read_word(pdev, reg , value) \
126 pci_read_config_word(pdev, reg, &value)
128 #define hp_register_read_dword(pdev, reg , value) \
129 pci_read_config_dword(pdev, reg, &value)
131 #define hp_register_write_word(pdev, reg , value) \
132 pci_write_config_word(pdev, reg, value)
134 #define hp_register_dwrite_word(pdev, reg , value) \
135 pci_write_config_dword(pdev, reg, value)
137 /* Field definitions in PCI Express Capabilities Register */
138 #define CAP_VER 0x000F
139 #define DEV_PORT_TYPE 0x00F0
140 #define SLOT_IMPL 0x0100
141 #define MSG_NUM 0x3E00
143 /* Device or Port Type */
144 #define NAT_ENDPT 0x00
145 #define LEG_ENDPT 0x01
146 #define ROOT_PORT 0x04
147 #define UP_STREAM 0x05
148 #define DN_STREAM 0x06
149 #define PCIE_PCI_BRDG 0x07
150 #define PCI_PCIE_BRDG 0x10
152 /* Field definitions in Device Capabilities Register */
153 #define DATTN_BUTTN_PRSN 0x1000
154 #define DATTN_LED_PRSN 0x2000
155 #define DPWR_LED_PRSN 0x4000
157 /* Field definitions in Link Capabilities Register */
158 #define MAX_LNK_SPEED 0x000F
159 #define MAX_LNK_WIDTH 0x03F0
161 /* Link Width Encoding */
170 /*Field definitions of Link Status Register */
171 #define LNK_SPEED 0x000F
172 #define NEG_LINK_WD 0x03F0
173 #define LNK_TRN_ERR 0x0400
174 #define LNK_TRN 0x0800
175 #define SLOT_CLK_CONF 0x1000
177 /* Field definitions in Slot Capabilities Register */
178 #define ATTN_BUTTN_PRSN 0x00000001
179 #define PWR_CTRL_PRSN 0x00000002
180 #define MRL_SENS_PRSN 0x00000004
181 #define ATTN_LED_PRSN 0x00000008
182 #define PWR_LED_PRSN 0x00000010
183 #define HP_SUPR_RM_SUP 0x00000020
184 #define HP_CAP 0x00000040
185 #define SLOT_PWR_VALUE 0x000003F8
186 #define SLOT_PWR_LIMIT 0x00000C00
187 #define PSN 0xFFF80000 /* PSN: Physical Slot Number */
189 /* Field definitions in Slot Control Register */
190 #define ATTN_BUTTN_ENABLE 0x0001
191 #define PWR_FAULT_DETECT_ENABLE 0x0002
192 #define MRL_DETECT_ENABLE 0x0004
193 #define PRSN_DETECT_ENABLE 0x0008
194 #define CMD_CMPL_INTR_ENABLE 0x0010
195 #define HP_INTR_ENABLE 0x0020
196 #define ATTN_LED_CTRL 0x00C0
197 #define PWR_LED_CTRL 0x0300
198 #define PWR_CTRL 0x0400
200 /* Attention indicator and Power indicator states */
202 #define LED_BLINK 0x10
205 /* Power Control Command */
207 #define POWER_OFF 0x0400
209 /* Field definitions in Slot Status Register */
210 #define ATTN_BUTTN_PRESSED 0x0001
211 #define PWR_FAULT_DETECTED 0x0002
212 #define MRL_SENS_CHANGED 0x0004
213 #define PRSN_DETECT_CHANGED 0x0008
214 #define CMD_COMPLETED 0x0010
215 #define MRL_STATE 0x0020
216 #define PRSN_STATE 0x0040
218 static spinlock_t hpc_event_lock;
220 DEFINE_DBG_BUFFER /* Debug string buffer for entire HPC defined here */
221 static int ctlr_seq_num = 0; /* Controller sequence # */
223 static irqreturn_t pcie_isr(int irq, void *dev_id);
224 static void start_int_poll_timer(struct controller *ctrl, int sec);
226 /* This is the interrupt polling timeout function. */
227 static void int_poll_timeout(unsigned long data)
229 struct controller *ctrl = (struct controller *)data;
233 /* Poll for interrupt events. regs == NULL => polling */
236 init_timer(&ctrl->poll_timer);
237 if (!pciehp_poll_time)
238 pciehp_poll_time = 2; /* reset timer to poll in 2 secs if user doesn't specify at module installation*/
240 start_int_poll_timer(ctrl, pciehp_poll_time);
243 /* This function starts the interrupt polling timer. */
244 static void start_int_poll_timer(struct controller *ctrl, int sec)
246 /* Clamp to sane value */
247 if ((sec <= 0) || (sec > 60))
250 ctrl->poll_timer.function = &int_poll_timeout;
251 ctrl->poll_timer.data = (unsigned long)ctrl;
252 ctrl->poll_timer.expires = jiffies + sec * HZ;
253 add_timer(&ctrl->poll_timer);
256 static int pcie_write_cmd(struct slot *slot, u16 cmd)
258 struct controller *ctrl = slot->ctrl;
264 retval = hp_register_read_word(ctrl->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
266 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
270 if ((slot_status & CMD_COMPLETED) == CMD_COMPLETED ) {
271 /* After 1 sec and CMD_COMPLETED still not set, just proceed forward to issue
272 the next command according to spec. Just print out the error message */
273 dbg("%s : CMD_COMPLETED not clear after 1 sec.\n", __FUNCTION__);
276 retval = hp_register_write_word(ctrl->pci_dev, SLOT_CTRL(slot->ctrl->cap_base), cmd | CMD_CMPL_INTR_ENABLE);
278 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
286 static int hpc_check_lnk_status(struct controller *ctrl)
293 retval = hp_register_read_word(ctrl->pci_dev, LNK_STATUS(ctrl->cap_base), lnk_status);
295 err("%s : hp_register_read_word LNK_STATUS failed\n", __FUNCTION__);
299 dbg("%s: lnk_status = %x\n", __FUNCTION__, lnk_status);
300 if ( (lnk_status & LNK_TRN) || (lnk_status & LNK_TRN_ERR) ||
301 !(lnk_status & NEG_LINK_WD)) {
302 err("%s : Link Training Error occurs \n", __FUNCTION__);
312 static int hpc_get_attention_status(struct slot *slot, u8 *status)
314 struct controller *ctrl = slot->ctrl;
321 retval = hp_register_read_word(ctrl->pci_dev, SLOT_CTRL(ctrl->cap_base), slot_ctrl);
323 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
327 dbg("%s: SLOT_CTRL %x, value read %x\n", __FUNCTION__,SLOT_CTRL(slot->ctrl->cap_base), slot_ctrl);
329 atten_led_state = (slot_ctrl & ATTN_LED_CTRL) >> 6;
331 switch (atten_led_state) {
333 *status = 0xFF; /* Reserved */
336 *status = 1; /* On */
339 *status = 2; /* Blink */
342 *status = 0; /* Off */
353 static int hpc_get_power_status(struct slot *slot, u8 *status)
355 struct controller *ctrl = slot->ctrl;
362 retval = hp_register_read_word(ctrl->pci_dev, SLOT_CTRL(ctrl->cap_base), slot_ctrl);
364 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
367 dbg("%s: SLOT_CTRL %x value read %x\n", __FUNCTION__, SLOT_CTRL(ctrl->cap_base), slot_ctrl);
369 pwr_state = (slot_ctrl & PWR_CTRL) >> 10;
388 static int hpc_get_latch_status(struct slot *slot, u8 *status)
390 struct controller *ctrl = slot->ctrl;
396 retval = hp_register_read_word(ctrl->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
398 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
402 *status = (((slot_status & MRL_STATE) >> 5) == 0) ? 0 : 1;
408 static int hpc_get_adapter_status(struct slot *slot, u8 *status)
410 struct controller *ctrl = slot->ctrl;
417 retval = hp_register_read_word(ctrl->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
419 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
422 card_state = (u8)((slot_status & PRSN_STATE) >> 6);
423 *status = (card_state == 1) ? 1 : 0;
429 static int hpc_query_power_fault(struct slot *slot)
431 struct controller *ctrl = slot->ctrl;
438 retval = hp_register_read_word(ctrl->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
440 err("%s : Cannot check for power fault\n", __FUNCTION__);
443 pwr_fault = (u8)((slot_status & PWR_FAULT_DETECTED) >> 1);
449 static int hpc_set_attention_status(struct slot *slot, u8 value)
451 struct controller *ctrl = slot->ctrl;
458 rc = hp_register_read_word(ctrl->pci_dev, SLOT_CTRL(ctrl->cap_base), slot_ctrl);
460 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
465 case 0 : /* turn off */
466 slot_cmd = (slot_ctrl & ~ATTN_LED_CTRL) | 0x00C0;
468 case 1: /* turn on */
469 slot_cmd = (slot_ctrl & ~ATTN_LED_CTRL) | 0x0040;
471 case 2: /* turn blink */
472 slot_cmd = (slot_ctrl & ~ATTN_LED_CTRL) | 0x0080;
477 if (!pciehp_poll_mode)
478 slot_cmd = slot_cmd | HP_INTR_ENABLE;
480 pcie_write_cmd(slot, slot_cmd);
481 dbg("%s: SLOT_CTRL %x write cmd %x\n", __FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd);
488 static void hpc_set_green_led_on(struct slot *slot)
490 struct controller *ctrl = slot->ctrl;
497 rc = hp_register_read_word(ctrl->pci_dev, SLOT_CTRL(ctrl->cap_base), slot_ctrl);
499 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
502 slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0100;
503 if (!pciehp_poll_mode)
504 slot_cmd = slot_cmd | HP_INTR_ENABLE;
506 pcie_write_cmd(slot, slot_cmd);
508 dbg("%s: SLOT_CTRL %x write cmd %x\n",__FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd);
513 static void hpc_set_green_led_off(struct slot *slot)
515 struct controller *ctrl = slot->ctrl;
522 rc = hp_register_read_word(ctrl->pci_dev, SLOT_CTRL(ctrl->cap_base), slot_ctrl);
524 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
528 slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0300;
530 if (!pciehp_poll_mode)
531 slot_cmd = slot_cmd | HP_INTR_ENABLE;
532 pcie_write_cmd(slot, slot_cmd);
533 dbg("%s: SLOT_CTRL %x write cmd %x\n", __FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd);
539 static void hpc_set_green_led_blink(struct slot *slot)
541 struct controller *ctrl = slot->ctrl;
548 rc = hp_register_read_word(ctrl->pci_dev, SLOT_CTRL(ctrl->cap_base), slot_ctrl);
550 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
554 slot_cmd = (slot_ctrl & ~PWR_LED_CTRL) | 0x0200;
556 if (!pciehp_poll_mode)
557 slot_cmd = slot_cmd | HP_INTR_ENABLE;
558 pcie_write_cmd(slot, slot_cmd);
560 dbg("%s: SLOT_CTRL %x write cmd %x\n",__FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd);
565 static void hpc_release_ctlr(struct controller *ctrl)
569 if (pciehp_poll_mode)
570 del_timer(&ctrl->poll_timer);
572 free_irq(ctrl->pci_dev->irq, ctrl);
577 static int hpc_power_on_slot(struct slot * slot)
579 struct controller *ctrl = slot->ctrl;
581 u16 slot_ctrl, slot_status;
586 dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot);
588 /* Clear sticky power-fault bit from previous power failures */
589 hp_register_read_word(ctrl->pci_dev,
590 SLOT_STATUS(ctrl->cap_base), slot_status);
591 slot_status &= PWR_FAULT_DETECTED;
593 hp_register_write_word(ctrl->pci_dev,
594 SLOT_STATUS(ctrl->cap_base), slot_status);
596 retval = hp_register_read_word(ctrl->pci_dev,
597 SLOT_CTRL(ctrl->cap_base), slot_ctrl);
599 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
603 slot_cmd = (slot_ctrl & ~PWR_CTRL) | POWER_ON;
605 /* Enable detection that we turned off at slot power-off time */
606 if (!pciehp_poll_mode)
607 slot_cmd = slot_cmd |
608 PWR_FAULT_DETECT_ENABLE |
613 retval = pcie_write_cmd(slot, slot_cmd);
616 err("%s: Write %x command failed!\n", __FUNCTION__, slot_cmd);
619 dbg("%s: SLOT_CTRL %x write cmd %x\n",__FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd);
626 static int hpc_power_off_slot(struct slot * slot)
628 struct controller *ctrl = slot->ctrl;
635 dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot);
637 retval = hp_register_read_word(ctrl->pci_dev, SLOT_CTRL(ctrl->cap_base), slot_ctrl);
639 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
643 slot_cmd = (slot_ctrl & ~PWR_CTRL) | POWER_OFF;
646 * If we get MRL or presence detect interrupts now, the isr
647 * will notice the sticky power-fault bit too and issue power
648 * indicator change commands. This will lead to an endless loop
649 * of command completions, since the power-fault bit remains on
650 * till the slot is powered on again.
652 if (!pciehp_poll_mode)
653 slot_cmd = (slot_cmd &
654 ~PWR_FAULT_DETECT_ENABLE &
656 ~PRSN_DETECT_ENABLE) | HP_INTR_ENABLE;
658 retval = pcie_write_cmd(slot, slot_cmd);
661 err("%s: Write command failed!\n", __FUNCTION__);
664 dbg("%s: SLOT_CTRL %x write cmd %x\n",__FUNCTION__, SLOT_CTRL(slot->ctrl->cap_base), slot_cmd);
671 static irqreturn_t pcie_isr(int irq, void *dev_id)
673 struct controller *ctrl = (struct controller *)dev_id;
674 u16 slot_status, intr_detect, intr_loc;
676 int hp_slot = 0; /* only 1 slot per PCI Express port */
679 rc = hp_register_read_word(ctrl->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
681 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
685 intr_detect = ( ATTN_BUTTN_PRESSED | PWR_FAULT_DETECTED | MRL_SENS_CHANGED |
686 PRSN_DETECT_CHANGED | CMD_COMPLETED );
688 intr_loc = slot_status & intr_detect;
690 /* Check to see if it was our interrupt */
694 dbg("%s: intr_loc %x\n", __FUNCTION__, intr_loc);
695 /* Mask Hot-plug Interrupt Enable */
696 if (!pciehp_poll_mode) {
697 rc = hp_register_read_word(ctrl->pci_dev, SLOT_CTRL(ctrl->cap_base), temp_word);
699 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
703 dbg("%s: hp_register_read_word SLOT_CTRL with value %x\n", __FUNCTION__, temp_word);
704 temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) | 0x00;
706 rc = hp_register_write_word(ctrl->pci_dev, SLOT_CTRL(ctrl->cap_base), temp_word);
708 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
712 rc = hp_register_read_word(ctrl->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
714 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
717 dbg("%s: hp_register_read_word SLOT_STATUS with value %x\n", __FUNCTION__, slot_status);
719 /* Clear command complete interrupt caused by this write */
721 rc = hp_register_write_word(ctrl->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word);
723 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
728 if (intr_loc & CMD_COMPLETED) {
730 * Command Complete Interrupt Pending
732 wake_up_interruptible(&ctrl->queue);
735 if (intr_loc & MRL_SENS_CHANGED)
736 pciehp_handle_switch_change(hp_slot, ctrl);
738 if (intr_loc & ATTN_BUTTN_PRESSED)
739 pciehp_handle_attention_button(hp_slot, ctrl);
741 if (intr_loc & PRSN_DETECT_CHANGED)
742 pciehp_handle_presence_change(hp_slot, ctrl);
744 if (intr_loc & PWR_FAULT_DETECTED)
745 pciehp_handle_power_fault(hp_slot, ctrl);
747 /* Clear all events after serving them */
749 rc = hp_register_write_word(ctrl->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word);
751 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
754 /* Unmask Hot-plug Interrupt Enable */
755 if (!pciehp_poll_mode) {
756 rc = hp_register_read_word(ctrl->pci_dev, SLOT_CTRL(ctrl->cap_base), temp_word);
758 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
762 dbg("%s: Unmask Hot-plug Interrupt Enable\n", __FUNCTION__);
763 temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE;
765 rc = hp_register_write_word(ctrl->pci_dev, SLOT_CTRL(ctrl->cap_base), temp_word);
767 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
771 rc = hp_register_read_word(ctrl->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
773 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
777 /* Clear command complete interrupt caused by this write */
779 rc = hp_register_write_word(ctrl->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word);
781 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
784 dbg("%s: hp_register_write_word SLOT_STATUS with value %x\n", __FUNCTION__, temp_word);
790 static int hpc_get_max_lnk_speed (struct slot *slot, enum pci_bus_speed *value)
792 struct controller *ctrl = slot->ctrl;
793 enum pcie_link_speed lnk_speed;
799 retval = hp_register_read_dword(ctrl->pci_dev, LNK_CAP(ctrl->cap_base), lnk_cap);
801 err("%s : hp_register_read_dword LNK_CAP failed\n", __FUNCTION__);
805 switch (lnk_cap & 0x000F) {
807 lnk_speed = PCIE_2PT5GB;
810 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
815 dbg("Max link speed = %d\n", lnk_speed);
820 static int hpc_get_max_lnk_width (struct slot *slot, enum pcie_link_width *value)
822 struct controller *ctrl = slot->ctrl;
823 enum pcie_link_width lnk_wdth;
829 retval = hp_register_read_dword(ctrl->pci_dev, LNK_CAP(ctrl->cap_base), lnk_cap);
831 err("%s : hp_register_read_dword LNK_CAP failed\n", __FUNCTION__);
835 switch ((lnk_cap & 0x03F0) >> 4){
837 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
840 lnk_wdth = PCIE_LNK_X1;
843 lnk_wdth = PCIE_LNK_X2;
846 lnk_wdth = PCIE_LNK_X4;
849 lnk_wdth = PCIE_LNK_X8;
852 lnk_wdth = PCIE_LNK_X12;
855 lnk_wdth = PCIE_LNK_X16;
858 lnk_wdth = PCIE_LNK_X32;
861 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
866 dbg("Max link width = %d\n", lnk_wdth);
871 static int hpc_get_cur_lnk_speed (struct slot *slot, enum pci_bus_speed *value)
873 struct controller *ctrl = slot->ctrl;
874 enum pcie_link_speed lnk_speed = PCI_SPEED_UNKNOWN;
880 retval = hp_register_read_word(ctrl->pci_dev, LNK_STATUS(ctrl->cap_base), lnk_status);
882 err("%s : hp_register_read_word LNK_STATUS failed\n", __FUNCTION__);
886 switch (lnk_status & 0x0F) {
888 lnk_speed = PCIE_2PT5GB;
891 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
896 dbg("Current link speed = %d\n", lnk_speed);
901 static int hpc_get_cur_lnk_width (struct slot *slot, enum pcie_link_width *value)
903 struct controller *ctrl = slot->ctrl;
904 enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
910 retval = hp_register_read_word(ctrl->pci_dev, LNK_STATUS(ctrl->cap_base), lnk_status);
912 err("%s : hp_register_read_word LNK_STATUS failed\n", __FUNCTION__);
916 switch ((lnk_status & 0x03F0) >> 4){
918 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
921 lnk_wdth = PCIE_LNK_X1;
924 lnk_wdth = PCIE_LNK_X2;
927 lnk_wdth = PCIE_LNK_X4;
930 lnk_wdth = PCIE_LNK_X8;
933 lnk_wdth = PCIE_LNK_X12;
936 lnk_wdth = PCIE_LNK_X16;
939 lnk_wdth = PCIE_LNK_X32;
942 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
947 dbg("Current link width = %d\n", lnk_wdth);
952 static struct hpc_ops pciehp_hpc_ops = {
953 .power_on_slot = hpc_power_on_slot,
954 .power_off_slot = hpc_power_off_slot,
955 .set_attention_status = hpc_set_attention_status,
956 .get_power_status = hpc_get_power_status,
957 .get_attention_status = hpc_get_attention_status,
958 .get_latch_status = hpc_get_latch_status,
959 .get_adapter_status = hpc_get_adapter_status,
961 .get_max_bus_speed = hpc_get_max_lnk_speed,
962 .get_cur_bus_speed = hpc_get_cur_lnk_speed,
963 .get_max_lnk_width = hpc_get_max_lnk_width,
964 .get_cur_lnk_width = hpc_get_cur_lnk_width,
966 .query_power_fault = hpc_query_power_fault,
967 .green_led_on = hpc_set_green_led_on,
968 .green_led_off = hpc_set_green_led_off,
969 .green_led_blink = hpc_set_green_led_blink,
971 .release_ctlr = hpc_release_ctlr,
972 .check_lnk_status = hpc_check_lnk_status,
976 int pciehp_acpi_get_hp_hw_control_from_firmware(struct pci_dev *dev)
979 acpi_handle chandle, handle = DEVICE_ACPI_HANDLE(&(dev->dev));
980 struct pci_dev *pdev = dev;
981 struct pci_bus *parent;
982 struct acpi_buffer string = { ACPI_ALLOCATE_BUFFER, NULL };
985 * Per PCI firmware specification, we should run the ACPI _OSC
986 * method to get control of hotplug hardware before using it.
987 * If an _OSC is missing, we look for an OSHP to do the same thing.
988 * To handle different BIOS behavior, we look for _OSC and OSHP
989 * within the scope of the hotplug controller and its parents, upto
990 * the host bridge under which this controller exists.
994 * This hotplug controller was not listed in the ACPI name
995 * space at all. Try to get acpi handle of parent pci bus.
997 if (!pdev || !pdev->bus->parent)
999 parent = pdev->bus->parent;
1000 dbg("Could not find %s in acpi namespace, trying parent\n",
1003 /* Parent must be a host bridge */
1004 handle = acpi_get_pci_rootbridge_handle(
1005 pci_domain_nr(parent),
1008 handle = DEVICE_ACPI_HANDLE(
1009 &(parent->self->dev));
1010 pdev = parent->self;
1014 acpi_get_name(handle, ACPI_FULL_PATHNAME, &string);
1015 dbg("Trying to get hotplug control for %s \n",
1016 (char *)string.pointer);
1017 status = pci_osc_control_set(handle,
1018 OSC_PCI_EXPRESS_NATIVE_HP_CONTROL);
1019 if (status == AE_NOT_FOUND)
1020 status = acpi_run_oshp(handle);
1021 if (ACPI_SUCCESS(status)) {
1022 dbg("Gained control for hotplug HW for pci %s (%s)\n",
1023 pci_name(dev), (char *)string.pointer);
1024 kfree(string.pointer);
1027 if (acpi_root_bridge(handle))
1030 status = acpi_get_parent(chandle, &handle);
1031 if (ACPI_FAILURE(status))
1035 err("Cannot get control of hotplug hardware for pci %s\n",
1038 kfree(string.pointer);
1045 int pcie_init(struct controller * ctrl, struct pcie_device *dev)
1048 static int first = 1;
1051 u16 intr_enable = 0;
1053 int cap_base, saved_cap_base;
1054 u16 slot_status, slot_ctrl;
1055 struct pci_dev *pdev;
1060 ctrl->pci_dev = pdev; /* save pci_dev in context */
1062 dbg("%s: hotplug controller vendor id 0x%x device id 0x%x\n",
1063 __FUNCTION__, pdev->vendor, pdev->device);
1065 saved_cap_base = pcie_cap_base;
1067 if ((cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP)) == 0) {
1068 dbg("%s: Can't find PCI_CAP_ID_EXP (0x10)\n", __FUNCTION__);
1069 goto abort_free_ctlr;
1072 ctrl->cap_base = cap_base;
1074 dbg("%s: pcie_cap_base %x\n", __FUNCTION__, pcie_cap_base);
1076 rc = hp_register_read_word(pdev, CAP_REG(ctrl->cap_base), cap_reg);
1078 err("%s : hp_register_read_word CAP_REG failed\n", __FUNCTION__);
1079 goto abort_free_ctlr;
1081 dbg("%s: CAP_REG offset %x cap_reg %x\n", __FUNCTION__, CAP_REG(ctrl->cap_base), cap_reg);
1083 if (((cap_reg & SLOT_IMPL) == 0) || (((cap_reg & DEV_PORT_TYPE) != 0x0040)
1084 && ((cap_reg & DEV_PORT_TYPE) != 0x0060))) {
1085 dbg("%s : This is not a root port or the port is not connected to a slot\n", __FUNCTION__);
1086 goto abort_free_ctlr;
1089 rc = hp_register_read_dword(ctrl->pci_dev, SLOT_CAP(ctrl->cap_base), slot_cap);
1091 err("%s : hp_register_read_word CAP_REG failed\n", __FUNCTION__);
1092 goto abort_free_ctlr;
1094 dbg("%s: SLOT_CAP offset %x slot_cap %x\n", __FUNCTION__, SLOT_CAP(ctrl->cap_base), slot_cap);
1096 if (!(slot_cap & HP_CAP)) {
1097 dbg("%s : This slot is not hot-plug capable\n", __FUNCTION__);
1098 goto abort_free_ctlr;
1100 /* For debugging purpose */
1101 rc = hp_register_read_word(ctrl->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
1103 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
1104 goto abort_free_ctlr;
1106 dbg("%s: SLOT_STATUS offset %x slot_status %x\n", __FUNCTION__, SLOT_STATUS(ctrl->cap_base), slot_status);
1108 rc = hp_register_read_word(ctrl->pci_dev, SLOT_CTRL(ctrl->cap_base), slot_ctrl);
1110 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
1111 goto abort_free_ctlr;
1113 dbg("%s: SLOT_CTRL offset %x slot_ctrl %x\n", __FUNCTION__, SLOT_CTRL(ctrl->cap_base), slot_ctrl);
1116 spin_lock_init(&hpc_event_lock);
1120 for ( rc = 0; rc < DEVICE_COUNT_RESOURCE; rc++)
1121 if (pci_resource_len(pdev, rc) > 0)
1122 dbg("pci resource[%d] start=0x%llx(len=0x%llx)\n", rc,
1123 (unsigned long long)pci_resource_start(pdev, rc),
1124 (unsigned long long)pci_resource_len(pdev, rc));
1126 info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", pdev->vendor, pdev->device,
1127 pdev->subsystem_vendor, pdev->subsystem_device);
1129 mutex_init(&ctrl->crit_sect);
1130 mutex_init(&ctrl->ctrl_lock);
1132 /* setup wait queue */
1133 init_waitqueue_head(&ctrl->queue);
1135 /* return PCI Controller Info */
1136 ctrl->slot_device_offset = 0;
1137 ctrl->num_slots = 1;
1138 ctrl->first_slot = slot_cap >> 19;
1139 ctrl->ctrlcap = slot_cap & 0x0000007f;
1141 /* Mask Hot-plug Interrupt Enable */
1142 rc = hp_register_read_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word);
1144 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
1145 goto abort_free_ctlr;
1148 dbg("%s: SLOT_CTRL %x value read %x\n", __FUNCTION__, SLOT_CTRL(ctrl->cap_base), temp_word);
1149 temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) | 0x00;
1151 rc = hp_register_write_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word);
1153 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
1154 goto abort_free_ctlr;
1157 rc = hp_register_read_word(ctrl->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
1159 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
1160 goto abort_free_ctlr;
1163 temp_word = 0x1F; /* Clear all events */
1164 rc = hp_register_write_word(ctrl->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word);
1166 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
1167 goto abort_free_ctlr;
1170 if (pciehp_poll_mode) {
1171 /* Install interrupt polling timer. Start with 10 sec delay */
1172 init_timer(&ctrl->poll_timer);
1173 start_int_poll_timer(ctrl, 10);
1175 /* Installs the interrupt handler */
1176 rc = request_irq(ctrl->pci_dev->irq, pcie_isr, IRQF_SHARED,
1177 MY_NAME, (void *)ctrl);
1178 dbg("%s: request_irq %d for hpc%d (returns %d)\n",
1179 __FUNCTION__, ctrl->pci_dev->irq, ctlr_seq_num, rc);
1181 err("Can't get irq %d for the hotplug controller\n",
1182 ctrl->pci_dev->irq);
1183 goto abort_free_ctlr;
1186 dbg("pciehp ctrl b:d:f:irq=0x%x:%x:%x:%x\n", pdev->bus->number,
1187 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), dev->irq);
1189 rc = hp_register_read_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word);
1191 err("%s : hp_register_read_word SLOT_CTRL failed\n", __FUNCTION__);
1192 goto abort_free_irq;
1195 intr_enable = intr_enable | PRSN_DETECT_ENABLE;
1197 if (ATTN_BUTTN(slot_cap))
1198 intr_enable = intr_enable | ATTN_BUTTN_ENABLE;
1200 if (POWER_CTRL(slot_cap))
1201 intr_enable = intr_enable | PWR_FAULT_DETECT_ENABLE;
1203 if (MRL_SENS(slot_cap))
1204 intr_enable = intr_enable | MRL_DETECT_ENABLE;
1206 temp_word = (temp_word & ~intr_enable) | intr_enable;
1208 if (pciehp_poll_mode) {
1209 temp_word = (temp_word & ~HP_INTR_ENABLE) | 0x0;
1211 temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE;
1214 /* Unmask Hot-plug Interrupt Enable for the interrupt notification mechanism case */
1215 rc = hp_register_write_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word);
1217 err("%s : hp_register_write_word SLOT_CTRL failed\n", __FUNCTION__);
1218 goto abort_free_irq;
1220 rc = hp_register_read_word(ctrl->pci_dev, SLOT_STATUS(ctrl->cap_base), slot_status);
1222 err("%s : hp_register_read_word SLOT_STATUS failed\n", __FUNCTION__);
1223 goto abort_disable_intr;
1226 temp_word = 0x1F; /* Clear all events */
1227 rc = hp_register_write_word(ctrl->pci_dev, SLOT_STATUS(ctrl->cap_base), temp_word);
1229 err("%s : hp_register_write_word SLOT_STATUS failed\n", __FUNCTION__);
1230 goto abort_disable_intr;
1234 dbg("Bypassing BIOS check for pciehp use on %s\n",
1235 pci_name(ctrl->pci_dev));
1237 rc = pciehp_get_hp_hw_control_from_firmware(ctrl->pci_dev);
1239 goto abort_disable_intr;
1243 ctrl->hpc_ops = &pciehp_hpc_ops;
1248 /* We end up here for the many possible ways to fail this API. */
1250 rc = hp_register_read_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word);
1252 temp_word &= ~(intr_enable | HP_INTR_ENABLE);
1253 rc = hp_register_write_word(pdev, SLOT_CTRL(ctrl->cap_base), temp_word);
1256 err("%s : disabling interrupts failed\n", __FUNCTION__);
1259 if (pciehp_poll_mode)
1260 del_timer_sync(&ctrl->poll_timer);
1262 free_irq(ctrl->pci_dev->irq, ctrl);
1265 pcie_cap_base = saved_cap_base;