drivers/net/wireless/wl12xx/wl1271_io.c

   1 /*
   2  * This file is part of wl1271
   3  *
   4  * Copyright (C) 2008-2010 Nokia Corporation
   5  *
   6  * Contact: Luciano Coelho <luciano.coelho@nokia.com>
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * version 2 as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but
  13  * WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  20  * 02110-1301 USA
  21  *
  22  */
  23
  24 #include <linux/module.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/crc7.h>
  27 #include <linux/spi/spi.h>
  28
  29 #include "wl1271.h"
  30 #include "wl12xx_80211.h"
  31 #include "wl1271_io.h"
  32
  33 #define OCP_CMD_LOOP  32
  34
  35 #define OCP_CMD_WRITE 0x1
  36 #define OCP_CMD_READ  0x2
  37
  38 #define OCP_READY_MASK  BIT(18)
  39 #define OCP_STATUS_MASK (BIT(16) | BIT(17))
  40
  41 #define OCP_STATUS_NO_RESP    0x00000
  42 #define OCP_STATUS_OK         0x10000
  43 #define OCP_STATUS_REQ_FAILED 0x20000
  44 #define OCP_STATUS_RESP_ERROR 0x30000
  45
  46 void wl1271_disable_interrupts(struct wl1271 *wl)
  47 {
  48         wl->if_ops->disable_irq(wl);
  49 }
  50
  51 void wl1271_enable_interrupts(struct wl1271 *wl)
  52 {
  53         wl->if_ops->enable_irq(wl);
  54 }
  55
  56 /* Set the SPI partitions to access the chip addresses
  57  *
  58  * To simplify driver code, a fixed (virtual) memory map is defined for
  59  * register and memory addresses. Because in the chipset, in different stages
  60  * of operation, those addresses will move around, an address translation
  61  * mechanism is required.
  62  *
  63  * There are four partitions (three memory and one register partition),
  64  * which are mapped to two different areas of the hardware memory.
  65  *
  66  *                                Virtual address
  67  *                                     space
  68  *
  69  *                                    |    |
  70  *                                 ...+----+--> mem.start
  71  *          Physical address    ...   |    |
  72  *               space       ...      |    | [PART_0]
  73  *                        ...         |    |
  74  *  00000000  <--+----+...         ...+----+--> mem.start + mem.size
  75  *               |    |         ...   |    |
  76  *               |MEM |      ...      |    |
  77  *               |    |   ...         |    |
  78  *  mem.size  <--+----+...            |    | {unused area)
  79  *               |    |   ...         |    |
  80  *               |REG |      ...      |    |
  81  *  mem.size     |    |         ...   |    |
  82  *      +     <--+----+...         ...+----+--> reg.start
  83  *  reg.size     |    |   ...         |    |
  84  *               |MEM2|      ...      |    | [PART_1]
  85  *               |    |         ...   |    |
  86  *                                 ...+----+--> reg.start + reg.size
  87  *                                    |    |
  88  *
  89  */
  90 int wl1271_set_partition(struct wl1271 *wl,
  91                          struct wl1271_partition_set *p)
  92 {
  93         /* copy partition info */
  94         memcpy(&wl->part, p, sizeof(*p));
  95
  96         wl1271_debug(DEBUG_SPI, "mem_start %08X mem_size %08X",
  97                      p->mem.start, p->mem.size);
  98         wl1271_debug(DEBUG_SPI, "reg_start %08X reg_size %08X",
  99                      p->reg.start, p->reg.size);
 100         wl1271_debug(DEBUG_SPI, "mem2_start %08X mem2_size %08X",
 101                      p->mem2.start, p->mem2.size);
 102         wl1271_debug(DEBUG_SPI, "mem3_start %08X mem3_size %08X",
 103                      p->mem3.start, p->mem3.size);
 104
 105         /* write partition info to the chipset */
 106         wl1271_raw_write32(wl, HW_PART0_START_ADDR, p->mem.start);
 107         wl1271_raw_write32(wl, HW_PART0_SIZE_ADDR, p->mem.size);
 108         wl1271_raw_write32(wl, HW_PART1_START_ADDR, p->reg.start);
 109         wl1271_raw_write32(wl, HW_PART1_SIZE_ADDR, p->reg.size);
 110         wl1271_raw_write32(wl, HW_PART2_START_ADDR, p->mem2.start);
 111         wl1271_raw_write32(wl, HW_PART2_SIZE_ADDR, p->mem2.size);
 112         wl1271_raw_write32(wl, HW_PART3_START_ADDR, p->mem3.start);
 113
 114         return 0;
 115 }
 116
 117 void wl1271_io_reset(struct wl1271 *wl)
 118 {
 119         wl->if_ops->reset(wl);
 120 }
 121
 122 void wl1271_io_init(struct wl1271 *wl)
 123 {
 124         wl->if_ops->init(wl);
 125 }
 126
 127 void wl1271_top_reg_write(struct wl1271 *wl, int addr, u16 val)
 128 {
 129         /* write address >> 1 + 0x30000 to OCP_POR_CTR */
 130         addr = (addr >> 1) + 0x30000;
 131         wl1271_write32(wl, OCP_POR_CTR, addr);
 132
 133         /* write value to OCP_POR_WDATA */
 134         wl1271_write32(wl, OCP_DATA_WRITE, val);
 135
 136         /* write 1 to OCP_CMD */
 137         wl1271_write32(wl, OCP_CMD, OCP_CMD_WRITE);
 138 }
 139
 140 u16 wl1271_top_reg_read(struct wl1271 *wl, int addr)
 141 {
 142         u32 val;
 143         int timeout = OCP_CMD_LOOP;
 144
 145         /* write address >> 1 + 0x30000 to OCP_POR_CTR */
 146         addr = (addr >> 1) + 0x30000;
 147         wl1271_write32(wl, OCP_POR_CTR, addr);
 148
 149         /* write 2 to OCP_CMD */
 150         wl1271_write32(wl, OCP_CMD, OCP_CMD_READ);
 151
 152         /* poll for data ready */
 153         do {
 154                 val = wl1271_read32(wl, OCP_DATA_READ);
 155         } while (!(val & OCP_READY_MASK) && --timeout);
 156
 157         if (!timeout) {
 158                 wl1271_warning("Top register access timed out.");
 159                 return 0xffff;
 160         }
 161
 162         /* check data status and return if OK */
 163         if ((val & OCP_STATUS_MASK) == OCP_STATUS_OK)
 164                 return val & 0xffff;
 165         else {
 166                 wl1271_warning("Top register access returned error.");
 167                 return 0xffff;
 168         }
 169 }
 170