drivers/net/wireless/wl12xx/wl1271_boot.c

   1 /*
   2  * This file is part of wl1271
   3  *
   4  * Copyright (C) 2008-2010 Nokia Corporation
   5  *
   6  * Contact: Luciano Coelho <luciano.coelho@nokia.com>
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * version 2 as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but
  13  * WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  20  * 02110-1301 USA
  21  *
  22  */
  23
  24 #include <linux/gpio.h>
  25 #include <linux/slab.h>
  26
  27 #include "wl1271_acx.h"
  28 #include "wl1271_reg.h"
  29 #include "wl1271_boot.h"
  30 #include "wl1271_io.h"
  31 #include "wl1271_event.h"
  32
  33 static struct wl1271_partition_set part_table[PART_TABLE_LEN] = {
  34         [PART_DOWN] = {
  35                 .mem = {
  36                         .start = 0x00000000,
  37                         .size  = 0x000177c0
  38                 },
  39                 .reg = {
  40                         .start = REGISTERS_BASE,
  41                         .size  = 0x00008800
  42                 },
  43                 .mem2 = {
  44                         .start = 0x00000000,
  45                         .size  = 0x00000000
  46                 },
  47                 .mem3 = {
  48                         .start = 0x00000000,
  49                         .size  = 0x00000000
  50                 },
  51         },
  52
  53         [PART_WORK] = {
  54                 .mem = {
  55                         .start = 0x00040000,
  56                         .size  = 0x00014fc0
  57                 },
  58                 .reg = {
  59                         .start = REGISTERS_BASE,
  60                         .size  = 0x0000a000
  61                 },
  62                 .mem2 = {
  63                         .start = 0x003004f8,
  64                         .size  = 0x00000004
  65                 },
  66                 .mem3 = {
  67                         .start = 0x00040404,
  68                         .size  = 0x00000000
  69                 },
  70         },
  71
  72         [PART_DRPW] = {
  73                 .mem = {
  74                         .start = 0x00040000,
  75                         .size  = 0x00014fc0
  76                 },
  77                 .reg = {
  78                         .start = DRPW_BASE,
  79                         .size  = 0x00006000
  80                 },
  81                 .mem2 = {
  82                         .start = 0x00000000,
  83                         .size  = 0x00000000
  84                 },
  85                 .mem3 = {
  86                         .start = 0x00000000,
  87                         .size  = 0x00000000
  88                 }
  89         }
  90 };
  91
  92 static void wl1271_boot_set_ecpu_ctrl(struct wl1271 *wl, u32 flag)
  93 {
  94         u32 cpu_ctrl;
  95
  96         /* 10.5.0 run the firmware (I) */
  97         cpu_ctrl = wl1271_read32(wl, ACX_REG_ECPU_CONTROL);
  98
  99         /* 10.5.1 run the firmware (II) */
 100         cpu_ctrl |= flag;
 101         wl1271_write32(wl, ACX_REG_ECPU_CONTROL, cpu_ctrl);
 102 }
 103
 104 static void wl1271_boot_fw_version(struct wl1271 *wl)
 105 {
 106         struct wl1271_static_data static_data;
 107
 108         wl1271_read(wl, wl->cmd_box_addr, &static_data, sizeof(static_data),
 109                     false);
 110
 111         strncpy(wl->chip.fw_ver, static_data.fw_version,
 112                 sizeof(wl->chip.fw_ver));
 113
 114         /* make sure the string is NULL-terminated */
 115         wl->chip.fw_ver[sizeof(wl->chip.fw_ver) - 1] = '\0';
 116 }
 117
 118 static int wl1271_boot_upload_firmware_chunk(struct wl1271 *wl, void *buf,
 119                                              size_t fw_data_len, u32 dest)
 120 {
 121         struct wl1271_partition_set partition;
 122         int addr, chunk_num, partition_limit;
 123         u8 *p, *chunk;
 124
 125         /* whal_FwCtrl_LoadFwImageSm() */
 126
 127         wl1271_debug(DEBUG_BOOT, "starting firmware upload");
 128
 129         wl1271_debug(DEBUG_BOOT, "fw_data_len %zd chunk_size %d",
 130                      fw_data_len, CHUNK_SIZE);
 131
 132         if ((fw_data_len % 4) != 0) {
 133                 wl1271_error("firmware length not multiple of four");
 134                 return -EIO;
 135         }
 136
 137         chunk = kmalloc(CHUNK_SIZE, GFP_KERNEL);
 138         if (!chunk) {
 139                 wl1271_error("allocation for firmware upload chunk failed");
 140                 return -ENOMEM;
 141         }
 142
 143         memcpy(&partition, &part_table[PART_DOWN], sizeof(partition));
 144         partition.mem.start = dest;
 145         wl1271_set_partition(wl, &partition);
 146
 147         /* 10.1 set partition limit and chunk num */
 148         chunk_num = 0;
 149         partition_limit = part_table[PART_DOWN].mem.size;
 150
 151         while (chunk_num < fw_data_len / CHUNK_SIZE) {
 152                 /* 10.2 update partition, if needed */
 153                 addr = dest + (chunk_num + 2) * CHUNK_SIZE;
 154                 if (addr > partition_limit) {
 155                         addr = dest + chunk_num * CHUNK_SIZE;
 156                         partition_limit = chunk_num * CHUNK_SIZE +
 157                                 part_table[PART_DOWN].mem.size;
 158                         partition.mem.start = addr;
 159                         wl1271_set_partition(wl, &partition);
 160                 }
 161
 162                 /* 10.3 upload the chunk */
 163                 addr = dest + chunk_num * CHUNK_SIZE;
 164                 p = buf + chunk_num * CHUNK_SIZE;
 165                 memcpy(chunk, p, CHUNK_SIZE);
 166                 wl1271_debug(DEBUG_BOOT, "uploading fw chunk 0x%p to 0x%x",
 167                              p, addr);
 168                 wl1271_write(wl, addr, chunk, CHUNK_SIZE, false);
 169
 170                 chunk_num++;
 171         }
 172
 173         /* 10.4 upload the last chunk */
 174         addr = dest + chunk_num * CHUNK_SIZE;
 175         p = buf + chunk_num * CHUNK_SIZE;
 176         memcpy(chunk, p, fw_data_len % CHUNK_SIZE);
 177         wl1271_debug(DEBUG_BOOT, "uploading fw last chunk (%zd B) 0x%p to 0x%x",
 178                      fw_data_len % CHUNK_SIZE, p, addr);
 179         wl1271_write(wl, addr, chunk, fw_data_len % CHUNK_SIZE, false);
 180
 181         kfree(chunk);
 182         return 0;
 183 }
 184
 185 static int wl1271_boot_upload_firmware(struct wl1271 *wl)
 186 {
 187         u32 chunks, addr, len;
 188         int ret = 0;
 189         u8 *fw;
 190
 191         fw = wl->fw;
 192         chunks = be32_to_cpup((__be32 *) fw);
 193         fw += sizeof(u32);
 194
 195         wl1271_debug(DEBUG_BOOT, "firmware chunks to be uploaded: %u", chunks);
 196
 197         while (chunks--) {
 198                 addr = be32_to_cpup((__be32 *) fw);
 199                 fw += sizeof(u32);
 200                 len = be32_to_cpup((__be32 *) fw);
 201                 fw += sizeof(u32);
 202
 203                 if (len > 300000) {
 204                         wl1271_info("firmware chunk too long: %u", len);
 205                         return -EINVAL;
 206                 }
 207                 wl1271_debug(DEBUG_BOOT, "chunk %d addr 0x%x len %u",
 208                              chunks, addr, len);
 209                 ret = wl1271_boot_upload_firmware_chunk(wl, fw, len, addr);
 210                 if (ret != 0)
 211                         break;
 212                 fw += len;
 213         }
 214
 215         return ret;
 216 }
 217
 218 static int wl1271_boot_upload_nvs(struct wl1271 *wl)
 219 {
 220         size_t nvs_len, burst_len;
 221         int i;
 222         u32 dest_addr, val;
 223         u8 *nvs_ptr, *nvs_aligned;
 224
 225         if (wl->nvs == NULL)
 226                 return -ENODEV;
 227
 228         /* only the first part of the NVS needs to be uploaded */
 229         nvs_len = sizeof(wl->nvs->nvs);
 230         nvs_ptr = (u8 *)wl->nvs->nvs;
 231
 232         /* update current MAC address to NVS */
 233         nvs_ptr[11] = wl->mac_addr[0];
 234         nvs_ptr[10] = wl->mac_addr[1];
 235         nvs_ptr[6] = wl->mac_addr[2];
 236         nvs_ptr[5] = wl->mac_addr[3];
 237         nvs_ptr[4] = wl->mac_addr[4];
 238         nvs_ptr[3] = wl->mac_addr[5];
 239
 240         /*
 241          * Layout before the actual NVS tables:
 242          * 1 byte : burst length.
 243          * 2 bytes: destination address.
 244          * n bytes: data to burst copy.
 245          *
 246          * This is ended by a 0 length, then the NVS tables.
 247          */
 248
 249         /* FIXME: Do we need to check here whether the LSB is 1? */
 250         while (nvs_ptr[0]) {
 251                 burst_len = nvs_ptr[0];
 252                 dest_addr = (nvs_ptr[1] & 0xfe) | ((u32)(nvs_ptr[2] << 8));
 253
 254                 /*
 255                  * Due to our new wl1271_translate_reg_addr function,
 256                  * we need to add the REGISTER_BASE to the destination
 257                  */
 258                 dest_addr += REGISTERS_BASE;
 259
 260                 /* We move our pointer to the data */
 261                 nvs_ptr += 3;
 262
 263                 for (i = 0; i < burst_len; i++) {
 264                         val = (nvs_ptr[0] | (nvs_ptr[1] << 8)
 265                                | (nvs_ptr[2] << 16) | (nvs_ptr[3] << 24));
 266
 267                         wl1271_debug(DEBUG_BOOT,
 268                                      "nvs burst write 0x%x: 0x%x",
 269                                      dest_addr, val);
 270                         wl1271_write32(wl, dest_addr, val);
 271
 272                         nvs_ptr += 4;
 273                         dest_addr += 4;
 274                 }
 275         }
 276
 277         /*
 278          * We've reached the first zero length, the first NVS table
 279          * is located at an aligned offset which is at least 7 bytes further.
 280          */
 281         nvs_ptr = (u8 *)wl->nvs->nvs +
 282                         ALIGN(nvs_ptr - (u8 *)wl->nvs->nvs + 7, 4);
 283         nvs_len -= nvs_ptr - (u8 *)wl->nvs->nvs;
 284
 285         /* Now we must set the partition correctly */
 286         wl1271_set_partition(wl, &part_table[PART_WORK]);
 287
 288         /* Copy the NVS tables to a new block to ensure alignment */
 289         nvs_aligned = kmemdup(nvs_ptr, nvs_len, GFP_KERNEL);
 290         if (!nvs_aligned)
 291                 return -ENOMEM;
 292
 293         /* And finally we upload the NVS tables */
 294         wl1271_write(wl, CMD_MBOX_ADDRESS, nvs_aligned, nvs_len, false);
 295
 296         kfree(nvs_aligned);
 297         return 0;
 298 }
 299
 300 static void wl1271_boot_enable_interrupts(struct wl1271 *wl)
 301 {
 302         wl1271_enable_interrupts(wl);
 303         wl1271_write32(wl, ACX_REG_INTERRUPT_MASK,
 304                        WL1271_ACX_INTR_ALL & ~(WL1271_INTR_MASK));
 305         wl1271_write32(wl, HI_CFG, HI_CFG_DEF_VAL);
 306 }
 307
 308 static int wl1271_boot_soft_reset(struct wl1271 *wl)
 309 {
 310         unsigned long timeout;
 311         u32 boot_data;
 312
 313         /* perform soft reset */
 314         wl1271_write32(wl, ACX_REG_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT);
 315
 316         /* SOFT_RESET is self clearing */
 317         timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME);
 318         while (1) {
 319                 boot_data = wl1271_read32(wl, ACX_REG_SLV_SOFT_RESET);
 320                 wl1271_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data);
 321                 if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0)
 322                         break;
 323
 324                 if (time_after(jiffies, timeout)) {
 325                         /* 1.2 check pWhalBus->uSelfClearTime if the
 326                          * timeout was reached */
 327                         wl1271_error("soft reset timeout");
 328                         return -1;
 329                 }
 330
 331                 udelay(SOFT_RESET_STALL_TIME);
 332         }
 333
 334         /* disable Rx/Tx */
 335         wl1271_write32(wl, ENABLE, 0x0);
 336
 337         /* disable auto calibration on start*/
 338         wl1271_write32(wl, SPARE_A2, 0xffff);
 339
 340         return 0;
 341 }
 342
 343 static int wl1271_boot_run_firmware(struct wl1271 *wl)
 344 {
 345         int loop, ret;
 346         u32 chip_id, intr;
 347
 348         wl1271_boot_set_ecpu_ctrl(wl, ECPU_CONTROL_HALT);
 349
 350         chip_id = wl1271_read32(wl, CHIP_ID_B);
 351
 352         wl1271_debug(DEBUG_BOOT, "chip id after firmware boot: 0x%x", chip_id);
 353
 354         if (chip_id != wl->chip.id) {
 355                 wl1271_error("chip id doesn't match after firmware boot");
 356                 return -EIO;
 357         }
 358
 359         /* wait for init to complete */
 360         loop = 0;
 361         while (loop++ < INIT_LOOP) {
 362                 udelay(INIT_LOOP_DELAY);
 363                 intr = wl1271_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR);
 364
 365                 if (intr == 0xffffffff) {
 366                         wl1271_error("error reading hardware complete "
 367                                      "init indication");
 368                         return -EIO;
 369                 }
 370                 /* check that ACX_INTR_INIT_COMPLETE is enabled */
 371                 else if (intr & WL1271_ACX_INTR_INIT_COMPLETE) {
 372                         wl1271_write32(wl, ACX_REG_INTERRUPT_ACK,
 373                                        WL1271_ACX_INTR_INIT_COMPLETE);
 374                         break;
 375                 }
 376         }
 377
 378         if (loop > INIT_LOOP) {
 379                 wl1271_error("timeout waiting for the hardware to "
 380                              "complete initialization");
 381                 return -EIO;
 382         }
 383
 384         /* get hardware config command mail box */
 385         wl->cmd_box_addr = wl1271_read32(wl, REG_COMMAND_MAILBOX_PTR);
 386
 387         /* get hardware config event mail box */
 388         wl->event_box_addr = wl1271_read32(wl, REG_EVENT_MAILBOX_PTR);
 389
 390         /* set the working partition to its "running" mode offset */
 391         wl1271_set_partition(wl, &part_table[PART_WORK]);
 392
 393         wl1271_debug(DEBUG_MAILBOX, "cmd_box_addr 0x%x event_box_addr 0x%x",
 394                      wl->cmd_box_addr, wl->event_box_addr);
 395
 396         wl1271_boot_fw_version(wl);
 397
 398         /*
 399          * in case of full asynchronous mode the firmware event must be
 400          * ready to receive event from the command mailbox
 401          */
 402
 403         /* unmask required mbox events  */
 404         wl->event_mask = BSS_LOSE_EVENT_ID |
 405                 SCAN_COMPLETE_EVENT_ID |
 406                 PS_REPORT_EVENT_ID |
 407                 JOIN_EVENT_COMPLETE_ID |
 408                 DISCONNECT_EVENT_COMPLETE_ID |
 409                 RSSI_SNR_TRIGGER_0_EVENT_ID |
 410                 PSPOLL_DELIVERY_FAILURE_EVENT_ID |
 411                 SOFT_GEMINI_SENSE_EVENT_ID;
 412
 413         ret = wl1271_event_unmask(wl);
 414         if (ret < 0) {
 415                 wl1271_error("EVENT mask setting failed");
 416                 return ret;
 417         }
 418
 419         wl1271_event_mbox_config(wl);
 420
 421         /* firmware startup completed */
 422         return 0;
 423 }
 424
 425 static int wl1271_boot_write_irq_polarity(struct wl1271 *wl)
 426 {
 427         u32 polarity;
 428
 429         polarity = wl1271_top_reg_read(wl, OCP_REG_POLARITY);
 430
 431         /* We use HIGH polarity, so unset the LOW bit */
 432         polarity &= ~POLARITY_LOW;
 433         wl1271_top_reg_write(wl, OCP_REG_POLARITY, polarity);
 434
 435         return 0;
 436 }
 437
 438 static void wl1271_boot_hw_version(struct wl1271 *wl)
 439 {
 440         u32 fuse;
 441
 442         fuse = wl1271_top_reg_read(wl, REG_FUSE_DATA_2_1);
 443         fuse = (fuse & PG_VER_MASK) >> PG_VER_OFFSET;
 444
 445         wl->hw_pg_ver = (s8)fuse;
 446 }
 447
 448 int wl1271_boot(struct wl1271 *wl)
 449 {
 450         int ret = 0;
 451         u32 tmp, clk, pause;
 452         int ref_clock = wl->ref_clock;
 453
 454         wl1271_boot_hw_version(wl);
 455
 456         if (ref_clock == 0 || ref_clock == 2 || ref_clock == 4)
 457                 /* ref clk: 19.2/38.4/38.4-XTAL */
 458                 clk = 0x3;
 459         else if (ref_clock == 1 || ref_clock == 3)
 460                 /* ref clk: 26/52 */
 461                 clk = 0x5;
 462         else
 463                 return -EINVAL;
 464
 465         if (ref_clock != 0) {
 466                 u16 val;
 467                 /* Set clock type (open drain) */
 468                 val = wl1271_top_reg_read(wl, OCP_REG_CLK_TYPE);
 469                 val &= FREF_CLK_TYPE_BITS;
 470                 wl1271_top_reg_write(wl, OCP_REG_CLK_TYPE, val);
 471
 472                 /* Set clock pull mode (no pull) */
 473                 val = wl1271_top_reg_read(wl, OCP_REG_CLK_PULL);
 474                 val |= NO_PULL;
 475                 wl1271_top_reg_write(wl, OCP_REG_CLK_PULL, val);
 476         } else {
 477                 u16 val;
 478                 /* Set clock polarity */
 479                 val = wl1271_top_reg_read(wl, OCP_REG_CLK_POLARITY);
 480                 val &= FREF_CLK_POLARITY_BITS;
 481                 val |= CLK_REQ_OUTN_SEL;
 482                 wl1271_top_reg_write(wl, OCP_REG_CLK_POLARITY, val);
 483         }
 484
 485         wl1271_write32(wl, PLL_PARAMETERS, clk);
 486
 487         pause = wl1271_read32(wl, PLL_PARAMETERS);
 488
 489         wl1271_debug(DEBUG_BOOT, "pause1 0x%x", pause);
 490
 491         pause &= ~(WU_COUNTER_PAUSE_VAL);
 492         pause |= WU_COUNTER_PAUSE_VAL;
 493         wl1271_write32(wl, WU_COUNTER_PAUSE, pause);
 494
 495         /* Continue the ELP wake up sequence */
 496         wl1271_write32(wl, WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
 497         udelay(500);
 498
 499         wl1271_set_partition(wl, &part_table[PART_DRPW]);
 500
 501         /* Read-modify-write DRPW_SCRATCH_START register (see next state)
 502            to be used by DRPw FW. The RTRIM value will be added by the FW
 503            before taking DRPw out of reset */
 504
 505         wl1271_debug(DEBUG_BOOT, "DRPW_SCRATCH_START %08x", DRPW_SCRATCH_START);
 506         clk = wl1271_read32(wl, DRPW_SCRATCH_START);
 507
 508         wl1271_debug(DEBUG_BOOT, "clk2 0x%x", clk);
 509
 510         /* 2 */
 511         clk |= (ref_clock << 1) << 4;
 512         wl1271_write32(wl, DRPW_SCRATCH_START, clk);
 513
 514         wl1271_set_partition(wl, &part_table[PART_WORK]);
 515
 516         /* Disable interrupts */
 517         wl1271_write32(wl, ACX_REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
 518
 519         ret = wl1271_boot_soft_reset(wl);
 520         if (ret < 0)
 521                 goto out;
 522
 523         /* 2. start processing NVS file */
 524         ret = wl1271_boot_upload_nvs(wl);
 525         if (ret < 0)
 526                 goto out;
 527
 528         /* write firmware's last address (ie. it's length) to
 529          * ACX_EEPROMLESS_IND_REG */
 530         wl1271_debug(DEBUG_BOOT, "ACX_EEPROMLESS_IND_REG");
 531
 532         wl1271_write32(wl, ACX_EEPROMLESS_IND_REG, ACX_EEPROMLESS_IND_REG);
 533
 534         tmp = wl1271_read32(wl, CHIP_ID_B);
 535
 536         wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);
 537
 538         /* 6. read the EEPROM parameters */
 539         tmp = wl1271_read32(wl, SCR_PAD2);
 540
 541         ret = wl1271_boot_write_irq_polarity(wl);
 542         if (ret < 0)
 543                 goto out;
 544
 545         wl1271_write32(wl, ACX_REG_INTERRUPT_MASK,
 546                        WL1271_ACX_ALL_EVENTS_VECTOR);
 547
 548         /* WL1271: The reference driver skips steps 7 to 10 (jumps directly
 549          * to upload_fw) */
 550
 551         ret = wl1271_boot_upload_firmware(wl);
 552         if (ret < 0)
 553                 goto out;
 554
 555         /* 10.5 start firmware */
 556         ret = wl1271_boot_run_firmware(wl);
 557         if (ret < 0)
 558                 goto out;
 559
 560         /* Enable firmware interrupts now */
 561         wl1271_boot_enable_interrupts(wl);
 562
 563         /* set the wl1271 default filters */
 564         wl->rx_config = WL1271_DEFAULT_RX_CONFIG;
 565         wl->rx_filter = WL1271_DEFAULT_RX_FILTER;
 566
 567         wl1271_event_mbox_config(wl);
 568
 569 out:
 570         return ret;
 571 }