2 * This file is part of wl1271
4 * Copyright (C) 2008-2010 Nokia Corporation
6 * Contact: Luciano Coelho <luciano.coelho@nokia.com>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
24 #include <linux/slab.h>
25 #include <linux/wl12xx.h>
34 static struct wl1271_partition_set part_table[PART_TABLE_LEN] = {
41 .start = REGISTERS_BASE,
60 .start = REGISTERS_BASE,
93 static void wl1271_boot_set_ecpu_ctrl(struct wl1271 *wl, u32 flag)
97 /* 10.5.0 run the firmware (I) */
98 cpu_ctrl = wl1271_read32(wl, ACX_REG_ECPU_CONTROL);
100 /* 10.5.1 run the firmware (II) */
102 wl1271_write32(wl, ACX_REG_ECPU_CONTROL, cpu_ctrl);
105 static void wl1271_parse_fw_ver(struct wl1271 *wl)
109 ret = sscanf(wl->chip.fw_ver_str + 4, "%u.%u.%u.%u.%u",
110 &wl->chip.fw_ver[0], &wl->chip.fw_ver[1],
111 &wl->chip.fw_ver[2], &wl->chip.fw_ver[3],
112 &wl->chip.fw_ver[4]);
115 wl1271_warning("fw version incorrect value");
116 memset(wl->chip.fw_ver, 0, sizeof(wl->chip.fw_ver));
121 static void wl1271_boot_fw_version(struct wl1271 *wl)
123 struct wl1271_static_data static_data;
125 wl1271_read(wl, wl->cmd_box_addr, &static_data, sizeof(static_data),
128 strncpy(wl->chip.fw_ver_str, static_data.fw_version,
129 sizeof(wl->chip.fw_ver_str));
131 /* make sure the string is NULL-terminated */
132 wl->chip.fw_ver_str[sizeof(wl->chip.fw_ver_str) - 1] = '\0';
134 wl1271_parse_fw_ver(wl);
137 static int wl1271_boot_upload_firmware_chunk(struct wl1271 *wl, void *buf,
138 size_t fw_data_len, u32 dest)
140 struct wl1271_partition_set partition;
141 int addr, chunk_num, partition_limit;
144 /* whal_FwCtrl_LoadFwImageSm() */
146 wl1271_debug(DEBUG_BOOT, "starting firmware upload");
148 wl1271_debug(DEBUG_BOOT, "fw_data_len %zd chunk_size %d",
149 fw_data_len, CHUNK_SIZE);
151 if ((fw_data_len % 4) != 0) {
152 wl1271_error("firmware length not multiple of four");
156 chunk = kmalloc(CHUNK_SIZE, GFP_KERNEL);
158 wl1271_error("allocation for firmware upload chunk failed");
162 memcpy(&partition, &part_table[PART_DOWN], sizeof(partition));
163 partition.mem.start = dest;
164 wl1271_set_partition(wl, &partition);
166 /* 10.1 set partition limit and chunk num */
168 partition_limit = part_table[PART_DOWN].mem.size;
170 while (chunk_num < fw_data_len / CHUNK_SIZE) {
171 /* 10.2 update partition, if needed */
172 addr = dest + (chunk_num + 2) * CHUNK_SIZE;
173 if (addr > partition_limit) {
174 addr = dest + chunk_num * CHUNK_SIZE;
175 partition_limit = chunk_num * CHUNK_SIZE +
176 part_table[PART_DOWN].mem.size;
177 partition.mem.start = addr;
178 wl1271_set_partition(wl, &partition);
181 /* 10.3 upload the chunk */
182 addr = dest + chunk_num * CHUNK_SIZE;
183 p = buf + chunk_num * CHUNK_SIZE;
184 memcpy(chunk, p, CHUNK_SIZE);
185 wl1271_debug(DEBUG_BOOT, "uploading fw chunk 0x%p to 0x%x",
187 wl1271_write(wl, addr, chunk, CHUNK_SIZE, false);
192 /* 10.4 upload the last chunk */
193 addr = dest + chunk_num * CHUNK_SIZE;
194 p = buf + chunk_num * CHUNK_SIZE;
195 memcpy(chunk, p, fw_data_len % CHUNK_SIZE);
196 wl1271_debug(DEBUG_BOOT, "uploading fw last chunk (%zd B) 0x%p to 0x%x",
197 fw_data_len % CHUNK_SIZE, p, addr);
198 wl1271_write(wl, addr, chunk, fw_data_len % CHUNK_SIZE, false);
204 static int wl1271_boot_upload_firmware(struct wl1271 *wl)
206 u32 chunks, addr, len;
211 chunks = be32_to_cpup((__be32 *) fw);
214 wl1271_debug(DEBUG_BOOT, "firmware chunks to be uploaded: %u", chunks);
217 addr = be32_to_cpup((__be32 *) fw);
219 len = be32_to_cpup((__be32 *) fw);
223 wl1271_info("firmware chunk too long: %u", len);
226 wl1271_debug(DEBUG_BOOT, "chunk %d addr 0x%x len %u",
228 ret = wl1271_boot_upload_firmware_chunk(wl, fw, len, addr);
237 static int wl1271_boot_upload_nvs(struct wl1271 *wl)
239 size_t nvs_len, burst_len;
242 u8 *nvs_ptr, *nvs_aligned;
247 if (wl->chip.id == CHIP_ID_1283_PG20) {
248 struct wl128x_nvs_file *nvs = (struct wl128x_nvs_file *)wl->nvs;
250 if (wl->nvs_len == sizeof(struct wl128x_nvs_file)) {
251 if (nvs->general_params.dual_mode_select)
252 wl->enable_11a = true;
254 wl1271_error("nvs size is not as expected: %zu != %zu",
256 sizeof(struct wl128x_nvs_file));
263 /* only the first part of the NVS needs to be uploaded */
264 nvs_len = sizeof(nvs->nvs);
265 nvs_ptr = (u8 *)nvs->nvs;
268 struct wl1271_nvs_file *nvs =
269 (struct wl1271_nvs_file *)wl->nvs;
271 * FIXME: the LEGACY NVS image support (NVS's missing the 5GHz
272 * band configurations) can be removed when those NVS files stop
275 if (wl->nvs_len == sizeof(struct wl1271_nvs_file) ||
276 wl->nvs_len == WL1271_INI_LEGACY_NVS_FILE_SIZE) {
277 /* for now 11a is unsupported in AP mode */
278 if (wl->bss_type != BSS_TYPE_AP_BSS &&
279 nvs->general_params.dual_mode_select)
280 wl->enable_11a = true;
283 if (wl->nvs_len != sizeof(struct wl1271_nvs_file) &&
284 (wl->nvs_len != WL1271_INI_LEGACY_NVS_FILE_SIZE ||
286 wl1271_error("nvs size is not as expected: %zu != %zu",
287 wl->nvs_len, sizeof(struct wl1271_nvs_file));
294 /* only the first part of the NVS needs to be uploaded */
295 nvs_len = sizeof(nvs->nvs);
296 nvs_ptr = (u8 *) nvs->nvs;
299 /* update current MAC address to NVS */
300 nvs_ptr[11] = wl->mac_addr[0];
301 nvs_ptr[10] = wl->mac_addr[1];
302 nvs_ptr[6] = wl->mac_addr[2];
303 nvs_ptr[5] = wl->mac_addr[3];
304 nvs_ptr[4] = wl->mac_addr[4];
305 nvs_ptr[3] = wl->mac_addr[5];
308 * Layout before the actual NVS tables:
309 * 1 byte : burst length.
310 * 2 bytes: destination address.
311 * n bytes: data to burst copy.
313 * This is ended by a 0 length, then the NVS tables.
316 /* FIXME: Do we need to check here whether the LSB is 1? */
318 burst_len = nvs_ptr[0];
319 dest_addr = (nvs_ptr[1] & 0xfe) | ((u32)(nvs_ptr[2] << 8));
322 * Due to our new wl1271_translate_reg_addr function,
323 * we need to add the REGISTER_BASE to the destination
325 dest_addr += REGISTERS_BASE;
327 /* We move our pointer to the data */
330 for (i = 0; i < burst_len; i++) {
331 val = (nvs_ptr[0] | (nvs_ptr[1] << 8)
332 | (nvs_ptr[2] << 16) | (nvs_ptr[3] << 24));
334 wl1271_debug(DEBUG_BOOT,
335 "nvs burst write 0x%x: 0x%x",
337 wl1271_write32(wl, dest_addr, val);
345 * We've reached the first zero length, the first NVS table
346 * is located at an aligned offset which is at least 7 bytes further.
347 * NOTE: The wl->nvs->nvs element must be first, in order to
348 * simplify the casting, we assume it is at the beginning of
349 * the wl->nvs structure.
351 nvs_ptr = (u8 *)wl->nvs +
352 ALIGN(nvs_ptr - (u8 *)wl->nvs + 7, 4);
353 nvs_len -= nvs_ptr - (u8 *)wl->nvs;
355 /* Now we must set the partition correctly */
356 wl1271_set_partition(wl, &part_table[PART_WORK]);
358 /* Copy the NVS tables to a new block to ensure alignment */
359 nvs_aligned = kmemdup(nvs_ptr, nvs_len, GFP_KERNEL);
363 /* And finally we upload the NVS tables */
364 wl1271_write(wl, CMD_MBOX_ADDRESS, nvs_aligned, nvs_len, false);
370 static void wl1271_boot_enable_interrupts(struct wl1271 *wl)
372 wl1271_enable_interrupts(wl);
373 wl1271_write32(wl, ACX_REG_INTERRUPT_MASK,
374 WL1271_ACX_INTR_ALL & ~(WL1271_INTR_MASK));
375 wl1271_write32(wl, HI_CFG, HI_CFG_DEF_VAL);
378 static int wl1271_boot_soft_reset(struct wl1271 *wl)
380 unsigned long timeout;
383 /* perform soft reset */
384 wl1271_write32(wl, ACX_REG_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT);
386 /* SOFT_RESET is self clearing */
387 timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME);
389 boot_data = wl1271_read32(wl, ACX_REG_SLV_SOFT_RESET);
390 wl1271_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data);
391 if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0)
394 if (time_after(jiffies, timeout)) {
395 /* 1.2 check pWhalBus->uSelfClearTime if the
396 * timeout was reached */
397 wl1271_error("soft reset timeout");
401 udelay(SOFT_RESET_STALL_TIME);
405 wl1271_write32(wl, ENABLE, 0x0);
407 /* disable auto calibration on start*/
408 wl1271_write32(wl, SPARE_A2, 0xffff);
413 static int wl1271_boot_run_firmware(struct wl1271 *wl)
418 wl1271_boot_set_ecpu_ctrl(wl, ECPU_CONTROL_HALT);
420 chip_id = wl1271_read32(wl, CHIP_ID_B);
422 wl1271_debug(DEBUG_BOOT, "chip id after firmware boot: 0x%x", chip_id);
424 if (chip_id != wl->chip.id) {
425 wl1271_error("chip id doesn't match after firmware boot");
429 /* wait for init to complete */
431 while (loop++ < INIT_LOOP) {
432 udelay(INIT_LOOP_DELAY);
433 intr = wl1271_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR);
435 if (intr == 0xffffffff) {
436 wl1271_error("error reading hardware complete "
440 /* check that ACX_INTR_INIT_COMPLETE is enabled */
441 else if (intr & WL1271_ACX_INTR_INIT_COMPLETE) {
442 wl1271_write32(wl, ACX_REG_INTERRUPT_ACK,
443 WL1271_ACX_INTR_INIT_COMPLETE);
448 if (loop > INIT_LOOP) {
449 wl1271_error("timeout waiting for the hardware to "
450 "complete initialization");
454 /* get hardware config command mail box */
455 wl->cmd_box_addr = wl1271_read32(wl, REG_COMMAND_MAILBOX_PTR);
457 /* get hardware config event mail box */
458 wl->event_box_addr = wl1271_read32(wl, REG_EVENT_MAILBOX_PTR);
460 /* set the working partition to its "running" mode offset */
461 wl1271_set_partition(wl, &part_table[PART_WORK]);
463 wl1271_debug(DEBUG_MAILBOX, "cmd_box_addr 0x%x event_box_addr 0x%x",
464 wl->cmd_box_addr, wl->event_box_addr);
466 wl1271_boot_fw_version(wl);
469 * in case of full asynchronous mode the firmware event must be
470 * ready to receive event from the command mailbox
473 /* unmask required mbox events */
474 wl->event_mask = BSS_LOSE_EVENT_ID |
475 SCAN_COMPLETE_EVENT_ID |
477 JOIN_EVENT_COMPLETE_ID |
478 DISCONNECT_EVENT_COMPLETE_ID |
479 RSSI_SNR_TRIGGER_0_EVENT_ID |
480 PSPOLL_DELIVERY_FAILURE_EVENT_ID |
481 SOFT_GEMINI_SENSE_EVENT_ID;
483 if (wl->bss_type == BSS_TYPE_AP_BSS)
484 wl->event_mask |= STA_REMOVE_COMPLETE_EVENT_ID;
486 wl->event_mask |= DUMMY_PACKET_EVENT_ID;
488 ret = wl1271_event_unmask(wl);
490 wl1271_error("EVENT mask setting failed");
494 wl1271_event_mbox_config(wl);
496 /* firmware startup completed */
500 static int wl1271_boot_write_irq_polarity(struct wl1271 *wl)
504 polarity = wl1271_top_reg_read(wl, OCP_REG_POLARITY);
506 /* We use HIGH polarity, so unset the LOW bit */
507 polarity &= ~POLARITY_LOW;
508 wl1271_top_reg_write(wl, OCP_REG_POLARITY, polarity);
513 static void wl1271_boot_hw_version(struct wl1271 *wl)
517 fuse = wl1271_top_reg_read(wl, REG_FUSE_DATA_2_1);
518 fuse = (fuse & PG_VER_MASK) >> PG_VER_OFFSET;
520 wl->hw_pg_ver = (s8)fuse;
522 if (((wl->hw_pg_ver & PG_MAJOR_VER_MASK) >> PG_MAJOR_VER_OFFSET) < 3)
523 wl->quirks |= WL12XX_QUIRK_END_OF_TRANSACTION;
527 * WL128x has two clocks input - TCXO and FREF.
528 * TCXO is the main clock of the device, while FREF is used to sync
529 * between the GPS and the cellular modem.
530 * In cases where TCXO is 32.736MHz or 16.368MHz, the FREF will be used
531 * as the WLAN/BT main clock.
533 static int wl128x_switch_fref(struct wl1271 *wl, bool *is_ref_clk)
537 /* if working on XTAL-only mode go directly to TCXO TO FREF SWITCH */
538 if ((wl->ref_clock == CONF_REF_CLK_38_4_M_XTAL) ||
539 (wl->ref_clock == CONF_REF_CLK_26_M_XTAL))
542 /* Read clock source FREF or TCXO */
543 sys_clk_cfg_val = wl1271_top_reg_read(wl, SYS_CLK_CFG_REG);
545 if (sys_clk_cfg_val & PRCM_CM_EN_MUX_WLAN_FREF) {
546 /* if bit 3 is set - working with FREF clock */
547 wl1271_debug(DEBUG_BOOT, "working with FREF clock, skip"
552 /* if bit 3 is clear - working with TCXO clock */
553 wl1271_debug(DEBUG_BOOT, "working with TCXO clock");
555 /* TCXO to FREF switch, check TXCO clock config */
556 if ((wl->tcxo_clock != WL12XX_TCXOCLOCK_16_368) &&
557 (wl->tcxo_clock != WL12XX_TCXOCLOCK_32_736)) {
559 * not 16.368Mhz and not 32.736Mhz - skip to
560 * configure ELP stage
562 wl1271_debug(DEBUG_BOOT, "NEW PLL ALGO:"
563 " TcxoRefClk=%d - not 16.368Mhz and not"
564 " 32.736Mhz - skip to configure ELP"
565 " stage", wl->tcxo_clock);
569 wl1271_debug(DEBUG_BOOT, "NEW PLL ALGO:"
570 "TcxoRefClk=%d - 16.368Mhz or 32.736Mhz"
571 " - TCXO to FREF switch",
581 static int wl128x_boot_clk(struct wl1271 *wl, bool *is_ref_clk)
583 if (wl128x_switch_fref(wl, is_ref_clk)) {
584 wl1271_debug(DEBUG_BOOT, "XTAL-only mode go directly to"
585 " TCXO TO FREF SWITCH");
586 /* TCXO to FREF switch - for PG2.0 */
587 wl1271_top_reg_write(wl, WL_SPARE_REG,
590 wl1271_top_reg_write(wl, SYS_CLK_CFG_REG,
591 WL_CLK_REQ_TYPE_PG2 | MCS_PLL_CLK_SEL_FREF);
597 /* Set bit 2 in spare register to avoid illegal access */
598 wl1271_top_reg_write(wl, WL_SPARE_REG, WL_SPARE_VAL);
600 /* working with TCXO clock */
601 if ((*is_ref_clk == false) &&
602 ((wl->tcxo_clock == WL12XX_TCXOCLOCK_16_8) ||
603 (wl->tcxo_clock == WL12XX_TCXOCLOCK_33_6))) {
604 wl1271_debug(DEBUG_BOOT, "16_8_M or 33_6_M TCXO detected");
606 /* Manually Configure MCS PLL settings PG2.0 Only */
607 wl1271_top_reg_write(wl, MCS_PLL_M_REG, MCS_PLL_M_REG_VAL);
608 wl1271_top_reg_write(wl, MCS_PLL_N_REG, MCS_PLL_N_REG_VAL);
609 wl1271_top_reg_write(wl, MCS_PLL_CONFIG_REG,
610 MCS_PLL_CONFIG_REG_VAL);
613 u16 mcs_pll_config_val;
616 * Configure MCS PLL settings to FREF Freq
617 * Set the values that determine the time elapse since the PLL's
618 * get their enable signal until the lock indication is set
620 wl1271_top_reg_write(wl, PLL_LOCK_COUNTERS_REG,
621 PLL_LOCK_COUNTERS_COEX | PLL_LOCK_COUNTERS_MCS);
623 mcs_pll_config_val = wl1271_top_reg_read(wl,
626 * Set the MCS PLL input frequency value according to the
627 * reference clock value detected/read
629 if (*is_ref_clk == false) {
630 if ((wl->tcxo_clock == WL12XX_TCXOCLOCK_19_2) ||
631 (wl->tcxo_clock == WL12XX_TCXOCLOCK_38_4))
633 else if ((wl->tcxo_clock == WL12XX_TCXOCLOCK_26)
635 (wl->tcxo_clock == WL12XX_TCXOCLOCK_52))
640 if ((wl->ref_clock == CONF_REF_CLK_19_2_E) ||
641 (wl->ref_clock == CONF_REF_CLK_38_4_E))
643 else if ((wl->ref_clock == CONF_REF_CLK_26_E) ||
644 (wl->ref_clock == CONF_REF_CLK_52_E))
650 mcs_pll_config_val |= (pll_config << (MCS_SEL_IN_FREQ_SHIFT)) &
651 (MCS_SEL_IN_FREQ_MASK);
652 wl1271_top_reg_write(wl, MCS_PLL_CONFIG_REG,
659 static int wl127x_boot_clk(struct wl1271 *wl)
664 wl1271_boot_hw_version(wl);
666 if (wl->ref_clock == CONF_REF_CLK_19_2_E ||
667 wl->ref_clock == CONF_REF_CLK_38_4_E ||
668 wl->ref_clock == CONF_REF_CLK_38_4_M_XTAL)
669 /* ref clk: 19.2/38.4/38.4-XTAL */
671 else if (wl->ref_clock == CONF_REF_CLK_26_E ||
672 wl->ref_clock == CONF_REF_CLK_52_E)
678 if (wl->ref_clock != CONF_REF_CLK_19_2_E) {
680 /* Set clock type (open drain) */
681 val = wl1271_top_reg_read(wl, OCP_REG_CLK_TYPE);
682 val &= FREF_CLK_TYPE_BITS;
683 wl1271_top_reg_write(wl, OCP_REG_CLK_TYPE, val);
685 /* Set clock pull mode (no pull) */
686 val = wl1271_top_reg_read(wl, OCP_REG_CLK_PULL);
688 wl1271_top_reg_write(wl, OCP_REG_CLK_PULL, val);
691 /* Set clock polarity */
692 val = wl1271_top_reg_read(wl, OCP_REG_CLK_POLARITY);
693 val &= FREF_CLK_POLARITY_BITS;
694 val |= CLK_REQ_OUTN_SEL;
695 wl1271_top_reg_write(wl, OCP_REG_CLK_POLARITY, val);
698 wl1271_write32(wl, PLL_PARAMETERS, clk);
700 pause = wl1271_read32(wl, PLL_PARAMETERS);
702 wl1271_debug(DEBUG_BOOT, "pause1 0x%x", pause);
704 pause &= ~(WU_COUNTER_PAUSE_VAL);
705 pause |= WU_COUNTER_PAUSE_VAL;
706 wl1271_write32(wl, WU_COUNTER_PAUSE, pause);
711 /* uploads NVS and firmware */
712 int wl1271_load_firmware(struct wl1271 *wl)
716 bool is_ref_clk = false;
718 if (wl->chip.id == CHIP_ID_1283_PG20) {
719 ret = wl128x_boot_clk(wl, &is_ref_clk);
723 ret = wl127x_boot_clk(wl);
728 /* Continue the ELP wake up sequence */
729 wl1271_write32(wl, WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
732 wl1271_set_partition(wl, &part_table[PART_DRPW]);
734 /* Read-modify-write DRPW_SCRATCH_START register (see next state)
735 to be used by DRPw FW. The RTRIM value will be added by the FW
736 before taking DRPw out of reset */
738 wl1271_debug(DEBUG_BOOT, "DRPW_SCRATCH_START %08x", DRPW_SCRATCH_START);
739 clk = wl1271_read32(wl, DRPW_SCRATCH_START);
741 wl1271_debug(DEBUG_BOOT, "clk2 0x%x", clk);
743 if (wl->chip.id == CHIP_ID_1283_PG20) {
744 if (is_ref_clk == false)
745 clk |= ((wl->tcxo_clock & 0x3) << 1) << 4;
747 clk |= ((wl->ref_clock & 0x3) << 1) << 4;
749 clk |= (wl->ref_clock << 1) << 4;
752 wl1271_write32(wl, DRPW_SCRATCH_START, clk);
754 wl1271_set_partition(wl, &part_table[PART_WORK]);
756 /* Disable interrupts */
757 wl1271_write32(wl, ACX_REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
759 ret = wl1271_boot_soft_reset(wl);
763 /* 2. start processing NVS file */
764 ret = wl1271_boot_upload_nvs(wl);
768 /* write firmware's last address (ie. it's length) to
769 * ACX_EEPROMLESS_IND_REG */
770 wl1271_debug(DEBUG_BOOT, "ACX_EEPROMLESS_IND_REG");
772 wl1271_write32(wl, ACX_EEPROMLESS_IND_REG, ACX_EEPROMLESS_IND_REG);
774 tmp = wl1271_read32(wl, CHIP_ID_B);
776 wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);
778 /* 6. read the EEPROM parameters */
779 tmp = wl1271_read32(wl, SCR_PAD2);
781 /* WL1271: The reference driver skips steps 7 to 10 (jumps directly
784 if (wl->chip.id == CHIP_ID_1283_PG20)
785 wl1271_top_reg_write(wl, SDIO_IO_DS, HCI_IO_DS_6MA);
787 ret = wl1271_boot_upload_firmware(wl);
794 EXPORT_SYMBOL_GPL(wl1271_load_firmware);
796 int wl1271_boot(struct wl1271 *wl)
800 /* upload NVS and firmware */
801 ret = wl1271_load_firmware(wl);
805 /* 10.5 start firmware */
806 ret = wl1271_boot_run_firmware(wl);
810 ret = wl1271_boot_write_irq_polarity(wl);
814 wl1271_write32(wl, ACX_REG_INTERRUPT_MASK,
815 WL1271_ACX_ALL_EVENTS_VECTOR);
817 /* Enable firmware interrupts now */
818 wl1271_boot_enable_interrupts(wl);
820 /* set the wl1271 default filters */
821 wl1271_set_default_filters(wl);
823 wl1271_event_mbox_config(wl);