1 /******************************************************************************
3 * Copyright(c) 2009-2010 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
26 * Larry Finger <Larry.Finger@lwfinger.net>
28 *****************************************************************************/
30 #ifndef __RTL_WIFI_H__
31 #define __RTL_WIFI_H__
33 #include <linux/sched.h>
34 #include <linux/firmware.h>
35 #include <linux/version.h>
36 #include <linux/etherdevice.h>
37 #include <linux/usb.h>
38 #include <net/mac80211.h>
41 #define RF_CHANGE_BY_INIT 0
42 #define RF_CHANGE_BY_IPS BIT(28)
43 #define RF_CHANGE_BY_PS BIT(29)
44 #define RF_CHANGE_BY_HW BIT(30)
45 #define RF_CHANGE_BY_SW BIT(31)
47 #define IQK_ADDA_REG_NUM 16
48 #define IQK_MAC_REG_NUM 4
50 #define MAX_KEY_LEN 61
51 #define KEY_BUF_SIZE 5
54 /*aci: 0x00 Best Effort*/
55 /*aci: 0x01 Background*/
58 /*Max: define total number.*/
64 #define QOS_QUEUE_NUM 4
65 #define RTL_MAC80211_NUM_QUEUE 5
67 #define QBSS_LOAD_SIZE 5
68 #define MAX_WMMELE_LENGTH 64
70 /*slot time for 11g. */
71 #define RTL_SLOT_TIME_9 9
72 #define RTL_SLOT_TIME_20 20
74 /*related with tcp/ip. */
76 #define ETH_P_PAE 0x888E /*Port Access Entity (IEEE 802.1X) */
77 #define ETH_P_IP 0x0800 /*Internet Protocol packet */
78 #define ETH_P_ARP 0x0806 /*Address Resolution packet */
80 #define PROTOC_TYPE_SIZE 2
82 /*related with 802.11 frame*/
83 #define MAC80211_3ADDR_LEN 24
84 #define MAC80211_4ADDR_LEN 30
105 RTL_STATUS_INTERFACE_START = 0,
109 HARDWARE_TYPE_RTL8192E,
110 HARDWARE_TYPE_RTL8192U,
111 HARDWARE_TYPE_RTL8192SE,
112 HARDWARE_TYPE_RTL8192SU,
113 HARDWARE_TYPE_RTL8192CE,
114 HARDWARE_TYPE_RTL8192CU,
115 HARDWARE_TYPE_RTL8192DE,
116 HARDWARE_TYPE_RTL8192DU,
122 #define IS_HARDWARE_TYPE_8192CE(rtlhal) \
123 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CE)
125 enum scan_operation_backup_opt {
148 u32 rfswitch_control;
151 u32 rfrxiq_imbalance;
153 u32 rftxiq_imbalance;
156 u32 rflssi_readbackpi;
160 IO_CMD_PAUSE_DM_BY_SCAN = 0,
161 IO_CMD_RESUME_DM_BY_SCAN = 1,
166 HW_VAR_MULTICAST_REG,
170 HW_VAR_SECURITY_CONF,
171 HW_VAR_BEACON_INTERVAL,
173 HW_VAR_LISTEN_INTERVAL,
186 HW_VAR_RATE_FALLBACK_CONTROL,
187 HW_VAR_CONTENTION_WINDOW,
192 HW_VAR_AMPDU_MIN_SPACE,
193 HW_VAR_SHORTGI_DENSITY,
195 HW_VAR_MCS_RATE_AVAILABLE,
198 HW_VAR_DIS_Req_Qsize,
199 HW_VAR_CCX_CHNL_LOAD,
200 HW_VAR_CCX_NOISE_HISTOGRAM,
207 HW_VAR_SET_DEV_POWER,
217 HW_VAR_USER_CONTROL_TURBO_MODE,
223 HW_VAR_AUTOLOAD_STATUS,
224 HW_VAR_RF_2R_DISABLE,
226 HW_VAR_H2C_FW_PWRMODE,
227 HW_VAR_H2C_FW_JOINBSSRPT,
228 HW_VAR_FW_PSMODE_STATUS,
229 HW_VAR_1X1_RECV_COMBINE,
230 HW_VAR_STOP_SEND_BEACON,
235 HW_VAR_H2C_FW_UPDATE_GTK,
238 HW_VAR_WF_IS_MAC_ADDR,
239 HW_VAR_H2C_FW_OFFLOAD,
242 HW_VAR_HANDLE_FW_C2H,
243 HW_VAR_DL_FW_RSVD_PAGE,
245 HW_VAR_HW_SEQ_ENABLE,
250 HW_VAR_SWITCH_EPHY_WoWLAN,
251 HW_VAR_INT_MIGRATION,
262 enum _RT_MEDIA_STATUS {
263 RT_MEDIA_DISCONNECT = 0,
269 RT_CID_8187_ALPHA0 = 1,
270 RT_CID_8187_SERCOMM_PS = 2,
271 RT_CID_8187_HW_LED = 3,
272 RT_CID_8187_NETGEAR = 4,
274 RT_CID_819x_CAMEO = 6,
275 RT_CID_819x_RUNTOP = 7,
276 RT_CID_819x_Senao = 8,
278 RT_CID_819x_Netcore = 10,
279 RT_CID_Nettronix = 11,
283 RT_CID_819x_ALPHA = 15,
284 RT_CID_819x_Sitecom = 16,
286 RT_CID_819x_Lenovo = 18,
287 RT_CID_819x_QMI = 19,
288 RT_CID_819x_Edimax_Belkin = 20,
289 RT_CID_819x_Sercomm_Belkin = 21,
290 RT_CID_819x_CAMEO1 = 22,
291 RT_CID_819x_MSI = 23,
292 RT_CID_819x_Acer = 24,
294 RT_CID_819x_CLEVO = 28,
295 RT_CID_819x_Arcadyan_Belkin = 29,
296 RT_CID_819x_SAMSUNG = 30,
297 RT_CID_819x_WNC_COREGA = 31,
298 RT_CID_819x_Foxcoon = 32,
299 RT_CID_819x_DELL = 33,
305 HW_DESC_TX_NEXTDESC_ADDR,
313 PRIME_CHNL_OFFSET_DONT_CARE = 0,
314 PRIME_CHNL_OFFSET_LOWER = 1,
315 PRIME_CHNL_OFFSET_UPPER = 2,
324 enum ht_channel_width {
325 HT_CHANNEL_WIDTH_20 = 0,
326 HT_CHANNEL_WIDTH_20_40 = 1,
329 /* Ref: 802.11i sepc D10.0 7.3.2.25.1
330 Cipher Suites Encryption Algorithms */
333 WEP40_ENCRYPTION = 1,
335 RSERVED_ENCRYPTION = 3,
336 AESCCMP_ENCRYPTION = 4,
337 WEP104_ENCRYPTION = 5,
342 _HAL_STATE_START = 1,
365 EFUSE_HWSET_MAX_SIZE,
380 RTL_IMR_BCNDMAINT6, /*Beacon DMA Interrupt 6 */
381 RTL_IMR_BCNDMAINT5, /*Beacon DMA Interrupt 5 */
382 RTL_IMR_BCNDMAINT4, /*Beacon DMA Interrupt 4 */
383 RTL_IMR_BCNDMAINT3, /*Beacon DMA Interrupt 3 */
384 RTL_IMR_BCNDMAINT2, /*Beacon DMA Interrupt 2 */
385 RTL_IMR_BCNDMAINT1, /*Beacon DMA Interrupt 1 */
386 RTL_IMR_BCNDOK8, /*Beacon Queue DMA OK Interrup 8 */
387 RTL_IMR_BCNDOK7, /*Beacon Queue DMA OK Interrup 7 */
388 RTL_IMR_BCNDOK6, /*Beacon Queue DMA OK Interrup 6 */
389 RTL_IMR_BCNDOK5, /*Beacon Queue DMA OK Interrup 5 */
390 RTL_IMR_BCNDOK4, /*Beacon Queue DMA OK Interrup 4 */
391 RTL_IMR_BCNDOK3, /*Beacon Queue DMA OK Interrup 3 */
392 RTL_IMR_BCNDOK2, /*Beacon Queue DMA OK Interrup 2 */
393 RTL_IMR_BCNDOK1, /*Beacon Queue DMA OK Interrup 1 */
394 RTL_IMR_TIMEOUT2, /*Timeout interrupt 2 */
395 RTL_IMR_TIMEOUT1, /*Timeout interrupt 1 */
396 RTL_IMR_TXFOVW, /*Transmit FIFO Overflow */
397 RTL_IMR_PSTIMEOUT, /*Power save time out interrupt */
398 RTL_IMR_BcnInt, /*Beacon DMA Interrupt 0 */
399 RTL_IMR_RXFOVW, /*Receive FIFO Overflow */
400 RTL_IMR_RDU, /*Receive Descriptor Unavailable */
401 RTL_IMR_ATIMEND, /*For 92C,ATIM Window End Interrupt */
402 RTL_IMR_BDOK, /*Beacon Queue DMA OK Interrup */
403 RTL_IMR_HIGHDOK, /*High Queue DMA OK Interrupt */
404 RTL_IMR_TBDOK, /*Transmit Beacon OK interrup */
405 RTL_IMR_MGNTDOK, /*Management Queue DMA OK Interrupt */
406 RTL_IMR_TBDER, /*For 92C,Transmit Beacon Error Interrupt */
407 RTL_IMR_BKDOK, /*AC_BK DMA OK Interrupt */
408 RTL_IMR_BEDOK, /*AC_BE DMA OK Interrupt */
409 RTL_IMR_VIDOK, /*AC_VI DMA OK Interrupt */
410 RTL_IMR_VODOK, /*AC_VO DMA Interrupt */
411 RTL_IMR_ROK, /*Receive DMA OK Interrupt */
412 RTL_IBSS_INT_MASKS, /*(RTL_IMR_BcnInt|RTL_IMR_TBDOK|RTL_IMR_TBDER)*/
414 /*CCK Rates, TxHT = 0 */
420 /*OFDM Rates, TxHT = 0 */
437 /*Firmware PS mode for control LPS.*/
439 FW_PS_ACTIVE_MODE = 0,
444 FW_PS_UAPSD_WMM_MODE = 5,
445 FW_PS_UAPSD_MODE = 6,
447 FW_PS_WWLAN_MODE = 8,
448 FW_PS_PM_Radio_Off = 9,
449 FW_PS_PM_Card_Disable = 10,
453 EACTIVE, /*Active/Continuous access. */
454 EMAXPS, /*Max power save mode. */
455 EFASTPS, /*Fast power save mode. */
456 EAUTOPS, /*Auto power save mode. */
461 LED_CTL_POWER_ON = 1,
466 LED_CTL_SITE_SURVEY = 6,
467 LED_CTL_POWER_OFF = 7,
468 LED_CTL_START_TO_LINK = 8,
469 LED_CTL_START_WPS = 9,
470 LED_CTL_STOP_WPS = 10,
481 /*acm implementation method.*/
483 eAcmWay0_SwAndHw = 0,
489 Ref: WMM spec 2.2.2: WME Parameter Element, p.12.*/
503 WIRELESS_MODE_UNKNOWN = 0x00,
504 WIRELESS_MODE_A = 0x01,
505 WIRELESS_MODE_B = 0x02,
506 WIRELESS_MODE_G = 0x04,
507 WIRELESS_MODE_AUTO = 0x08,
508 WIRELESS_MODE_N_24G = 0x10,
509 WIRELESS_MODE_N_5G = 0x20
512 enum ratr_table_mode {
513 RATR_INX_WIRELESS_NGB = 0,
514 RATR_INX_WIRELESS_NG = 1,
515 RATR_INX_WIRELESS_NB = 2,
516 RATR_INX_WIRELESS_N = 3,
517 RATR_INX_WIRELESS_GB = 4,
518 RATR_INX_WIRELESS_G = 5,
519 RATR_INX_WIRELESS_B = 6,
520 RATR_INX_WIRELESS_MC = 7,
521 RATR_INX_WIRELESS_A = 8,
524 enum rtl_link_state {
526 MAC80211_LINKING = 1,
528 MAC80211_LINKED_SCANNING = 3,
545 struct octet_string {
550 struct rtl_hdr_3addr {
560 struct rtl_info_element {
566 struct rtl_probe_rsp {
567 struct rtl_hdr_3addr header;
569 __le16 beacon_interval;
571 /*SSID, supported rates, FH params, DS params,
572 CF params, IBSS params, TIM (if beacon), RSN */
573 struct rtl_info_element info_element[0];
577 /*ledpin Identify how to implement this SW led.*/
580 enum rtl_led_pin ledpin;
586 struct rtl_led sw_led0;
587 struct rtl_led sw_led1;
590 struct rtl_qos_parameters {
598 struct rt_smooth_data {
599 u32 elements[100]; /*array to store values */
600 u32 index; /*index to current array to store */
601 u32 total_num; /*num of valid elements */
602 u32 total_val; /*sum of valid elements */
605 struct false_alarm_statistics {
607 u32 cnt_rate_illegal;
624 struct wireless_stats {
625 unsigned long txbytesunicast;
626 unsigned long txbytesmulticast;
627 unsigned long txbytesbroadcast;
628 unsigned long rxbytesunicast;
631 /*Correct smoothed ss in Dbm, only used
632 in driver to report real power now. */
633 long recv_signal_power;
635 long last_sigstrength_inpercent;
637 u32 rssi_calculate_cnt;
639 /*Transformed, in dbm. Beautified signal
640 strength for UI, not correct. */
641 long signal_strength;
643 u8 rx_rssi_percentage[4];
644 u8 rx_evm_percentage[2];
646 struct rt_smooth_data ui_rssi;
647 struct rt_smooth_data ui_link_quality;
650 struct rate_adaptive {
651 u8 rate_adaptive_disabled;
655 u32 high_rssi_thresh_for_ra;
656 u32 high2low_rssi_thresh_for_ra;
657 u8 low2high_rssi_thresh_for_ra40m;
658 u32 low_rssi_thresh_for_ra40M;
659 u8 low2high_rssi_thresh_for_ra20m;
660 u32 low_rssi_thresh_for_ra20M;
661 u32 upper_rssi_threshold_ratr;
662 u32 middleupper_rssi_threshold_ratr;
663 u32 middle_rssi_threshold_ratr;
664 u32 middlelow_rssi_threshold_ratr;
665 u32 low_rssi_threshold_ratr;
666 u32 ultralow_rssi_threshold_ratr;
667 u32 low_rssi_threshold_ratr_40m;
668 u32 low_rssi_threshold_ratr_20m;
671 u32 ping_rssi_thresh_for_ra;
676 struct regd_pair_mapping {
682 struct rtl_regulatory {
690 struct regd_pair_mapping *regpair;
694 bool rfkill_state; /*0 is off, 1 is on */
698 struct bb_reg_def phyreg_def[4]; /*Radio A/B/C/D */
699 struct init_gain initgain_backup;
700 enum io_type current_io_type;
705 u8 set_bwmode_inprogress;
706 u8 sw_chnl_inprogress;
711 u8 set_io_inprogress;
713 /*record for power tracking*/
725 u32 reg_c04, reg_c08, reg_874;
727 u32 iqk_mac_backup[IQK_MAC_REG_NUM];
728 u32 iqk_bb_backup[10];
734 /* 3 groups of pwr diff by rates*/
735 u32 mcs_txpwrlevel_origoffset[4][16];
736 u8 default_initialgain[4];
738 /*the current Tx power level*/
740 u8 cur_ofdm24g_txpwridx;
742 u32 rfreg_chnlval[2];
752 #define MAX_TID_COUNT 9
753 #define RTL_AGG_OFF 0
755 #define RTL_AGG_EMPTYING_HW_QUEUE_ADDBA 2
756 #define RTL_AGG_EMPTYING_HW_QUEUE_DELBA 3
767 struct rtl_tid_data {
769 struct rtl_ht_agg agg;
775 struct mutex bb_mutex;
778 unsigned long pci_mem_end; /*shared mem end */
779 unsigned long pci_mem_start; /*shared mem start */
782 unsigned long pci_base_addr; /*device I/O address */
784 void (*write8_async) (struct rtl_priv *rtlpriv, u32 addr, u8 val);
785 void (*write16_async) (struct rtl_priv *rtlpriv, u32 addr, u16 val);
786 void (*write32_async) (struct rtl_priv *rtlpriv, u32 addr, u32 val);
787 int (*writeN_async) (struct rtl_priv *rtlpriv, u32 addr, u16 len,
790 u8(*read8_sync) (struct rtl_priv *rtlpriv, u32 addr);
791 u16(*read16_sync) (struct rtl_priv *rtlpriv, u32 addr);
792 u32(*read32_sync) (struct rtl_priv *rtlpriv, u32 addr);
793 int (*readN_sync) (struct rtl_priv *rtlpriv, u32 addr, u16 len,
799 u8 mac_addr[ETH_ALEN];
800 u8 mac80211_registered;
806 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
807 struct ieee80211_hw *hw;
808 struct ieee80211_vif *vif;
809 enum nl80211_iftype opmode;
811 /*Probe Beacon management */
812 struct rtl_tid_data tids[MAX_TID_COUNT];
813 enum rtl_link_state link_state;
830 u8 mcs[16]; /*16 bytes mcs for HT rates.*/
831 u32 basic_rates; /*b/g rates*/
836 u8 mode; /*wireless mode*/
841 u8 cur_40_prime_sc_bk;
847 /*IBSS*/ int beacon_interval;
849 /*AMPDU*/ u8 min_space_cfg; /*For Min spacing configurations */
851 u8 current_ampdu_factor;
852 u8 current_ampdu_density;
855 struct ieee80211_tx_queue_params edca_param[RTL_MAC80211_NUM_QUEUE];
856 struct rtl_qos_parameters ac[AC_MAX];
860 struct ieee80211_hw *hw;
862 enum intf_type interface;
863 u16 hw_type; /*92c or 92d or 92s and so on */
865 u8 version; /*version of chip */
866 u8 state; /*stop 0, start 1 */
870 bool b_h2c_setinprogress;
873 /*Reserve page start offset except beacon in TxQ. */
874 u8 fw_rsvdpage_startoffset;
877 struct rtl_security {
883 /*Encryption Algorithm for Unicast Packet */
884 enum rt_enc_alg pairwise_enc_algorithm;
885 /*Encryption Algorithm for Brocast/Multicast */
886 enum rt_enc_alg group_enc_algorithm;
888 /*local Key buffer, indx 0 is for
889 pairwise key 1-4 is for agoup key. */
890 u8 key_buf[KEY_BUF_SIZE][MAX_KEY_LEN];
891 u8 key_len[KEY_BUF_SIZE];
893 /*The pointer of Pairwise Key,
894 it always points to KeyBuf[4] */
899 /*PHY status for DM */
900 long entry_min_undecoratedsmoothed_pwdb;
901 long undecorated_smoothed_pwdb; /*out dm */
902 long entry_max_undecoratedsmoothed_pwdb;
903 bool b_dm_initialgain_enable;
904 bool bdynamic_txpower_enable;
905 bool bcurrent_turbo_edca;
906 bool bis_any_nonbepkts; /*out dm */
907 bool bis_cur_rdlstate;
908 bool btxpower_trackingInit;
909 bool b_disable_framebursting;
911 bool btxpower_tracking;
913 bool brfpath_rxenable[4];
919 u8 dynamic_txhighpower_lvl; /*Tx high power level */
920 u8 dm_flag; /*Indicate if each dynamic mechanism's status. */
922 u8 txpower_track_control;
928 #define EFUSE_MAX_LOGICAL_SIZE 128
933 u16 max_physical_size;
934 u8 contents[EFUSE_MAX_LOGICAL_SIZE];
936 u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE];
938 u8 efuse_usedpercentage;
940 u8 autoload_failflag;
948 u16 eeprom_channelplan;
953 bool b_txpwr_fromeprom;
955 u8 eeprom_pwrlimit_ht20[3];
956 u8 eeprom_pwrlimit_ht40[3];
957 u8 eeprom_chnlarea_txpwr_cck[2][3];
958 u8 eeprom_chnlarea_txpwr_ht40_1s[2][3];
959 u8 eeprom_chnlarea_txpwr_ht40_2sdiif[2][3];
960 u8 txpwrlevel_cck[2][14];
961 u8 txpwrlevel_ht40_1s[2][14]; /*For HT 40MHZ pwr */
962 u8 txpwrlevel_ht40_2s[2][14]; /*For HT 40MHZ pwr */
965 u8 pwrgroup_ht20[2][14];
966 u8 pwrgroup_ht40[2][14];
968 char txpwr_ht20diff[2][14]; /*HT 20<->40 Pwr diff */
969 u8 txpwr_legacyhtdiff[2][14]; /*For HT<->legacy pwr diff */
971 u8 eeprom_regulatory;
972 u8 eeprom_thermalmeter;
973 /*ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 */
976 u8 legacy_ht_txpowerdiff; /*Legacy to HT rate power diff */
977 bool b_apk_thermalmeterignore;
981 bool set_rfpowerstate_inprogress;
982 bool b_in_powersavemode;
983 bool rfchange_inprogress;
984 bool b_swrf_processing;
987 u32 last_sleep_jiffies;
988 u32 last_awake_jiffies;
989 u32 last_delaylps_stamp_jiffies;
993 * If it supports ASPM, Offset[560h] = 0x40,
994 * otherwise Offset[560h] = 0x00.
997 bool b_support_backdoor;
1000 enum rt_psmode dot11_psmode; /*Power save mode configured. */
1004 /*For Fw control LPS mode */
1005 u8 b_reg_fwctrl_lps;
1006 /*Record Fw PS mode status. */
1007 bool b_fw_current_inpsmode;
1008 u8 reg_max_lps_awakeintvl;
1020 /*just for PCIE ASPM */
1021 u8 const_amdpci_aspm;
1023 enum rf_pwrstate inactive_pwrstate;
1024 enum rf_pwrstate rfpwr_state; /*cur power state */
1032 u16 rate; /*in 100 kbps */
1033 u8 received_channel;
1042 u8 signalquality; /*in 0-100 index. */
1044 * Real power in dBm for this packet,
1045 * no beautification and aggregation.
1047 s32 recvsignalpower;
1048 s8 rxpower; /*in dBm Translate from PWdB */
1049 u8 signalstrength; /*in 0-100 index. */
1053 u16 b_shortpreamble:1;
1063 bool rx_is40Mhzpacket;
1065 u8 rx_mimo_signalstrength[4]; /*in 0~100 index */
1066 s8 rx_mimo_signalquality[2];
1067 bool b_packet_matchbssid;
1069 bool b_packet_toself;
1070 bool b_packet_beacon; /*for rssi */
1071 char cck_adc_pwdb[4]; /*for rx path selection */
1074 struct rt_link_detect {
1075 u32 num_tx_in4period[4];
1076 u32 num_rx_in4period[4];
1078 u32 num_tx_inperiod;
1079 u32 num_rx_inperiod;
1082 bool b_higher_busytraffic;
1083 bool b_higher_busyrxtraffic;
1086 struct rtl_tcb_desc {
1094 u8 b_rts_use_shortpreamble:1;
1095 u8 b_rts_use_shortgi:1;
1101 u8 use_shortpreamble:1;
1102 u8 use_driver_rate:1;
1103 u8 disable_ratefallback:1;
1110 struct rtl_hal_ops {
1111 int (*init_sw_vars) (struct ieee80211_hw *hw);
1112 void (*deinit_sw_vars) (struct ieee80211_hw *hw);
1113 void (*read_chip_version)(struct ieee80211_hw *hw);
1114 void (*read_eeprom_info) (struct ieee80211_hw *hw);
1115 void (*interrupt_recognized) (struct ieee80211_hw *hw,
1116 u32 *p_inta, u32 *p_intb);
1117 int (*hw_init) (struct ieee80211_hw *hw);
1118 void (*hw_disable) (struct ieee80211_hw *hw);
1119 void (*enable_interrupt) (struct ieee80211_hw *hw);
1120 void (*disable_interrupt) (struct ieee80211_hw *hw);
1121 int (*set_network_type) (struct ieee80211_hw *hw,
1122 enum nl80211_iftype type);
1123 void (*set_bw_mode) (struct ieee80211_hw *hw,
1124 enum nl80211_channel_type ch_type);
1125 u8(*switch_channel) (struct ieee80211_hw *hw);
1126 void (*set_qos) (struct ieee80211_hw *hw, int aci);
1127 void (*set_bcn_reg) (struct ieee80211_hw *hw);
1128 void (*set_bcn_intv) (struct ieee80211_hw *hw);
1129 void (*update_interrupt_mask) (struct ieee80211_hw *hw,
1130 u32 add_msr, u32 rm_msr);
1131 void (*get_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
1132 void (*set_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
1133 void (*update_rate_table) (struct ieee80211_hw *hw);
1134 void (*update_rate_mask) (struct ieee80211_hw *hw, u8 rssi_level);
1135 void (*fill_tx_desc) (struct ieee80211_hw *hw,
1136 struct ieee80211_hdr *hdr, u8 *pdesc_tx,
1137 struct ieee80211_tx_info *info,
1138 struct sk_buff *skb, unsigned int queue_index);
1139 void (*fill_tx_cmddesc) (struct ieee80211_hw *hw, u8 *pdesc,
1140 bool b_firstseg, bool b_lastseg,
1141 struct sk_buff *skb);
1142 bool (*cmd_send_packet)(struct ieee80211_hw *hw, struct sk_buff *skb);
1143 bool(*query_rx_desc) (struct ieee80211_hw *hw,
1144 struct rtl_stats *stats,
1145 struct ieee80211_rx_status *rx_status,
1146 u8 *pdesc, struct sk_buff *skb);
1147 void (*set_channel_access) (struct ieee80211_hw *hw);
1148 bool(*radio_onoff_checking) (struct ieee80211_hw *hw, u8 *valid);
1149 void (*dm_watchdog) (struct ieee80211_hw *hw);
1150 void (*scan_operation_backup) (struct ieee80211_hw *hw, u8 operation);
1151 bool(*set_rf_power_state) (struct ieee80211_hw *hw,
1152 enum rf_pwrstate rfpwr_state);
1153 void (*led_control) (struct ieee80211_hw *hw,
1154 enum led_ctl_mode ledaction);
1155 void (*set_desc) (u8 *pdesc, bool istx, u8 desc_name, u8 *val);
1156 u32(*get_desc) (u8 *pdesc, bool istx, u8 desc_name);
1157 void (*tx_polling) (struct ieee80211_hw *hw, unsigned int hw_queue);
1158 void (*enable_hw_sec) (struct ieee80211_hw *hw);
1159 void (*set_key) (struct ieee80211_hw *hw, u32 key_index,
1160 u8 *p_macaddr, bool is_group, u8 enc_algo,
1161 bool is_wepkey, bool clear_all);
1162 void (*init_sw_leds) (struct ieee80211_hw *hw);
1163 void (*deinit_sw_leds) (struct ieee80211_hw *hw);
1164 u32(*get_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask);
1165 void (*set_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
1167 u32(*get_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
1168 u32 regaddr, u32 bitmask);
1169 void (*set_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
1170 u32 regaddr, u32 bitmask, u32 data);
1173 struct rtl_intf_ops {
1175 int (*adapter_start) (struct ieee80211_hw *hw);
1176 void (*adapter_stop) (struct ieee80211_hw *hw);
1178 int (*adapter_tx) (struct ieee80211_hw *hw, struct sk_buff *skb);
1179 int (*reset_trx_ring) (struct ieee80211_hw *hw);
1180 bool (*waitq_insert) (struct ieee80211_hw *hw, struct sk_buff *skb);
1183 void (*disable_aspm) (struct ieee80211_hw *hw);
1184 void (*enable_aspm) (struct ieee80211_hw *hw);
1189 struct rtl_mod_params {
1190 /* default: 0 = using hardware encryption */
1194 struct rtl_hal_usbint_cfg {
1201 void (*usb_rx_hdl)(struct ieee80211_hw *, struct sk_buff *);
1202 void (*usb_rx_segregate_hdl)(struct ieee80211_hw *, struct sk_buff *,
1203 struct sk_buff_head *);
1206 void (*usb_tx_cleanup)(struct ieee80211_hw *, struct sk_buff *);
1207 int (*usb_tx_post_hdl)(struct ieee80211_hw *, struct urb *,
1209 struct sk_buff *(*usb_tx_aggregate_hdl)(struct ieee80211_hw *,
1210 struct sk_buff_head *);
1212 /* endpoint mapping */
1213 int (*usb_endpoint_mapping)(struct ieee80211_hw *hw);
1214 u16 (*usb_mq_to_hwq)(u16 fc, u16 mac80211_queue_index);
1217 struct rtl_hal_cfg {
1220 struct rtl_hal_ops *ops;
1221 struct rtl_mod_params *mod_params;
1222 struct rtl_hal_usbint_cfg *usb_interface_cfg;
1224 /*this map used for some registers or vars
1225 defined int HAL but used in MAIN */
1226 u32 maps[RTL_VAR_MAP_MAX];
1232 struct mutex conf_mutex;
1235 spinlock_t ips_lock;
1236 spinlock_t irq_th_lock;
1237 spinlock_t h2c_lock;
1238 spinlock_t rf_ps_lock;
1240 spinlock_t lps_lock;
1241 spinlock_t tx_urb_lock;
1245 struct ieee80211_hw *hw;
1248 struct timer_list watchdog_timer;
1251 struct tasklet_struct irq_tasklet;
1252 struct tasklet_struct irq_prepare_bcn_tasklet;
1255 struct workqueue_struct *rtl_wq;
1256 struct delayed_work watchdog_wq;
1257 struct delayed_work ips_nic_off_wq;
1261 u32 dbgp_type[DBGP_TYPE_MAX];
1262 u32 global_debuglevel;
1263 u64 global_debugcomponents;
1267 struct rtl_locks locks;
1268 struct rtl_works works;
1269 struct rtl_mac mac80211;
1270 struct rtl_hal rtlhal;
1271 struct rtl_regulatory regd;
1272 struct rtl_rfkill rfkill;
1276 struct rtl_security sec;
1277 struct rtl_efuse efuse;
1279 struct rtl_ps_ctl psc;
1280 struct rate_adaptive ra;
1281 struct wireless_stats stats;
1282 struct rt_link_detect link_info;
1283 struct false_alarm_statistics falsealm_cnt;
1285 struct rtl_rate_priv *rate_priv;
1287 struct rtl_debug dbg;
1290 *hal_cfg : for diff cards
1291 *intf_ops : for diff interrface usb/pcie
1293 struct rtl_hal_cfg *cfg;
1294 struct rtl_intf_ops *intf_ops;
1296 /*this var will be set by set_bit,
1297 and was used to indicate status of
1298 interface or hardware */
1299 unsigned long status;
1301 /*This must be the last item so
1302 that it points to the data allocated
1303 beyond this structure like:
1304 rtl_pci_priv or rtl_usb_priv */
1308 #define rtl_priv(hw) (((struct rtl_priv *)(hw)->priv))
1309 #define rtl_mac(rtlpriv) (&((rtlpriv)->mac80211))
1310 #define rtl_hal(rtlpriv) (&((rtlpriv)->rtlhal))
1311 #define rtl_efuse(rtlpriv) (&((rtlpriv)->efuse))
1312 #define rtl_psc(rtlpriv) (&((rtlpriv)->psc))
1314 /****************************************
1315 mem access macro define start
1316 Call endian free function when
1317 1. Read/write packet content.
1318 2. Before write integer to IO.
1319 3. After read integer from IO.
1320 ****************************************/
1321 /* Convert little data endian to host */
1322 #define EF1BYTE(_val) \
1324 #define EF2BYTE(_val) \
1326 #define EF4BYTE(_val) \
1329 /* Read data from memory */
1330 #define READEF1BYTE(_ptr) \
1331 EF1BYTE(*((u8 *)(_ptr)))
1332 #define READEF2BYTE(_ptr) \
1333 EF2BYTE(*((u16 *)(_ptr)))
1334 #define READEF4BYTE(_ptr) \
1335 EF4BYTE(*((u32 *)(_ptr)))
1337 /* Write data to memory */
1338 #define WRITEEF1BYTE(_ptr, _val) \
1339 (*((u8 *)(_ptr))) = EF1BYTE(_val)
1340 #define WRITEEF2BYTE(_ptr, _val) \
1341 (*((u16 *)(_ptr))) = EF2BYTE(_val)
1342 #define WRITEEF4BYTE(_ptr, _val) \
1343 (*((u32 *)(_ptr))) = EF4BYTE(_val)
1346 BIT_LEN_MASK_32(0) => 0x00000000
1347 BIT_LEN_MASK_32(1) => 0x00000001
1348 BIT_LEN_MASK_32(2) => 0x00000003
1349 BIT_LEN_MASK_32(32) => 0xFFFFFFFF*/
1350 #define BIT_LEN_MASK_32(__bitlen) \
1351 (0xFFFFFFFF >> (32 - (__bitlen)))
1352 #define BIT_LEN_MASK_16(__bitlen) \
1353 (0xFFFF >> (16 - (__bitlen)))
1354 #define BIT_LEN_MASK_8(__bitlen) \
1355 (0xFF >> (8 - (__bitlen)))
1358 BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
1359 BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000*/
1360 #define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \
1361 (BIT_LEN_MASK_32(__bitlen) << (__bitoffset))
1362 #define BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) \
1363 (BIT_LEN_MASK_16(__bitlen) << (__bitoffset))
1364 #define BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) \
1365 (BIT_LEN_MASK_8(__bitlen) << (__bitoffset))
1368 Return 4-byte value in host byte ordering from
1369 4-byte pointer in little-endian system.*/
1370 #define LE_P4BYTE_TO_HOST_4BYTE(__pstart) \
1371 (EF4BYTE(*((u32 *)(__pstart))))
1372 #define LE_P2BYTE_TO_HOST_2BYTE(__pstart) \
1373 (EF2BYTE(*((u16 *)(__pstart))))
1374 #define LE_P1BYTE_TO_HOST_1BYTE(__pstart) \
1375 (EF1BYTE(*((u8 *)(__pstart))))
1378 Translate subfield (continuous bits in little-endian) of 4-byte
1379 value to host byte ordering.*/
1380 #define LE_BITS_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
1382 (LE_P4BYTE_TO_HOST_4BYTE(__pstart) >> (__bitoffset)) & \
1383 BIT_LEN_MASK_32(__bitlen) \
1385 #define LE_BITS_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
1387 (LE_P2BYTE_TO_HOST_2BYTE(__pstart) >> (__bitoffset)) & \
1388 BIT_LEN_MASK_16(__bitlen) \
1390 #define LE_BITS_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
1392 (LE_P1BYTE_TO_HOST_1BYTE(__pstart) >> (__bitoffset)) & \
1393 BIT_LEN_MASK_8(__bitlen) \
1397 Mask subfield (continuous bits in little-endian) of 4-byte value
1398 and return the result in 4-byte value in host byte ordering.*/
1399 #define LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
1401 LE_P4BYTE_TO_HOST_4BYTE(__pstart) & \
1402 (~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)) \
1404 #define LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
1406 LE_P2BYTE_TO_HOST_2BYTE(__pstart) & \
1407 (~BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen)) \
1409 #define LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
1411 LE_P1BYTE_TO_HOST_1BYTE(__pstart) & \
1412 (~BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen)) \
1416 Set subfield of little-endian 4-byte value to specified value. */
1417 #define SET_BITS_TO_LE_4BYTE(__pstart, __bitoffset, __bitlen, __val) \
1418 *((u32 *)(__pstart)) = EF4BYTE \
1420 LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) | \
1421 ((((u32)__val) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset)) \
1423 #define SET_BITS_TO_LE_2BYTE(__pstart, __bitoffset, __bitlen, __val) \
1424 *((u16 *)(__pstart)) = EF2BYTE \
1426 LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) | \
1427 ((((u16)__val) & BIT_LEN_MASK_16(__bitlen)) << (__bitoffset)) \
1429 #define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \
1430 *((u8 *)(__pstart)) = EF1BYTE \
1432 LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) | \
1433 ((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \
1436 /****************************************
1437 mem access macro define end
1438 ****************************************/
1440 #define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC)
1441 #define RTL_WATCH_DOG_TIME 2000
1442 #define MSECS(t) msecs_to_jiffies(t)
1443 #define WLAN_FC_GET_VERS(fc) ((fc) & IEEE80211_FCTL_VERS)
1444 #define WLAN_FC_GET_TYPE(fc) ((fc) & IEEE80211_FCTL_FTYPE)
1445 #define WLAN_FC_GET_STYPE(fc) ((fc) & IEEE80211_FCTL_STYPE)
1446 #define WLAN_FC_MORE_DATA(fc) ((fc) & IEEE80211_FCTL_MOREDATA)
1447 #define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4)
1448 #define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ)
1449 #define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4)
1451 #define RT_RF_OFF_LEVL_ASPM BIT(0) /*PCI ASPM */
1452 #define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /*PCI clock request */
1453 #define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /*PCI D3 mode */
1454 /*NIC halt, re-initialize hw parameters*/
1455 #define RT_RF_OFF_LEVL_HALT_NIC BIT(3)
1456 #define RT_RF_OFF_LEVL_FREE_FW BIT(4) /*FW free, re-download the FW */
1457 #define RT_RF_OFF_LEVL_FW_32K BIT(5) /*FW in 32k */
1458 /*Always enable ASPM and Clock Req in initialization.*/
1459 #define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6)
1460 /*When LPS is on, disable 2R if no packet is received or transmittd.*/
1461 #define RT_RF_LPS_DISALBE_2R BIT(30)
1462 #define RT_RF_LPS_LEVEL_ASPM BIT(31) /*LPS with ASPM */
1463 #define RT_IN_PS_LEVEL(ppsc, _ps_flg) \
1464 ((ppsc->cur_ps_level & _ps_flg) ? true : false)
1465 #define RT_CLEAR_PS_LEVEL(ppsc, _ps_flg) \
1466 (ppsc->cur_ps_level &= (~(_ps_flg)))
1467 #define RT_SET_PS_LEVEL(ppsc, _ps_flg) \
1468 (ppsc->cur_ps_level |= _ps_flg)
1470 #define container_of_dwork_rtl(x, y, z) \
1471 container_of(container_of(x, struct delayed_work, work), y, z)
1473 #define FILL_OCTET_STRING(_os, _octet, _len) \
1474 (_os).octet = (u8 *)(_octet); \
1475 (_os).length = (_len);
1477 #define CP_MACADDR(des, src) \
1478 memcpy((des), (src), ETH_ALEN)
1480 static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr)
1482 return rtlpriv->io.read8_sync(rtlpriv, addr);
1485 static inline u16 rtl_read_word(struct rtl_priv *rtlpriv, u32 addr)
1487 return rtlpriv->io.read16_sync(rtlpriv, addr);
1490 static inline u32 rtl_read_dword(struct rtl_priv *rtlpriv, u32 addr)
1492 return rtlpriv->io.read32_sync(rtlpriv, addr);
1495 static inline void rtl_write_byte(struct rtl_priv *rtlpriv, u32 addr, u8 val8)
1497 rtlpriv->io.write8_async(rtlpriv, addr, val8);
1500 static inline void rtl_write_word(struct rtl_priv *rtlpriv, u32 addr, u16 val16)
1502 rtlpriv->io.write16_async(rtlpriv, addr, val16);
1505 static inline void rtl_write_dword(struct rtl_priv *rtlpriv,
1506 u32 addr, u32 val32)
1508 rtlpriv->io.write32_async(rtlpriv, addr, val32);
1511 static inline u32 rtl_get_bbreg(struct ieee80211_hw *hw,
1512 u32 regaddr, u32 bitmask)
1514 return ((struct rtl_priv *)(hw)->priv)->cfg->ops->get_bbreg(hw,
1519 static inline void rtl_set_bbreg(struct ieee80211_hw *hw, u32 regaddr,
1520 u32 bitmask, u32 data)
1522 ((struct rtl_priv *)(hw)->priv)->cfg->ops->set_bbreg(hw,
1528 static inline u32 rtl_get_rfreg(struct ieee80211_hw *hw,
1529 enum radio_path rfpath, u32 regaddr,
1532 return ((struct rtl_priv *)(hw)->priv)->cfg->ops->get_rfreg(hw,
1538 static inline void rtl_set_rfreg(struct ieee80211_hw *hw,
1539 enum radio_path rfpath, u32 regaddr,
1540 u32 bitmask, u32 data)
1542 ((struct rtl_priv *)(hw)->priv)->cfg->ops->set_rfreg(hw,
1547 static inline bool is_hal_stop(struct rtl_hal *rtlhal)
1549 return (_HAL_STATE_STOP == rtlhal->state);
1552 static inline void set_hal_start(struct rtl_hal *rtlhal)
1554 rtlhal->state = _HAL_STATE_START;
1557 static inline void set_hal_stop(struct rtl_hal *rtlhal)
1559 rtlhal->state = _HAL_STATE_STOP;
1562 static inline u8 get_rf_type(struct rtl_phy *rtlphy)
1564 return rtlphy->rf_type;