1 /******************************************************************************
3 * Copyright(c) 2009-2010 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
26 * Larry Finger <Larry.Finger@lwfinger.net>
28 *****************************************************************************/
37 static void _rtl92s_fw_set_rqpn(struct ieee80211_hw *hw)
39 struct rtl_priv *rtlpriv = rtl_priv(hw);
41 rtl_write_dword(rtlpriv, RQPN, 0xffffffff);
42 rtl_write_dword(rtlpriv, RQPN + 4, 0xffffffff);
43 rtl_write_byte(rtlpriv, RQPN + 8, 0xff);
44 rtl_write_byte(rtlpriv, RQPN + 0xB, 0x80);
47 static bool _rtl92s_firmware_enable_cpu(struct ieee80211_hw *hw)
49 struct rtl_priv *rtlpriv = rtl_priv(hw);
52 u8 tmpu1b, cpustatus = 0;
54 _rtl92s_fw_set_rqpn(hw);
57 tmpu1b = rtl_read_byte(rtlpriv, SYS_CLKR);
59 rtl_write_byte(rtlpriv, SYS_CLKR, (tmpu1b | SYS_CPU_CLKSEL));
61 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
62 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | FEN_CPUEN));
64 /* Polling IMEM Ready after CPU has refilled. */
66 cpustatus = rtl_read_byte(rtlpriv, TCR);
67 if (cpustatus & IMEM_RDY) {
68 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
69 ("IMEM Ready after CPU has refilled.\n"));
74 } while (ichecktime--);
76 if (!(cpustatus & IMEM_RDY))
82 static enum fw_status _rtl92s_firmware_get_nextstatus(
83 enum fw_status fw_currentstatus)
85 enum fw_status next_fwstatus = 0;
87 switch (fw_currentstatus) {
89 next_fwstatus = FW_STATUS_LOAD_IMEM;
91 case FW_STATUS_LOAD_IMEM:
92 next_fwstatus = FW_STATUS_LOAD_EMEM;
94 case FW_STATUS_LOAD_EMEM:
95 next_fwstatus = FW_STATUS_LOAD_DMEM;
97 case FW_STATUS_LOAD_DMEM:
98 next_fwstatus = FW_STATUS_READY;
104 return next_fwstatus;
107 static u8 _rtl92s_firmware_header_map_rftype(struct ieee80211_hw *hw)
109 struct rtl_priv *rtlpriv = rtl_priv(hw);
110 struct rtl_phy *rtlphy = &(rtlpriv->phy);
112 switch (rtlphy->rf_type) {
123 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
124 ("Unknown RF type(%x)\n",
131 static void _rtl92s_firmwareheader_priveupdate(struct ieee80211_hw *hw,
132 struct fw_priv *pfw_priv)
134 /* Update RF types for RATR settings. */
135 pfw_priv->rf_config = _rtl92s_firmware_header_map_rftype(hw);
140 static bool _rtl92s_cmd_send_packet(struct ieee80211_hw *hw,
141 struct sk_buff *skb, u8 last)
143 struct rtl_priv *rtlpriv = rtl_priv(hw);
144 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
145 struct rtl8192_tx_ring *ring;
146 struct rtl_tx_desc *pdesc;
150 ring = &rtlpci->tx_ring[TXCMD_QUEUE];
152 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
154 idx = (ring->idx + skb_queue_len(&ring->queue)) % ring->entries;
155 pdesc = &ring->desc[idx];
156 rtlpriv->cfg->ops->fill_tx_cmddesc(hw, (u8 *)pdesc, 1, 1, skb);
157 __skb_queue_tail(&ring->queue, skb);
159 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
164 static bool _rtl92s_firmware_downloadcode(struct ieee80211_hw *hw,
165 u8 *code_virtual_address, u32 buffer_len)
167 struct rtl_priv *rtlpriv = rtl_priv(hw);
169 struct rtl_tcb_desc *tcb_desc;
170 unsigned char *seg_ptr;
171 u16 frag_threshold = MAX_FIRMWARE_CODE_SIZE;
172 u16 frag_length, frag_offset = 0;
173 u16 extra_descoffset = 0;
176 _rtl92s_fw_set_rqpn(hw);
178 if (buffer_len >= MAX_FIRMWARE_CODE_SIZE) {
179 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
180 ("Size over FIRMWARE_CODE_SIZE!\n"));
185 extra_descoffset = 0;
188 if ((buffer_len - frag_offset) > frag_threshold) {
189 frag_length = frag_threshold + extra_descoffset;
191 frag_length = (u16)(buffer_len - frag_offset +
196 /* Allocate skb buffer to contain firmware */
197 /* info and tx descriptor info. */
198 skb = dev_alloc_skb(frag_length);
201 skb_reserve(skb, extra_descoffset);
202 seg_ptr = (u8 *)skb_put(skb, (u32)(frag_length -
204 memcpy(seg_ptr, code_virtual_address + frag_offset,
205 (u32)(frag_length - extra_descoffset));
207 tcb_desc = (struct rtl_tcb_desc *)(skb->cb);
208 tcb_desc->queue_index = TXCMD_QUEUE;
209 tcb_desc->cmd_or_init = DESC_PACKET_TYPE_INIT;
210 tcb_desc->last_inipkt = last_inipkt;
212 _rtl92s_cmd_send_packet(hw, skb, last_inipkt);
214 frag_offset += (frag_length - extra_descoffset);
216 } while (frag_offset < buffer_len);
218 rtl_write_byte(rtlpriv, TP_POLL, TPPOLL_CQ);
223 static bool _rtl92s_firmware_checkready(struct ieee80211_hw *hw,
226 struct rtl_priv *rtlpriv = rtl_priv(hw);
227 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
228 struct rt_firmware *firmware = (struct rt_firmware *)rtlhal->pfirmware;
231 short pollingcnt = 1000;
232 bool rtstatus = true;
234 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("LoadStaus(%d)\n",
237 firmware->fwstatus = (enum fw_status)loadfw_status;
239 switch (loadfw_status) {
240 case FW_STATUS_LOAD_IMEM:
241 /* Polling IMEM code done. */
243 cpustatus = rtl_read_byte(rtlpriv, TCR);
244 if (cpustatus & IMEM_CODE_DONE)
247 } while (pollingcnt--);
249 if (!(cpustatus & IMEM_CHK_RPT) || (pollingcnt <= 0)) {
250 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
251 ("FW_STATUS_LOAD_IMEM"
252 " FAIL CPU, Status=%x\r\n", cpustatus));
253 goto status_check_fail;
257 case FW_STATUS_LOAD_EMEM:
258 /* Check Put Code OK and Turn On CPU */
259 /* Polling EMEM code done. */
261 cpustatus = rtl_read_byte(rtlpriv, TCR);
262 if (cpustatus & EMEM_CODE_DONE)
265 } while (pollingcnt--);
267 if (!(cpustatus & EMEM_CHK_RPT) || (pollingcnt <= 0)) {
268 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
269 ("FW_STATUS_LOAD_EMEM"
270 " FAIL CPU, Status=%x\r\n", cpustatus));
271 goto status_check_fail;
275 rtstatus = _rtl92s_firmware_enable_cpu(hw);
276 if (rtstatus != true) {
277 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
278 ("Enable CPU fail!\n"));
279 goto status_check_fail;
283 case FW_STATUS_LOAD_DMEM:
284 /* Polling DMEM code done */
286 cpustatus = rtl_read_byte(rtlpriv, TCR);
287 if (cpustatus & DMEM_CODE_DONE)
290 } while (pollingcnt--);
292 if (!(cpustatus & DMEM_CODE_DONE) || (pollingcnt <= 0)) {
293 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
294 ("Polling DMEM code done"
295 " fail ! cpustatus(%#x)\n", cpustatus));
296 goto status_check_fail;
299 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
300 ("DMEM code download success,"
301 " cpustatus(%#x)\n", cpustatus));
303 /* Prevent Delay too much and being scheduled out */
304 /* Polling Load Firmware ready */
307 cpustatus = rtl_read_byte(rtlpriv, TCR);
308 if (cpustatus & FWRDY)
311 } while (pollingcnt--);
313 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
314 ("Polling Load Firmware ready,"
315 " cpustatus(%x)\n", cpustatus));
317 if (((cpustatus & LOAD_FW_READY) != LOAD_FW_READY) ||
319 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
320 ("Polling Load Firmware"
321 " ready fail ! cpustatus(%x)\n", cpustatus));
322 goto status_check_fail;
325 /* If right here, we can set TCR/RCR to desired value */
326 /* and config MAC lookback mode to normal mode */
327 tmpu4b = rtl_read_dword(rtlpriv, TCR);
328 rtl_write_dword(rtlpriv, TCR, (tmpu4b & (~TCR_ICV)));
330 tmpu4b = rtl_read_dword(rtlpriv, RCR);
331 rtl_write_dword(rtlpriv, RCR, (tmpu4b | RCR_APPFCS |
332 RCR_APP_ICV | RCR_APP_MIC));
334 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
335 ("Current RCR settings(%#x)\n", tmpu4b));
337 /* Set to normal mode. */
338 rtl_write_byte(rtlpriv, LBKMD_SEL, LBK_NORMAL);
342 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
343 ("Unknown status check!\n"));
349 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("loadfw_status(%d), "
350 "rtstatus(%x)\n", loadfw_status, rtstatus));
354 int rtl92s_download_fw(struct ieee80211_hw *hw)
356 struct rtl_priv *rtlpriv = rtl_priv(hw);
357 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
358 struct rt_firmware *firmware = NULL;
359 struct fw_hdr *pfwheader;
360 struct fw_priv *pfw_priv = NULL;
361 u8 *puc_mappedfile = NULL;
362 u32 ul_filelength = 0;
363 u8 fwhdr_size = RT_8192S_FIRMWARE_HDR_SIZE;
364 u8 fwstatus = FW_STATUS_INIT;
365 bool rtstatus = true;
367 if (!rtlhal->pfirmware)
370 firmware = (struct rt_firmware *)rtlhal->pfirmware;
371 firmware->fwstatus = FW_STATUS_INIT;
373 puc_mappedfile = firmware->sz_fw_tmpbuffer;
375 /* 1. Retrieve FW header. */
376 firmware->pfwheader = (struct fw_hdr *) puc_mappedfile;
377 pfwheader = firmware->pfwheader;
378 firmware->firmwareversion = byte(pfwheader->version, 0);
379 firmware->pfwheader->fwpriv.hci_sel = 1;/* pcie */
381 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("signature:%x, version:"
383 "imemsize:%x, sram size:%x\n", pfwheader->signature,
384 pfwheader->version, pfwheader->dmem_size,
385 pfwheader->img_imem_size, pfwheader->img_sram_size));
387 /* 2. Retrieve IMEM image. */
388 if ((pfwheader->img_imem_size == 0) || (pfwheader->img_imem_size >
389 sizeof(firmware->fw_imem))) {
390 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
391 ("memory for data image is less than IMEM required\n"));
394 puc_mappedfile += fwhdr_size;
396 memcpy(firmware->fw_imem, puc_mappedfile,
397 pfwheader->img_imem_size);
398 firmware->fw_imem_len = pfwheader->img_imem_size;
401 /* 3. Retriecve EMEM image. */
402 if (pfwheader->img_sram_size > sizeof(firmware->fw_emem)) {
403 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
404 ("memory for data image is less than EMEM required\n"));
407 puc_mappedfile += firmware->fw_imem_len;
409 memcpy(firmware->fw_emem, puc_mappedfile,
410 pfwheader->img_sram_size);
411 firmware->fw_emem_len = pfwheader->img_sram_size;
414 /* 4. download fw now */
415 fwstatus = _rtl92s_firmware_get_nextstatus(firmware->fwstatus);
416 while (fwstatus != FW_STATUS_READY) {
417 /* Image buffer redirection. */
419 case FW_STATUS_LOAD_IMEM:
420 puc_mappedfile = firmware->fw_imem;
421 ul_filelength = firmware->fw_imem_len;
423 case FW_STATUS_LOAD_EMEM:
424 puc_mappedfile = firmware->fw_emem;
425 ul_filelength = firmware->fw_emem_len;
427 case FW_STATUS_LOAD_DMEM:
428 /* Partial update the content of header private. */
429 pfwheader = firmware->pfwheader;
430 pfw_priv = &pfwheader->fwpriv;
431 _rtl92s_firmwareheader_priveupdate(hw, pfw_priv);
432 puc_mappedfile = (u8 *)(firmware->pfwheader) +
433 RT_8192S_FIRMWARE_HDR_EXCLUDE_PRI_SIZE;
434 ul_filelength = fwhdr_size -
435 RT_8192S_FIRMWARE_HDR_EXCLUDE_PRI_SIZE;
438 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
439 ("Unexpected Download step!!\n"));
444 /* <2> Download image file */
445 rtstatus = _rtl92s_firmware_downloadcode(hw, puc_mappedfile,
448 if (rtstatus != true) {
449 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("fail!\n"));
453 /* <3> Check whether load FW process is ready */
454 rtstatus = _rtl92s_firmware_checkready(hw, fwstatus);
455 if (rtstatus != true) {
456 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("fail!\n"));
460 fwstatus = _rtl92s_firmware_get_nextstatus(firmware->fwstatus);
468 static u32 _rtl92s_fill_h2c_cmd(struct sk_buff *skb, u32 h2cbufferlen,
469 u32 cmd_num, u32 *pelement_id, u32 *pcmd_len,
470 u8 **pcmb_buffer, u8 *cmd_start_seq)
472 u32 totallen = 0, len = 0, tx_desclen = 0;
473 u32 pre_continueoffset = 0;
478 /* 8 - Byte aligment */
479 len = H2C_TX_CMD_HDR_LEN + N_BYTE_ALIGMENT(pcmd_len[i], 8);
481 /* Buffer length is not enough */
482 if (h2cbufferlen < totallen + len + tx_desclen)
486 ph2c_buffer = (u8 *)skb_put(skb, (u32)len);
487 memset((ph2c_buffer + totallen + tx_desclen), 0, len);
490 SET_BITS_TO_LE_4BYTE((ph2c_buffer + totallen + tx_desclen),
494 SET_BITS_TO_LE_4BYTE((ph2c_buffer + totallen + tx_desclen),
495 16, 8, pelement_id[i]);
498 *cmd_start_seq = *cmd_start_seq % 0x80;
499 SET_BITS_TO_LE_4BYTE((ph2c_buffer + totallen + tx_desclen),
500 24, 7, *cmd_start_seq);
504 memcpy((ph2c_buffer + totallen + tx_desclen +
505 H2C_TX_CMD_HDR_LEN), pcmb_buffer[i], pcmd_len[i]);
508 /* set the continue in prevoius cmd. */
510 SET_BITS_TO_LE_4BYTE((ph2c_buffer + pre_continueoffset),
513 pre_continueoffset = totallen;
516 } while (++i < cmd_num);
521 static u32 _rtl92s_get_h2c_cmdlen(u32 h2cbufferlen, u32 cmd_num, u32 *pcmd_len)
523 u32 totallen = 0, len = 0, tx_desclen = 0;
527 /* 8 - Byte aligment */
528 len = H2C_TX_CMD_HDR_LEN + N_BYTE_ALIGMENT(pcmd_len[i], 8);
530 /* Buffer length is not enough */
531 if (h2cbufferlen < totallen + len + tx_desclen)
535 } while (++i < cmd_num);
537 return totallen + tx_desclen;
540 static bool _rtl92s_firmware_set_h2c_cmd(struct ieee80211_hw *hw, u8 h2c_cmd,
543 struct rtl_priv *rtlpriv = rtl_priv(hw);
544 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
545 struct rtl_tcb_desc *cb_desc;
552 case FW_H2C_SETPWRMODE:
553 element_id = H2C_SETPWRMODE_CMD ;
554 cmd_len = sizeof(struct h2c_set_pwrmode_parm);
556 case FW_H2C_JOINBSSRPT:
557 element_id = H2C_JOINBSSRPT_CMD;
558 cmd_len = sizeof(struct h2c_joinbss_rpt_parm);
560 case FW_H2C_WOWLAN_UPDATE_GTK:
561 element_id = H2C_WOWLAN_UPDATE_GTK_CMD;
562 cmd_len = sizeof(struct h2c_wpa_two_way_parm);
564 case FW_H2C_WOWLAN_UPDATE_IV:
565 element_id = H2C_WOWLAN_UPDATE_IV_CMD;
566 cmd_len = sizeof(unsigned long long);
568 case FW_H2C_WOWLAN_OFFLOAD:
569 element_id = H2C_WOWLAN_FW_OFFLOAD;
570 cmd_len = sizeof(u8);
576 len = _rtl92s_get_h2c_cmdlen(MAX_TRANSMIT_BUFFER_SIZE, 1, &cmd_len);
577 skb = dev_alloc_skb(len);
580 cb_desc = (struct rtl_tcb_desc *)(skb->cb);
581 cb_desc->queue_index = TXCMD_QUEUE;
582 cb_desc->cmd_or_init = DESC_PACKET_TYPE_NORMAL;
583 cb_desc->last_inipkt = false;
585 _rtl92s_fill_h2c_cmd(skb, MAX_TRANSMIT_BUFFER_SIZE, 1, &element_id,
586 &cmd_len, &pcmd_buffer, &rtlhal->h2c_txcmd_seq);
587 _rtl92s_cmd_send_packet(hw, skb, false);
588 rtlpriv->cfg->ops->tx_polling(hw, TXCMD_QUEUE);
593 void rtl92s_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 Mode)
595 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
596 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
597 struct h2c_set_pwrmode_parm pwrmode;
598 u16 max_wakeup_period = 0;
601 pwrmode.flag_low_traffic_en = 0;
602 pwrmode.flag_lpnav_en = 0;
603 pwrmode.flag_rf_low_snr_en = 0;
604 pwrmode.flag_dps_en = 0;
605 pwrmode.bcn_rx_en = 0;
607 SET_BITS_TO_LE_2BYTE((u8 *)(&pwrmode) + 8, 0, 16,
608 mac->vif->bss_conf.beacon_int);
610 pwrmode.awake_bcn_itvl = ppsc->reg_max_lps_awakeintvl;
611 pwrmode.smart_ps = 1;
612 pwrmode.bcn_pass_period = 10;
614 /* Set beacon pass count */
615 if (pwrmode.mode == FW_PS_MIN_MODE)
616 max_wakeup_period = mac->vif->bss_conf.beacon_int;
617 else if (pwrmode.mode == FW_PS_MAX_MODE)
618 max_wakeup_period = mac->vif->bss_conf.beacon_int *
619 mac->vif->bss_conf.dtim_period;
621 if (max_wakeup_period >= 500)
622 pwrmode.bcn_pass_cnt = 1;
623 else if ((max_wakeup_period >= 300) && (max_wakeup_period < 500))
624 pwrmode.bcn_pass_cnt = 2;
625 else if ((max_wakeup_period >= 200) && (max_wakeup_period < 300))
626 pwrmode.bcn_pass_cnt = 3;
627 else if ((max_wakeup_period >= 20) && (max_wakeup_period < 200))
628 pwrmode.bcn_pass_cnt = 5;
630 pwrmode.bcn_pass_cnt = 1;
632 _rtl92s_firmware_set_h2c_cmd(hw, FW_H2C_SETPWRMODE, (u8 *)&pwrmode);
636 void rtl92s_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw,
637 u8 mstatus, u8 ps_qosinfo)
639 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
640 struct h2c_joinbss_rpt_parm joinbss_rpt;
642 joinbss_rpt.opmode = mstatus;
643 joinbss_rpt.ps_qos_info = ps_qosinfo;
644 joinbss_rpt.bssid[0] = mac->bssid[0];
645 joinbss_rpt.bssid[1] = mac->bssid[1];
646 joinbss_rpt.bssid[2] = mac->bssid[2];
647 joinbss_rpt.bssid[3] = mac->bssid[3];
648 joinbss_rpt.bssid[4] = mac->bssid[4];
649 joinbss_rpt.bssid[5] = mac->bssid[5];
650 SET_BITS_TO_LE_2BYTE((u8 *)(&joinbss_rpt) + 8, 0, 16,
651 mac->vif->bss_conf.beacon_int);
652 SET_BITS_TO_LE_2BYTE((u8 *)(&joinbss_rpt) + 10, 0, 16, mac->assoc_id);
654 _rtl92s_firmware_set_h2c_cmd(hw, FW_H2C_JOINBSSRPT, (u8 *)&joinbss_rpt);