drivers/net/wireless/rtlwifi/rtl8192cu/rf.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2010  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #include "../wifi.h"
  31 #include "reg.h"
  32 #include "def.h"
  33 #include "phy.h"
  34 #include "rf.h"
  35 #include "dm.h"
  36
  37 static bool _rtl92c_phy_rf6052_config_parafile(struct ieee80211_hw *hw);
  38
  39 void rtl92cu_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth)
  40 {
  41         struct rtl_priv *rtlpriv = rtl_priv(hw);
  42         struct rtl_phy *rtlphy = &(rtlpriv->phy);
  43
  44         switch (bandwidth) {
  45         case HT_CHANNEL_WIDTH_20:
  46                 rtlphy->rfreg_chnlval[0] = ((rtlphy->rfreg_chnlval[0] &
  47                                              0xfffff3ff) | 0x0400);
  48                 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
  49                               rtlphy->rfreg_chnlval[0]);
  50                 break;
  51         case HT_CHANNEL_WIDTH_20_40:
  52                 rtlphy->rfreg_chnlval[0] = ((rtlphy->rfreg_chnlval[0] &
  53                                              0xfffff3ff));
  54                 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
  55                               rtlphy->rfreg_chnlval[0]);
  56                 break;
  57         default:
  58                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  59                          ("unknown bandwidth: %#X\n", bandwidth));
  60                 break;
  61         }
  62 }
  63
  64 void rtl92cu_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
  65                                         u8 *ppowerlevel)
  66 {
  67         struct rtl_priv *rtlpriv = rtl_priv(hw);
  68         struct rtl_phy *rtlphy = &(rtlpriv->phy);
  69         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
  70         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  71         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
  72         u32 tx_agc[2] = { 0, 0 }, tmpval = 0;
  73         bool turbo_scanoff = false;
  74         u8 idx1, idx2;
  75         u8 *ptr;
  76
  77         if (rtlhal->interface == INTF_PCI) {
  78                 if (rtlefuse->eeprom_regulatory != 0)
  79                         turbo_scanoff = true;
  80         } else {
  81                 if ((rtlefuse->eeprom_regulatory != 0) ||
  82                     (rtlefuse->external_pa))
  83                         turbo_scanoff = true;
  84         }
  85         if (mac->act_scanning) {
  86                 tx_agc[RF90_PATH_A] = 0x3f3f3f3f;
  87                 tx_agc[RF90_PATH_B] = 0x3f3f3f3f;
  88                 for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
  89                         tx_agc[idx1] = ppowerlevel[idx1] |
  90                             (ppowerlevel[idx1] << 8) |
  91                             (ppowerlevel[idx1] << 16) |
  92                             (ppowerlevel[idx1] << 24);
  93                         if (rtlhal->interface == INTF_USB) {
  94                                 if (tx_agc[idx1] > 0x20 &&
  95                                     rtlefuse->external_pa)
  96                                         tx_agc[idx1] = 0x20;
  97                         }
  98                 }
  99         } else {
 100                 if (rtlpriv->dm.dynamic_txhighpower_lvl ==
 101                     TXHIGHPWRLEVEL_LEVEL1) {
 102                         tx_agc[RF90_PATH_A] = 0x10101010;
 103                         tx_agc[RF90_PATH_B] = 0x10101010;
 104                 } else if (rtlpriv->dm.dynamic_txhighpower_lvl ==
 105                            TXHIGHPWRLEVEL_LEVEL2) {
 106                         tx_agc[RF90_PATH_A] = 0x00000000;
 107                         tx_agc[RF90_PATH_B] = 0x00000000;
 108                 } else {
 109                         for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
 110                                 tx_agc[idx1] = ppowerlevel[idx1] |
 111                                     (ppowerlevel[idx1] << 8) |
 112                                     (ppowerlevel[idx1] << 16) |
 113                                     (ppowerlevel[idx1] << 24);
 114                         }
 115                         if (rtlefuse->eeprom_regulatory == 0) {
 116                                 tmpval = (rtlphy->mcs_txpwrlevel_origoffset
 117                                         [0][6]) +
 118                                         (rtlphy->mcs_txpwrlevel_origoffset
 119                                         [0][7] <<  8);
 120                                 tx_agc[RF90_PATH_A] += tmpval;
 121                                 tmpval = (rtlphy->mcs_txpwrlevel_origoffset
 122                                         [0][14]) +
 123                                         (rtlphy->mcs_txpwrlevel_origoffset
 124                                         [0][15] << 24);
 125                                 tx_agc[RF90_PATH_B] += tmpval;
 126                         }
 127                 }
 128         }
 129         for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
 130                 ptr = (u8 *) (&(tx_agc[idx1]));
 131                 for (idx2 = 0; idx2 < 4; idx2++) {
 132                         if (*ptr > RF6052_MAX_TX_PWR)
 133                                 *ptr = RF6052_MAX_TX_PWR;
 134                         ptr++;
 135                 }
 136         }
 137         tmpval = tx_agc[RF90_PATH_A] & 0xff;
 138         rtl_set_bbreg(hw, RTXAGC_A_CCK1_MCS32, MASKBYTE1, tmpval);
 139
 140         RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 141                 ("CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n", tmpval,
 142                  RTXAGC_A_CCK1_MCS32));
 143
 144         tmpval = tx_agc[RF90_PATH_A] >> 8;
 145         if (mac->mode == WIRELESS_MODE_B)
 146                 tmpval = tmpval & 0xff00ffff;
 147         rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval);
 148         RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 149                 ("CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n", tmpval,
 150                  RTXAGC_B_CCK11_A_CCK2_11));
 151         tmpval = tx_agc[RF90_PATH_B] >> 24;
 152         rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE0, tmpval);
 153         RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 154                 ("CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", tmpval,
 155                  RTXAGC_B_CCK11_A_CCK2_11));
 156         tmpval = tx_agc[RF90_PATH_B] & 0x00ffffff;
 157         rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, 0xffffff00, tmpval);
 158         RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 159                 ("CCK PWR 1~5.5M (rf-B) = 0x%x (reg 0x%x)\n", tmpval,
 160                  RTXAGC_B_CCK1_55_MCS32));
 161 }
 162
 163 static void rtl92c_phy_get_power_base(struct ieee80211_hw *hw,
 164                                       u8 *ppowerlevel, u8 channel,
 165                                       u32 *ofdmbase, u32 *mcsbase)
 166 {
 167         struct rtl_priv *rtlpriv = rtl_priv(hw);
 168         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 169         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 170         u32 powerBase0, powerBase1;
 171         u8 legacy_pwrdiff = 0, ht20_pwrdiff = 0;
 172         u8 i, powerlevel[2];
 173
 174         for (i = 0; i < 2; i++) {
 175                 powerlevel[i] = ppowerlevel[i];
 176                 legacy_pwrdiff = rtlefuse->txpwr_legacyhtdiff[i][channel - 1];
 177                 powerBase0 = powerlevel[i] + legacy_pwrdiff;
 178                 powerBase0 = (powerBase0 << 24) | (powerBase0 << 16) |
 179                     (powerBase0 << 8) | powerBase0;
 180                 *(ofdmbase + i) = powerBase0;
 181                 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 182                         (" [OFDM power base index rf(%c) = 0x%x]\n",
 183                          ((i == 0) ? 'A' : 'B'), *(ofdmbase + i)));
 184         }
 185         for (i = 0; i < 2; i++) {
 186                 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20) {
 187                         ht20_pwrdiff = rtlefuse->txpwr_ht20diff[i][channel - 1];
 188                         powerlevel[i] += ht20_pwrdiff;
 189                 }
 190                 powerBase1 = powerlevel[i];
 191                 powerBase1 = (powerBase1 << 24) |
 192                     (powerBase1 << 16) | (powerBase1 << 8) | powerBase1;
 193                 *(mcsbase + i) = powerBase1;
 194                 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 195                         (" [MCS power base index rf(%c) = 0x%x]\n",
 196                          ((i == 0) ? 'A' : 'B'), *(mcsbase + i)));
 197         }
 198 }
 199
 200 static void _rtl92c_get_txpower_writeval_by_regulatory(struct ieee80211_hw *hw,
 201                                                        u8 channel, u8 index,
 202                                                        u32 *powerBase0,
 203                                                        u32 *powerBase1,
 204                                                        u32 *p_outwriteval)
 205 {
 206         struct rtl_priv *rtlpriv = rtl_priv(hw);
 207         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 208         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 209         u8 i, chnlgroup = 0, pwr_diff_limit[4];
 210         u32 writeVal, customer_limit, rf;
 211
 212         for (rf = 0; rf < 2; rf++) {
 213                 switch (rtlefuse->eeprom_regulatory) {
 214                 case 0:
 215                         chnlgroup = 0;
 216                         writeVal = rtlphy->mcs_txpwrlevel_origoffset
 217                             [chnlgroup][index + (rf ? 8 : 0)]
 218                             + ((index < 2) ? powerBase0[rf] : powerBase1[rf]);
 219                         RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 220                                 ("RTK better performance,writeVal(%c) = 0x%x\n",
 221                                 ((rf == 0) ? 'A' : 'B'), writeVal));
 222                         break;
 223                 case 1:
 224                         if (rtlphy->pwrgroup_cnt == 1)
 225                                 chnlgroup = 0;
 226                         if (rtlphy->pwrgroup_cnt >= 3) {
 227                                 if (channel <= 3)
 228                                         chnlgroup = 0;
 229                                 else if (channel >= 4 && channel <= 9)
 230                                         chnlgroup = 1;
 231                                 else if (channel > 9)
 232                                         chnlgroup = 2;
 233                                 if (rtlphy->current_chan_bw ==
 234                                     HT_CHANNEL_WIDTH_20)
 235                                         chnlgroup++;
 236                                 else
 237                                         chnlgroup += 4;
 238                         }
 239                         writeVal = rtlphy->mcs_txpwrlevel_origoffset
 240                                         [chnlgroup][index +
 241                                         (rf ? 8 : 0)] +
 242                                         ((index < 2) ? powerBase0[rf] :
 243                                         powerBase1[rf]);
 244                         RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 245                                 ("Realtek regulatory, 20MHz, "
 246                                 "writeVal(%c) = 0x%x\n",
 247                                 ((rf == 0) ? 'A' : 'B'), writeVal));
 248                         break;
 249                 case 2:
 250                         writeVal = ((index < 2) ? powerBase0[rf] :
 251                                    powerBase1[rf]);
 252                         RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 253                                 ("Better regulatory,writeVal(%c) = 0x%x\n",
 254                                  ((rf == 0) ? 'A' : 'B'), writeVal));
 255                         break;
 256                 case 3:
 257                         chnlgroup = 0;
 258                         if (rtlphy->current_chan_bw ==
 259                             HT_CHANNEL_WIDTH_20_40) {
 260                                 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 261                                         ("customer's limit, 40MHzrf(%c) = "
 262                                         "0x%x\n", ((rf == 0) ? 'A' : 'B'),
 263                                         rtlefuse->pwrgroup_ht40[rf]
 264                                         [channel - 1]));
 265                         } else {
 266                                 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 267                                         ("customer's limit, 20MHz rf(%c) = "
 268                                         "0x%x\n", ((rf == 0) ? 'A' : 'B'),
 269                                         rtlefuse->pwrgroup_ht20[rf]
 270                                         [channel - 1]));
 271                         }
 272                         for (i = 0; i < 4; i++) {
 273                                 pwr_diff_limit[i] =
 274                                     (u8) ((rtlphy->mcs_txpwrlevel_origoffset
 275                                     [chnlgroup][index + (rf ? 8 : 0)]
 276                                     & (0x7f << (i * 8))) >> (i * 8));
 277                                 if (rtlphy->current_chan_bw ==
 278                                     HT_CHANNEL_WIDTH_20_40) {
 279                                         if (pwr_diff_limit[i] >
 280                                             rtlefuse->pwrgroup_ht40[rf]
 281                                                 [channel - 1])
 282                                                 pwr_diff_limit[i] = rtlefuse->
 283                                                     pwrgroup_ht40[rf]
 284                                                     [channel - 1];
 285                                 } else {
 286                                         if (pwr_diff_limit[i] >
 287                                             rtlefuse->pwrgroup_ht20[rf]
 288                                                 [channel - 1])
 289                                                 pwr_diff_limit[i] =
 290                                                     rtlefuse->pwrgroup_ht20[rf]
 291                                                     [channel - 1];
 292                                 }
 293                         }
 294                         customer_limit = (pwr_diff_limit[3] << 24) |
 295                             (pwr_diff_limit[2] << 16) |
 296                             (pwr_diff_limit[1] << 8) | (pwr_diff_limit[0]);
 297                         RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 298                                 ("Customer's limit rf(%c) = 0x%x\n",
 299                                  ((rf == 0) ? 'A' : 'B'), customer_limit));
 300                         writeVal = customer_limit + ((index < 2) ?
 301                                    powerBase0[rf] : powerBase1[rf]);
 302                         RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 303                                 ("Customer, writeVal rf(%c)= 0x%x\n",
 304                                  ((rf == 0) ? 'A' : 'B'), writeVal));
 305                         break;
 306                 default:
 307                         chnlgroup = 0;
 308                         writeVal = rtlphy->mcs_txpwrlevel_origoffset[chnlgroup]
 309                                    [index + (rf ? 8 : 0)] + ((index < 2) ?
 310                                    powerBase0[rf] : powerBase1[rf]);
 311                         RTPRINT(rtlpriv, FPHY, PHY_TXPWR, ("RTK better "
 312                                 "performance, writeValrf(%c) = 0x%x\n",
 313                                 ((rf == 0) ? 'A' : 'B'), writeVal));
 314                         break;
 315                 }
 316                 if (rtlpriv->dm.dynamic_txhighpower_lvl ==
 317                     TXHIGHPWRLEVEL_LEVEL1)
 318                         writeVal = 0x14141414;
 319                 else if (rtlpriv->dm.dynamic_txhighpower_lvl ==
 320                          TXHIGHPWRLEVEL_LEVEL2)
 321                         writeVal = 0x00000000;
 322                 if (rtlpriv->dm.dynamic_txhighpower_lvl == TXHIGHPWRLEVEL_BT1)
 323                         writeVal = writeVal - 0x06060606;
 324                 else if (rtlpriv->dm.dynamic_txhighpower_lvl ==
 325                          TXHIGHPWRLEVEL_BT2)
 326                         writeVal = writeVal;
 327                 *(p_outwriteval + rf) = writeVal;
 328         }
 329 }
 330
 331 static void _rtl92c_write_ofdm_power_reg(struct ieee80211_hw *hw,
 332                                          u8 index, u32 *pValue)
 333 {
 334         struct rtl_priv *rtlpriv = rtl_priv(hw);
 335         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 336         u16 regoffset_a[6] = {
 337                 RTXAGC_A_RATE18_06, RTXAGC_A_RATE54_24,
 338                 RTXAGC_A_MCS03_MCS00, RTXAGC_A_MCS07_MCS04,
 339                 RTXAGC_A_MCS11_MCS08, RTXAGC_A_MCS15_MCS12
 340         };
 341         u16 regoffset_b[6] = {
 342                 RTXAGC_B_RATE18_06, RTXAGC_B_RATE54_24,
 343                 RTXAGC_B_MCS03_MCS00, RTXAGC_B_MCS07_MCS04,
 344                 RTXAGC_B_MCS11_MCS08, RTXAGC_B_MCS15_MCS12
 345         };
 346         u8 i, rf, pwr_val[4];
 347         u32 writeVal;
 348         u16 regoffset;
 349
 350         for (rf = 0; rf < 2; rf++) {
 351                 writeVal = pValue[rf];
 352                 for (i = 0; i < 4; i++) {
 353                         pwr_val[i] = (u8)((writeVal & (0x7f << (i * 8))) >>
 354                                           (i * 8));
 355                         if (pwr_val[i] > RF6052_MAX_TX_PWR)
 356                                 pwr_val[i] = RF6052_MAX_TX_PWR;
 357                 }
 358                 writeVal = (pwr_val[3] << 24) | (pwr_val[2] << 16) |
 359                     (pwr_val[1] << 8) | pwr_val[0];
 360                 if (rf == 0)
 361                         regoffset = regoffset_a[index];
 362                 else
 363                         regoffset = regoffset_b[index];
 364                 rtl_set_bbreg(hw, regoffset, MASKDWORD, writeVal);
 365                 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
 366                         ("Set 0x%x = %08x\n", regoffset, writeVal));
 367                 if (((get_rf_type(rtlphy) == RF_2T2R) &&
 368                      (regoffset == RTXAGC_A_MCS15_MCS12 ||
 369                       regoffset == RTXAGC_B_MCS15_MCS12)) ||
 370                     ((get_rf_type(rtlphy) != RF_2T2R) &&
 371                      (regoffset == RTXAGC_A_MCS07_MCS04 ||
 372                       regoffset == RTXAGC_B_MCS07_MCS04))) {
 373                         writeVal = pwr_val[3];
 374                         if (regoffset == RTXAGC_A_MCS15_MCS12 ||
 375                             regoffset == RTXAGC_A_MCS07_MCS04)
 376                                 regoffset = 0xc90;
 377                         if (regoffset == RTXAGC_B_MCS15_MCS12 ||
 378                             regoffset == RTXAGC_B_MCS07_MCS04)
 379                                 regoffset = 0xc98;
 380                         for (i = 0; i < 3; i++) {
 381                                 if (i != 2)
 382                                         writeVal = (writeVal > 8) ?
 383                                                    (writeVal - 8) : 0;
 384                                 else
 385                                         writeVal = (writeVal > 6) ?
 386                                                    (writeVal - 6) : 0;
 387                                 rtl_write_byte(rtlpriv, (u32)(regoffset + i),
 388                                               (u8)writeVal);
 389                         }
 390                 }
 391         }
 392 }
 393
 394 void rtl92cu_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw,
 395                                          u8 *ppowerlevel, u8 channel)
 396 {
 397         u32 writeVal[2], powerBase0[2], powerBase1[2];
 398         u8 index = 0;
 399
 400         rtl92c_phy_get_power_base(hw, ppowerlevel,
 401                                   channel, &powerBase0[0], &powerBase1[0]);
 402         for (index = 0; index < 6; index++) {
 403                 _rtl92c_get_txpower_writeval_by_regulatory(hw,
 404                                                            channel, index,
 405                                                            &powerBase0[0],
 406                                                            &powerBase1[0],
 407                                                            &writeVal[0]);
 408                 _rtl92c_write_ofdm_power_reg(hw, index, &writeVal[0]);
 409         }
 410 }
 411
 412 bool rtl92cu_phy_rf6052_config(struct ieee80211_hw *hw)
 413 {
 414         struct rtl_priv *rtlpriv = rtl_priv(hw);
 415         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 416         bool rtstatus = true;
 417         u8 b_reg_hwparafile = 1;
 418
 419         if (rtlphy->rf_type == RF_1T1R)
 420                 rtlphy->num_total_rfpath = 1;
 421         else
 422                 rtlphy->num_total_rfpath = 2;
 423         if (b_reg_hwparafile == 1)
 424                 rtstatus = _rtl92c_phy_rf6052_config_parafile(hw);
 425         return rtstatus;
 426 }
 427
 428 static bool _rtl92c_phy_rf6052_config_parafile(struct ieee80211_hw *hw)
 429 {
 430         struct rtl_priv *rtlpriv = rtl_priv(hw);
 431         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 432         u32 u4_regvalue = 0;
 433         u8 rfpath;
 434         bool rtstatus = true;
 435         struct bb_reg_def *pphyreg;
 436
 437         for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) {
 438                 pphyreg = &rtlphy->phyreg_def[rfpath];
 439                 switch (rfpath) {
 440                 case RF90_PATH_A:
 441                 case RF90_PATH_C:
 442                         u4_regvalue = rtl_get_bbreg(hw, pphyreg->rfintfs,
 443                                                     BRFSI_RFENV);
 444                         break;
 445                 case RF90_PATH_B:
 446                 case RF90_PATH_D:
 447                         u4_regvalue = rtl_get_bbreg(hw, pphyreg->rfintfs,
 448                                                     BRFSI_RFENV << 16);
 449                         break;
 450                 }
 451                 rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1);
 452                 udelay(1);
 453                 rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1);
 454                 udelay(1);
 455                 rtl_set_bbreg(hw, pphyreg->rfhssi_para2,
 456                               B3WIREADDREAALENGTH, 0x0);
 457                 udelay(1);
 458                 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0);
 459                 udelay(1);
 460                 switch (rfpath) {
 461                 case RF90_PATH_A:
 462                         rtstatus = rtl92cu_phy_config_rf_with_headerfile(hw,
 463                                         (enum radio_path) rfpath);
 464                         break;
 465                 case RF90_PATH_B:
 466                         rtstatus = rtl92cu_phy_config_rf_with_headerfile(hw,
 467                                         (enum radio_path) rfpath);
 468                         break;
 469                 case RF90_PATH_C:
 470                         break;
 471                 case RF90_PATH_D:
 472                         break;
 473                 }
 474                 switch (rfpath) {
 475                 case RF90_PATH_A:
 476                 case RF90_PATH_C:
 477                         rtl_set_bbreg(hw, pphyreg->rfintfs,
 478                                       BRFSI_RFENV, u4_regvalue);
 479                         break;
 480                 case RF90_PATH_B:
 481                 case RF90_PATH_D:
 482                         rtl_set_bbreg(hw, pphyreg->rfintfs,
 483                                       BRFSI_RFENV << 16, u4_regvalue);
 484                         break;
 485                 }
 486                 if (rtstatus != true) {
 487                         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 488                                  ("Radio[%d] Fail!!", rfpath));
 489                         goto phy_rf_cfg_fail;
 490                 }
 491         }
 492         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("<---\n"));
 493         return rtstatus;
 494 phy_rf_cfg_fail:
 495         return rtstatus;
 496 }