drivers/net/wireless/rtlwifi/rtl8192cu/hw.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2010  Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #include "../wifi.h"
  31 #include "../efuse.h"
  32 #include "../base.h"
  33 #include "../cam.h"
  34 #include "../ps.h"
  35 #include "../usb.h"
  36 #include "reg.h"
  37 #include "def.h"
  38 #include "phy.h"
  39 #include "mac.h"
  40 #include "dm.h"
  41 #include "hw.h"
  42 #include "trx.h"
  43 #include "led.h"
  44 #include "table.h"
  45
  46 static void _rtl92cu_phy_param_tab_init(struct ieee80211_hw *hw)
  47 {
  48         struct rtl_priv *rtlpriv = rtl_priv(hw);
  49         struct rtl_phy *rtlphy = &(rtlpriv->phy);
  50         struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv);
  51
  52         rtlphy->hwparam_tables[MAC_REG].length = RTL8192CUMAC_2T_ARRAYLENGTH;
  53         rtlphy->hwparam_tables[MAC_REG].pdata = RTL8192CUMAC_2T_ARRAY;
  54         if (IS_HIGHT_PA(rtlefuse->board_type)) {
  55                 rtlphy->hwparam_tables[PHY_REG_PG].length =
  56                         RTL8192CUPHY_REG_Array_PG_HPLength;
  57                 rtlphy->hwparam_tables[PHY_REG_PG].pdata =
  58                         RTL8192CUPHY_REG_Array_PG_HP;
  59         } else {
  60                 rtlphy->hwparam_tables[PHY_REG_PG].length =
  61                         RTL8192CUPHY_REG_ARRAY_PGLENGTH;
  62                 rtlphy->hwparam_tables[PHY_REG_PG].pdata =
  63                         RTL8192CUPHY_REG_ARRAY_PG;
  64         }
  65         /* 2T */
  66         rtlphy->hwparam_tables[PHY_REG_2T].length =
  67                         RTL8192CUPHY_REG_2TARRAY_LENGTH;
  68         rtlphy->hwparam_tables[PHY_REG_2T].pdata =
  69                         RTL8192CUPHY_REG_2TARRAY;
  70         rtlphy->hwparam_tables[RADIOA_2T].length =
  71                         RTL8192CURADIOA_2TARRAYLENGTH;
  72         rtlphy->hwparam_tables[RADIOA_2T].pdata =
  73                         RTL8192CURADIOA_2TARRAY;
  74         rtlphy->hwparam_tables[RADIOB_2T].length =
  75                         RTL8192CURADIOB_2TARRAYLENGTH;
  76         rtlphy->hwparam_tables[RADIOB_2T].pdata =
  77                         RTL8192CU_RADIOB_2TARRAY;
  78         rtlphy->hwparam_tables[AGCTAB_2T].length =
  79                         RTL8192CUAGCTAB_2TARRAYLENGTH;
  80         rtlphy->hwparam_tables[AGCTAB_2T].pdata =
  81                         RTL8192CUAGCTAB_2TARRAY;
  82         /* 1T */
  83         if (IS_HIGHT_PA(rtlefuse->board_type)) {
  84                 rtlphy->hwparam_tables[PHY_REG_1T].length =
  85                         RTL8192CUPHY_REG_1T_HPArrayLength;
  86                 rtlphy->hwparam_tables[PHY_REG_1T].pdata =
  87                         RTL8192CUPHY_REG_1T_HPArray;
  88                 rtlphy->hwparam_tables[RADIOA_1T].length =
  89                         RTL8192CURadioA_1T_HPArrayLength;
  90                 rtlphy->hwparam_tables[RADIOA_1T].pdata =
  91                         RTL8192CURadioA_1T_HPArray;
  92                 rtlphy->hwparam_tables[RADIOB_1T].length =
  93                         RTL8192CURADIOB_1TARRAYLENGTH;
  94                 rtlphy->hwparam_tables[RADIOB_1T].pdata =
  95                         RTL8192CU_RADIOB_1TARRAY;
  96                 rtlphy->hwparam_tables[AGCTAB_1T].length =
  97                         RTL8192CUAGCTAB_1T_HPArrayLength;
  98                 rtlphy->hwparam_tables[AGCTAB_1T].pdata =
  99                         Rtl8192CUAGCTAB_1T_HPArray;
 100         } else {
 101                 rtlphy->hwparam_tables[PHY_REG_1T].length =
 102                          RTL8192CUPHY_REG_1TARRAY_LENGTH;
 103                 rtlphy->hwparam_tables[PHY_REG_1T].pdata =
 104                         RTL8192CUPHY_REG_1TARRAY;
 105                 rtlphy->hwparam_tables[RADIOA_1T].length =
 106                         RTL8192CURADIOA_1TARRAYLENGTH;
 107                 rtlphy->hwparam_tables[RADIOA_1T].pdata =
 108                         RTL8192CU_RADIOA_1TARRAY;
 109                 rtlphy->hwparam_tables[RADIOB_1T].length =
 110                         RTL8192CURADIOB_1TARRAYLENGTH;
 111                 rtlphy->hwparam_tables[RADIOB_1T].pdata =
 112                         RTL8192CU_RADIOB_1TARRAY;
 113                 rtlphy->hwparam_tables[AGCTAB_1T].length =
 114                         RTL8192CUAGCTAB_1TARRAYLENGTH;
 115                 rtlphy->hwparam_tables[AGCTAB_1T].pdata =
 116                         RTL8192CUAGCTAB_1TARRAY;
 117         }
 118 }
 119
 120 static void _rtl92cu_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
 121                                                  bool autoload_fail,
 122                                                  u8 *hwinfo)
 123 {
 124         struct rtl_priv *rtlpriv = rtl_priv(hw);
 125         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 126         u8 rf_path, index, tempval;
 127         u16 i;
 128
 129         for (rf_path = 0; rf_path < 2; rf_path++) {
 130                 for (i = 0; i < 3; i++) {
 131                         if (!autoload_fail) {
 132                                 rtlefuse->
 133                                     eeprom_chnlarea_txpwr_cck[rf_path][i] =
 134                                     hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i];
 135                                 rtlefuse->
 136                                     eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
 137                                     hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 +
 138                                            i];
 139                         } else {
 140                                 rtlefuse->
 141                                     eeprom_chnlarea_txpwr_cck[rf_path][i] =
 142                                     EEPROM_DEFAULT_TXPOWERLEVEL;
 143                                 rtlefuse->
 144                                     eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
 145                                     EEPROM_DEFAULT_TXPOWERLEVEL;
 146                         }
 147                 }
 148         }
 149         for (i = 0; i < 3; i++) {
 150                 if (!autoload_fail)
 151                         tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i];
 152                 else
 153                         tempval = EEPROM_DEFAULT_HT40_2SDIFF;
 154                 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif[RF90_PATH_A][i] =
 155                     (tempval & 0xf);
 156                 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif[RF90_PATH_B][i] =
 157                     ((tempval & 0xf0) >> 4);
 158         }
 159         for (rf_path = 0; rf_path < 2; rf_path++)
 160                 for (i = 0; i < 3; i++)
 161                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
 162                                 ("RF(%d) EEPROM CCK Area(%d) = 0x%x\n", rf_path,
 163                                  i, rtlefuse->
 164                                  eeprom_chnlarea_txpwr_cck[rf_path][i]));
 165         for (rf_path = 0; rf_path < 2; rf_path++)
 166                 for (i = 0; i < 3; i++)
 167                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
 168                                 ("RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
 169                                  rf_path, i,
 170                                  rtlefuse->
 171                                  eeprom_chnlarea_txpwr_ht40_1s[rf_path][i]));
 172         for (rf_path = 0; rf_path < 2; rf_path++)
 173                 for (i = 0; i < 3; i++)
 174                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
 175                                 ("RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
 176                                  rf_path, i,
 177                                  rtlefuse->
 178                                  eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path]
 179                                  [i]));
 180         for (rf_path = 0; rf_path < 2; rf_path++) {
 181                 for (i = 0; i < 14; i++) {
 182                         index = _rtl92c_get_chnl_group((u8) i);
 183                         rtlefuse->txpwrlevel_cck[rf_path][i] =
 184                             rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][index];
 185                         rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
 186                             rtlefuse->
 187                             eeprom_chnlarea_txpwr_ht40_1s[rf_path][index];
 188                         if ((rtlefuse->
 189                              eeprom_chnlarea_txpwr_ht40_1s[rf_path][index] -
 190                              rtlefuse->
 191                              eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path][index])
 192                             > 0) {
 193                                 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
 194                                     rtlefuse->
 195                                     eeprom_chnlarea_txpwr_ht40_1s[rf_path]
 196                                     [index] - rtlefuse->
 197                                     eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path]
 198                                     [index];
 199                         } else {
 200                                 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0;
 201                         }
 202                 }
 203                 for (i = 0; i < 14; i++) {
 204                         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
 205                                 ("RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = "
 206                                  "[0x%x / 0x%x / 0x%x]\n", rf_path, i,
 207                                  rtlefuse->txpwrlevel_cck[rf_path][i],
 208                                  rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
 209                                  rtlefuse->txpwrlevel_ht40_2s[rf_path][i]));
 210                 }
 211         }
 212         for (i = 0; i < 3; i++) {
 213                 if (!autoload_fail) {
 214                         rtlefuse->eeprom_pwrlimit_ht40[i] =
 215                             hwinfo[EEPROM_TXPWR_GROUP + i];
 216                         rtlefuse->eeprom_pwrlimit_ht20[i] =
 217                             hwinfo[EEPROM_TXPWR_GROUP + 3 + i];
 218                 } else {
 219                         rtlefuse->eeprom_pwrlimit_ht40[i] = 0;
 220                         rtlefuse->eeprom_pwrlimit_ht20[i] = 0;
 221                 }
 222         }
 223         for (rf_path = 0; rf_path < 2; rf_path++) {
 224                 for (i = 0; i < 14; i++) {
 225                         index = _rtl92c_get_chnl_group((u8) i);
 226                         if (rf_path == RF90_PATH_A) {
 227                                 rtlefuse->pwrgroup_ht20[rf_path][i] =
 228                                     (rtlefuse->eeprom_pwrlimit_ht20[index]
 229                                      & 0xf);
 230                                 rtlefuse->pwrgroup_ht40[rf_path][i] =
 231                                     (rtlefuse->eeprom_pwrlimit_ht40[index]
 232                                      & 0xf);
 233                         } else if (rf_path == RF90_PATH_B) {
 234                                 rtlefuse->pwrgroup_ht20[rf_path][i] =
 235                                     ((rtlefuse->eeprom_pwrlimit_ht20[index]
 236                                       & 0xf0) >> 4);
 237                                 rtlefuse->pwrgroup_ht40[rf_path][i] =
 238                                     ((rtlefuse->eeprom_pwrlimit_ht40[index]
 239                                       & 0xf0) >> 4);
 240                         }
 241                         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
 242                                 ("RF-%d pwrgroup_ht20[%d] = 0x%x\n",
 243                                  rf_path, i,
 244                                  rtlefuse->pwrgroup_ht20[rf_path][i]));
 245                         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
 246                                 ("RF-%d pwrgroup_ht40[%d] = 0x%x\n",
 247                                  rf_path, i,
 248                                  rtlefuse->pwrgroup_ht40[rf_path][i]));
 249                 }
 250         }
 251         for (i = 0; i < 14; i++) {
 252                 index = _rtl92c_get_chnl_group((u8) i);
 253                 if (!autoload_fail)
 254                         tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index];
 255                 else
 256                         tempval = EEPROM_DEFAULT_HT20_DIFF;
 257                 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
 258                 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
 259                     ((tempval >> 4) & 0xF);
 260                 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3))
 261                         rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0;
 262                 if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3))
 263                         rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0;
 264                 index = _rtl92c_get_chnl_group((u8) i);
 265                 if (!autoload_fail)
 266                         tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index];
 267                 else
 268                         tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
 269                 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF);
 270                 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
 271                     ((tempval >> 4) & 0xF);
 272         }
 273         rtlefuse->legacy_ht_txpowerdiff =
 274             rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7];
 275         for (i = 0; i < 14; i++)
 276                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
 277                         ("RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", i,
 278                          rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]));
 279         for (i = 0; i < 14; i++)
 280                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
 281                         ("RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", i,
 282                          rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]));
 283         for (i = 0; i < 14; i++)
 284                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
 285                         ("RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", i,
 286                          rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]));
 287         for (i = 0; i < 14; i++)
 288                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
 289                         ("RF-B Legacy to HT40 Diff[%d] = 0x%x\n", i,
 290                          rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]));
 291         if (!autoload_fail)
 292                 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7);
 293         else
 294                 rtlefuse->eeprom_regulatory = 0;
 295         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
 296                 ("eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory));
 297         if (!autoload_fail) {
 298                 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A];
 299                 rtlefuse->eeprom_tssi[RF90_PATH_B] = hwinfo[EEPROM_TSSI_B];
 300         } else {
 301                 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI;
 302                 rtlefuse->eeprom_tssi[RF90_PATH_B] = EEPROM_DEFAULT_TSSI;
 303         }
 304         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
 305                 ("TSSI_A = 0x%x, TSSI_B = 0x%x\n",
 306                  rtlefuse->eeprom_tssi[RF90_PATH_A],
 307                  rtlefuse->eeprom_tssi[RF90_PATH_B]));
 308         if (!autoload_fail)
 309                 tempval = hwinfo[EEPROM_THERMAL_METER];
 310         else
 311                 tempval = EEPROM_DEFAULT_THERMALMETER;
 312         rtlefuse->eeprom_thermalmeter = (tempval & 0x1f);
 313         if (rtlefuse->eeprom_thermalmeter < 0x06 ||
 314             rtlefuse->eeprom_thermalmeter > 0x1c)
 315                 rtlefuse->eeprom_thermalmeter = 0x12;
 316         if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail)
 317                 rtlefuse->apk_thermalmeterignore = true;
 318         rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
 319         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
 320                 ("thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter));
 321 }
 322
 323 static void _rtl92cu_read_board_type(struct ieee80211_hw *hw, u8 *contents)
 324 {
 325         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 326         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 327         u8 boardType;
 328
 329         if (IS_NORMAL_CHIP(rtlhal->version)) {
 330                 boardType = ((contents[EEPROM_RF_OPT1]) &
 331                             BOARD_TYPE_NORMAL_MASK) >> 5; /*bit[7:5]*/
 332         } else {
 333                 boardType = contents[EEPROM_RF_OPT4];
 334                 boardType &= BOARD_TYPE_TEST_MASK;
 335         }
 336         rtlefuse->board_type = boardType;
 337         if (IS_HIGHT_PA(rtlefuse->board_type))
 338                 rtlefuse->external_pa = 1;
 339         printk(KERN_INFO "rtl8192cu: Board Type %x\n", rtlefuse->board_type);
 340
 341 #ifdef CONFIG_ANTENNA_DIVERSITY
 342         /* Antenna Diversity setting. */
 343         if (registry_par->antdiv_cfg == 2) /* 2: From Efuse */
 344                 rtl_efuse->antenna_cfg = (contents[EEPROM_RF_OPT1]&0x18)>>3;
 345         else
 346                 rtl_efuse->antenna_cfg = registry_par->antdiv_cfg; /* 0:OFF, */
 347
 348         printk(KERN_INFO "rtl8192cu: Antenna Config %x\n",
 349                rtl_efuse->antenna_cfg);
 350 #endif
 351 }
 352
 353 #ifdef CONFIG_BT_COEXIST
 354 static void _update_bt_param(_adapter *padapter)
 355 {
 356         struct btcoexist_priv    *pbtpriv = &(padapter->halpriv.bt_coexist);
 357         struct registry_priv    *registry_par = &padapter->registrypriv;
 358         if (2 != registry_par->bt_iso) {
 359                 /* 0:Low, 1:High, 2:From Efuse */
 360                 pbtpriv->BT_Ant_isolation = registry_par->bt_iso;
 361         }
 362         if (registry_par->bt_sco == 1) {
 363                 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter, 4.Busy,
 364                  * 5.OtherBusy */
 365                 pbtpriv->BT_Service = BT_OtherAction;
 366         } else if (registry_par->bt_sco == 2) {
 367                 pbtpriv->BT_Service = BT_SCO;
 368         } else if (registry_par->bt_sco == 4) {
 369                 pbtpriv->BT_Service = BT_Busy;
 370         } else if (registry_par->bt_sco == 5) {
 371                 pbtpriv->BT_Service = BT_OtherBusy;
 372         } else {
 373                 pbtpriv->BT_Service = BT_Idle;
 374         }
 375         pbtpriv->BT_Ampdu = registry_par->bt_ampdu;
 376         pbtpriv->bCOBT = _TRUE;
 377         pbtpriv->BtEdcaUL = 0;
 378         pbtpriv->BtEdcaDL = 0;
 379         pbtpriv->BtRssiState = 0xff;
 380         pbtpriv->bInitSet = _FALSE;
 381         pbtpriv->bBTBusyTraffic = _FALSE;
 382         pbtpriv->bBTTrafficModeSet = _FALSE;
 383         pbtpriv->bBTNonTrafficModeSet = _FALSE;
 384         pbtpriv->CurrentState = 0;
 385         pbtpriv->PreviousState = 0;
 386         printk(KERN_INFO "rtl8192cu: BT Coexistance = %s\n",
 387                (pbtpriv->BT_Coexist == _TRUE) ? "enable" : "disable");
 388         if (pbtpriv->BT_Coexist) {
 389                 if (pbtpriv->BT_Ant_Num == Ant_x2)
 390                         printk(KERN_INFO "rtl8192cu: BlueTooth BT_"
 391                                "Ant_Num = Antx2\n");
 392                 else if (pbtpriv->BT_Ant_Num == Ant_x1)
 393                         printk(KERN_INFO "rtl8192cu: BlueTooth BT_"
 394                                "Ant_Num = Antx1\n");
 395                 switch (pbtpriv->BT_CoexistType) {
 396                 case BT_2Wire:
 397                         printk(KERN_INFO "rtl8192cu: BlueTooth BT_"
 398                                "CoexistType = BT_2Wire\n");
 399                         break;
 400                 case BT_ISSC_3Wire:
 401                         printk(KERN_INFO "rtl8192cu: BlueTooth BT_"
 402                                "CoexistType = BT_ISSC_3Wire\n");
 403                         break;
 404                 case BT_Accel:
 405                         printk(KERN_INFO "rtl8192cu: BlueTooth BT_"
 406                                "CoexistType = BT_Accel\n");
 407                         break;
 408                 case BT_CSR_BC4:
 409                         printk(KERN_INFO "rtl8192cu: BlueTooth BT_"
 410                                "CoexistType = BT_CSR_BC4\n");
 411                         break;
 412                 case BT_CSR_BC8:
 413                         printk(KERN_INFO "rtl8192cu: BlueTooth BT_"
 414                                "CoexistType = BT_CSR_BC8\n");
 415                         break;
 416                 case BT_RTL8756:
 417                         printk(KERN_INFO "rtl8192cu: BlueTooth BT_"
 418                                "CoexistType = BT_RTL8756\n");
 419                         break;
 420                 default:
 421                         printk(KERN_INFO "rtl8192cu: BlueTooth BT_"
 422                                "CoexistType = Unknown\n");
 423                         break;
 424                 }
 425                 printk(KERN_INFO "rtl8192cu: BlueTooth BT_Ant_isolation = %d\n",
 426                        pbtpriv->BT_Ant_isolation);
 427                 switch (pbtpriv->BT_Service) {
 428                 case BT_OtherAction:
 429                         printk(KERN_INFO "rtl8192cu: BlueTooth BT_Service = "
 430                                "BT_OtherAction\n");
 431                         break;
 432                 case BT_SCO:
 433                         printk(KERN_INFO "rtl8192cu: BlueTooth BT_Service = "
 434                                "BT_SCO\n");
 435                         break;
 436                 case BT_Busy:
 437                         printk(KERN_INFO "rtl8192cu: BlueTooth BT_Service = "
 438                                "BT_Busy\n");
 439                         break;
 440                 case BT_OtherBusy:
 441                         printk(KERN_INFO "rtl8192cu: BlueTooth BT_Service = "
 442                                "BT_OtherBusy\n");
 443                         break;
 444                 default:
 445                         printk(KERN_INFO "rtl8192cu: BlueTooth BT_Service = "
 446                                "BT_Idle\n");
 447                         break;
 448                 }
 449                 printk(KERN_INFO "rtl8192cu: BT_RadioSharedType = 0x%x\n",
 450                        pbtpriv->BT_RadioSharedType);
 451         }
 452 }
 453
 454 #define GET_BT_COEXIST(priv) (&priv->bt_coexist)
 455
 456 static void _rtl92cu_read_bluetooth_coexistInfo(struct ieee80211_hw *hw,
 457                                                 u8 *contents,
 458                                                 bool bautoloadfailed);
 459 {
 460         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
 461         bool isNormal = IS_NORMAL_CHIP(pHalData->VersionID);
 462         struct btcoexist_priv    *pbtpriv = &pHalData->bt_coexist;
 463         u8      rf_opt4;
 464
 465         _rtw_memset(pbtpriv, 0, sizeof(struct btcoexist_priv));
 466         if (AutoloadFail) {
 467                 pbtpriv->BT_Coexist = _FALSE;
 468                 pbtpriv->BT_CoexistType = BT_2Wire;
 469                 pbtpriv->BT_Ant_Num = Ant_x2;
 470                 pbtpriv->BT_Ant_isolation = 0;
 471                 pbtpriv->BT_RadioSharedType = BT_Radio_Shared;
 472                 return;
 473         }
 474         if (isNormal) {
 475                 if (pHalData->BoardType == BOARD_USB_COMBO)
 476                         pbtpriv->BT_Coexist = _TRUE;
 477                 else
 478                         pbtpriv->BT_Coexist = ((PROMContent[EEPROM_RF_OPT3] &
 479                                               0x20) >> 5); /* bit[5] */
 480                 rf_opt4 = PROMContent[EEPROM_RF_OPT4];
 481                 pbtpriv->BT_CoexistType = ((rf_opt4&0xe)>>1); /* bit [3:1] */
 482                 pbtpriv->BT_Ant_Num = (rf_opt4&0x1); /* bit [0] */
 483                 pbtpriv->BT_Ant_isolation = ((rf_opt4&0x10)>>4); /* bit [4] */
 484                 pbtpriv->BT_RadioSharedType = ((rf_opt4&0x20)>>5); /* bit [5] */
 485         } else {
 486                 pbtpriv->BT_Coexist = (PROMContent[EEPROM_RF_OPT4] >> 4) ?
 487                                        _TRUE : _FALSE;
 488         }
 489         _update_bt_param(Adapter);
 490 }
 491 #endif
 492
 493 static void _rtl92cu_read_adapter_info(struct ieee80211_hw *hw)
 494 {
 495         struct rtl_priv *rtlpriv = rtl_priv(hw);
 496         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 497         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 498         u16 i, usvalue;
 499         u8 hwinfo[HWSET_MAX_SIZE] = {0};
 500         u16 eeprom_id;
 501
 502         if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
 503                 rtl_efuse_shadow_map_update(hw);
 504                 memcpy((void *)hwinfo,
 505                        (void *)&rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
 506                        HWSET_MAX_SIZE);
 507         } else if (rtlefuse->epromtype == EEPROM_93C46) {
 508                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 509                          ("RTL819X Not boot from eeprom, check it !!"));
 510         }
 511         RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_LOUD, ("MAP\n"),
 512                       hwinfo, HWSET_MAX_SIZE);
 513         eeprom_id = *((u16 *)&hwinfo[0]);
 514         if (eeprom_id != RTL8190_EEPROM_ID) {
 515                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 516                          ("EEPROM ID(%#x) is invalid!!\n", eeprom_id));
 517                 rtlefuse->autoload_failflag = true;
 518         } else {
 519                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("Autoload OK\n"));
 520                 rtlefuse->autoload_failflag = false;
 521         }
 522         if (rtlefuse->autoload_failflag == true)
 523                 return;
 524         for (i = 0; i < 6; i += 2) {
 525                 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
 526                 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
 527         }
 528         printk(KERN_INFO "rtl8192cu: MAC address: %pM\n", rtlefuse->dev_addr);
 529         _rtl92cu_read_txpower_info_from_hwpg(hw,
 530                                            rtlefuse->autoload_failflag, hwinfo);
 531         rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID];
 532         rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID];
 533         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
 534                  (" VID = 0x%02x PID = 0x%02x\n",
 535                  rtlefuse->eeprom_vid, rtlefuse->eeprom_did));
 536         rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN];
 537         rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION];
 538         rtlefuse->txpwr_fromeprom = true;
 539         rtlefuse->eeprom_oemid = *(u8 *)&hwinfo[EEPROM_CUSTOMER_ID];
 540         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 541                  ("EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid));
 542         if (rtlhal->oem_id == RT_CID_DEFAULT) {
 543                 switch (rtlefuse->eeprom_oemid) {
 544                 case EEPROM_CID_DEFAULT:
 545                         if (rtlefuse->eeprom_did == 0x8176) {
 546                                 if ((rtlefuse->eeprom_svid == 0x103C &&
 547                                      rtlefuse->eeprom_smid == 0x1629))
 548                                         rtlhal->oem_id = RT_CID_819x_HP;
 549                                 else
 550                                         rtlhal->oem_id = RT_CID_DEFAULT;
 551                         } else {
 552                                 rtlhal->oem_id = RT_CID_DEFAULT;
 553                         }
 554                         break;
 555                 case EEPROM_CID_TOSHIBA:
 556                         rtlhal->oem_id = RT_CID_TOSHIBA;
 557                         break;
 558                 case EEPROM_CID_QMI:
 559                         rtlhal->oem_id = RT_CID_819x_QMI;
 560                         break;
 561                 case EEPROM_CID_WHQL:
 562                 default:
 563                         rtlhal->oem_id = RT_CID_DEFAULT;
 564                         break;
 565                 }
 566         }
 567         _rtl92cu_read_board_type(hw, hwinfo);
 568 #ifdef CONFIG_BT_COEXIST
 569         _rtl92cu_read_bluetooth_coexistInfo(hw, hwinfo,
 570                                             rtlefuse->autoload_failflag);
 571 #endif
 572 }
 573
 574 static void _rtl92cu_hal_customized_behavior(struct ieee80211_hw *hw)
 575 {
 576         struct rtl_priv *rtlpriv = rtl_priv(hw);
 577         struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw);
 578         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 579
 580         switch (rtlhal->oem_id) {
 581         case RT_CID_819x_HP:
 582                 usb_priv->ledctl.led_opendrain = true;
 583                 break;
 584         case RT_CID_819x_Lenovo:
 585         case RT_CID_DEFAULT:
 586         case RT_CID_TOSHIBA:
 587         case RT_CID_CCX:
 588         case RT_CID_819x_Acer:
 589         case RT_CID_WHQL:
 590         default:
 591                 break;
 592         }
 593         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
 594                  ("RT Customized ID: 0x%02X\n", rtlhal->oem_id));
 595 }
 596
 597 void rtl92cu_read_eeprom_info(struct ieee80211_hw *hw)
 598 {
 599
 600         struct rtl_priv *rtlpriv = rtl_priv(hw);
 601         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 602         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 603         u8 tmp_u1b;
 604
 605         if (!IS_NORMAL_CHIP(rtlhal->version))
 606                 return;
 607         tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
 608         rtlefuse->epromtype = (tmp_u1b & EEPROMSEL) ?
 609                                EEPROM_93C46 : EEPROM_BOOT_EFUSE;
 610         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("Boot from %s\n",
 611                  (tmp_u1b & EEPROMSEL) ? "EERROM" : "EFUSE"));
 612         rtlefuse->autoload_failflag = (tmp_u1b & EEPROM_EN) ? false : true;
 613         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("Autoload %s\n",
 614                  (tmp_u1b & EEPROM_EN) ? "OK!!" : "ERR!!"));
 615         _rtl92cu_read_adapter_info(hw);
 616         _rtl92cu_hal_customized_behavior(hw);
 617         return;
 618 }
 619
 620 static int _rtl92cu_init_power_on(struct ieee80211_hw *hw)
 621 {
 622         struct rtl_priv *rtlpriv = rtl_priv(hw);
 623         int             status = 0;
 624         u16             value16;
 625         u8              value8;
 626         /*  polling autoload done. */
 627         u32     pollingCount = 0;
 628
 629         do {
 630                 if (rtl_read_byte(rtlpriv, REG_APS_FSMCO) & PFM_ALDN) {
 631                         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
 632                                  ("Autoload Done!\n"));
 633                         break;
 634                 }
 635                 if (pollingCount++ > 100) {
 636                         RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
 637                                  ("Failed to polling REG_APS_FSMCO[PFM_ALDN]"
 638                                  " done!\n"));
 639                         return -ENODEV;
 640                 }
 641         } while (true);
 642         /* 0. RSV_CTRL 0x1C[7:0] = 0 unlock ISO/CLK/Power control register */
 643         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0);
 644         /* Power on when re-enter from IPS/Radio off/card disable */
 645         /* enable SPS into PWM mode */
 646         rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
 647         udelay(100);
 648         value8 = rtl_read_byte(rtlpriv, REG_LDOV12D_CTRL);
 649         if (0 == (value8 & LDV12_EN)) {
 650                 value8 |= LDV12_EN;
 651                 rtl_write_byte(rtlpriv, REG_LDOV12D_CTRL, value8);
 652                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
 653                          (" power-on :REG_LDOV12D_CTRL Reg0x21:0x%02x.\n",
 654                          value8));
 655                 udelay(100);
 656                 value8 = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL);
 657                 value8 &= ~ISO_MD2PP;
 658                 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, value8);
 659         }
 660         /*  auto enable WLAN */
 661         pollingCount = 0;
 662         value16 = rtl_read_word(rtlpriv, REG_APS_FSMCO);
 663         value16 |= APFM_ONMAC;
 664         rtl_write_word(rtlpriv, REG_APS_FSMCO, value16);
 665         do {
 666                 if (!(rtl_read_word(rtlpriv, REG_APS_FSMCO) & APFM_ONMAC)) {
 667                         printk(KERN_INFO "rtl8192cu: MAC auto ON okay!\n");
 668                         break;
 669                 }
 670                 if (pollingCount++ > 100) {
 671                         RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
 672                                  ("Failed to polling REG_APS_FSMCO[APFM_ONMAC]"
 673                                  " done!\n"));
 674                         return -ENODEV;
 675                 }
 676         } while (true);
 677         /* Enable Radio ,GPIO ,and LED function */
 678         rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x0812);
 679         /* release RF digital isolation */
 680         value16 = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL);
 681         value16 &= ~ISO_DIOR;
 682         rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, value16);
 683         /* Reconsider when to do this operation after asking HWSD. */
 684         pollingCount = 0;
 685         rtl_write_byte(rtlpriv, REG_APSD_CTRL, (rtl_read_byte(rtlpriv,
 686                                                 REG_APSD_CTRL) & ~BIT(6)));
 687         do {
 688                 pollingCount++;
 689         } while ((pollingCount < 200) &&
 690                  (rtl_read_byte(rtlpriv, REG_APSD_CTRL) & BIT(7)));
 691         /* Enable MAC DMA/WMAC/SCHEDULE/SEC block */
 692         value16 = rtl_read_word(rtlpriv,  REG_CR);
 693         value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN |
 694                     PROTOCOL_EN | SCHEDULE_EN | MACTXEN | MACRXEN | ENSEC);
 695         rtl_write_word(rtlpriv, REG_CR, value16);
 696         return status;
 697 }
 698
 699 static void _rtl92cu_init_queue_reserved_page(struct ieee80211_hw *hw,
 700                                               bool wmm_enable,
 701                                               u8 out_ep_num,
 702                                               u8 queue_sel)
 703 {
 704         struct rtl_priv *rtlpriv = rtl_priv(hw);
 705         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 706         bool isChipN = IS_NORMAL_CHIP(rtlhal->version);
 707         u32 outEPNum = (u32)out_ep_num;
 708         u32 numHQ = 0;
 709         u32 numLQ = 0;
 710         u32 numNQ = 0;
 711         u32 numPubQ;
 712         u32 value32;
 713         u8 value8;
 714         u32 txQPageNum, txQPageUnit, txQRemainPage;
 715
 716         if (!wmm_enable) {
 717                 numPubQ = (isChipN) ? CHIP_B_PAGE_NUM_PUBQ :
 718                           CHIP_A_PAGE_NUM_PUBQ;
 719                 txQPageNum = TX_TOTAL_PAGE_NUMBER - numPubQ;
 720
 721                 txQPageUnit = txQPageNum/outEPNum;
 722                 txQRemainPage = txQPageNum % outEPNum;
 723                 if (queue_sel & TX_SELE_HQ)
 724                         numHQ = txQPageUnit;
 725                 if (queue_sel & TX_SELE_LQ)
 726                         numLQ = txQPageUnit;
 727                 /* HIGH priority queue always present in the configuration of
 728                  * 2 out-ep. Remainder pages have assigned to High queue */
 729                 if ((outEPNum > 1) && (txQRemainPage))
 730                         numHQ += txQRemainPage;
 731                 /* NOTE: This step done before writting REG_RQPN. */
 732                 if (isChipN) {
 733                         if (queue_sel & TX_SELE_NQ)
 734                                 numNQ = txQPageUnit;
 735                         value8 = (u8)_NPQ(numNQ);
 736                         rtl_write_byte(rtlpriv,  REG_RQPN_NPQ, value8);
 737                 }
 738         } else {
 739                 /* for WMM ,number of out-ep must more than or equal to 2! */
 740                 numPubQ = isChipN ? WMM_CHIP_B_PAGE_NUM_PUBQ :
 741                           WMM_CHIP_A_PAGE_NUM_PUBQ;
 742                 if (queue_sel & TX_SELE_HQ) {
 743                         numHQ = isChipN ? WMM_CHIP_B_PAGE_NUM_HPQ :
 744                                 WMM_CHIP_A_PAGE_NUM_HPQ;
 745                 }
 746                 if (queue_sel & TX_SELE_LQ) {
 747                         numLQ = isChipN ? WMM_CHIP_B_PAGE_NUM_LPQ :
 748                                 WMM_CHIP_A_PAGE_NUM_LPQ;
 749                 }
 750                 /* NOTE: This step done before writting REG_RQPN. */
 751                 if (isChipN) {
 752                         if (queue_sel & TX_SELE_NQ)
 753                                 numNQ = WMM_CHIP_B_PAGE_NUM_NPQ;
 754                         value8 = (u8)_NPQ(numNQ);
 755                         rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8);
 756                 }
 757         }
 758         /* TX DMA */
 759         value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
 760         rtl_write_dword(rtlpriv, REG_RQPN, value32);
 761 }
 762
 763 static void _rtl92c_init_trx_buffer(struct ieee80211_hw *hw, bool wmm_enable)
 764 {
 765         struct rtl_priv *rtlpriv = rtl_priv(hw);
 766         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 767         u8      txpktbuf_bndy;
 768         u8      value8;
 769
 770         if (!wmm_enable)
 771                 txpktbuf_bndy = TX_PAGE_BOUNDARY;
 772         else /* for WMM */
 773                 txpktbuf_bndy = (IS_NORMAL_CHIP(rtlhal->version))
 774                                                 ? WMM_CHIP_B_TX_PAGE_BOUNDARY
 775                                                 : WMM_CHIP_A_TX_PAGE_BOUNDARY;
 776         rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
 777         rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
 778         rtl_write_byte(rtlpriv, REG_TXPKTBUF_WMAC_LBK_BF_HD, txpktbuf_bndy);
 779         rtl_write_byte(rtlpriv, REG_TRXFF_BNDY, txpktbuf_bndy);
 780         rtl_write_byte(rtlpriv, REG_TDECTRL+1, txpktbuf_bndy);
 781         rtl_write_word(rtlpriv,  (REG_TRXFF_BNDY + 2), 0x27FF);
 782         value8 = _PSRX(RX_PAGE_SIZE_REG_VALUE) | _PSTX(PBP_128);
 783         rtl_write_byte(rtlpriv, REG_PBP, value8);
 784 }
 785
 786 static void _rtl92c_init_chipN_reg_priority(struct ieee80211_hw *hw, u16 beQ,
 787                                             u16 bkQ, u16 viQ, u16 voQ,
 788                                             u16 mgtQ, u16 hiQ)
 789 {
 790         struct rtl_priv *rtlpriv = rtl_priv(hw);
 791         u16 value16 = (rtl_read_word(rtlpriv, REG_TRXDMA_CTRL) & 0x7);
 792
 793         value16 |= _TXDMA_BEQ_MAP(beQ) | _TXDMA_BKQ_MAP(bkQ) |
 794                    _TXDMA_VIQ_MAP(viQ) | _TXDMA_VOQ_MAP(voQ) |
 795                    _TXDMA_MGQ_MAP(mgtQ) | _TXDMA_HIQ_MAP(hiQ);
 796         rtl_write_word(rtlpriv,  REG_TRXDMA_CTRL, value16);
 797 }
 798
 799 static void _rtl92cu_init_chipN_one_out_ep_priority(struct ieee80211_hw *hw,
 800                                                     bool wmm_enable,
 801                                                     u8 queue_sel)
 802 {
 803         u16 uninitialized_var(value);
 804
 805         switch (queue_sel) {
 806         case TX_SELE_HQ:
 807                 value = QUEUE_HIGH;
 808                 break;
 809         case TX_SELE_LQ:
 810                 value = QUEUE_LOW;
 811                 break;
 812         case TX_SELE_NQ:
 813                 value = QUEUE_NORMAL;
 814                 break;
 815         default:
 816                 WARN_ON(1); /* Shall not reach here! */
 817                 break;
 818         }
 819         _rtl92c_init_chipN_reg_priority(hw, value, value, value, value,
 820                                         value, value);
 821         printk(KERN_INFO "rtl8192cu: Tx queue select: 0x%02x\n", queue_sel);
 822 }
 823
 824 static void _rtl92cu_init_chipN_two_out_ep_priority(struct ieee80211_hw *hw,
 825                                                                 bool wmm_enable,
 826                                                                 u8 queue_sel)
 827 {
 828         u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
 829         u16 uninitialized_var(valueHi);
 830         u16 uninitialized_var(valueLow);
 831
 832         switch (queue_sel) {
 833         case (TX_SELE_HQ | TX_SELE_LQ):
 834                 valueHi = QUEUE_HIGH;
 835                 valueLow = QUEUE_LOW;
 836                 break;
 837         case (TX_SELE_NQ | TX_SELE_LQ):
 838                 valueHi = QUEUE_NORMAL;
 839                 valueLow = QUEUE_LOW;
 840                 break;
 841         case (TX_SELE_HQ | TX_SELE_NQ):
 842                 valueHi = QUEUE_HIGH;
 843                 valueLow = QUEUE_NORMAL;
 844                 break;
 845         default:
 846                 WARN_ON(1);
 847                 break;
 848         }
 849         if (!wmm_enable) {
 850                 beQ = valueLow;
 851                 bkQ = valueLow;
 852                 viQ = valueHi;
 853                 voQ = valueHi;
 854                 mgtQ = valueHi;
 855                 hiQ = valueHi;
 856         } else {/* for WMM ,CONFIG_OUT_EP_WIFI_MODE */
 857                 beQ = valueHi;
 858                 bkQ = valueLow;
 859                 viQ = valueLow;
 860                 voQ = valueHi;
 861                 mgtQ = valueHi;
 862                 hiQ = valueHi;
 863         }
 864         _rtl92c_init_chipN_reg_priority(hw, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
 865         printk(KERN_INFO "rtl8192cu: Tx queue select: 0x%02x\n", queue_sel);
 866 }
 867
 868 static void _rtl92cu_init_chipN_three_out_ep_priority(struct ieee80211_hw *hw,
 869                                                       bool wmm_enable,
 870                                                       u8 queue_sel)
 871 {
 872         u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
 873         struct rtl_priv *rtlpriv = rtl_priv(hw);
 874
 875         if (!wmm_enable) { /* typical setting */
 876                 beQ     = QUEUE_LOW;
 877                 bkQ     = QUEUE_LOW;
 878                 viQ     = QUEUE_NORMAL;
 879                 voQ     = QUEUE_HIGH;
 880                 mgtQ    = QUEUE_HIGH;
 881                 hiQ     = QUEUE_HIGH;
 882         } else { /* for WMM */
 883                 beQ     = QUEUE_LOW;
 884                 bkQ     = QUEUE_NORMAL;
 885                 viQ     = QUEUE_NORMAL;
 886                 voQ     = QUEUE_HIGH;
 887                 mgtQ    = QUEUE_HIGH;
 888                 hiQ     = QUEUE_HIGH;
 889         }
 890         _rtl92c_init_chipN_reg_priority(hw, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
 891         RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
 892                  ("Tx queue select :0x%02x..\n", queue_sel));
 893 }
 894
 895 static void _rtl92cu_init_chipN_queue_priority(struct ieee80211_hw *hw,
 896                                                bool wmm_enable,
 897                                                u8 out_ep_num,
 898                                                u8 queue_sel)
 899 {
 900         switch (out_ep_num) {
 901         case 1:
 902                 _rtl92cu_init_chipN_one_out_ep_priority(hw, wmm_enable,
 903                                                         queue_sel);
 904                 break;
 905         case 2:
 906                 _rtl92cu_init_chipN_two_out_ep_priority(hw, wmm_enable,
 907                                                         queue_sel);
 908                 break;
 909         case 3:
 910                 _rtl92cu_init_chipN_three_out_ep_priority(hw, wmm_enable,
 911                                                           queue_sel);
 912                 break;
 913         default:
 914                 WARN_ON(1); /* Shall not reach here! */
 915                 break;
 916         }
 917 }
 918
 919 static void _rtl92cu_init_chipT_queue_priority(struct ieee80211_hw *hw,
 920                                                bool wmm_enable,
 921                                                u8 out_ep_num,
 922                                                u8 queue_sel)
 923 {
 924         u8      hq_sele;
 925         struct rtl_priv *rtlpriv = rtl_priv(hw);
 926
 927         switch (out_ep_num) {
 928         case 2: /* (TX_SELE_HQ|TX_SELE_LQ) */
 929                 if (!wmm_enable) /* typical setting */
 930                         hq_sele =  HQSEL_VOQ | HQSEL_VIQ | HQSEL_MGTQ |
 931                                    HQSEL_HIQ;
 932                 else    /* for WMM */
 933                         hq_sele = HQSEL_VOQ | HQSEL_BEQ | HQSEL_MGTQ |
 934                                   HQSEL_HIQ;
 935                 break;
 936         case 1:
 937                 if (TX_SELE_LQ == queue_sel) {
 938                         /* map all endpoint to Low queue */
 939                         hq_sele = 0;
 940                 } else if (TX_SELE_HQ == queue_sel) {
 941                         /* map all endpoint to High queue */
 942                         hq_sele =  HQSEL_VOQ | HQSEL_VIQ | HQSEL_BEQ |
 943                                    HQSEL_BKQ | HQSEL_MGTQ | HQSEL_HIQ;
 944                 }
 945                 break;
 946         default:
 947                 WARN_ON(1); /* Shall not reach here! */
 948                 break;
 949         }
 950         rtl_write_byte(rtlpriv, (REG_TRXDMA_CTRL+1), hq_sele);
 951         RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
 952                  ("Tx queue select :0x%02x..\n", hq_sele));
 953 }
 954
 955 static void _rtl92cu_init_queue_priority(struct ieee80211_hw *hw,
 956                                                 bool wmm_enable,
 957                                                 u8 out_ep_num,
 958                                                 u8 queue_sel)
 959 {
 960         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 961         if (IS_NORMAL_CHIP(rtlhal->version))
 962                 _rtl92cu_init_chipN_queue_priority(hw, wmm_enable, out_ep_num,
 963                                                    queue_sel);
 964         else
 965                 _rtl92cu_init_chipT_queue_priority(hw, wmm_enable, out_ep_num,
 966                                                    queue_sel);
 967 }
 968
 969 static void _rtl92cu_init_usb_aggregation(struct ieee80211_hw *hw)
 970 {
 971 }
 972
 973 static void _rtl92cu_init_wmac_setting(struct ieee80211_hw *hw)
 974 {
 975         u16                     value16;
 976
 977         struct rtl_priv *rtlpriv = rtl_priv(hw);
 978         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 979
 980         mac->rx_conf = (RCR_APM | RCR_AM | RCR_ADF | RCR_AB | RCR_APP_FCS |
 981                       RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL |
 982                       RCR_APP_MIC | RCR_APP_PHYSTS | RCR_ACRC32);
 983         rtl_write_dword(rtlpriv, REG_RCR, mac->rx_conf);
 984         /* Accept all multicast address */
 985         rtl_write_dword(rtlpriv,  REG_MAR, 0xFFFFFFFF);
 986         rtl_write_dword(rtlpriv,  REG_MAR + 4, 0xFFFFFFFF);
 987         /* Accept all management frames */
 988         value16 = 0xFFFF;
 989         rtl92c_set_mgt_filter(hw, value16);
 990         /* Reject all control frame - default value is 0 */
 991         rtl92c_set_ctrl_filter(hw, 0x0);
 992         /* Accept all data frames */
 993         value16 = 0xFFFF;
 994         rtl92c_set_data_filter(hw, value16);
 995 }
 996
 997 static int _rtl92cu_init_mac(struct ieee80211_hw *hw)
 998 {
 999         struct rtl_priv *rtlpriv = rtl_priv(hw);
1000         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1001         struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw);
1002         struct rtl_usb *rtlusb = rtl_usbdev(usb_priv);
1003         int err = 0;
1004         u32     boundary = 0;
1005         u8 wmm_enable = false; /* TODO */
1006         u8 out_ep_nums = rtlusb->out_ep_nums;
1007         u8 queue_sel = rtlusb->out_queue_sel;
1008         err = _rtl92cu_init_power_on(hw);
1009
1010         if (err) {
1011                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1012                         ("Failed to init power on!\n"));
1013                 return err;
1014         }
1015         if (!wmm_enable) {
1016                 boundary = TX_PAGE_BOUNDARY;
1017         } else { /* for WMM */
1018                 boundary = (IS_NORMAL_CHIP(rtlhal->version))
1019                                         ? WMM_CHIP_B_TX_PAGE_BOUNDARY
1020                                         : WMM_CHIP_A_TX_PAGE_BOUNDARY;
1021         }
1022         if (false == rtl92c_init_llt_table(hw, boundary)) {
1023                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1024                         ("Failed to init LLT Table!\n"));
1025                 return -EINVAL;
1026         }
1027         _rtl92cu_init_queue_reserved_page(hw, wmm_enable, out_ep_nums,
1028                                           queue_sel);
1029         _rtl92c_init_trx_buffer(hw, wmm_enable);
1030         _rtl92cu_init_queue_priority(hw, wmm_enable, out_ep_nums,
1031                                      queue_sel);
1032         /* Get Rx PHY status in order to report RSSI and others. */
1033         rtl92c_init_driver_info_size(hw, RTL92C_DRIVER_INFO_SIZE);
1034         rtl92c_init_interrupt(hw);
1035         rtl92c_init_network_type(hw);
1036         _rtl92cu_init_wmac_setting(hw);
1037         rtl92c_init_adaptive_ctrl(hw);
1038         rtl92c_init_edca(hw);
1039         rtl92c_init_rate_fallback(hw);
1040         rtl92c_init_retry_function(hw);
1041         _rtl92cu_init_usb_aggregation(hw);
1042         rtlpriv->cfg->ops->set_bw_mode(hw, NL80211_CHAN_HT20);
1043         rtl92c_set_min_space(hw, IS_92C_SERIAL(rtlhal->version));
1044         rtl92c_init_beacon_parameters(hw, rtlhal->version);
1045         rtl92c_init_ampdu_aggregation(hw);
1046         rtl92c_init_beacon_max_error(hw, true);
1047         return err;
1048 }
1049
1050 void rtl92cu_enable_hw_security_config(struct ieee80211_hw *hw)
1051 {
1052         struct rtl_priv *rtlpriv = rtl_priv(hw);
1053         u8 sec_reg_value = 0x0;
1054         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1055
1056         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1057                  ("PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
1058                   rtlpriv->sec.pairwise_enc_algorithm,
1059                   rtlpriv->sec.group_enc_algorithm));
1060         if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
1061                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1062                          ("not open sw encryption\n"));
1063                 return;
1064         }
1065         sec_reg_value = SCR_TxEncEnable | SCR_RxDecEnable;
1066         if (rtlpriv->sec.use_defaultkey) {
1067                 sec_reg_value |= SCR_TxUseDK;
1068                 sec_reg_value |= SCR_RxUseDK;
1069         }
1070         if (IS_NORMAL_CHIP(rtlhal->version))
1071                 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
1072         rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
1073         RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
1074                  ("The SECR-value %x\n", sec_reg_value));
1075         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
1076 }
1077
1078 static void _rtl92cu_hw_configure(struct ieee80211_hw *hw)
1079 {
1080         struct rtl_priv *rtlpriv = rtl_priv(hw);
1081         struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1082
1083         /* To Fix MAC loopback mode fail. */
1084         rtl_write_byte(rtlpriv, REG_LDOHCI12_CTRL, 0x0f);
1085         rtl_write_byte(rtlpriv, 0x15, 0xe9);
1086         /* HW SEQ CTRL */
1087         /* set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */
1088         rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
1089         /* fixed USB interface interference issue */
1090         rtl_write_byte(rtlpriv, 0xfe40, 0xe0);
1091         rtl_write_byte(rtlpriv, 0xfe41, 0x8d);
1092         rtl_write_byte(rtlpriv, 0xfe42, 0x80);
1093         rtlusb->reg_bcn_ctrl_val = 0x18;
1094         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlusb->reg_bcn_ctrl_val);
1095 }
1096
1097 static void _InitPABias(struct ieee80211_hw *hw)
1098 {
1099         struct rtl_priv *rtlpriv = rtl_priv(hw);
1100         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1101         u8 pa_setting;
1102
1103         /* FIXED PA current issue */
1104         pa_setting = efuse_read_1byte(hw, 0x1FA);
1105         if (!(pa_setting & BIT(0))) {
1106                 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x0F406);
1107                 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x4F406);
1108                 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x8F406);
1109                 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0xCF406);
1110         }
1111         if (!(pa_setting & BIT(1)) && IS_NORMAL_CHIP(rtlhal->version) &&
1112             IS_92C_SERIAL(rtlhal->version)) {
1113                 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x0F406);
1114                 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x4F406);
1115                 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x8F406);
1116                 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0xCF406);
1117         }
1118         if (!(pa_setting & BIT(4))) {
1119                 pa_setting = rtl_read_byte(rtlpriv, 0x16);
1120                 pa_setting &= 0x0F;
1121                 rtl_write_byte(rtlpriv, 0x16, pa_setting | 0x90);
1122         }
1123 }
1124
1125 static void _InitAntenna_Selection(struct ieee80211_hw *hw)
1126 {
1127 #ifdef CONFIG_ANTENNA_DIVERSITY
1128         struct rtl_priv *rtlpriv = rtl_priv(hw);
1129         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1130         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1131
1132         if (pHalData->AntDivCfg == 0)
1133                 return;
1134
1135         if (rtlphy->rf_type == RF_1T1R) {
1136                 rtl_write_dword(rtlpriv, REG_LEDCFG0,
1137                                 rtl_read_dword(rtlpriv,
1138                                 REG_LEDCFG0)|BIT(23));
1139                 rtl_set_bbreg(hw, rFPGA0_XAB_RFPARAMETER, BIT(13), 0x01);
1140                 if (rtl_get_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300) ==
1141                     Antenna_A)
1142                         pHalData->CurAntenna = Antenna_A;
1143                 else
1144                         pHalData->CurAntenna = Antenna_B;
1145         }
1146 #endif
1147 }
1148
1149 static void _dump_registers(struct ieee80211_hw *hw)
1150 {
1151 }
1152
1153 static void _update_mac_setting(struct ieee80211_hw *hw)
1154 {
1155         struct rtl_priv *rtlpriv = rtl_priv(hw);
1156         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1157
1158         mac->rx_conf = rtl_read_dword(rtlpriv, REG_RCR);
1159         mac->rx_mgt_filter = rtl_read_word(rtlpriv, REG_RXFLTMAP0);
1160         mac->rx_ctrl_filter = rtl_read_word(rtlpriv, REG_RXFLTMAP1);
1161         mac->rx_data_filter = rtl_read_word(rtlpriv, REG_RXFLTMAP2);
1162 }
1163
1164 int rtl92cu_hw_init(struct ieee80211_hw *hw)
1165 {
1166         struct rtl_priv *rtlpriv = rtl_priv(hw);
1167         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1168         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1169         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1170         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1171         int err = 0;
1172         static bool iqk_initialized;
1173
1174         rtlhal->hw_type = HARDWARE_TYPE_RTL8192CU;
1175         err = _rtl92cu_init_mac(hw);
1176         if (err) {
1177                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("init mac failed!\n"));
1178                 return err;
1179         }
1180         err = rtl92c_download_fw(hw);
1181         if (err) {
1182                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1183                          ("Failed to download FW. Init HW without FW now..\n"));
1184                 err = 1;
1185                 rtlhal->fw_ready = false;
1186                 return err;
1187         } else {
1188                 rtlhal->fw_ready = true;
1189         }
1190         rtlhal->last_hmeboxnum = 0; /* h2c */
1191         _rtl92cu_phy_param_tab_init(hw);
1192         rtl92cu_phy_mac_config(hw);
1193         rtl92cu_phy_bb_config(hw);
1194         rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
1195         rtl92c_phy_rf_config(hw);
1196         if (IS_VENDOR_UMC_A_CUT(rtlhal->version) &&
1197             !IS_92C_SERIAL(rtlhal->version)) {
1198                 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255);
1199                 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00);
1200         }
1201         rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
1202                                                  RF_CHNLBW, RFREG_OFFSET_MASK);
1203         rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
1204                                                  RF_CHNLBW, RFREG_OFFSET_MASK);
1205         rtl92cu_bb_block_on(hw);
1206         rtl_cam_reset_all_entry(hw);
1207         rtl92cu_enable_hw_security_config(hw);
1208         ppsc->rfpwr_state = ERFON;
1209         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1210         if (ppsc->rfpwr_state == ERFON) {
1211                 rtl92c_phy_set_rfpath_switch(hw, 1);
1212                 if (iqk_initialized) {
1213                         rtl92c_phy_iq_calibrate(hw, false);
1214                 } else {
1215                         rtl92c_phy_iq_calibrate(hw, false);
1216                         iqk_initialized = true;
1217                 }
1218                 rtl92c_dm_check_txpower_tracking(hw);
1219                 rtl92c_phy_lc_calibrate(hw);
1220         }
1221         _rtl92cu_hw_configure(hw);
1222         _InitPABias(hw);
1223         _InitAntenna_Selection(hw);
1224         _update_mac_setting(hw);
1225         rtl92c_dm_init(hw);
1226         _dump_registers(hw);
1227         return err;
1228 }
1229
1230 static void _DisableRFAFEAndResetBB(struct ieee80211_hw *hw)
1231 {
1232         struct rtl_priv *rtlpriv = rtl_priv(hw);
1233 /**************************************
1234 a.      TXPAUSE 0x522[7:0] = 0xFF       Pause MAC TX queue
1235 b.      RF path 0 offset 0x00 = 0x00    disable RF
1236 c.      APSD_CTRL 0x600[7:0] = 0x40
1237 d.      SYS_FUNC_EN 0x02[7:0] = 0x16    reset BB state machine
1238 e.      SYS_FUNC_EN 0x02[7:0] = 0x14    reset BB state machine
1239 ***************************************/
1240         u8 eRFPath = 0, value8 = 0;
1241         rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1242         rtl_set_rfreg(hw, (enum radio_path)eRFPath, 0x0, MASKBYTE0, 0x0);
1243
1244         value8 |= APSDOFF;
1245         rtl_write_byte(rtlpriv, REG_APSD_CTRL, value8); /*0x40*/
1246         value8 = 0;
1247         value8 |= (FEN_USBD | FEN_USBA | FEN_BB_GLB_RSTn);
1248         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, value8);/*0x16*/
1249         value8 &= (~FEN_BB_GLB_RSTn);
1250         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, value8); /*0x14*/
1251 }
1252
1253 static void  _ResetDigitalProcedure1(struct ieee80211_hw *hw, bool bWithoutHWSM)
1254 {
1255         struct rtl_priv *rtlpriv = rtl_priv(hw);
1256         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1257
1258         if (rtlhal->fw_version <=  0x20) {
1259                 /*****************************
1260                 f. MCUFWDL 0x80[7:0]=0          reset MCU ready status
1261                 g. SYS_FUNC_EN 0x02[10]= 0      reset MCU reg, (8051 reset)
1262                 h. SYS_FUNC_EN 0x02[15-12]= 5   reset MAC reg, DCORE
1263                 i. SYS_FUNC_EN 0x02[10]= 1      enable MCU reg, (8051 enable)
1264                 ******************************/
1265                 u16 valu16 = 0;
1266
1267                 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
1268                 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1269                 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 &
1270                                (~FEN_CPUEN))); /* reset MCU ,8051 */
1271                 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN)&0x0FFF;
1272                 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 |
1273                               (FEN_HWPDN|FEN_ELDR))); /* reset MAC */
1274                 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1275                 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 |
1276                                FEN_CPUEN)); /* enable MCU ,8051 */
1277         } else {
1278                 u8 retry_cnts = 0;
1279
1280                 /* IF fw in RAM code, do reset */
1281                 if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(1)) {
1282                         /* reset MCU ready status */
1283                         rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
1284                         if (rtlhal->fw_ready) {
1285                                 /* 8051 reset by self */
1286                                 rtl_write_byte(rtlpriv, REG_HMETFR+3, 0x20);
1287                                 while ((retry_cnts++ < 100) &&
1288                                        (FEN_CPUEN & rtl_read_word(rtlpriv,
1289                                        REG_SYS_FUNC_EN))) {
1290                                         udelay(50);
1291                                 }
1292                                 if (retry_cnts >= 100) {
1293                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1294                                                 ("#####=> 8051 reset failed!.."
1295                                                 ".......................\n"););
1296                                         /* if 8051 reset fail, reset MAC. */
1297                                         rtl_write_byte(rtlpriv,
1298                                                        REG_SYS_FUNC_EN + 1,
1299                                                        0x50);
1300                                         udelay(100);
1301                                 }
1302                         }
1303                 }
1304                 /* Reset MAC and Enable 8051 */
1305                 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x54);
1306                 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
1307         }
1308         if (bWithoutHWSM) {
1309                 /*****************************
1310                   Without HW auto state machine
1311                 g.SYS_CLKR 0x08[15:0] = 0x30A3          disable MAC clock
1312                 h.AFE_PLL_CTRL 0x28[7:0] = 0x80         disable AFE PLL
1313                 i.AFE_XTAL_CTRL 0x24[15:0] = 0x880F     gated AFE DIG_CLOCK
1314                 j.SYS_ISu_CTRL 0x00[7:0] = 0xF9         isolated digital to PON
1315                 ******************************/
1316                 rtl_write_word(rtlpriv, REG_SYS_CLKR, 0x70A3);
1317                 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80);
1318                 rtl_write_word(rtlpriv, REG_AFE_XTAL_CTRL, 0x880F);
1319                 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xF9);
1320         }
1321 }
1322
1323 static void _ResetDigitalProcedure2(struct ieee80211_hw *hw)
1324 {
1325         struct rtl_priv *rtlpriv = rtl_priv(hw);
1326 /*****************************
1327 k. SYS_FUNC_EN 0x03[7:0] = 0x44         disable ELDR runction
1328 l. SYS_CLKR 0x08[15:0] = 0x3083         disable ELDR clock
1329 m. SYS_ISO_CTRL 0x01[7:0] = 0x83        isolated ELDR to PON
1330 ******************************/
1331         rtl_write_word(rtlpriv, REG_SYS_CLKR, 0x70A3);
1332         rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL+1, 0x82);
1333 }
1334
1335 static void _DisableGPIO(struct ieee80211_hw *hw)
1336 {
1337         struct rtl_priv *rtlpriv = rtl_priv(hw);
1338 /***************************************
1339 j. GPIO_PIN_CTRL 0x44[31:0]=0x000
1340 k. Value = GPIO_PIN_CTRL[7:0]
1341 l.  GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8); write ext PIN level
1342 m. GPIO_MUXCFG 0x42 [15:0] = 0x0780
1343 n. LEDCFG 0x4C[15:0] = 0x8080
1344 ***************************************/
1345         u8      value8;
1346         u16     value16;
1347         u32     value32;
1348
1349         /* 1. Disable GPIO[7:0] */
1350         rtl_write_word(rtlpriv, REG_GPIO_PIN_CTRL+2, 0x0000);
1351         value32 = rtl_read_dword(rtlpriv, REG_GPIO_PIN_CTRL) & 0xFFFF00FF;
1352         value8 = (u8) (value32&0x000000FF);
1353         value32 |= ((value8<<8) | 0x00FF0000);
1354         rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, value32);
1355         /* 2. Disable GPIO[10:8] */
1356         rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG+3, 0x00);
1357         value16 = rtl_read_word(rtlpriv, REG_GPIO_MUXCFG+2) & 0xFF0F;
1358         value8 = (u8) (value16&0x000F);
1359         value16 |= ((value8<<4) | 0x0780);
1360         rtl_write_word(rtlpriv, REG_GPIO_PIN_CTRL+2, value16);
1361         /* 3. Disable LED0 & 1 */
1362         rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080);
1363 }
1364
1365 static void _DisableAnalog(struct ieee80211_hw *hw, bool bWithoutHWSM)
1366 {
1367         struct rtl_priv *rtlpriv = rtl_priv(hw);
1368         u16 value16 = 0;
1369         u8 value8 = 0;
1370
1371         if (bWithoutHWSM) {
1372                 /*****************************
1373                 n. LDOA15_CTRL 0x20[7:0] = 0x04  disable A15 power
1374                 o. LDOV12D_CTRL 0x21[7:0] = 0x54 disable digital core power
1375                 r. When driver call disable, the ASIC will turn off remaining
1376                    clock automatically
1377                 ******************************/
1378                 rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x04);
1379                 value8 = rtl_read_byte(rtlpriv, REG_LDOV12D_CTRL);
1380                 value8 &= (~LDV12_EN);
1381                 rtl_write_byte(rtlpriv, REG_LDOV12D_CTRL, value8);
1382         }
1383
1384 /*****************************
1385 h. SPS0_CTRL 0x11[7:0] = 0x23           enter PFM mode
1386 i. APS_FSMCO 0x04[15:0] = 0x4802        set USB suspend
1387 ******************************/
1388         rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23);
1389         value16 |= (APDM_HOST | AFSM_HSUS | PFM_ALDN);
1390         rtl_write_word(rtlpriv, REG_APS_FSMCO, (u16)value16);
1391         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0E);
1392 }
1393
1394 static void _CardDisableHWSM(struct ieee80211_hw *hw)
1395 {
1396         /* ==== RF Off Sequence ==== */
1397         _DisableRFAFEAndResetBB(hw);
1398         /* ==== Reset digital sequence   ====== */
1399         _ResetDigitalProcedure1(hw, false);
1400         /*  ==== Pull GPIO PIN to balance level and LED control ====== */
1401         _DisableGPIO(hw);
1402         /* ==== Disable analog sequence === */
1403         _DisableAnalog(hw, false);
1404 }
1405
1406 static void _CardDisableWithoutHWSM(struct ieee80211_hw *hw)
1407 {
1408         /*==== RF Off Sequence ==== */
1409         _DisableRFAFEAndResetBB(hw);
1410         /*  ==== Reset digital sequence   ====== */
1411         _ResetDigitalProcedure1(hw, true);
1412         /*  ==== Pull GPIO PIN to balance level and LED control ====== */
1413         _DisableGPIO(hw);
1414         /*  ==== Reset digital sequence   ====== */
1415         _ResetDigitalProcedure2(hw);
1416         /*  ==== Disable analog sequence === */
1417         _DisableAnalog(hw, true);
1418 }
1419
1420 static void _rtl92cu_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
1421                                       u8 set_bits, u8 clear_bits)
1422 {
1423         struct rtl_priv *rtlpriv = rtl_priv(hw);
1424         struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1425
1426         rtlusb->reg_bcn_ctrl_val |= set_bits;
1427         rtlusb->reg_bcn_ctrl_val &= ~clear_bits;
1428         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlusb->reg_bcn_ctrl_val);
1429 }
1430
1431 static void _rtl92cu_stop_tx_beacon(struct ieee80211_hw *hw)
1432 {
1433         struct rtl_priv *rtlpriv = rtl_priv(hw);
1434         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1435         u8 tmp1byte = 0;
1436         if (IS_NORMAL_CHIP(rtlhal->version)) {
1437                 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
1438                 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
1439                                tmp1byte & (~BIT(6)));
1440                 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
1441                 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
1442                 tmp1byte &= ~(BIT(0));
1443                 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
1444         } else {
1445                 rtl_write_byte(rtlpriv, REG_TXPAUSE,
1446                                rtl_read_byte(rtlpriv, REG_TXPAUSE) | BIT(6));
1447         }
1448 }
1449
1450 static void _rtl92cu_resume_tx_beacon(struct ieee80211_hw *hw)
1451 {
1452         struct rtl_priv *rtlpriv = rtl_priv(hw);
1453         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1454         u8 tmp1byte = 0;
1455
1456         if (IS_NORMAL_CHIP(rtlhal->version)) {
1457                 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
1458                 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
1459                                tmp1byte | BIT(6));
1460                 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
1461                 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
1462                 tmp1byte |= BIT(0);
1463                 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
1464         } else {
1465                 rtl_write_byte(rtlpriv, REG_TXPAUSE,
1466                                rtl_read_byte(rtlpriv, REG_TXPAUSE) & (~BIT(6)));
1467         }
1468 }
1469
1470 static void _rtl92cu_enable_bcn_sub_func(struct ieee80211_hw *hw)
1471 {
1472         struct rtl_priv *rtlpriv = rtl_priv(hw);
1473         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1474
1475         if (IS_NORMAL_CHIP(rtlhal->version))
1476                 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(1));
1477         else
1478                 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4));
1479 }
1480
1481 static void _rtl92cu_disable_bcn_sub_func(struct ieee80211_hw *hw)
1482 {
1483         struct rtl_priv *rtlpriv = rtl_priv(hw);
1484         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1485
1486         if (IS_NORMAL_CHIP(rtlhal->version))
1487                 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(1), 0);
1488         else
1489                 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);
1490 }
1491
1492 static int _rtl92cu_set_media_status(struct ieee80211_hw *hw,
1493                                      enum nl80211_iftype type)
1494 {
1495         struct rtl_priv *rtlpriv = rtl_priv(hw);
1496         u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1497         enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1498
1499         bt_msr &= 0xfc;
1500         rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xFF);
1501         if (type == NL80211_IFTYPE_UNSPECIFIED || type ==
1502             NL80211_IFTYPE_STATION) {
1503                 _rtl92cu_stop_tx_beacon(hw);
1504                 _rtl92cu_enable_bcn_sub_func(hw);
1505         } else if (type == NL80211_IFTYPE_ADHOC || type == NL80211_IFTYPE_AP) {
1506                 _rtl92cu_resume_tx_beacon(hw);
1507                 _rtl92cu_disable_bcn_sub_func(hw);
1508         } else {
1509                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, ("Set HW_VAR_MEDIA_"
1510                          "STATUS:No such media status(%x).\n", type));
1511         }
1512         switch (type) {
1513         case NL80211_IFTYPE_UNSPECIFIED:
1514                 bt_msr |= MSR_NOLINK;
1515                 ledaction = LED_CTL_LINK;
1516                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1517                          ("Set Network type to NO LINK!\n"));
1518                 break;
1519         case NL80211_IFTYPE_ADHOC:
1520                 bt_msr |= MSR_ADHOC;
1521                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1522                          ("Set Network type to Ad Hoc!\n"));
1523                 break;
1524         case NL80211_IFTYPE_STATION:
1525                 bt_msr |= MSR_INFRA;
1526                 ledaction = LED_CTL_LINK;
1527                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1528                          ("Set Network type to STA!\n"));
1529                 break;
1530         case NL80211_IFTYPE_AP:
1531                 bt_msr |= MSR_AP;
1532                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1533                          ("Set Network type to AP!\n"));
1534                 break;
1535         default:
1536                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1537                          ("Network type %d not support!\n", type));
1538                 goto error_out;
1539         }
1540         rtl_write_byte(rtlpriv, (MSR), bt_msr);
1541         rtlpriv->cfg->ops->led_control(hw, ledaction);
1542         if ((bt_msr & 0xfc) == MSR_AP)
1543                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1544         else
1545                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1546         return 0;
1547 error_out:
1548         return 1;
1549 }
1550
1551 void rtl92cu_card_disable(struct ieee80211_hw *hw)
1552 {
1553         struct rtl_priv *rtlpriv = rtl_priv(hw);
1554         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1555         struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1556         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1557         enum nl80211_iftype opmode;
1558
1559         mac->link_state = MAC80211_NOLINK;
1560         opmode = NL80211_IFTYPE_UNSPECIFIED;
1561         _rtl92cu_set_media_status(hw, opmode);
1562         rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1563         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1564         if (rtlusb->disableHWSM)
1565                 _CardDisableHWSM(hw);
1566         else
1567                 _CardDisableWithoutHWSM(hw);
1568 }
1569
1570 void rtl92cu_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1571 {
1572         /* dummy routine needed for callback from rtl_op_configure_filter() */
1573 }
1574
1575 /*========================================================================== */
1576
1577 static void _rtl92cu_set_check_bssid(struct ieee80211_hw *hw,
1578                               enum nl80211_iftype type)
1579 {
1580         struct rtl_priv *rtlpriv = rtl_priv(hw);
1581         u32 reg_rcr = rtl_read_dword(rtlpriv, REG_RCR);
1582         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1583         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1584         u8 filterout_non_associated_bssid = false;
1585
1586         switch (type) {
1587         case NL80211_IFTYPE_ADHOC:
1588         case NL80211_IFTYPE_STATION:
1589                 filterout_non_associated_bssid = true;
1590                 break;
1591         case NL80211_IFTYPE_UNSPECIFIED:
1592         case NL80211_IFTYPE_AP:
1593         default:
1594                 break;
1595         }
1596         if (filterout_non_associated_bssid == true) {
1597                 if (IS_NORMAL_CHIP(rtlhal->version)) {
1598                         switch (rtlphy->current_io_type) {
1599                         case IO_CMD_RESUME_DM_BY_SCAN:
1600                                 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1601                                 rtlpriv->cfg->ops->set_hw_reg(hw,
1602                                                  HW_VAR_RCR, (u8 *)(&reg_rcr));
1603                                 /* enable update TSF */
1604                                 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4));
1605                                 break;
1606                         case IO_CMD_PAUSE_DM_BY_SCAN:
1607                                 reg_rcr &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1608                                 rtlpriv->cfg->ops->set_hw_reg(hw,
1609                                                  HW_VAR_RCR, (u8 *)(&reg_rcr));
1610                                 /* disable update TSF */
1611                                 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);
1612                                 break;
1613                         }
1614                 } else {
1615                         reg_rcr |= (RCR_CBSSID);
1616                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1617                                                       (u8 *)(&reg_rcr));
1618                         _rtl92cu_set_bcn_ctrl_reg(hw, 0, (BIT(4)|BIT(5)));
1619                 }
1620         } else if (filterout_non_associated_bssid == false) {
1621                 if (IS_NORMAL_CHIP(rtlhal->version)) {
1622                         reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1623                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1624                                                       (u8 *)(&reg_rcr));
1625                         _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);
1626                 } else {
1627                         reg_rcr &= (~RCR_CBSSID);
1628                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1629                                                       (u8 *)(&reg_rcr));
1630                         _rtl92cu_set_bcn_ctrl_reg(hw, (BIT(4)|BIT(5)), 0);
1631                 }
1632         }
1633 }
1634
1635 int rtl92cu_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1636 {
1637         if (_rtl92cu_set_media_status(hw, type))
1638                 return -EOPNOTSUPP;
1639         _rtl92cu_set_check_bssid(hw, type);
1640         return 0;
1641 }
1642
1643 static void _InitBeaconParameters(struct ieee80211_hw *hw)
1644 {
1645         struct rtl_priv *rtlpriv = rtl_priv(hw);
1646         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1647
1648         rtl_write_word(rtlpriv, REG_BCN_CTRL, 0x1010);
1649
1650         /* TODO: Remove these magic number */
1651         rtl_write_word(rtlpriv, REG_TBTT_PROHIBIT, 0x6404);
1652         rtl_write_byte(rtlpriv, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME);
1653         rtl_write_byte(rtlpriv, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME);
1654         /* Change beacon AIFS to the largest number
1655          * beacause test chip does not contension before sending beacon. */
1656         if (IS_NORMAL_CHIP(rtlhal->version))
1657                 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660F);
1658         else
1659                 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x66FF);
1660 }
1661
1662 static void _beacon_function_enable(struct ieee80211_hw *hw, bool Enable,
1663                                     bool Linked)
1664 {
1665         struct rtl_priv *rtlpriv = rtl_priv(hw);
1666
1667         _rtl92cu_set_bcn_ctrl_reg(hw, (BIT(4) | BIT(3) | BIT(1)), 0x00);
1668         rtl_write_byte(rtlpriv, REG_RD_CTRL+1, 0x6F);
1669 }
1670
1671 void rtl92cu_set_beacon_related_registers(struct ieee80211_hw *hw)
1672 {
1673
1674         struct rtl_priv *rtlpriv = rtl_priv(hw);
1675         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1676         u16 bcn_interval, atim_window;
1677         u32 value32;
1678
1679         bcn_interval = mac->beacon_interval;
1680         atim_window = 2;        /*FIX MERGE */
1681         rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1682         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1683         _InitBeaconParameters(hw);
1684         rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
1685         /*
1686          * Force beacon frame transmission even after receiving beacon frame
1687          * from other ad hoc STA
1688          *
1689          *
1690          * Reset TSF Timer to zero, added by Roger. 2008.06.24
1691          */
1692         value32 = rtl_read_dword(rtlpriv, REG_TCR);
1693         value32 &= ~TSFRST;
1694         rtl_write_dword(rtlpriv, REG_TCR, value32);
1695         value32 |= TSFRST;
1696         rtl_write_dword(rtlpriv, REG_TCR, value32);
1697         RT_TRACE(rtlpriv, COMP_INIT|COMP_BEACON, DBG_LOUD,
1698                  ("SetBeaconRelatedRegisters8192CUsb(): Set TCR(%x)\n",
1699                  value32));
1700         /* TODO: Modify later (Find the right parameters)
1701          * NOTE: Fix test chip's bug (about contention windows's randomness) */
1702         if ((mac->opmode == NL80211_IFTYPE_ADHOC) ||
1703             (mac->opmode == NL80211_IFTYPE_AP)) {
1704                 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x50);
1705                 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x50);
1706         }
1707         _beacon_function_enable(hw, true, true);
1708 }
1709
1710 void rtl92cu_set_beacon_interval(struct ieee80211_hw *hw)
1711 {
1712         struct rtl_priv *rtlpriv = rtl_priv(hw);
1713         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1714         u16 bcn_interval = mac->beacon_interval;
1715
1716         RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1717                  ("beacon_interval:%d\n", bcn_interval));
1718         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1719 }
1720
1721 void rtl92cu_update_interrupt_mask(struct ieee80211_hw *hw,
1722                                    u32 add_msr, u32 rm_msr)
1723 {
1724 }
1725
1726 void rtl92cu_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
1727 {
1728         struct rtl_priv *rtlpriv = rtl_priv(hw);
1729         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1730         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1731
1732         switch (variable) {
1733         case HW_VAR_RCR:
1734                 *((u32 *)(val)) = mac->rx_conf;
1735                 break;
1736         case HW_VAR_RF_STATE:
1737                 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
1738                 break;
1739         case HW_VAR_FWLPS_RF_ON:{
1740                         enum rf_pwrstate rfState;
1741                         u32 val_rcr;
1742
1743                         rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE,
1744                                                       (u8 *)(&rfState));
1745                         if (rfState == ERFOFF) {
1746                                 *((bool *) (val)) = true;
1747                         } else {
1748                                 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
1749                                 val_rcr &= 0x00070000;
1750                                 if (val_rcr)
1751                                         *((bool *) (val)) = false;
1752                                 else
1753                                         *((bool *) (val)) = true;
1754                         }
1755                         break;
1756                 }
1757         case HW_VAR_FW_PSMODE_STATUS:
1758                 *((bool *) (val)) = ppsc->fw_current_inpsmode;
1759                 break;
1760         case HW_VAR_CORRECT_TSF:{
1761                         u64 tsf;
1762                         u32 *ptsf_low = (u32 *)&tsf;
1763                         u32 *ptsf_high = ((u32 *)&tsf) + 1;
1764
1765                         *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
1766                         *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
1767                         *((u64 *)(val)) = tsf;
1768                         break;
1769                 }
1770         case HW_VAR_MGT_FILTER:
1771                 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP0);
1772                 break;
1773         case HW_VAR_CTRL_FILTER:
1774                 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP1);
1775                 break;
1776         case HW_VAR_DATA_FILTER:
1777                 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP2);
1778                 break;
1779         default:
1780                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1781                          ("switch case not process\n"));
1782                 break;
1783         }
1784 }
1785
1786 void rtl92cu_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
1787 {
1788         struct rtl_priv *rtlpriv = rtl_priv(hw);
1789         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1790         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1791         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1792         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1793         struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1794         enum wireless_mode wirelessmode = mac->mode;
1795         u8 idx = 0;
1796
1797         switch (variable) {
1798         case HW_VAR_ETHER_ADDR:{
1799                         for (idx = 0; idx < ETH_ALEN; idx++) {
1800                                 rtl_write_byte(rtlpriv, (REG_MACID + idx),
1801                                                val[idx]);
1802                         }
1803                         break;
1804                 }
1805         case HW_VAR_BASIC_RATE:{
1806                         u16 rate_cfg = ((u16 *) val)[0];
1807                         u8 rate_index = 0;
1808
1809                         rate_cfg &= 0x15f;
1810                         /* TODO */
1811                         /* if (mac->current_network.vender == HT_IOT_PEER_CISCO
1812                          *     && ((rate_cfg & 0x150) == 0)) {
1813                          *        rate_cfg |= 0x010;
1814                          * } */
1815                         rate_cfg |= 0x01;
1816                         rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff);
1817                         rtl_write_byte(rtlpriv, REG_RRSR + 1,
1818                                        (rate_cfg >> 8) & 0xff);
1819                         while (rate_cfg > 0x1) {
1820                                 rate_cfg >>= 1;
1821                                 rate_index++;
1822                         }
1823                         rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
1824                                        rate_index);
1825                         break;
1826                 }
1827         case HW_VAR_BSSID:{
1828                         for (idx = 0; idx < ETH_ALEN; idx++) {
1829                                 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
1830                                                val[idx]);
1831                         }
1832                         break;
1833                 }
1834         case HW_VAR_SIFS:{
1835                         rtl_write_byte(rtlpriv, REG_SIFS_CCK + 1, val[0]);
1836                         rtl_write_byte(rtlpriv, REG_SIFS_OFDM + 1, val[1]);
1837                         rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
1838                         rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
1839                         rtl_write_byte(rtlpriv, REG_R2T_SIFS+1, val[0]);
1840                         rtl_write_byte(rtlpriv, REG_T2T_SIFS+1, val[0]);
1841                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1842                                  ("HW_VAR_SIFS\n"));
1843                         break;
1844                 }
1845         case HW_VAR_SLOT_TIME:{
1846                         u8 e_aci;
1847                         u8 QOS_MODE = 1;
1848
1849                         rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
1850                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1851                                  ("HW_VAR_SLOT_TIME %x\n", val[0]));
1852                         if (QOS_MODE) {
1853                                 for (e_aci = 0; e_aci < AC_MAX; e_aci++)
1854                                         rtlpriv->cfg->ops->set_hw_reg(hw,
1855                                                                 HW_VAR_AC_PARAM,
1856                                                                 (u8 *)(&e_aci));
1857                         } else {
1858                                 u8 sifstime = 0;
1859                                 u8      u1bAIFS;
1860
1861                                 if (IS_WIRELESS_MODE_A(wirelessmode) ||
1862                                     IS_WIRELESS_MODE_N_24G(wirelessmode) ||
1863                                     IS_WIRELESS_MODE_N_5G(wirelessmode))
1864                                         sifstime = 16;
1865                                 else
1866                                         sifstime = 10;
1867                                 u1bAIFS = sifstime + (2 *  val[0]);
1868                                 rtl_write_byte(rtlpriv, REG_EDCA_VO_PARAM,
1869                                                u1bAIFS);
1870                                 rtl_write_byte(rtlpriv, REG_EDCA_VI_PARAM,
1871                                                u1bAIFS);
1872                                 rtl_write_byte(rtlpriv, REG_EDCA_BE_PARAM,
1873                                                u1bAIFS);
1874                                 rtl_write_byte(rtlpriv, REG_EDCA_BK_PARAM,
1875                                                u1bAIFS);
1876                         }
1877                         break;
1878                 }
1879         case HW_VAR_ACK_PREAMBLE:{
1880                         u8 reg_tmp;
1881                         u8 short_preamble = (bool) (*(u8 *) val);
1882                         reg_tmp = 0;
1883                         if (short_preamble)
1884                                 reg_tmp |= 0x80;
1885                         rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
1886                         break;
1887                 }
1888         case HW_VAR_AMPDU_MIN_SPACE:{
1889                         u8 min_spacing_to_set;
1890                         u8 sec_min_space;
1891
1892                         min_spacing_to_set = *((u8 *) val);
1893                         if (min_spacing_to_set <= 7) {
1894                                 switch (rtlpriv->sec.pairwise_enc_algorithm) {
1895                                 case NO_ENCRYPTION:
1896                                 case AESCCMP_ENCRYPTION:
1897                                         sec_min_space = 0;
1898                                         break;
1899                                 case WEP40_ENCRYPTION:
1900                                 case WEP104_ENCRYPTION:
1901                                 case TKIP_ENCRYPTION:
1902                                         sec_min_space = 6;
1903                                         break;
1904                                 default:
1905                                         sec_min_space = 7;
1906                                         break;
1907                                 }
1908                                 if (min_spacing_to_set < sec_min_space)
1909                                         min_spacing_to_set = sec_min_space;
1910                                 mac->min_space_cfg = ((mac->min_space_cfg &
1911                                                      0xf8) |
1912                                                      min_spacing_to_set);
1913                                 *val = min_spacing_to_set;
1914                                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1915                                         ("Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
1916                                         mac->min_space_cfg));
1917                                 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
1918                                                mac->min_space_cfg);
1919                         }
1920                         break;
1921                 }
1922         case HW_VAR_SHORTGI_DENSITY:{
1923                         u8 density_to_set;
1924
1925                         density_to_set = *((u8 *) val);
1926                         density_to_set &= 0x1f;
1927                         mac->min_space_cfg &= 0x07;
1928                         mac->min_space_cfg |= (density_to_set << 3);
1929                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1930                                  ("Set HW_VAR_SHORTGI_DENSITY: %#x\n",
1931                                   mac->min_space_cfg));
1932                         rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
1933                                        mac->min_space_cfg);
1934                         break;
1935                 }
1936         case HW_VAR_AMPDU_FACTOR:{
1937                         u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9};
1938                         u8 factor_toset;
1939                         u8 *p_regtoset = NULL;
1940                         u8 index = 0;
1941
1942                         p_regtoset = regtoset_normal;
1943                         factor_toset = *((u8 *) val);
1944                         if (factor_toset <= 3) {
1945                                 factor_toset = (1 << (factor_toset + 2));
1946                                 if (factor_toset > 0xf)
1947                                         factor_toset = 0xf;
1948                                 for (index = 0; index < 4; index++) {
1949                                         if ((p_regtoset[index] & 0xf0) >
1950                                             (factor_toset << 4))
1951                                                 p_regtoset[index] =
1952                                                      (p_regtoset[index] & 0x0f)
1953                                                      | (factor_toset << 4);
1954                                         if ((p_regtoset[index] & 0x0f) >
1955                                              factor_toset)
1956                                                 p_regtoset[index] =
1957                                                      (p_regtoset[index] & 0xf0)
1958                                                      | (factor_toset);
1959                                         rtl_write_byte(rtlpriv,
1960                                                        (REG_AGGLEN_LMT + index),
1961                                                        p_regtoset[index]);
1962                                 }
1963                                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1964                                          ("Set HW_VAR_AMPDU_FACTOR: %#x\n",
1965                                           factor_toset));
1966                         }
1967                         break;
1968                 }
1969         case HW_VAR_AC_PARAM:{
1970                         u8 e_aci = *((u8 *) val);
1971                         u32 u4b_ac_param;
1972                         u16 cw_min = le16_to_cpu(mac->ac[e_aci].cw_min);
1973                         u16 cw_max = le16_to_cpu(mac->ac[e_aci].cw_max);
1974                         u16 tx_op = le16_to_cpu(mac->ac[e_aci].tx_op);
1975
1976                         u4b_ac_param = (u32) mac->ac[e_aci].aifs;
1977                         u4b_ac_param |= (u32) ((cw_min & 0xF) <<
1978                                          AC_PARAM_ECW_MIN_OFFSET);
1979                         u4b_ac_param |= (u32) ((cw_max & 0xF) <<
1980                                          AC_PARAM_ECW_MAX_OFFSET);
1981                         u4b_ac_param |= (u32) tx_op << AC_PARAM_TXOP_OFFSET;
1982                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1983                                  ("queue:%x, ac_param:%x\n", e_aci,
1984                                   u4b_ac_param));
1985                         switch (e_aci) {
1986                         case AC1_BK:
1987                                 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM,
1988                                                 u4b_ac_param);
1989                                 break;
1990                         case AC0_BE:
1991                                 rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM,
1992                                                 u4b_ac_param);
1993                                 break;
1994                         case AC2_VI:
1995                                 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM,
1996                                                 u4b_ac_param);
1997                                 break;
1998                         case AC3_VO:
1999                                 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM,
2000                                                 u4b_ac_param);
2001                                 break;
2002                         default:
2003                                 RT_ASSERT(false, ("SetHwReg8185(): invalid"
2004                                           " aci: %d !\n", e_aci));
2005                                 break;
2006                         }
2007                         if (rtlusb->acm_method != eAcmWay2_SW)
2008                                 rtlpriv->cfg->ops->set_hw_reg(hw,
2009                                          HW_VAR_ACM_CTRL, (u8 *)(&e_aci));
2010                         break;
2011                 }
2012         case HW_VAR_ACM_CTRL:{
2013                         u8 e_aci = *((u8 *) val);
2014                         union aci_aifsn *p_aci_aifsn = (union aci_aifsn *)
2015                                                         (&(mac->ac[0].aifs));
2016                         u8 acm = p_aci_aifsn->f.acm;
2017                         u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
2018
2019                         acm_ctrl =
2020                             acm_ctrl | ((rtlusb->acm_method == 2) ? 0x0 : 0x1);
2021                         if (acm) {
2022                                 switch (e_aci) {
2023                                 case AC0_BE:
2024                                         acm_ctrl |= AcmHw_BeqEn;
2025                                         break;
2026                                 case AC2_VI:
2027                                         acm_ctrl |= AcmHw_ViqEn;
2028                                         break;
2029                                 case AC3_VO:
2030                                         acm_ctrl |= AcmHw_VoqEn;
2031                                         break;
2032                                 default:
2033                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2034                                                  ("HW_VAR_ACM_CTRL acm set "
2035                                                   "failed: eACI is %d\n", acm));
2036                                         break;
2037                                 }
2038                         } else {
2039                                 switch (e_aci) {
2040                                 case AC0_BE:
2041                                         acm_ctrl &= (~AcmHw_BeqEn);
2042                                         break;
2043                                 case AC2_VI:
2044                                         acm_ctrl &= (~AcmHw_ViqEn);
2045                                         break;
2046                                 case AC3_VO:
2047                                         acm_ctrl &= (~AcmHw_BeqEn);
2048                                         break;
2049                                 default:
2050                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2051                                                  ("switch case not process\n"));
2052                                         break;
2053                                 }
2054                         }
2055                         RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
2056                                  ("SetHwReg8190pci(): [HW_VAR_ACM_CTRL] "
2057                                   "Write 0x%X\n", acm_ctrl));
2058                         rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
2059                         break;
2060                 }
2061         case HW_VAR_RCR:{
2062                         rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);
2063                         mac->rx_conf = ((u32 *) (val))[0];
2064                         RT_TRACE(rtlpriv, COMP_RECV, DBG_DMESG,
2065                                  ("### Set RCR(0x%08x) ###\n", mac->rx_conf));
2066                         break;
2067                 }
2068         case HW_VAR_RETRY_LIMIT:{
2069                         u8 retry_limit = ((u8 *) (val))[0];
2070
2071                         rtl_write_word(rtlpriv, REG_RL,
2072                                        retry_limit << RETRY_LIMIT_SHORT_SHIFT |
2073                                        retry_limit << RETRY_LIMIT_LONG_SHIFT);
2074                         RT_TRACE(rtlpriv, COMP_MLME, DBG_DMESG, ("Set HW_VAR_R"
2075                                  "ETRY_LIMIT(0x%08x)\n", retry_limit));
2076                         break;
2077                 }
2078         case HW_VAR_DUAL_TSF_RST:
2079                 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
2080                 break;
2081         case HW_VAR_EFUSE_BYTES:
2082                 rtlefuse->efuse_usedbytes = *((u16 *) val);
2083                 break;
2084         case HW_VAR_EFUSE_USAGE:
2085                 rtlefuse->efuse_usedpercentage = *((u8 *) val);
2086                 break;
2087         case HW_VAR_IO_CMD:
2088                 rtl92c_phy_set_io_cmd(hw, (*(enum io_type *)val));
2089                 break;
2090         case HW_VAR_WPA_CONFIG:
2091                 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *) val));
2092                 break;
2093         case HW_VAR_SET_RPWM:{
2094                         u8 rpwm_val = rtl_read_byte(rtlpriv, REG_USB_HRPWM);
2095
2096                         if (rpwm_val & BIT(7))
2097                                 rtl_write_byte(rtlpriv, REG_USB_HRPWM,
2098                                                (*(u8 *)val));
2099                         else
2100                                 rtl_write_byte(rtlpriv, REG_USB_HRPWM,
2101                                                ((*(u8 *)val) | BIT(7)));
2102                         break;
2103                 }
2104         case HW_VAR_H2C_FW_PWRMODE:{
2105                         u8 psmode = (*(u8 *) val);
2106
2107                         if ((psmode != FW_PS_ACTIVE_MODE) &&
2108                            (!IS_92C_SERIAL(rtlhal->version)))
2109                                 rtl92c_dm_rf_saving(hw, true);
2110                         rtl92c_set_fw_pwrmode_cmd(hw, (*(u8 *) val));
2111                         break;
2112                 }
2113         case HW_VAR_FW_PSMODE_STATUS:
2114                 ppsc->fw_current_inpsmode = *((bool *) val);
2115                 break;
2116         case HW_VAR_H2C_FW_JOINBSSRPT:{
2117                         u8 mstatus = (*(u8 *) val);
2118                         u8 tmp_reg422;
2119                         bool recover = false;
2120
2121                         if (mstatus == RT_MEDIA_CONNECT) {
2122                                 rtlpriv->cfg->ops->set_hw_reg(hw,
2123                                                          HW_VAR_AID, NULL);
2124                                 rtl_write_byte(rtlpriv, REG_CR + 1, 0x03);
2125                                 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(3));
2126                                 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);
2127                                 tmp_reg422 = rtl_read_byte(rtlpriv,
2128                                                         REG_FWHW_TXQ_CTRL + 2);
2129                                 if (tmp_reg422 & BIT(6))
2130                                         recover = true;
2131                                 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
2132                                                tmp_reg422 & (~BIT(6)));
2133                                 rtl92c_set_fw_rsvdpagepkt(hw, 0);
2134                                 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(3), 0);
2135                                 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4));
2136                                 if (recover)
2137                                         rtl_write_byte(rtlpriv,
2138                                                  REG_FWHW_TXQ_CTRL + 2,
2139                                                 tmp_reg422 | BIT(6));
2140                                 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
2141                         }
2142                         rtl92c_set_fw_joinbss_report_cmd(hw, (*(u8 *) val));
2143                         break;
2144                 }
2145         case HW_VAR_AID:{
2146                         u16 u2btmp;
2147
2148                         u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
2149                         u2btmp &= 0xC000;
2150                         rtl_write_word(rtlpriv, REG_BCN_PSR_RPT,
2151                                        (u2btmp | mac->assoc_id));
2152                         break;
2153                 }
2154         case HW_VAR_CORRECT_TSF:{
2155                         u8 btype_ibss = ((u8 *) (val))[0];
2156
2157                         if (btype_ibss == true)
2158                                 _rtl92cu_stop_tx_beacon(hw);
2159                         _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(3));
2160                         rtl_write_dword(rtlpriv, REG_TSFTR, (u32)(mac->tsf &
2161                                         0xffffffff));
2162                         rtl_write_dword(rtlpriv, REG_TSFTR + 4,
2163                                         (u32)((mac->tsf >> 32) & 0xffffffff));
2164                         _rtl92cu_set_bcn_ctrl_reg(hw, BIT(3), 0);
2165                         if (btype_ibss == true)
2166                                 _rtl92cu_resume_tx_beacon(hw);
2167                         break;
2168                 }
2169         case HW_VAR_MGT_FILTER:
2170                 rtl_write_word(rtlpriv, REG_RXFLTMAP0, *(u16 *)val);
2171                 break;
2172         case HW_VAR_CTRL_FILTER:
2173                 rtl_write_word(rtlpriv, REG_RXFLTMAP1, *(u16 *)val);
2174                 break;
2175         case HW_VAR_DATA_FILTER:
2176                 rtl_write_word(rtlpriv, REG_RXFLTMAP2, *(u16 *)val);
2177                 break;
2178         default:
2179                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("switch case "
2180                                                         "not process\n"));
2181                 break;
2182         }
2183 }
2184
2185 void rtl92cu_update_hal_rate_table(struct ieee80211_hw *hw)
2186 {
2187         struct rtl_priv *rtlpriv = rtl_priv(hw);
2188         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2189         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2190         u32 ratr_value = (u32) mac->basic_rates;
2191         u8 *mcsrate = mac->mcs;
2192         u8 ratr_index = 0;
2193         u8 nmode = mac->ht_enable;
2194         u8 mimo_ps = 1;
2195         u16 shortgi_rate = 0;
2196         u32 tmp_ratr_value = 0;
2197         u8 curtxbw_40mhz = mac->bw_40;
2198         u8 curshortgi_40mhz = mac->sgi_40;
2199         u8 curshortgi_20mhz = mac->sgi_20;
2200         enum wireless_mode wirelessmode = mac->mode;
2201
2202         ratr_value |= ((*(u16 *) (mcsrate))) << 12;
2203         switch (wirelessmode) {
2204         case WIRELESS_MODE_B:
2205                 if (ratr_value & 0x0000000c)
2206                         ratr_value &= 0x0000000d;
2207                 else
2208                         ratr_value &= 0x0000000f;
2209                 break;
2210         case WIRELESS_MODE_G:
2211                 ratr_value &= 0x00000FF5;
2212                 break;
2213         case WIRELESS_MODE_N_24G:
2214         case WIRELESS_MODE_N_5G:
2215                 nmode = 1;
2216                 if (mimo_ps == 0) {
2217                         ratr_value &= 0x0007F005;
2218                 } else {
2219                         u32 ratr_mask;
2220
2221                         if (get_rf_type(rtlphy) == RF_1T2R ||
2222                             get_rf_type(rtlphy) == RF_1T1R)
2223                                 ratr_mask = 0x000ff005;
2224                         else
2225                                 ratr_mask = 0x0f0ff005;
2226                         if (curtxbw_40mhz)
2227                                 ratr_mask |= 0x00000010;
2228                         ratr_value &= ratr_mask;
2229                 }
2230                 break;
2231         default:
2232                 if (rtlphy->rf_type == RF_1T2R)
2233                         ratr_value &= 0x000ff0ff;
2234                 else
2235                         ratr_value &= 0x0f0ff0ff;
2236                 break;
2237         }
2238         ratr_value &= 0x0FFFFFFF;
2239         if (nmode && ((curtxbw_40mhz && curshortgi_40mhz) ||
2240             (!curtxbw_40mhz && curshortgi_20mhz))) {
2241                 ratr_value |= 0x10000000;
2242                 tmp_ratr_value = (ratr_value >> 12);
2243                 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2244                         if ((1 << shortgi_rate) & tmp_ratr_value)
2245                                 break;
2246                 }
2247                 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2248                                (shortgi_rate << 4) | (shortgi_rate);
2249         }
2250         rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
2251         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, ("%x\n", rtl_read_dword(rtlpriv,
2252                  REG_ARFR0)));
2253 }
2254
2255 void rtl92cu_update_hal_rate_mask(struct ieee80211_hw *hw, u8 rssi_level)
2256 {
2257         struct rtl_priv *rtlpriv = rtl_priv(hw);
2258         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2259         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2260         u32 ratr_bitmap = (u32) mac->basic_rates;
2261         u8 *p_mcsrate = mac->mcs;
2262         u8 ratr_index = 0;
2263         u8 curtxbw_40mhz = mac->bw_40;
2264         u8 curshortgi_40mhz = mac->sgi_40;
2265         u8 curshortgi_20mhz = mac->sgi_20;
2266         enum wireless_mode wirelessmode = mac->mode;
2267         bool shortgi = false;
2268         u8 rate_mask[5];
2269         u8 macid = 0;
2270         u8 mimops = 1;
2271
2272         ratr_bitmap |= (p_mcsrate[1] << 20) | (p_mcsrate[0] << 12);
2273         switch (wirelessmode) {
2274         case WIRELESS_MODE_B:
2275                 ratr_index = RATR_INX_WIRELESS_B;
2276                 if (ratr_bitmap & 0x0000000c)
2277                         ratr_bitmap &= 0x0000000d;
2278                 else
2279                         ratr_bitmap &= 0x0000000f;
2280                 break;
2281         case WIRELESS_MODE_G:
2282                 ratr_index = RATR_INX_WIRELESS_GB;
2283                 if (rssi_level == 1)
2284                         ratr_bitmap &= 0x00000f00;
2285                 else if (rssi_level == 2)
2286                         ratr_bitmap &= 0x00000ff0;
2287                 else
2288                         ratr_bitmap &= 0x00000ff5;
2289                 break;
2290         case WIRELESS_MODE_A:
2291                 ratr_index = RATR_INX_WIRELESS_A;
2292                 ratr_bitmap &= 0x00000ff0;
2293                 break;
2294         case WIRELESS_MODE_N_24G:
2295         case WIRELESS_MODE_N_5G:
2296                 ratr_index = RATR_INX_WIRELESS_NGB;
2297                 if (mimops == 0) {
2298                         if (rssi_level == 1)
2299                                 ratr_bitmap &= 0x00070000;
2300                         else if (rssi_level == 2)
2301                                 ratr_bitmap &= 0x0007f000;
2302                         else
2303                                 ratr_bitmap &= 0x0007f005;
2304                 } else {
2305                         if (rtlphy->rf_type == RF_1T2R ||
2306                             rtlphy->rf_type == RF_1T1R) {
2307                                 if (curtxbw_40mhz) {
2308                                         if (rssi_level == 1)
2309                                                 ratr_bitmap &= 0x000f0000;
2310                                         else if (rssi_level == 2)
2311                                                 ratr_bitmap &= 0x000ff000;
2312                                         else
2313                                                 ratr_bitmap &= 0x000ff015;
2314                                 } else {
2315                                         if (rssi_level == 1)
2316                                                 ratr_bitmap &= 0x000f0000;
2317                                         else if (rssi_level == 2)
2318                                                 ratr_bitmap &= 0x000ff000;
2319                                         else
2320                                                 ratr_bitmap &= 0x000ff005;
2321                                 }
2322                         } else {
2323                                 if (curtxbw_40mhz) {
2324                                         if (rssi_level == 1)
2325                                                 ratr_bitmap &= 0x0f0f0000;
2326                                         else if (rssi_level == 2)
2327                                                 ratr_bitmap &= 0x0f0ff000;
2328                                         else
2329                                                 ratr_bitmap &= 0x0f0ff015;
2330                                 } else {
2331                                         if (rssi_level == 1)
2332                                                 ratr_bitmap &= 0x0f0f0000;
2333                                         else if (rssi_level == 2)
2334                                                 ratr_bitmap &= 0x0f0ff000;
2335                                         else
2336                                                 ratr_bitmap &= 0x0f0ff005;
2337                                 }
2338                         }
2339                 }
2340                 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2341                     (!curtxbw_40mhz && curshortgi_20mhz)) {
2342                         if (macid == 0)
2343                                 shortgi = true;
2344                         else if (macid == 1)
2345                                 shortgi = false;
2346                 }
2347                 break;
2348         default:
2349                 ratr_index = RATR_INX_WIRELESS_NGB;
2350                 if (rtlphy->rf_type == RF_1T2R)
2351                         ratr_bitmap &= 0x000ff0ff;
2352                 else
2353                         ratr_bitmap &= 0x0f0ff0ff;
2354                 break;
2355         }
2356         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, ("ratr_bitmap :%x\n",
2357                  ratr_bitmap));
2358         *(u32 *)&rate_mask = ((ratr_bitmap & 0x0fffffff) |
2359                                       ratr_index << 28);
2360         rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
2361         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, ("Rate_index:%x, "
2362                                                 "ratr_val:%x, %x:%x:%x:%x:%x\n",
2363                                                 ratr_index, ratr_bitmap,
2364                                                 rate_mask[0], rate_mask[1],
2365                                                 rate_mask[2], rate_mask[3],
2366                                                 rate_mask[4]));
2367         rtl92c_fill_h2c_cmd(hw, H2C_RA_MASK, 5, rate_mask);
2368 }
2369
2370 void rtl92cu_update_channel_access_setting(struct ieee80211_hw *hw)
2371 {
2372         struct rtl_priv *rtlpriv = rtl_priv(hw);
2373         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2374         u16 sifs_timer;
2375
2376         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2377                                       (u8 *)&mac->slot_time);
2378         if (!mac->ht_enable)
2379                 sifs_timer = 0x0a0a;
2380         else
2381                 sifs_timer = 0x0e0e;
2382         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2383 }
2384
2385 bool rtl92cu_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 * valid)
2386 {
2387         struct rtl_priv *rtlpriv = rtl_priv(hw);
2388         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2389         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2390         enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate;
2391         u8 u1tmp = 0;
2392         bool actuallyset = false;
2393         unsigned long flag = 0;
2394         /* to do - usb autosuspend */
2395         u8 usb_autosuspend = 0;
2396
2397         if (ppsc->swrf_processing)
2398                 return false;
2399         spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2400         if (ppsc->rfchange_inprogress) {
2401                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2402                 return false;
2403         } else {
2404                 ppsc->rfchange_inprogress = true;
2405                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2406         }
2407         cur_rfstate = ppsc->rfpwr_state;
2408         if (usb_autosuspend) {
2409                 /* to do................... */
2410         } else {
2411                 if (ppsc->pwrdown_mode) {
2412                         u1tmp = rtl_read_byte(rtlpriv, REG_HSISR);
2413                         e_rfpowerstate_toset = (u1tmp & BIT(7)) ?
2414                                                ERFOFF : ERFON;
2415                         RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
2416                                  ("pwrdown, 0x5c(BIT7)=%02x\n", u1tmp));
2417                 } else {
2418                         rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG,
2419                                        rtl_read_byte(rtlpriv,
2420                                        REG_MAC_PINMUX_CFG) & ~(BIT(3)));
2421                         u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
2422                         e_rfpowerstate_toset  = (u1tmp & BIT(3)) ?
2423                                                  ERFON : ERFOFF;
2424                         RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
2425                                 ("GPIO_IN=%02x\n", u1tmp));
2426                 }
2427                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, ("N-SS RF =%x\n",
2428                          e_rfpowerstate_toset));
2429         }
2430         if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
2431                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, ("GPIOChangeRF  - HW "
2432                          "Radio ON, RF ON\n"));
2433                 ppsc->hwradiooff = false;
2434                 actuallyset = true;
2435         } else if ((!ppsc->hwradiooff) && (e_rfpowerstate_toset  ==
2436                     ERFOFF)) {
2437                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, ("GPIOChangeRF  - HW"
2438                          " Radio OFF\n"));
2439                 ppsc->hwradiooff = true;
2440                 actuallyset = true;
2441         } else {
2442                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD ,
2443                          ("pHalData->bHwRadioOff and eRfPowerStateToSet do not"
2444                          " match: pHalData->bHwRadioOff %x, eRfPowerStateToSet "
2445                          "%x\n", ppsc->hwradiooff, e_rfpowerstate_toset));
2446         }
2447         if (actuallyset) {
2448                 ppsc->hwradiooff = 1;
2449                 if (e_rfpowerstate_toset == ERFON) {
2450                         if ((ppsc->reg_rfps_level  & RT_RF_OFF_LEVL_ASPM) &&
2451                              RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM))
2452                                 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2453                         else if ((ppsc->reg_rfps_level  & RT_RF_OFF_LEVL_PCI_D3)
2454                                  && RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3))
2455                                 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);
2456                 }
2457                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2458                 ppsc->rfchange_inprogress = false;
2459                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2460                 /* For power down module, we need to enable register block
2461                  * contrl reg at 0x1c. Then enable power down control bit
2462                  * of register 0x04 BIT4 and BIT15 as 1.
2463                  */
2464                 if (ppsc->pwrdown_mode && e_rfpowerstate_toset == ERFOFF) {
2465                         /* Enable register area 0x0-0xc. */
2466                         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0);
2467                         if (IS_HARDWARE_TYPE_8723U(rtlhal)) {
2468                                 /*
2469                                  * We should configure HW PDn source for WiFi
2470                                  * ONLY, and then our HW will be set in
2471                                  * power-down mode if PDn source from all
2472                                  * functions are configured.
2473                                  */
2474                                 u1tmp = rtl_read_byte(rtlpriv,
2475                                                       REG_MULTI_FUNC_CTRL);
2476                                 rtl_write_byte(rtlpriv, REG_MULTI_FUNC_CTRL,
2477                                                (u1tmp|WL_HWPDN_EN));
2478                         } else {
2479                                 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x8812);
2480                         }
2481                 }
2482                 if (e_rfpowerstate_toset == ERFOFF) {
2483                         if (ppsc->reg_rfps_level  & RT_RF_OFF_LEVL_ASPM)
2484                                 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2485                         else if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3)
2486                                 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);
2487                 }
2488         } else if (e_rfpowerstate_toset == ERFOFF || cur_rfstate == ERFOFF) {
2489                 /* Enter D3 or ASPM after GPIO had been done. */
2490                 if (ppsc->reg_rfps_level  & RT_RF_OFF_LEVL_ASPM)
2491                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2492                 else if (ppsc->reg_rfps_level  & RT_RF_OFF_LEVL_PCI_D3)
2493                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);
2494                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2495                 ppsc->rfchange_inprogress = false;
2496                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2497         } else {
2498                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2499                 ppsc->rfchange_inprogress = false;
2500                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2501         }
2502         *valid = 1;
2503         return !ppsc->hwradiooff;
2504 }