drivers/net/wireless/rtlwifi/rtl8192ce/phy.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2010  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #include "../wifi.h"
  31 #include "../pci.h"
  32 #include "../ps.h"
  33 #include "reg.h"
  34 #include "def.h"
  35 #include "phy.h"
  36 #include "rf.h"
  37 #include "dm.h"
  38 #include "table.h"
  39
  40 #include "../rtl8192c/phy_common.c"
  41
  42 u32 rtl92c_phy_query_rf_reg(struct ieee80211_hw *hw,
  43                             enum radio_path rfpath, u32 regaddr, u32 bitmask)
  44 {
  45         struct rtl_priv *rtlpriv = rtl_priv(hw);
  46         u32 original_value, readback_value, bitshift;
  47         struct rtl_phy *rtlphy = &(rtlpriv->phy);
  48         unsigned long flags;
  49
  50         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), "
  51                                                "rfpath(%#x), bitmask(%#x)\n",
  52                                                regaddr, rfpath, bitmask));
  53
  54         spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
  55
  56         if (rtlphy->rf_mode != RF_OP_BY_FW) {
  57                 original_value = _rtl92c_phy_rf_serial_read(hw,
  58                                                             rfpath, regaddr);
  59         } else {
  60                 original_value = _rtl92c_phy_fw_rf_serial_read(hw,
  61                                                                rfpath, regaddr);
  62         }
  63
  64         bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
  65         readback_value = (original_value & bitmask) >> bitshift;
  66
  67         spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
  68
  69         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
  70                  ("regaddr(%#x), rfpath(%#x), "
  71                   "bitmask(%#x), original_value(%#x)\n",
  72                   regaddr, rfpath, bitmask, original_value));
  73
  74         return readback_value;
  75 }
  76
  77 void rtl92c_phy_set_rf_reg(struct ieee80211_hw *hw,
  78                            enum radio_path rfpath,
  79                            u32 regaddr, u32 bitmask, u32 data)
  80 {
  81         struct rtl_priv *rtlpriv = rtl_priv(hw);
  82         struct rtl_phy *rtlphy = &(rtlpriv->phy);
  83         u32 original_value, bitshift;
  84         unsigned long flags;
  85
  86         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
  87                  ("regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
  88                   regaddr, bitmask, data, rfpath));
  89
  90         spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
  91
  92         if (rtlphy->rf_mode != RF_OP_BY_FW) {
  93                 if (bitmask != RFREG_OFFSET_MASK) {
  94                         original_value = _rtl92c_phy_rf_serial_read(hw,
  95                                                                     rfpath,
  96                                                                     regaddr);
  97                         bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
  98                         data =
  99                             ((original_value & (~bitmask)) |
 100                              (data << bitshift));
 101                 }
 102
 103                 _rtl92c_phy_rf_serial_write(hw, rfpath, regaddr, data);
 104         } else {
 105                 if (bitmask != RFREG_OFFSET_MASK) {
 106                         original_value = _rtl92c_phy_fw_rf_serial_read(hw,
 107                                                                        rfpath,
 108                                                                        regaddr);
 109                         bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
 110                         data =
 111                             ((original_value & (~bitmask)) |
 112                              (data << bitshift));
 113                 }
 114                 _rtl92c_phy_fw_rf_serial_write(hw, rfpath, regaddr, data);
 115         }
 116
 117         spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
 118
 119         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), "
 120                                                "bitmask(%#x), data(%#x), "
 121                                                "rfpath(%#x)\n", regaddr,
 122                                                bitmask, data, rfpath));
 123 }
 124
 125 bool rtl92c_phy_mac_config(struct ieee80211_hw *hw)
 126 {
 127         struct rtl_priv *rtlpriv = rtl_priv(hw);
 128         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 129         bool is92c = IS_92C_SERIAL(rtlhal->version);
 130         bool rtstatus = _rtl92c_phy_config_mac_with_headerfile(hw);
 131
 132         if (is92c)
 133                 rtl_write_byte(rtlpriv, 0x14, 0x71);
 134         return rtstatus;
 135 }
 136
 137 bool rtl92c_phy_bb_config(struct ieee80211_hw *hw)
 138 {
 139         bool rtstatus = true;
 140         struct rtl_priv *rtlpriv = rtl_priv(hw);
 141         u16 regval;
 142         u32 regvaldw;
 143         u8 reg_hwparafile = 1;
 144
 145         _rtl92c_phy_init_bb_rf_register_definition(hw);
 146         regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
 147         rtl_write_word(rtlpriv, REG_SYS_FUNC_EN,
 148                        regval | BIT(13) | BIT(0) | BIT(1));
 149         rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x83);
 150         rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL + 1, 0xdb);
 151         rtl_write_byte(rtlpriv, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB);
 152         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN,
 153                        FEN_PPLL | FEN_PCIEA | FEN_DIO_PCIE |
 154                        FEN_BB_GLB_RSTn | FEN_BBRSTB);
 155         rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80);
 156         regvaldw = rtl_read_dword(rtlpriv, REG_LEDCFG0);
 157         rtl_write_dword(rtlpriv, REG_LEDCFG0, regvaldw | BIT(23));
 158         if (reg_hwparafile == 1)
 159                 rtstatus = _rtl92c_phy_bb8192c_config_parafile(hw);
 160         return rtstatus;
 161 }
 162
 163 static bool _rtl92c_phy_config_mac_with_headerfile(struct ieee80211_hw *hw)
 164 {
 165         struct rtl_priv *rtlpriv = rtl_priv(hw);
 166         u32 i;
 167         u32 arraylength;
 168         u32 *ptrarray;
 169
 170         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("Read Rtl819XMACPHY_Array\n"));
 171         arraylength = MAC_2T_ARRAYLENGTH;
 172         ptrarray = RTL8192CEMAC_2T_ARRAY;
 173         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 174                  ("Img:RTL8192CEMAC_2T_ARRAY\n"));
 175         for (i = 0; i < arraylength; i = i + 2)
 176                 rtl_write_byte(rtlpriv, ptrarray[i], (u8) ptrarray[i + 1]);
 177         return true;
 178 }
 179
 180 static bool _rtl92c_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
 181                                                   u8 configtype)
 182 {
 183         int i;
 184         u32 *phy_regarray_table;
 185         u32 *agctab_array_table;
 186         u16 phy_reg_arraylen, agctab_arraylen;
 187         struct rtl_priv *rtlpriv = rtl_priv(hw);
 188         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 189
 190         if (IS_92C_SERIAL(rtlhal->version)) {
 191                 agctab_arraylen = AGCTAB_2TARRAYLENGTH;
 192                 agctab_array_table = RTL8192CEAGCTAB_2TARRAY;
 193                 phy_reg_arraylen = PHY_REG_2TARRAY_LENGTH;
 194                 phy_regarray_table = RTL8192CEPHY_REG_2TARRAY;
 195         } else {
 196                 agctab_arraylen = AGCTAB_1TARRAYLENGTH;
 197                 agctab_array_table = RTL8192CEAGCTAB_1TARRAY;
 198                 phy_reg_arraylen = PHY_REG_1TARRAY_LENGTH;
 199                 phy_regarray_table = RTL8192CEPHY_REG_1TARRAY;
 200         }
 201         if (configtype == BASEBAND_CONFIG_PHY_REG) {
 202                 for (i = 0; i < phy_reg_arraylen; i = i + 2) {
 203                         if (phy_regarray_table[i] == 0xfe)
 204                                 mdelay(50);
 205                         else if (phy_regarray_table[i] == 0xfd)
 206                                 mdelay(5);
 207                         else if (phy_regarray_table[i] == 0xfc)
 208                                 mdelay(1);
 209                         else if (phy_regarray_table[i] == 0xfb)
 210                                 udelay(50);
 211                         else if (phy_regarray_table[i] == 0xfa)
 212                                 udelay(5);
 213                         else if (phy_regarray_table[i] == 0xf9)
 214                                 udelay(1);
 215                         rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD,
 216                                       phy_regarray_table[i + 1]);
 217                         udelay(1);
 218                         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 219                                  ("The phy_regarray_table[0] is %x"
 220                                   " Rtl819XPHY_REGArray[1] is %x\n",
 221                                   phy_regarray_table[i],
 222                                   phy_regarray_table[i + 1]));
 223                 }
 224                 rtl92c_phy_config_bb_external_pa(hw);
 225         } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
 226                 for (i = 0; i < agctab_arraylen; i = i + 2) {
 227                         rtl_set_bbreg(hw, agctab_array_table[i], MASKDWORD,
 228                                       agctab_array_table[i + 1]);
 229                         udelay(1);
 230                         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 231                                  ("The agctab_array_table[0] is "
 232                                   "%x Rtl819XPHY_REGArray[1] is %x\n",
 233                                   agctab_array_table[i],
 234                                   agctab_array_table[i + 1]));
 235                 }
 236         }
 237         return true;
 238 }
 239
 240 static bool _rtl92c_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
 241                                                     u8 configtype)
 242 {
 243         struct rtl_priv *rtlpriv = rtl_priv(hw);
 244         int i;
 245         u32 *phy_regarray_table_pg;
 246         u16 phy_regarray_pg_len;
 247
 248         phy_regarray_pg_len = PHY_REG_ARRAY_PGLENGTH;
 249         phy_regarray_table_pg = RTL8192CEPHY_REG_ARRAY_PG;
 250
 251         if (configtype == BASEBAND_CONFIG_PHY_REG) {
 252                 for (i = 0; i < phy_regarray_pg_len; i = i + 3) {
 253                         if (phy_regarray_table_pg[i] == 0xfe)
 254                                 mdelay(50);
 255                         else if (phy_regarray_table_pg[i] == 0xfd)
 256                                 mdelay(5);
 257                         else if (phy_regarray_table_pg[i] == 0xfc)
 258                                 mdelay(1);
 259                         else if (phy_regarray_table_pg[i] == 0xfb)
 260                                 udelay(50);
 261                         else if (phy_regarray_table_pg[i] == 0xfa)
 262                                 udelay(5);
 263                         else if (phy_regarray_table_pg[i] == 0xf9)
 264                                 udelay(1);
 265
 266                         _rtl92c_store_pwrIndex_diffrate_offset(hw,
 267                                                phy_regarray_table_pg[i],
 268                                                phy_regarray_table_pg[i + 1],
 269                                                phy_regarray_table_pg[i + 2]);
 270                 }
 271         } else {
 272
 273                 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
 274                          ("configtype != BaseBand_Config_PHY_REG\n"));
 275         }
 276         return true;
 277 }
 278
 279 bool rtl92c_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
 280                                           enum radio_path rfpath)
 281 {
 282
 283         int i;
 284         bool rtstatus = true;
 285         u32 *radioa_array_table;
 286         u32 *radiob_array_table;
 287         u16 radioa_arraylen, radiob_arraylen;
 288         struct rtl_priv *rtlpriv = rtl_priv(hw);
 289         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 290
 291         if (IS_92C_SERIAL(rtlhal->version)) {
 292                 radioa_arraylen = RADIOA_2TARRAYLENGTH;
 293                 radioa_array_table = RTL8192CERADIOA_2TARRAY;
 294                 radiob_arraylen = RADIOB_2TARRAYLENGTH;
 295                 radiob_array_table = RTL8192CE_RADIOB_2TARRAY;
 296                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 297                          ("Radio_A:RTL8192CERADIOA_2TARRAY\n"));
 298                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 299                          ("Radio_B:RTL8192CE_RADIOB_2TARRAY\n"));
 300         } else {
 301                 radioa_arraylen = RADIOA_1TARRAYLENGTH;
 302                 radioa_array_table = RTL8192CE_RADIOA_1TARRAY;
 303                 radiob_arraylen = RADIOB_1TARRAYLENGTH;
 304                 radiob_array_table = RTL8192CE_RADIOB_1TARRAY;
 305                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 306                          ("Radio_A:RTL8192CE_RADIOA_1TARRAY\n"));
 307                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 308                          ("Radio_B:RTL8192CE_RADIOB_1TARRAY\n"));
 309         }
 310         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("Radio No %x\n", rfpath));
 311         rtstatus = true;
 312         switch (rfpath) {
 313         case RF90_PATH_A:
 314                 for (i = 0; i < radioa_arraylen; i = i + 2) {
 315                         if (radioa_array_table[i] == 0xfe)
 316                                 mdelay(50);
 317                         else if (radioa_array_table[i] == 0xfd)
 318                                 mdelay(5);
 319                         else if (radioa_array_table[i] == 0xfc)
 320                                 mdelay(1);
 321                         else if (radioa_array_table[i] == 0xfb)
 322                                 udelay(50);
 323                         else if (radioa_array_table[i] == 0xfa)
 324                                 udelay(5);
 325                         else if (radioa_array_table[i] == 0xf9)
 326                                 udelay(1);
 327                         else {
 328                                 rtl_set_rfreg(hw, rfpath, radioa_array_table[i],
 329                                               RFREG_OFFSET_MASK,
 330                                               radioa_array_table[i + 1]);
 331                                 udelay(1);
 332                         }
 333                 }
 334                 _rtl92c_phy_config_rf_external_pa(hw, rfpath);
 335                 break;
 336         case RF90_PATH_B:
 337                 for (i = 0; i < radiob_arraylen; i = i + 2) {
 338                         if (radiob_array_table[i] == 0xfe) {
 339                                 mdelay(50);
 340                         } else if (radiob_array_table[i] == 0xfd)
 341                                 mdelay(5);
 342                         else if (radiob_array_table[i] == 0xfc)
 343                                 mdelay(1);
 344                         else if (radiob_array_table[i] == 0xfb)
 345                                 udelay(50);
 346                         else if (radiob_array_table[i] == 0xfa)
 347                                 udelay(5);
 348                         else if (radiob_array_table[i] == 0xf9)
 349                                 udelay(1);
 350                         else {
 351                                 rtl_set_rfreg(hw, rfpath, radiob_array_table[i],
 352                                               RFREG_OFFSET_MASK,
 353                                               radiob_array_table[i + 1]);
 354                                 udelay(1);
 355                         }
 356                 }
 357                 break;
 358         case RF90_PATH_C:
 359                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 360                          ("switch case not process\n"));
 361                 break;
 362         case RF90_PATH_D:
 363                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 364                          ("switch case not process\n"));
 365                 break;
 366         }
 367         return true;
 368 }
 369
 370 void rtl92c_phy_set_bw_mode_callback(struct ieee80211_hw *hw)
 371 {
 372         struct rtl_priv *rtlpriv = rtl_priv(hw);
 373         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 374         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 375         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 376         u8 reg_bw_opmode;
 377         u8 reg_prsr_rsc;
 378
 379         RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
 380                  ("Switch to %s bandwidth\n",
 381                   rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
 382                   "20MHz" : "40MHz"))
 383
 384             if (is_hal_stop(rtlhal))
 385                 return;
 386
 387         reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE);
 388         reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2);
 389
 390         switch (rtlphy->current_chan_bw) {
 391         case HT_CHANNEL_WIDTH_20:
 392                 reg_bw_opmode |= BW_OPMODE_20MHZ;
 393                 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
 394                 break;
 395
 396         case HT_CHANNEL_WIDTH_20_40:
 397                 reg_bw_opmode &= ~BW_OPMODE_20MHZ;
 398                 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
 399
 400                 reg_prsr_rsc =
 401                     (reg_prsr_rsc & 0x90) | (mac->cur_40_prime_sc << 5);
 402                 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc);
 403                 break;
 404
 405         default:
 406                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 407                          ("unknown bandwidth: %#X\n", rtlphy->current_chan_bw));
 408                 break;
 409         }
 410
 411         switch (rtlphy->current_chan_bw) {
 412         case HT_CHANNEL_WIDTH_20:
 413                 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
 414                 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
 415                 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
 416                 break;
 417         case HT_CHANNEL_WIDTH_20_40:
 418                 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
 419                 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
 420                 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND,
 421                               (mac->cur_40_prime_sc >> 1));
 422                 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
 423                 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 0);
 424                 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)),
 425                               (mac->cur_40_prime_sc ==
 426                                HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
 427                 break;
 428         default:
 429                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 430                          ("unknown bandwidth: %#X\n", rtlphy->current_chan_bw));
 431                 break;
 432         }
 433         rtl92c_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
 434         rtlphy->set_bwmode_inprogress = false;
 435         RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, ("<==\n"));
 436 }
 437
 438 static void _rtl92c_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
 439 {
 440         u8 tmpreg;
 441         u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal;
 442         struct rtl_priv *rtlpriv = rtl_priv(hw);
 443
 444         tmpreg = rtl_read_byte(rtlpriv, 0xd03);
 445
 446         if ((tmpreg & 0x70) != 0)
 447                 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F);
 448         else
 449                 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
 450
 451         if ((tmpreg & 0x70) != 0) {
 452                 rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS);
 453
 454                 if (is2t)
 455                         rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00,
 456                                                   MASK12BITS);
 457
 458                 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS,
 459                               (rf_a_mode & 0x8FFFF) | 0x10000);
 460
 461                 if (is2t)
 462                         rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
 463                                       (rf_b_mode & 0x8FFFF) | 0x10000);
 464         }
 465         lc_cal = rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS);
 466
 467         rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, lc_cal | 0x08000);
 468
 469         mdelay(100);
 470
 471         if ((tmpreg & 0x70) != 0) {
 472                 rtl_write_byte(rtlpriv, 0xd03, tmpreg);
 473                 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode);
 474
 475                 if (is2t)
 476                         rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
 477                                       rf_b_mode);
 478         } else {
 479                 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
 480         }
 481 }
 482
 483 static bool _rtl92ce_phy_set_rf_power_state(struct ieee80211_hw *hw,
 484                                             enum rf_pwrstate rfpwr_state)
 485 {
 486         struct rtl_priv *rtlpriv = rtl_priv(hw);
 487         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 488         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 489         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 490         bool bresult = true;
 491         u8 i, queue_id;
 492         struct rtl8192_tx_ring *ring = NULL;
 493
 494         ppsc->set_rfpowerstate_inprogress = true;
 495         switch (rfpwr_state) {
 496         case ERFON:{
 497                         if ((ppsc->rfpwr_state == ERFOFF) &&
 498                             RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
 499                                 bool rtstatus;
 500                                 u32 InitializeCount = 0;
 501                                 do {
 502                                         InitializeCount++;
 503                                         RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
 504                                                  ("IPS Set eRf nic enable\n"));
 505                                         rtstatus = rtl_ps_enable_nic(hw);
 506                                 } while ((rtstatus != true)
 507                                          && (InitializeCount < 10));
 508                                 RT_CLEAR_PS_LEVEL(ppsc,
 509                                                   RT_RF_OFF_LEVL_HALT_NIC);
 510                         } else {
 511                                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
 512                                          ("Set ERFON sleeped:%d ms\n",
 513                                           jiffies_to_msecs(jiffies -
 514                                                    ppsc->
 515                                                    last_sleep_jiffies)));
 516                                 ppsc->last_awake_jiffies = jiffies;
 517                                 rtl92ce_phy_set_rf_on(hw);
 518                         }
 519                         if (mac->link_state == MAC80211_LINKED) {
 520                                 rtlpriv->cfg->ops->led_control(hw,
 521                                                                LED_CTL_LINK);
 522                         } else {
 523                                 rtlpriv->cfg->ops->led_control(hw,
 524                                                                LED_CTL_NO_LINK);
 525                         }
 526                         break;
 527                 }
 528         case ERFOFF:{
 529                         for (queue_id = 0, i = 0;
 530                              queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
 531                                 ring = &pcipriv->dev.tx_ring[queue_id];
 532                                 if (skb_queue_len(&ring->queue) == 0 ||
 533                                     queue_id == BEACON_QUEUE) {
 534                                         queue_id++;
 535                                         continue;
 536                                 } else {
 537                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 538                                                  ("eRf Off/Sleep: %d times "
 539                                                   "TcbBusyQueue[%d] "
 540                                                   "=%d before doze!\n", (i + 1),
 541                                                   queue_id,
 542                                                   skb_queue_len(&ring->queue)));
 543                                         udelay(10);
 544                                         i++;
 545                                 }
 546                                 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
 547                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 548                                                  ("\nERFOFF: %d times "
 549                                                   "TcbBusyQueue[%d] = %d !\n",
 550                                                   MAX_DOZE_WAITING_TIMES_9x,
 551                                                   queue_id,
 552                                                   skb_queue_len(&ring->queue)));
 553                                         break;
 554                                 }
 555                         }
 556                         if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
 557                                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
 558                                          ("IPS Set eRf nic disable\n"));
 559                                 rtl_ps_disable_nic(hw);
 560                                 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
 561                         } else {
 562                                 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) {
 563                                         rtlpriv->cfg->ops->led_control(hw,
 564                                                                LED_CTL_NO_LINK);
 565                                 } else {
 566                                         rtlpriv->cfg->ops->led_control(hw,
 567                                                              LED_CTL_POWER_OFF);
 568                                 }
 569                         }
 570                         break;
 571                 }
 572         case ERFSLEEP:{
 573                         if (ppsc->rfpwr_state == ERFOFF)
 574                                 break;
 575                         for (queue_id = 0, i = 0;
 576                              queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
 577                                 ring = &pcipriv->dev.tx_ring[queue_id];
 578                                 if (skb_queue_len(&ring->queue) == 0) {
 579                                         queue_id++;
 580                                         continue;
 581                                 } else {
 582                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 583                                                  ("eRf Off/Sleep: %d times "
 584                                                   "TcbBusyQueue[%d] =%d before "
 585                                                   "doze!\n", (i + 1), queue_id,
 586                                                   skb_queue_len(&ring->queue)));
 587                                         udelay(10);
 588                                         i++;
 589                                 }
 590                                 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
 591                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 592                                                  ("\n ERFSLEEP: %d times "
 593                                                   "TcbBusyQueue[%d] = %d !\n",
 594                                                   MAX_DOZE_WAITING_TIMES_9x,
 595                                                   queue_id,
 596                                                   skb_queue_len(&ring->queue)));
 597                                         break;
 598                                 }
 599                         }
 600                         RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
 601                                  ("Set ERFSLEEP awaked:%d ms\n",
 602                                   jiffies_to_msecs(jiffies -
 603                                                    ppsc->last_awake_jiffies)));
 604                         ppsc->last_sleep_jiffies = jiffies;
 605                         _rtl92ce_phy_set_rf_sleep(hw);
 606                         break;
 607                 }
 608         default:
 609                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 610                          ("switch case not process\n"));
 611                 bresult = false;
 612                 break;
 613         }
 614         if (bresult)
 615                 ppsc->rfpwr_state = rfpwr_state;
 616         ppsc->set_rfpowerstate_inprogress = false;
 617         return bresult;
 618 }
 619
 620 bool rtl92c_phy_set_rf_power_state(struct ieee80211_hw *hw,
 621                                    enum rf_pwrstate rfpwr_state)
 622 {
 623         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 624         bool bresult = false;
 625
 626         if (rfpwr_state == ppsc->rfpwr_state)
 627                 return bresult;
 628         bresult = _rtl92ce_phy_set_rf_power_state(hw, rfpwr_state);
 629         return bresult;
 630 }