drivers/net/wireless/rtlwifi/rtl8192ce/phy.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2010  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #include "../wifi.h"
  31 #include "../pci.h"
  32 #include "../ps.h"
  33 #include "reg.h"
  34 #include "def.h"
  35 #include "phy.h"
  36 #include "rf.h"
  37 #include "dm.h"
  38 #include "table.h"
  39
  40 static u32 _rtl92c_phy_fw_rf_serial_read(struct ieee80211_hw *hw,
  41                                          enum radio_path rfpath, u32 offset);
  42 static void _rtl92c_phy_fw_rf_serial_write(struct ieee80211_hw *hw,
  43                                            enum radio_path rfpath, u32 offset,
  44                                            u32 data);
  45 static u32 _rtl92c_phy_rf_serial_read(struct ieee80211_hw *hw,
  46                                       enum radio_path rfpath, u32 offset);
  47 static void _rtl92c_phy_rf_serial_write(struct ieee80211_hw *hw,
  48                                         enum radio_path rfpath, u32 offset,
  49                                         u32 data);
  50 static u32 _rtl92c_phy_calculate_bit_shift(u32 bitmask);
  51 static bool _rtl92c_phy_bb8192c_config_parafile(struct ieee80211_hw *hw);
  52 static bool _rtl92c_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);
  53 static bool _rtl92c_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
  54                                                   u8 configtype);
  55 static bool _rtl92c_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
  56                                                     u8 configtype);
  57 static void _rtl92c_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw);
  58 static bool _rtl92c_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
  59                                              u32 cmdtableidx, u32 cmdtablesz,
  60                                              enum swchnlcmd_id cmdid, u32 para1,
  61                                              u32 para2, u32 msdelay);
  62 static bool _rtl92c_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
  63                                              u8 channel, u8 *stage, u8 *step,
  64                                              u32 *delay);
  65 static u8 _rtl92c_phy_dbm_to_txpwr_Idx(struct ieee80211_hw *hw,
  66                                        enum wireless_mode wirelessmode,
  67                                        long power_indbm);
  68 static bool _rtl92c_phy_config_rf_external_pa(struct ieee80211_hw *hw,
  69                                               enum radio_path rfpath);
  70 static long _rtl92c_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
  71                                          enum wireless_mode wirelessmode,
  72                                          u8 txpwridx);
  73 u32 rtl92c_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask)
  74 {
  75         struct rtl_priv *rtlpriv = rtl_priv(hw);
  76         u32 returnvalue, originalvalue, bitshift;
  77
  78         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), "
  79                                                "bitmask(%#x)\n", regaddr,
  80                                                bitmask));
  81         originalvalue = rtl_read_dword(rtlpriv, regaddr);
  82         bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
  83         returnvalue = (originalvalue & bitmask) >> bitshift;
  84
  85         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("BBR MASK=0x%x "
  86                                                "Addr[0x%x]=0x%x\n", bitmask,
  87                                                regaddr, originalvalue));
  88
  89         return returnvalue;
  90
  91 }
  92
  93 void rtl92c_phy_set_bb_reg(struct ieee80211_hw *hw,
  94                            u32 regaddr, u32 bitmask, u32 data)
  95 {
  96         struct rtl_priv *rtlpriv = rtl_priv(hw);
  97         u32 originalvalue, bitshift;
  98
  99         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), bitmask(%#x),"
 100                                                " data(%#x)\n", regaddr, bitmask,
 101                                                data));
 102
 103         if (bitmask != MASKDWORD) {
 104                 originalvalue = rtl_read_dword(rtlpriv, regaddr);
 105                 bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
 106                 data = ((originalvalue & (~bitmask)) | (data << bitshift));
 107         }
 108
 109         rtl_write_dword(rtlpriv, regaddr, data);
 110
 111         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), bitmask(%#x),"
 112                                                " data(%#x)\n", regaddr, bitmask,
 113                                                data));
 114
 115 }
 116
 117 u32 rtl92c_phy_query_rf_reg(struct ieee80211_hw *hw,
 118                             enum radio_path rfpath, u32 regaddr, u32 bitmask)
 119 {
 120         struct rtl_priv *rtlpriv = rtl_priv(hw);
 121         u32 original_value, readback_value, bitshift;
 122         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 123         unsigned long flags;
 124
 125         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), "
 126                                                "rfpath(%#x), bitmask(%#x)\n",
 127                                                regaddr, rfpath, bitmask));
 128
 129         spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
 130
 131         if (rtlphy->rf_mode != RF_OP_BY_FW) {
 132                 original_value = _rtl92c_phy_rf_serial_read(hw,
 133                                                             rfpath, regaddr);
 134         } else {
 135                 original_value = _rtl92c_phy_fw_rf_serial_read(hw,
 136                                                                rfpath, regaddr);
 137         }
 138
 139         bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
 140         readback_value = (original_value & bitmask) >> bitshift;
 141
 142         spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
 143
 144         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
 145                  ("regaddr(%#x), rfpath(%#x), "
 146                   "bitmask(%#x), original_value(%#x)\n",
 147                   regaddr, rfpath, bitmask, original_value));
 148
 149         return readback_value;
 150 }
 151
 152 void rtl92c_phy_set_rf_reg(struct ieee80211_hw *hw,
 153                            enum radio_path rfpath,
 154                            u32 regaddr, u32 bitmask, u32 data)
 155 {
 156         struct rtl_priv *rtlpriv = rtl_priv(hw);
 157         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 158         u32 original_value, bitshift;
 159         unsigned long flags;
 160
 161         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
 162                  ("regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
 163                   regaddr, bitmask, data, rfpath));
 164
 165         spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
 166
 167         if (rtlphy->rf_mode != RF_OP_BY_FW) {
 168                 if (bitmask != RFREG_OFFSET_MASK) {
 169                         original_value = _rtl92c_phy_rf_serial_read(hw,
 170                                                                     rfpath,
 171                                                                     regaddr);
 172                         bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
 173                         data =
 174                             ((original_value & (~bitmask)) |
 175                              (data << bitshift));
 176                 }
 177
 178                 _rtl92c_phy_rf_serial_write(hw, rfpath, regaddr, data);
 179         } else {
 180                 if (bitmask != RFREG_OFFSET_MASK) {
 181                         original_value = _rtl92c_phy_fw_rf_serial_read(hw,
 182                                                                        rfpath,
 183                                                                        regaddr);
 184                         bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
 185                         data =
 186                             ((original_value & (~bitmask)) |
 187                              (data << bitshift));
 188                 }
 189                 _rtl92c_phy_fw_rf_serial_write(hw, rfpath, regaddr, data);
 190         }
 191
 192         spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
 193
 194         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), "
 195                                                "bitmask(%#x), data(%#x), "
 196                                                "rfpath(%#x)\n", regaddr,
 197                                                bitmask, data, rfpath));
 198 }
 199
 200 static u32 _rtl92c_phy_fw_rf_serial_read(struct ieee80211_hw *hw,
 201                                          enum radio_path rfpath, u32 offset)
 202 {
 203         RT_ASSERT(false, ("deprecated!\n"));
 204         return 0;
 205 }
 206
 207 static void _rtl92c_phy_fw_rf_serial_write(struct ieee80211_hw *hw,
 208                                            enum radio_path rfpath, u32 offset,
 209                                            u32 data)
 210 {
 211         RT_ASSERT(false, ("deprecated!\n"));
 212 }
 213
 214 static u32 _rtl92c_phy_rf_serial_read(struct ieee80211_hw *hw,
 215                                       enum radio_path rfpath, u32 offset)
 216 {
 217         struct rtl_priv *rtlpriv = rtl_priv(hw);
 218         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 219         struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
 220         u32 newoffset;
 221         u32 tmplong, tmplong2;
 222         u8 rfpi_enable = 0;
 223         u32 retvalue;
 224
 225         offset &= 0x3f;
 226         newoffset = offset;
 227         if (RT_CANNOT_IO(hw)) {
 228                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("return all one\n"));
 229                 return 0xFFFFFFFF;
 230         }
 231         tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);
 232         if (rfpath == RF90_PATH_A)
 233                 tmplong2 = tmplong;
 234         else
 235                 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);
 236         tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) |
 237             (newoffset << 23) | BLSSIREADEDGE;
 238         rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
 239                       tmplong & (~BLSSIREADEDGE));
 240         mdelay(1);
 241         rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);
 242         mdelay(1);
 243         rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
 244                       tmplong | BLSSIREADEDGE);
 245         mdelay(1);
 246         if (rfpath == RF90_PATH_A)
 247                 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
 248                                                  BIT(8));
 249         else if (rfpath == RF90_PATH_B)
 250                 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,
 251                                                  BIT(8));
 252         if (rfpi_enable)
 253                 retvalue = rtl_get_bbreg(hw, pphyreg->rflssi_readbackpi,
 254                                          BLSSIREADBACKDATA);
 255         else
 256                 retvalue = rtl_get_bbreg(hw, pphyreg->rflssi_readback,
 257                                          BLSSIREADBACKDATA);
 258         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("RFR-%d Addr[0x%x]=0x%x\n",
 259                                                rfpath, pphyreg->rflssi_readback,
 260                                                retvalue));
 261         return retvalue;
 262 }
 263
 264 static void _rtl92c_phy_rf_serial_write(struct ieee80211_hw *hw,
 265                                         enum radio_path rfpath, u32 offset,
 266                                         u32 data)
 267 {
 268         u32 data_and_addr;
 269         u32 newoffset;
 270         struct rtl_priv *rtlpriv = rtl_priv(hw);
 271         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 272         struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
 273
 274         if (RT_CANNOT_IO(hw)) {
 275                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("stop\n"));
 276                 return;
 277         }
 278         offset &= 0x3f;
 279         newoffset = offset;
 280         data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
 281         rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
 282         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("RFW-%d Addr[0x%x]=0x%x\n",
 283                                                rfpath, pphyreg->rf3wire_offset,
 284                                                data_and_addr));
 285 }
 286
 287 static u32 _rtl92c_phy_calculate_bit_shift(u32 bitmask)
 288 {
 289         u32 i;
 290
 291         for (i = 0; i <= 31; i++) {
 292                 if (((bitmask >> i) & 0x1) == 1)
 293                         break;
 294         }
 295         return i;
 296 }
 297
 298 static void _rtl92c_phy_bb_config_1t(struct ieee80211_hw *hw)
 299 {
 300         rtl_set_bbreg(hw, RFPGA0_TXINFO, 0x3, 0x2);
 301         rtl_set_bbreg(hw, RFPGA1_TXINFO, 0x300033, 0x200022);
 302         rtl_set_bbreg(hw, RCCK0_AFESETTING, MASKBYTE3, 0x45);
 303         rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x23);
 304         rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, 0x30, 0x1);
 305         rtl_set_bbreg(hw, 0xe74, 0x0c000000, 0x2);
 306         rtl_set_bbreg(hw, 0xe78, 0x0c000000, 0x2);
 307         rtl_set_bbreg(hw, 0xe7c, 0x0c000000, 0x2);
 308         rtl_set_bbreg(hw, 0xe80, 0x0c000000, 0x2);
 309         rtl_set_bbreg(hw, 0xe88, 0x0c000000, 0x2);
 310 }
 311
 312 bool rtl92c_phy_mac_config(struct ieee80211_hw *hw)
 313 {
 314         struct rtl_priv *rtlpriv = rtl_priv(hw);
 315         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 316         bool is92c = IS_92C_SERIAL(rtlhal->version);
 317         bool rtstatus = _rtl92c_phy_config_mac_with_headerfile(hw);
 318
 319         if (is92c)
 320                 rtl_write_byte(rtlpriv, 0x14, 0x71);
 321         return rtstatus;
 322 }
 323
 324 bool rtl92c_phy_bb_config(struct ieee80211_hw *hw)
 325 {
 326         bool rtstatus = true;
 327         struct rtl_priv *rtlpriv = rtl_priv(hw);
 328         u16 regval;
 329         u32 regvaldw;
 330         u8 b_reg_hwparafile = 1;
 331
 332         _rtl92c_phy_init_bb_rf_register_definition(hw);
 333         regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
 334         rtl_write_word(rtlpriv, REG_SYS_FUNC_EN,
 335                        regval | BIT(13) | BIT(0) | BIT(1));
 336         rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x83);
 337         rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL + 1, 0xdb);
 338         rtl_write_byte(rtlpriv, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB);
 339         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN,
 340                        FEN_PPLL | FEN_PCIEA | FEN_DIO_PCIE |
 341                        FEN_BB_GLB_RSTn | FEN_BBRSTB);
 342         rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80);
 343         regvaldw = rtl_read_dword(rtlpriv, REG_LEDCFG0);
 344         rtl_write_dword(rtlpriv, REG_LEDCFG0, regvaldw | BIT(23));
 345         if (b_reg_hwparafile == 1)
 346                 rtstatus = _rtl92c_phy_bb8192c_config_parafile(hw);
 347         return rtstatus;
 348 }
 349
 350 bool rtl92c_phy_rf_config(struct ieee80211_hw *hw)
 351 {
 352         return rtl92c_phy_rf6052_config(hw);
 353 }
 354
 355 static bool _rtl92c_phy_bb8192c_config_parafile(struct ieee80211_hw *hw)
 356 {
 357         struct rtl_priv *rtlpriv = rtl_priv(hw);
 358         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 359         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 360         bool rtstatus;
 361
 362         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("==>\n"));
 363         rtstatus = _rtl92c_phy_config_bb_with_headerfile(hw,
 364                                                  BASEBAND_CONFIG_PHY_REG);
 365         if (rtstatus != true) {
 366                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("Write BB Reg Fail!!"));
 367                 return false;
 368         }
 369         if (rtlphy->rf_type == RF_1T2R) {
 370                 _rtl92c_phy_bb_config_1t(hw);
 371                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("Config to 1T!!\n"));
 372         }
 373         if (rtlefuse->autoload_failflag == false) {
 374                 rtlphy->pwrgroup_cnt = 0;
 375                 rtstatus = _rtl92c_phy_config_bb_with_pgheaderfile(hw,
 376                                                    BASEBAND_CONFIG_PHY_REG);
 377         }
 378         if (rtstatus != true) {
 379                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("BB_PG Reg Fail!!"));
 380                 return false;
 381         }
 382         rtstatus = _rtl92c_phy_config_bb_with_headerfile(hw,
 383                                                  BASEBAND_CONFIG_AGC_TAB);
 384         if (rtstatus != true) {
 385                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("AGC Table Fail\n"));
 386                 return false;
 387         }
 388         rtlphy->bcck_high_power = (bool) (rtl_get_bbreg(hw,
 389                                                 RFPGA0_XA_HSSIPARAMETER2,
 390                                                 0x200));
 391         return true;
 392 }
 393
 394 static bool _rtl92c_phy_config_mac_with_headerfile(struct ieee80211_hw *hw)
 395 {
 396         struct rtl_priv *rtlpriv = rtl_priv(hw);
 397         u32 i;
 398         u32 arraylength;
 399         u32 *ptrarray;
 400
 401         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("Read Rtl819XMACPHY_Array\n"));
 402         arraylength = MAC_2T_ARRAYLENGTH;
 403         ptrarray = RTL8192CEMAC_2T_ARRAY;
 404         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 405                  ("Img:RTL8192CEMAC_2T_ARRAY\n"));
 406         for (i = 0; i < arraylength; i = i + 2)
 407                 rtl_write_byte(rtlpriv, ptrarray[i], (u8) ptrarray[i + 1]);
 408         return true;
 409 }
 410
 411 void rtl92c_phy_config_bb_external_pa(struct ieee80211_hw *hw)
 412 {
 413 }
 414
 415 static bool _rtl92c_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
 416                                                   u8 configtype)
 417 {
 418         int i;
 419         u32 *phy_regarray_table;
 420         u32 *agctab_array_table;
 421         u16 phy_reg_arraylen, agctab_arraylen;
 422         struct rtl_priv *rtlpriv = rtl_priv(hw);
 423         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 424
 425         if (IS_92C_SERIAL(rtlhal->version)) {
 426                 agctab_arraylen = AGCTAB_2TARRAYLENGTH;
 427                 agctab_array_table = RTL8192CEAGCTAB_2TARRAY;
 428                 phy_reg_arraylen = PHY_REG_2TARRAY_LENGTH;
 429                 phy_regarray_table = RTL8192CEPHY_REG_2TARRAY;
 430         } else {
 431                 agctab_arraylen = AGCTAB_1TARRAYLENGTH;
 432                 agctab_array_table = RTL8192CEAGCTAB_1TARRAY;
 433                 phy_reg_arraylen = PHY_REG_1TARRAY_LENGTH;
 434                 phy_regarray_table = RTL8192CEPHY_REG_1TARRAY;
 435         }
 436         if (configtype == BASEBAND_CONFIG_PHY_REG) {
 437                 for (i = 0; i < phy_reg_arraylen; i = i + 2) {
 438                         if (phy_regarray_table[i] == 0xfe)
 439                                 mdelay(50);
 440                         else if (phy_regarray_table[i] == 0xfd)
 441                                 mdelay(5);
 442                         else if (phy_regarray_table[i] == 0xfc)
 443                                 mdelay(1);
 444                         else if (phy_regarray_table[i] == 0xfb)
 445                                 udelay(50);
 446                         else if (phy_regarray_table[i] == 0xfa)
 447                                 udelay(5);
 448                         else if (phy_regarray_table[i] == 0xf9)
 449                                 udelay(1);
 450                         rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD,
 451                                       phy_regarray_table[i + 1]);
 452                         udelay(1);
 453                         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 454                                  ("The phy_regarray_table[0] is %x"
 455                                   " Rtl819XPHY_REGArray[1] is %x\n",
 456                                   phy_regarray_table[i],
 457                                   phy_regarray_table[i + 1]));
 458                 }
 459                 rtl92c_phy_config_bb_external_pa(hw);
 460         } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
 461                 for (i = 0; i < agctab_arraylen; i = i + 2) {
 462                         rtl_set_bbreg(hw, agctab_array_table[i], MASKDWORD,
 463                                       agctab_array_table[i + 1]);
 464                         udelay(1);
 465                         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 466                                  ("The agctab_array_table[0] is "
 467                                   "%x Rtl819XPHY_REGArray[1] is %x\n",
 468                                   agctab_array_table[i],
 469                                   agctab_array_table[i + 1]));
 470                 }
 471         }
 472         return true;
 473 }
 474
 475 static void _rtl92c_store_pwrIndex_diffrate_offset(struct ieee80211_hw *hw,
 476                                                    u32 regaddr, u32 bitmask,
 477                                                    u32 data)
 478 {
 479         struct rtl_priv *rtlpriv = rtl_priv(hw);
 480         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 481
 482         if (regaddr == RTXAGC_A_RATE18_06) {
 483                 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][0] =
 484                     data;
 485                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 486                          ("MCSTxPowerLevelOriginalOffset[%d][0] = 0x%x\n",
 487                           rtlphy->pwrgroup_cnt,
 488                           rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
 489                                                             pwrgroup_cnt][0]));
 490         }
 491         if (regaddr == RTXAGC_A_RATE54_24) {
 492                 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][1] =
 493                     data;
 494                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 495                          ("MCSTxPowerLevelOriginalOffset[%d][1] = 0x%x\n",
 496                           rtlphy->pwrgroup_cnt,
 497                           rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
 498                                                             pwrgroup_cnt][1]));
 499         }
 500         if (regaddr == RTXAGC_A_CCK1_MCS32) {
 501                 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][6] =
 502                     data;
 503                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 504                          ("MCSTxPowerLevelOriginalOffset[%d][6] = 0x%x\n",
 505                           rtlphy->pwrgroup_cnt,
 506                           rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
 507                                                             pwrgroup_cnt][6]));
 508         }
 509         if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00) {
 510                 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][7] =
 511                     data;
 512                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 513                          ("MCSTxPowerLevelOriginalOffset[%d][7] = 0x%x\n",
 514                           rtlphy->pwrgroup_cnt,
 515                           rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
 516                                                             pwrgroup_cnt][7]));
 517         }
 518         if (regaddr == RTXAGC_A_MCS03_MCS00) {
 519                 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][2] =
 520                     data;
 521                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 522                          ("MCSTxPowerLevelOriginalOffset[%d][2] = 0x%x\n",
 523                           rtlphy->pwrgroup_cnt,
 524                           rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
 525                                                             pwrgroup_cnt][2]));
 526         }
 527         if (regaddr == RTXAGC_A_MCS07_MCS04) {
 528                 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][3] =
 529                     data;
 530                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 531                          ("MCSTxPowerLevelOriginalOffset[%d][3] = 0x%x\n",
 532                           rtlphy->pwrgroup_cnt,
 533                           rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
 534                                                             pwrgroup_cnt][3]));
 535         }
 536         if (regaddr == RTXAGC_A_MCS11_MCS08) {
 537                 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][4] =
 538                     data;
 539                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 540                          ("MCSTxPowerLevelOriginalOffset[%d][4] = 0x%x\n",
 541                           rtlphy->pwrgroup_cnt,
 542                           rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
 543                                                             pwrgroup_cnt][4]));
 544         }
 545         if (regaddr == RTXAGC_A_MCS15_MCS12) {
 546                 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][5] =
 547                     data;
 548                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 549                          ("MCSTxPowerLevelOriginalOffset[%d][5] = 0x%x\n",
 550                           rtlphy->pwrgroup_cnt,
 551                           rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
 552                                                             pwrgroup_cnt][5]));
 553         }
 554         if (regaddr == RTXAGC_B_RATE18_06) {
 555                 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][8] =
 556                     data;
 557                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 558                          ("MCSTxPowerLevelOriginalOffset[%d][8] = 0x%x\n",
 559                           rtlphy->pwrgroup_cnt,
 560                           rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
 561                                                             pwrgroup_cnt][8]));
 562         }
 563         if (regaddr == RTXAGC_B_RATE54_24) {
 564                 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][9] =
 565                     data;
 566
 567                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 568                          ("MCSTxPowerLevelOriginalOffset[%d][9] = 0x%x\n",
 569                           rtlphy->pwrgroup_cnt,
 570                           rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
 571                                                             pwrgroup_cnt][9]));
 572         }
 573
 574         if (regaddr == RTXAGC_B_CCK1_55_MCS32) {
 575                 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][14] =
 576                     data;
 577
 578                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 579                          ("MCSTxPowerLevelOriginalOffset[%d][14] = 0x%x\n",
 580                           rtlphy->pwrgroup_cnt,
 581                           rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
 582                                                             pwrgroup_cnt][14]));
 583         }
 584
 585         if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff) {
 586                 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][15] =
 587                     data;
 588
 589                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 590                          ("MCSTxPowerLevelOriginalOffset[%d][15] = 0x%x\n",
 591                           rtlphy->pwrgroup_cnt,
 592                           rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
 593                                                             pwrgroup_cnt][15]));
 594         }
 595
 596         if (regaddr == RTXAGC_B_MCS03_MCS00) {
 597                 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][10] =
 598                     data;
 599
 600                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 601                          ("MCSTxPowerLevelOriginalOffset[%d][10] = 0x%x\n",
 602                           rtlphy->pwrgroup_cnt,
 603                           rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
 604                                                             pwrgroup_cnt][10]));
 605         }
 606
 607         if (regaddr == RTXAGC_B_MCS07_MCS04) {
 608                 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][11] =
 609                     data;
 610
 611                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 612                          ("MCSTxPowerLevelOriginalOffset[%d][11] = 0x%x\n",
 613                           rtlphy->pwrgroup_cnt,
 614                           rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
 615                                                             pwrgroup_cnt][11]));
 616         }
 617
 618         if (regaddr == RTXAGC_B_MCS11_MCS08) {
 619                 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][12] =
 620                     data;
 621
 622                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 623                          ("MCSTxPowerLevelOriginalOffset[%d][12] = 0x%x\n",
 624                           rtlphy->pwrgroup_cnt,
 625                           rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
 626                                                             pwrgroup_cnt][12]));
 627         }
 628
 629         if (regaddr == RTXAGC_B_MCS15_MCS12) {
 630                 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][13] =
 631                     data;
 632
 633                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 634                          ("MCSTxPowerLevelOriginalOffset[%d][13] = 0x%x\n",
 635                           rtlphy->pwrgroup_cnt,
 636                           rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
 637                                                             pwrgroup_cnt][13]));
 638
 639                 rtlphy->pwrgroup_cnt++;
 640         }
 641 }
 642
 643 static bool _rtl92c_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
 644                                                     u8 configtype)
 645 {
 646         struct rtl_priv *rtlpriv = rtl_priv(hw);
 647         int i;
 648         u32 *phy_regarray_table_pg;
 649         u16 phy_regarray_pg_len;
 650
 651         phy_regarray_pg_len = PHY_REG_ARRAY_PGLENGTH;
 652         phy_regarray_table_pg = RTL8192CEPHY_REG_ARRAY_PG;
 653
 654         if (configtype == BASEBAND_CONFIG_PHY_REG) {
 655                 for (i = 0; i < phy_regarray_pg_len; i = i + 3) {
 656                         if (phy_regarray_table_pg[i] == 0xfe)
 657                                 mdelay(50);
 658                         else if (phy_regarray_table_pg[i] == 0xfd)
 659                                 mdelay(5);
 660                         else if (phy_regarray_table_pg[i] == 0xfc)
 661                                 mdelay(1);
 662                         else if (phy_regarray_table_pg[i] == 0xfb)
 663                                 udelay(50);
 664                         else if (phy_regarray_table_pg[i] == 0xfa)
 665                                 udelay(5);
 666                         else if (phy_regarray_table_pg[i] == 0xf9)
 667                                 udelay(1);
 668
 669                         _rtl92c_store_pwrIndex_diffrate_offset(hw,
 670                                                phy_regarray_table_pg[i],
 671                                                phy_regarray_table_pg[i + 1],
 672                                                phy_regarray_table_pg[i + 2]);
 673                 }
 674         } else {
 675
 676                 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
 677                          ("configtype != BaseBand_Config_PHY_REG\n"));
 678         }
 679         return true;
 680 }
 681
 682 static bool _rtl92c_phy_config_rf_external_pa(struct ieee80211_hw *hw,
 683                                               enum radio_path rfpath)
 684 {
 685         return true;
 686 }
 687
 688 bool rtl92c_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
 689                                           enum radio_path rfpath)
 690 {
 691
 692         int i;
 693         bool rtstatus = true;
 694         u32 *radioa_array_table;
 695         u32 *radiob_array_table;
 696         u16 radioa_arraylen, radiob_arraylen;
 697         struct rtl_priv *rtlpriv = rtl_priv(hw);
 698         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 699
 700         if (IS_92C_SERIAL(rtlhal->version)) {
 701                 radioa_arraylen = RADIOA_2TARRAYLENGTH;
 702                 radioa_array_table = RTL8192CERADIOA_2TARRAY;
 703                 radiob_arraylen = RADIOB_2TARRAYLENGTH;
 704                 radiob_array_table = RTL8192CE_RADIOB_2TARRAY;
 705                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 706                          ("Radio_A:RTL8192CERADIOA_2TARRAY\n"));
 707                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 708                          ("Radio_B:RTL8192CE_RADIOB_2TARRAY\n"));
 709         } else {
 710                 radioa_arraylen = RADIOA_1TARRAYLENGTH;
 711                 radioa_array_table = RTL8192CE_RADIOA_1TARRAY;
 712                 radiob_arraylen = RADIOB_1TARRAYLENGTH;
 713                 radiob_array_table = RTL8192CE_RADIOB_1TARRAY;
 714                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 715                          ("Radio_A:RTL8192CE_RADIOA_1TARRAY\n"));
 716                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 717                          ("Radio_B:RTL8192CE_RADIOB_1TARRAY\n"));
 718         }
 719         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("Radio No %x\n", rfpath));
 720         rtstatus = true;
 721         switch (rfpath) {
 722         case RF90_PATH_A:
 723                 for (i = 0; i < radioa_arraylen; i = i + 2) {
 724                         if (radioa_array_table[i] == 0xfe)
 725                                 mdelay(50);
 726                         else if (radioa_array_table[i] == 0xfd)
 727                                 mdelay(5);
 728                         else if (radioa_array_table[i] == 0xfc)
 729                                 mdelay(1);
 730                         else if (radioa_array_table[i] == 0xfb)
 731                                 udelay(50);
 732                         else if (radioa_array_table[i] == 0xfa)
 733                                 udelay(5);
 734                         else if (radioa_array_table[i] == 0xf9)
 735                                 udelay(1);
 736                         else {
 737                                 rtl_set_rfreg(hw, rfpath, radioa_array_table[i],
 738                                               RFREG_OFFSET_MASK,
 739                                               radioa_array_table[i + 1]);
 740                                 udelay(1);
 741                         }
 742                 }
 743                 _rtl92c_phy_config_rf_external_pa(hw, rfpath);
 744                 break;
 745         case RF90_PATH_B:
 746                 for (i = 0; i < radiob_arraylen; i = i + 2) {
 747                         if (radiob_array_table[i] == 0xfe) {
 748                                 mdelay(50);
 749                         } else if (radiob_array_table[i] == 0xfd)
 750                                 mdelay(5);
 751                         else if (radiob_array_table[i] == 0xfc)
 752                                 mdelay(1);
 753                         else if (radiob_array_table[i] == 0xfb)
 754                                 udelay(50);
 755                         else if (radiob_array_table[i] == 0xfa)
 756                                 udelay(5);
 757                         else if (radiob_array_table[i] == 0xf9)
 758                                 udelay(1);
 759                         else {
 760                                 rtl_set_rfreg(hw, rfpath, radiob_array_table[i],
 761                                               RFREG_OFFSET_MASK,
 762                                               radiob_array_table[i + 1]);
 763                                 udelay(1);
 764                         }
 765                 }
 766                 break;
 767         case RF90_PATH_C:
 768                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 769                          ("switch case not process\n"));
 770                 break;
 771         case RF90_PATH_D:
 772                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 773                          ("switch case not process\n"));
 774                 break;
 775         }
 776         return true;
 777 }
 778
 779 void rtl92c_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
 780 {
 781         struct rtl_priv *rtlpriv = rtl_priv(hw);
 782         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 783
 784         rtlphy->default_initialgain[0] =
 785             (u8) rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0);
 786         rtlphy->default_initialgain[1] =
 787             (u8) rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0);
 788         rtlphy->default_initialgain[2] =
 789             (u8) rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0);
 790         rtlphy->default_initialgain[3] =
 791             (u8) rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0);
 792
 793         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 794                  ("Default initial gain (c50=0x%x, "
 795                   "c58=0x%x, c60=0x%x, c68=0x%x\n",
 796                   rtlphy->default_initialgain[0],
 797                   rtlphy->default_initialgain[1],
 798                   rtlphy->default_initialgain[2],
 799                   rtlphy->default_initialgain[3]));
 800
 801         rtlphy->framesync = (u8) rtl_get_bbreg(hw,
 802                                                ROFDM0_RXDETECTOR3, MASKBYTE0);
 803         rtlphy->framesync_c34 = rtl_get_bbreg(hw,
 804                                               ROFDM0_RXDETECTOR2, MASKDWORD);
 805
 806         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 807                  ("Default framesync (0x%x) = 0x%x\n",
 808                   ROFDM0_RXDETECTOR3, rtlphy->framesync));
 809 }
 810
 811 static void _rtl92c_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw)
 812 {
 813         struct rtl_priv *rtlpriv = rtl_priv(hw);
 814         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 815
 816         rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
 817         rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
 818         rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;
 819         rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;
 820
 821         rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB;
 822         rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;
 823         rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;
 824         rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB;
 825
 826         rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
 827         rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
 828
 829         rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
 830         rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
 831
 832         rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =
 833             RFPGA0_XA_LSSIPARAMETER;
 834         rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =
 835             RFPGA0_XB_LSSIPARAMETER;
 836
 837         rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = rFPGA0_XAB_RFPARAMETER;
 838         rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = rFPGA0_XAB_RFPARAMETER;
 839         rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = rFPGA0_XCD_RFPARAMETER;
 840         rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = rFPGA0_XCD_RFPARAMETER;
 841
 842         rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;
 843         rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;
 844         rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;
 845         rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE;
 846
 847         rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1;
 848         rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;
 849
 850         rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;
 851         rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;
 852
 853         rtlphy->phyreg_def[RF90_PATH_A].rfswitch_control =
 854             RFPGA0_XAB_SWITCHCONTROL;
 855         rtlphy->phyreg_def[RF90_PATH_B].rfswitch_control =
 856             RFPGA0_XAB_SWITCHCONTROL;
 857         rtlphy->phyreg_def[RF90_PATH_C].rfswitch_control =
 858             RFPGA0_XCD_SWITCHCONTROL;
 859         rtlphy->phyreg_def[RF90_PATH_D].rfswitch_control =
 860             RFPGA0_XCD_SWITCHCONTROL;
 861
 862         rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1;
 863         rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;
 864         rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;
 865         rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1;
 866
 867         rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2;
 868         rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;
 869         rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;
 870         rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2;
 871
 872         rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbalance =
 873             ROFDM0_XARXIQIMBALANCE;
 874         rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbalance =
 875             ROFDM0_XBRXIQIMBALANCE;
 876         rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbalance =
 877             ROFDM0_XCRXIQIMBANLANCE;
 878         rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbalance =
 879             ROFDM0_XDRXIQIMBALANCE;
 880
 881         rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE;
 882         rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;
 883         rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;
 884         rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;
 885
 886         rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbalance =
 887             ROFDM0_XATXIQIMBALANCE;
 888         rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbalance =
 889             ROFDM0_XBTXIQIMBALANCE;
 890         rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbalance =
 891             ROFDM0_XCTXIQIMBALANCE;
 892         rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbalance =
 893             ROFDM0_XDTXIQIMBALANCE;
 894
 895         rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE;
 896         rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE;
 897         rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTXAFE;
 898         rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTXAFE;
 899
 900         rtlphy->phyreg_def[RF90_PATH_A].rflssi_readback =
 901             RFPGA0_XA_LSSIREADBACK;
 902         rtlphy->phyreg_def[RF90_PATH_B].rflssi_readback =
 903             RFPGA0_XB_LSSIREADBACK;
 904         rtlphy->phyreg_def[RF90_PATH_C].rflssi_readback =
 905             RFPGA0_XC_LSSIREADBACK;
 906         rtlphy->phyreg_def[RF90_PATH_D].rflssi_readback =
 907             RFPGA0_XD_LSSIREADBACK;
 908
 909         rtlphy->phyreg_def[RF90_PATH_A].rflssi_readbackpi =
 910             TRANSCEIVEA_HSPI_READBACK;
 911         rtlphy->phyreg_def[RF90_PATH_B].rflssi_readbackpi =
 912             TRANSCEIVEB_HSPI_READBACK;
 913
 914 }
 915
 916 void rtl92c_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel)
 917 {
 918         struct rtl_priv *rtlpriv = rtl_priv(hw);
 919         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 920         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 921         u8 txpwr_level;
 922         long txpwr_dbm;
 923
 924         txpwr_level = rtlphy->cur_cck_txpwridx;
 925         txpwr_dbm = _rtl92c_phy_txpwr_idx_to_dbm(hw,
 926                                                  WIRELESS_MODE_B, txpwr_level);
 927         txpwr_level = rtlphy->cur_ofdm24g_txpwridx +
 928             rtlefuse->legacy_ht_txpowerdiff;
 929         if (_rtl92c_phy_txpwr_idx_to_dbm(hw,
 930                                          WIRELESS_MODE_G,
 931                                          txpwr_level) > txpwr_dbm)
 932                 txpwr_dbm =
 933                     _rtl92c_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G,
 934                                                  txpwr_level);
 935         txpwr_level = rtlphy->cur_ofdm24g_txpwridx;
 936         if (_rtl92c_phy_txpwr_idx_to_dbm(hw,
 937                                          WIRELESS_MODE_N_24G,
 938                                          txpwr_level) > txpwr_dbm)
 939                 txpwr_dbm =
 940                     _rtl92c_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G,
 941                                                  txpwr_level);
 942         *powerlevel = txpwr_dbm;
 943 }
 944
 945 static void _rtl92c_get_txpower_index(struct ieee80211_hw *hw, u8 channel,
 946                                       u8 *cckpowerlevel, u8 *ofdmpowerlevel)
 947 {
 948         struct rtl_priv *rtlpriv = rtl_priv(hw);
 949         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 950         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 951         u8 index = (channel - 1);
 952
 953         cckpowerlevel[RF90_PATH_A] =
 954             rtlefuse->txpwrlevel_cck[RF90_PATH_A][index];
 955         cckpowerlevel[RF90_PATH_B] =
 956             rtlefuse->txpwrlevel_cck[RF90_PATH_B][index];
 957         if (get_rf_type(rtlphy) == RF_1T2R || get_rf_type(rtlphy) == RF_1T1R) {
 958                 ofdmpowerlevel[RF90_PATH_A] =
 959                     rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index];
 960                 ofdmpowerlevel[RF90_PATH_B] =
 961                     rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index];
 962         } else if (get_rf_type(rtlphy) == RF_2T2R) {
 963                 ofdmpowerlevel[RF90_PATH_A] =
 964                     rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_A][index];
 965                 ofdmpowerlevel[RF90_PATH_B] =
 966                     rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_B][index];
 967         }
 968 }
 969
 970 static void _rtl92c_ccxpower_index_check(struct ieee80211_hw *hw,
 971                                          u8 channel, u8 *cckpowerlevel,
 972                                          u8 *ofdmpowerlevel)
 973 {
 974         struct rtl_priv *rtlpriv = rtl_priv(hw);
 975         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 976
 977         rtlphy->cur_cck_txpwridx = cckpowerlevel[0];
 978         rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0];
 979 }
 980
 981 void rtl92c_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel)
 982 {
 983         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 984         u8 cckpowerlevel[2], ofdmpowerlevel[2];
 985
 986         if (rtlefuse->b_txpwr_fromeprom == false)
 987                 return;
 988         _rtl92c_get_txpower_index(hw, channel,
 989                                   &cckpowerlevel[0], &ofdmpowerlevel[0]);
 990         _rtl92c_ccxpower_index_check(hw,
 991                                      channel, &cckpowerlevel[0],
 992                                      &ofdmpowerlevel[0]);
 993         rtl92c_phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]);
 994         rtl92c_phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0], channel);
 995 }
 996
 997 bool rtl92c_phy_update_txpower_dbm(struct ieee80211_hw *hw, long power_indbm)
 998 {
 999         struct rtl_priv *rtlpriv = rtl_priv(hw);
1000         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1001         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1002         u8 idx;
1003         u8 rf_path;
1004
1005         u8 ccktxpwridx = _rtl92c_phy_dbm_to_txpwr_Idx(hw,
1006                                                       WIRELESS_MODE_B,
1007                                                       power_indbm);
1008         u8 ofdmtxpwridx = _rtl92c_phy_dbm_to_txpwr_Idx(hw,
1009                                                        WIRELESS_MODE_N_24G,
1010                                                        power_indbm);
1011         if (ofdmtxpwridx - rtlefuse->legacy_ht_txpowerdiff > 0)
1012                 ofdmtxpwridx -= rtlefuse->legacy_ht_txpowerdiff;
1013         else
1014                 ofdmtxpwridx = 0;
1015         RT_TRACE(rtlpriv, COMP_TXAGC, DBG_TRACE,
1016                  ("%lx dBm, ccktxpwridx = %d, ofdmtxpwridx = %d\n",
1017                   power_indbm, ccktxpwridx, ofdmtxpwridx));
1018         for (idx = 0; idx < 14; idx++) {
1019                 for (rf_path = 0; rf_path < 2; rf_path++) {
1020                         rtlefuse->txpwrlevel_cck[rf_path][idx] = ccktxpwridx;
1021                         rtlefuse->txpwrlevel_ht40_1s[rf_path][idx] =
1022                             ofdmtxpwridx;
1023                         rtlefuse->txpwrlevel_ht40_2s[rf_path][idx] =
1024                             ofdmtxpwridx;
1025                 }
1026         }
1027         rtl92c_phy_set_txpower_level(hw, rtlphy->current_channel);
1028         return true;
1029 }
1030
1031 void rtl92c_phy_set_beacon_hw_reg(struct ieee80211_hw *hw, u16 beaconinterval)
1032 {
1033 }
1034
1035 static u8 _rtl92c_phy_dbm_to_txpwr_Idx(struct ieee80211_hw *hw,
1036                                        enum wireless_mode wirelessmode,
1037                                        long power_indbm)
1038 {
1039         u8 txpwridx;
1040         long offset;
1041
1042         switch (wirelessmode) {
1043         case WIRELESS_MODE_B:
1044                 offset = -7;
1045                 break;
1046         case WIRELESS_MODE_G:
1047         case WIRELESS_MODE_N_24G:
1048                 offset = -8;
1049                 break;
1050         default:
1051                 offset = -8;
1052                 break;
1053         }
1054
1055         if ((power_indbm - offset) > 0)
1056                 txpwridx = (u8) ((power_indbm - offset) * 2);
1057         else
1058                 txpwridx = 0;
1059
1060         if (txpwridx > MAX_TXPWR_IDX_NMODE_92S)
1061                 txpwridx = MAX_TXPWR_IDX_NMODE_92S;
1062
1063         return txpwridx;
1064 }
1065
1066 static long _rtl92c_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
1067                                          enum wireless_mode wirelessmode,
1068                                          u8 txpwridx)
1069 {
1070         long offset;
1071         long pwrout_dbm;
1072
1073         switch (wirelessmode) {
1074         case WIRELESS_MODE_B:
1075                 offset = -7;
1076                 break;
1077         case WIRELESS_MODE_G:
1078         case WIRELESS_MODE_N_24G:
1079                 offset = -8;
1080                 break;
1081         default:
1082                 offset = -8;
1083                 break;
1084         }
1085         pwrout_dbm = txpwridx / 2 + offset;
1086         return pwrout_dbm;
1087 }
1088
1089 void rtl92c_phy_scan_operation_backup(struct ieee80211_hw *hw, u8 operation)
1090 {
1091         struct rtl_priv *rtlpriv = rtl_priv(hw);
1092         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1093         enum io_type iotype;
1094
1095         if (!is_hal_stop(rtlhal)) {
1096                 switch (operation) {
1097                 case SCAN_OPT_BACKUP:
1098                         iotype = IO_CMD_PAUSE_DM_BY_SCAN;
1099                         rtlpriv->cfg->ops->set_hw_reg(hw,
1100                                                       HW_VAR_IO_CMD,
1101                                                       (u8 *)&iotype);
1102
1103                         break;
1104                 case SCAN_OPT_RESTORE:
1105                         iotype = IO_CMD_RESUME_DM_BY_SCAN;
1106                         rtlpriv->cfg->ops->set_hw_reg(hw,
1107                                                       HW_VAR_IO_CMD,
1108                                                       (u8 *)&iotype);
1109                         break;
1110                 default:
1111                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1112                                  ("Unknown Scan Backup operation.\n"));
1113                         break;
1114                 }
1115         }
1116 }
1117
1118 void rtl92c_phy_set_bw_mode_callback(struct ieee80211_hw *hw)
1119 {
1120         struct rtl_priv *rtlpriv = rtl_priv(hw);
1121         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1122         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1123         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1124         u8 reg_bw_opmode;
1125         u8 reg_prsr_rsc;
1126
1127         RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
1128                  ("Switch to %s bandwidth\n",
1129                   rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
1130                   "20MHz" : "40MHz"))
1131
1132             if (is_hal_stop(rtlhal))
1133                 return;
1134
1135         reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE);
1136         reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2);
1137
1138         switch (rtlphy->current_chan_bw) {
1139         case HT_CHANNEL_WIDTH_20:
1140                 reg_bw_opmode |= BW_OPMODE_20MHZ;
1141                 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
1142                 break;
1143
1144         case HT_CHANNEL_WIDTH_20_40:
1145                 reg_bw_opmode &= ~BW_OPMODE_20MHZ;
1146                 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
1147
1148                 reg_prsr_rsc =
1149                     (reg_prsr_rsc & 0x90) | (mac->cur_40_prime_sc << 5);
1150                 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc);
1151                 break;
1152
1153         default:
1154                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1155                          ("unknown bandwidth: %#X\n", rtlphy->current_chan_bw));
1156                 break;
1157         }
1158
1159         switch (rtlphy->current_chan_bw) {
1160         case HT_CHANNEL_WIDTH_20:
1161                 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
1162                 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
1163                 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
1164                 break;
1165         case HT_CHANNEL_WIDTH_20_40:
1166                 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
1167                 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
1168                 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND,
1169                               (mac->cur_40_prime_sc >> 1));
1170                 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
1171                 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 0);
1172                 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)),
1173                               (mac->cur_40_prime_sc ==
1174                                HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
1175                 break;
1176         default:
1177                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1178                          ("unknown bandwidth: %#X\n", rtlphy->current_chan_bw));
1179                 break;
1180         }
1181         rtl92c_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
1182         rtlphy->set_bwmode_inprogress = false;
1183         RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, ("<==\n"));
1184 }
1185
1186 void rtl92c_phy_set_bw_mode(struct ieee80211_hw *hw,
1187                             enum nl80211_channel_type ch_type)
1188 {
1189         struct rtl_priv *rtlpriv = rtl_priv(hw);
1190         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1191         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1192         u8 tmp_bw = rtlphy->current_chan_bw;
1193
1194         if (rtlphy->set_bwmode_inprogress)
1195                 return;
1196         rtlphy->set_bwmode_inprogress = true;
1197         if ((!is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw)))
1198                 rtl92c_phy_set_bw_mode_callback(hw);
1199         else {
1200                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1201                          ("FALSE driver sleep or unload\n"));
1202                 rtlphy->set_bwmode_inprogress = false;
1203                 rtlphy->current_chan_bw = tmp_bw;
1204         }
1205 }
1206
1207 void rtl92c_phy_sw_chnl_callback(struct ieee80211_hw *hw)
1208 {
1209         struct rtl_priv *rtlpriv = rtl_priv(hw);
1210         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1211         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1212         u32 delay;
1213
1214         RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
1215                  ("switch to channel%d\n", rtlphy->current_channel));
1216         if (is_hal_stop(rtlhal))
1217                 return;
1218         do {
1219                 if (!rtlphy->sw_chnl_inprogress)
1220                         break;
1221                 if (!_rtl92c_phy_sw_chnl_step_by_step
1222                     (hw, rtlphy->current_channel, &rtlphy->sw_chnl_stage,
1223                      &rtlphy->sw_chnl_step, &delay)) {
1224                         if (delay > 0)
1225                                 mdelay(delay);
1226                         else
1227                                 continue;
1228                 } else
1229                         rtlphy->sw_chnl_inprogress = false;
1230                 break;
1231         } while (true);
1232         RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, ("<==\n"));
1233 }
1234
1235 u8 rtl92c_phy_sw_chnl(struct ieee80211_hw *hw)
1236 {
1237         struct rtl_priv *rtlpriv = rtl_priv(hw);
1238         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1239         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1240
1241         if (rtlphy->sw_chnl_inprogress)
1242                 return 0;
1243         if (rtlphy->set_bwmode_inprogress)
1244                 return 0;
1245         RT_ASSERT((rtlphy->current_channel <= 14),
1246                   ("WIRELESS_MODE_G but channel>14"));
1247         rtlphy->sw_chnl_inprogress = true;
1248         rtlphy->sw_chnl_stage = 0;
1249         rtlphy->sw_chnl_step = 0;
1250         if (!(is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
1251                 rtl92c_phy_sw_chnl_callback(hw);
1252                 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
1253                          ("sw_chnl_inprogress false schdule workitem\n"));
1254                 rtlphy->sw_chnl_inprogress = false;
1255         } else {
1256                 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
1257                          ("sw_chnl_inprogress false driver sleep or"
1258                           " unload\n"));
1259                 rtlphy->sw_chnl_inprogress = false;
1260         }
1261         return 1;
1262 }
1263
1264 static bool _rtl92c_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
1265                                              u8 channel, u8 *stage, u8 *step,
1266                                              u32 *delay)
1267 {
1268         struct rtl_priv *rtlpriv = rtl_priv(hw);
1269         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1270         struct swchnlcmd precommoncmd[MAX_PRECMD_CNT];
1271         u32 precommoncmdcnt;
1272         struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT];
1273         u32 postcommoncmdcnt;
1274         struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT];
1275         u32 rfdependcmdcnt;
1276         struct swchnlcmd *currentcmd = NULL;
1277         u8 rfpath;
1278         u8 num_total_rfpath = rtlphy->num_total_rfpath;
1279
1280         precommoncmdcnt = 0;
1281         _rtl92c_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
1282                                          MAX_PRECMD_CNT,
1283                                          CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0);
1284         _rtl92c_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
1285                                          MAX_PRECMD_CNT, CMDID_END, 0, 0, 0);
1286
1287         postcommoncmdcnt = 0;
1288
1289         _rtl92c_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++,
1290                                          MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0);
1291
1292         rfdependcmdcnt = 0;
1293
1294         RT_ASSERT((channel >= 1 && channel <= 14),
1295                   ("illegal channel for Zebra: %d\n", channel));
1296
1297         _rtl92c_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
1298                                          MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG,
1299                                          RF_CHNLBW, channel, 10);
1300
1301         _rtl92c_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
1302                                          MAX_RFDEPENDCMD_CNT, CMDID_END, 0, 0,
1303                                          0);
1304
1305         do {
1306                 switch (*stage) {
1307                 case 0:
1308                         currentcmd = &precommoncmd[*step];
1309                         break;
1310                 case 1:
1311                         currentcmd = &rfdependcmd[*step];
1312                         break;
1313                 case 2:
1314                         currentcmd = &postcommoncmd[*step];
1315                         break;
1316                 }
1317
1318                 if (currentcmd->cmdid == CMDID_END) {
1319                         if ((*stage) == 2) {
1320                                 return true;
1321                         } else {
1322                                 (*stage)++;
1323                                 (*step) = 0;
1324                                 continue;
1325                         }
1326                 }
1327
1328                 switch (currentcmd->cmdid) {
1329                 case CMDID_SET_TXPOWEROWER_LEVEL:
1330                         rtl92c_phy_set_txpower_level(hw, channel);
1331                         break;
1332                 case CMDID_WRITEPORT_ULONG:
1333                         rtl_write_dword(rtlpriv, currentcmd->para1,
1334                                         currentcmd->para2);
1335                         break;
1336                 case CMDID_WRITEPORT_USHORT:
1337                         rtl_write_word(rtlpriv, currentcmd->para1,
1338                                        (u16) currentcmd->para2);
1339                         break;
1340                 case CMDID_WRITEPORT_UCHAR:
1341                         rtl_write_byte(rtlpriv, currentcmd->para1,
1342                                        (u8) currentcmd->para2);
1343                         break;
1344                 case CMDID_RF_WRITEREG:
1345                         for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) {
1346                                 rtlphy->rfreg_chnlval[rfpath] =
1347                                     ((rtlphy->rfreg_chnlval[rfpath] &
1348                                       0xfffffc00) | currentcmd->para2);
1349
1350                                 rtl_set_rfreg(hw, (enum radio_path)rfpath,
1351                                               currentcmd->para1,
1352                                               RFREG_OFFSET_MASK,
1353                                               rtlphy->rfreg_chnlval[rfpath]);
1354                         }
1355                         break;
1356                 default:
1357                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1358                                  ("switch case not process\n"));
1359                         break;
1360                 }
1361
1362                 break;
1363         } while (true);
1364
1365         (*delay) = currentcmd->msdelay;
1366         (*step)++;
1367         return false;
1368 }
1369
1370 static bool _rtl92c_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
1371                                              u32 cmdtableidx, u32 cmdtablesz,
1372                                              enum swchnlcmd_id cmdid,
1373                                              u32 para1, u32 para2, u32 msdelay)
1374 {
1375         struct swchnlcmd *pcmd;
1376
1377         if (cmdtable == NULL) {
1378                 RT_ASSERT(false, ("cmdtable cannot be NULL.\n"));
1379                 return false;
1380         }
1381
1382         if (cmdtableidx >= cmdtablesz)
1383                 return false;
1384
1385         pcmd = cmdtable + cmdtableidx;
1386         pcmd->cmdid = cmdid;
1387         pcmd->para1 = para1;
1388         pcmd->para2 = para2;
1389         pcmd->msdelay = msdelay;
1390         return true;
1391 }
1392
1393 bool rtl8192_phy_check_is_legal_rfpath(struct ieee80211_hw *hw, u32 rfpath)
1394 {
1395         return true;
1396 }
1397
1398 static u8 _rtl92c_phy_path_a_iqk(struct ieee80211_hw *hw, bool config_pathb)
1399 {
1400         u32 reg_eac, reg_e94, reg_e9c, reg_ea4;
1401         u8 result = 0x00;
1402
1403         rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1f);
1404         rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c1f);
1405         rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140102);
1406         rtl_set_bbreg(hw, 0xe3c, MASKDWORD,
1407                       config_pathb ? 0x28160202 : 0x28160502);
1408
1409         if (config_pathb) {
1410                 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x10008c22);
1411                 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x10008c22);
1412                 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140102);
1413                 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x28160202);
1414         }
1415
1416         rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x001028d1);
1417         rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000);
1418         rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000);
1419
1420         mdelay(IQK_DELAY_TIME);
1421
1422         reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1423         reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);
1424         reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);
1425         reg_ea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD);
1426
1427         if (!(reg_eac & BIT(28)) &&
1428             (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
1429             (((reg_e9c & 0x03FF0000) >> 16) != 0x42))
1430                 result |= 0x01;
1431         else
1432                 return result;
1433
1434         if (!(reg_eac & BIT(27)) &&
1435             (((reg_ea4 & 0x03FF0000) >> 16) != 0x132) &&
1436             (((reg_eac & 0x03FF0000) >> 16) != 0x36))
1437                 result |= 0x02;
1438         return result;
1439 }
1440
1441 static u8 _rtl92c_phy_path_b_iqk(struct ieee80211_hw *hw)
1442 {
1443         u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
1444         u8 result = 0x00;
1445
1446         rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002);
1447         rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000);
1448         mdelay(IQK_DELAY_TIME);
1449         reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1450         reg_eb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD);
1451         reg_ebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD);
1452         reg_ec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD);
1453         reg_ecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD);
1454         if (!(reg_eac & BIT(31)) &&
1455             (((reg_eb4 & 0x03FF0000) >> 16) != 0x142) &&
1456             (((reg_ebc & 0x03FF0000) >> 16) != 0x42))
1457                 result |= 0x01;
1458         else
1459                 return result;
1460
1461         if (!(reg_eac & BIT(30)) &&
1462             (((reg_ec4 & 0x03FF0000) >> 16) != 0x132) &&
1463             (((reg_ecc & 0x03FF0000) >> 16) != 0x36))
1464                 result |= 0x02;
1465         return result;
1466 }
1467
1468 static void _rtl92c_phy_path_a_fill_iqk_matrix(struct ieee80211_hw *hw,
1469                                                bool b_iqk_ok, long result[][8],
1470                                                u8 final_candidate, bool btxonly)
1471 {
1472         u32 oldval_0, x, tx0_a, reg;
1473         long y, tx0_c;
1474
1475         if (final_candidate == 0xFF)
1476                 return;
1477         else if (b_iqk_ok) {
1478                 oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
1479                                           MASKDWORD) >> 22) & 0x3FF;
1480                 x = result[final_candidate][0];
1481                 if ((x & 0x00000200) != 0)
1482                         x = x | 0xFFFFFC00;
1483                 tx0_a = (x * oldval_0) >> 8;
1484                 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a);
1485                 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(31),
1486                               ((x * oldval_0 >> 7) & 0x1));
1487                 y = result[final_candidate][1];
1488                 if ((y & 0x00000200) != 0)
1489                         y = y | 0xFFFFFC00;
1490                 tx0_c = (y * oldval_0) >> 8;
1491                 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000,
1492                               ((tx0_c & 0x3C0) >> 6));
1493                 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000,
1494                               (tx0_c & 0x3F));
1495                 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(29),
1496                               ((y * oldval_0 >> 7) & 0x1));
1497                 if (btxonly)
1498                         return;
1499                 reg = result[final_candidate][2];
1500                 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg);
1501                 reg = result[final_candidate][3] & 0x3F;
1502                 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg);
1503                 reg = (result[final_candidate][3] >> 6) & 0xF;
1504                 rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg);
1505         }
1506 }
1507
1508 static void _rtl92c_phy_path_b_fill_iqk_matrix(struct ieee80211_hw *hw,
1509                                                bool b_iqk_ok, long result[][8],
1510                                                u8 final_candidate, bool btxonly)
1511 {
1512         u32 oldval_1, x, tx1_a, reg;
1513         long y, tx1_c;
1514
1515         if (final_candidate == 0xFF)
1516                 return;
1517         else if (b_iqk_ok) {
1518                 oldval_1 = (rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE,
1519                                           MASKDWORD) >> 22) & 0x3FF;
1520                 x = result[final_candidate][4];
1521                 if ((x & 0x00000200) != 0)
1522                         x = x | 0xFFFFFC00;
1523                 tx1_a = (x * oldval_1) >> 8;
1524                 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x3FF, tx1_a);
1525                 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(27),
1526                               ((x * oldval_1 >> 7) & 0x1));
1527                 y = result[final_candidate][5];
1528                 if ((y & 0x00000200) != 0)
1529                         y = y | 0xFFFFFC00;
1530                 tx1_c = (y * oldval_1) >> 8;
1531                 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000,
1532                               ((tx1_c & 0x3C0) >> 6));
1533                 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x003F0000,
1534                               (tx1_c & 0x3F));
1535                 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(25),
1536                               ((y * oldval_1 >> 7) & 0x1));
1537                 if (btxonly)
1538                         return;
1539                 reg = result[final_candidate][6];
1540                 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg);
1541                 reg = result[final_candidate][7] & 0x3F;
1542                 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg);
1543                 reg = (result[final_candidate][7] >> 6) & 0xF;
1544                 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, reg);
1545         }
1546 }
1547
1548 static void _rtl92c_phy_save_adda_registers(struct ieee80211_hw *hw,
1549                                             u32 *addareg, u32 *addabackup,
1550                                             u32 registernum)
1551 {
1552         u32 i;
1553
1554         for (i = 0; i < registernum; i++)
1555                 addabackup[i] = rtl_get_bbreg(hw, addareg[i], MASKDWORD);
1556 }
1557
1558 static void _rtl92c_phy_save_mac_registers(struct ieee80211_hw *hw,
1559                                            u32 *macreg, u32 *macbackup)
1560 {
1561         struct rtl_priv *rtlpriv = rtl_priv(hw);
1562         u32 i;
1563
1564         for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1565                 macbackup[i] = rtl_read_byte(rtlpriv, macreg[i]);
1566         macbackup[i] = rtl_read_dword(rtlpriv, macreg[i]);
1567 }
1568
1569 static void _rtl92c_phy_reload_adda_registers(struct ieee80211_hw *hw,
1570                                               u32 *addareg, u32 *addabackup,
1571                                               u32 regiesternum)
1572 {
1573         u32 i;
1574
1575         for (i = 0; i < regiesternum; i++)
1576                 rtl_set_bbreg(hw, addareg[i], MASKDWORD, addabackup[i]);
1577 }
1578
1579 static void _rtl92c_phy_reload_mac_registers(struct ieee80211_hw *hw,
1580                                              u32 *macreg, u32 *macbackup)
1581 {
1582         struct rtl_priv *rtlpriv = rtl_priv(hw);
1583         u32 i;
1584
1585         for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1586                 rtl_write_byte(rtlpriv, macreg[i], (u8) macbackup[i]);
1587         rtl_write_dword(rtlpriv, macreg[i], macbackup[i]);
1588 }
1589
1590 static void _rtl92c_phy_path_adda_on(struct ieee80211_hw *hw,
1591                                      u32 *addareg, bool is_patha_on, bool is2t)
1592 {
1593         u32 pathOn;
1594         u32 i;
1595
1596         pathOn = is_patha_on ? 0x04db25a4 : 0x0b1b25a4;
1597         if (false == is2t) {
1598                 pathOn = 0x0bdb25a0;
1599                 rtl_set_bbreg(hw, addareg[0], MASKDWORD, 0x0b1b25a0);
1600         } else {
1601                 rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathOn);
1602         }
1603
1604         for (i = 1; i < IQK_ADDA_REG_NUM; i++)
1605                 rtl_set_bbreg(hw, addareg[i], MASKDWORD, pathOn);
1606 }
1607
1608 static void _rtl92c_phy_mac_setting_calibration(struct ieee80211_hw *hw,
1609                                                 u32 *macreg, u32 *macbackup)
1610 {
1611         struct rtl_priv *rtlpriv = rtl_priv(hw);
1612         u32 i;
1613
1614         rtl_write_byte(rtlpriv, macreg[0], 0x3F);
1615
1616         for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++)
1617                 rtl_write_byte(rtlpriv, macreg[i],
1618                                (u8) (macbackup[i] & (~BIT(3))));
1619         rtl_write_byte(rtlpriv, macreg[i], (u8) (macbackup[i] & (~BIT(5))));
1620 }
1621
1622 static void _rtl92c_phy_path_a_standby(struct ieee80211_hw *hw)
1623 {
1624         rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0);
1625         rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000);
1626         rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1627 }
1628
1629 static void _rtl92c_phy_pi_mode_switch(struct ieee80211_hw *hw, bool pi_mode)
1630 {
1631         u32 mode;
1632
1633         mode = pi_mode ? 0x01000100 : 0x01000000;
1634         rtl_set_bbreg(hw, 0x820, MASKDWORD, mode);
1635         rtl_set_bbreg(hw, 0x828, MASKDWORD, mode);
1636 }
1637
1638 static bool _rtl92c_phy_simularity_compare(struct ieee80211_hw *hw,
1639                                            long result[][8], u8 c1, u8 c2)
1640 {
1641         u32 i, j, diff, simularity_bitmap, bound;
1642         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1643
1644         u8 final_candidate[2] = { 0xFF, 0xFF };
1645         bool bresult = true, is2t = IS_92C_SERIAL(rtlhal->version);
1646
1647         if (is2t)
1648                 bound = 8;
1649         else
1650                 bound = 4;
1651
1652         simularity_bitmap = 0;
1653
1654         for (i = 0; i < bound; i++) {
1655                 diff = (result[c1][i] > result[c2][i]) ?
1656                     (result[c1][i] - result[c2][i]) :
1657                     (result[c2][i] - result[c1][i]);
1658
1659                 if (diff > MAX_TOLERANCE) {
1660                         if ((i == 2 || i == 6) && !simularity_bitmap) {
1661                                 if (result[c1][i] + result[c1][i + 1] == 0)
1662                                         final_candidate[(i / 4)] = c2;
1663                                 else if (result[c2][i] + result[c2][i + 1] == 0)
1664                                         final_candidate[(i / 4)] = c1;
1665                                 else
1666                                         simularity_bitmap = simularity_bitmap |
1667                                             (1 << i);
1668                         } else
1669                                 simularity_bitmap =
1670                                     simularity_bitmap | (1 << i);
1671                 }
1672         }
1673
1674         if (simularity_bitmap == 0) {
1675                 for (i = 0; i < (bound / 4); i++) {
1676                         if (final_candidate[i] != 0xFF) {
1677                                 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
1678                                         result[3][j] =
1679                                             result[final_candidate[i]][j];
1680                                 bresult = false;
1681                         }
1682                 }
1683                 return bresult;
1684         } else if (!(simularity_bitmap & 0x0F)) {
1685                 for (i = 0; i < 4; i++)
1686                         result[3][i] = result[c1][i];
1687                 return false;
1688         } else if (!(simularity_bitmap & 0xF0) && is2t) {
1689                 for (i = 4; i < 8; i++)
1690                         result[3][i] = result[c1][i];
1691                 return false;
1692         } else {
1693                 return false;
1694         }
1695
1696 }
1697
1698 static void _rtl92c_phy_iq_calibrate(struct ieee80211_hw *hw,
1699                                      long result[][8], u8 t, bool is2t)
1700 {
1701         struct rtl_priv *rtlpriv = rtl_priv(hw);
1702         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1703         u32 i;
1704         u8 patha_ok, pathb_ok;
1705         u32 adda_reg[IQK_ADDA_REG_NUM] = {
1706                 0x85c, 0xe6c, 0xe70, 0xe74,
1707                 0xe78, 0xe7c, 0xe80, 0xe84,
1708                 0xe88, 0xe8c, 0xed0, 0xed4,
1709                 0xed8, 0xedc, 0xee0, 0xeec
1710         };
1711
1712         u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
1713                 0x522, 0x550, 0x551, 0x040
1714         };
1715
1716         const u32 retrycount = 2;
1717
1718         u32 bbvalue;
1719
1720         if (t == 0) {
1721                 bbvalue = rtl_get_bbreg(hw, 0x800, MASKDWORD);
1722
1723                 _rtl92c_phy_save_adda_registers(hw, adda_reg,
1724                                                 rtlphy->adda_backup, 16);
1725                 _rtl92c_phy_save_mac_registers(hw, iqk_mac_reg,
1726                                                rtlphy->iqk_mac_backup);
1727         }
1728         _rtl92c_phy_path_adda_on(hw, adda_reg, true, is2t);
1729         if (t == 0) {
1730                 rtlphy->b_rfpi_enable = (u8) rtl_get_bbreg(hw,
1731                                                    RFPGA0_XA_HSSIPARAMETER1,
1732                                                    BIT(8));
1733         }
1734         if (!rtlphy->b_rfpi_enable)
1735                 _rtl92c_phy_pi_mode_switch(hw, true);
1736         if (t == 0) {
1737                 rtlphy->reg_c04 = rtl_get_bbreg(hw, 0xc04, MASKDWORD);
1738                 rtlphy->reg_c08 = rtl_get_bbreg(hw, 0xc08, MASKDWORD);
1739                 rtlphy->reg_874 = rtl_get_bbreg(hw, 0x874, MASKDWORD);
1740         }
1741         rtl_set_bbreg(hw, 0xc04, MASKDWORD, 0x03a05600);
1742         rtl_set_bbreg(hw, 0xc08, MASKDWORD, 0x000800e4);
1743         rtl_set_bbreg(hw, 0x874, MASKDWORD, 0x22204000);
1744         if (is2t) {
1745                 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000);
1746                 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00010000);
1747         }
1748         _rtl92c_phy_mac_setting_calibration(hw, iqk_mac_reg,
1749                                             rtlphy->iqk_mac_backup);
1750         rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x00080000);
1751         if (is2t)
1752                 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x00080000);
1753         rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1754         rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00);
1755         rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800);
1756         for (i = 0; i < retrycount; i++) {
1757                 patha_ok = _rtl92c_phy_path_a_iqk(hw, is2t);
1758                 if (patha_ok == 0x03) {
1759                         result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
1760                                         0x3FF0000) >> 16;
1761                         result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
1762                                         0x3FF0000) >> 16;
1763                         result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) &
1764                                         0x3FF0000) >> 16;
1765                         result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) &
1766                                         0x3FF0000) >> 16;
1767                         break;
1768                 } else if (i == (retrycount - 1) && patha_ok == 0x01)
1769                         result[t][0] = (rtl_get_bbreg(hw, 0xe94,
1770                                                       MASKDWORD) & 0x3FF0000) >>
1771                                                       16;
1772                 result[t][1] =
1773                     (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & 0x3FF0000) >> 16;
1774
1775         }
1776
1777         if (is2t) {
1778                 _rtl92c_phy_path_a_standby(hw);
1779                 _rtl92c_phy_path_adda_on(hw, adda_reg, false, is2t);
1780                 for (i = 0; i < retrycount; i++) {
1781                         pathb_ok = _rtl92c_phy_path_b_iqk(hw);
1782                         if (pathb_ok == 0x03) {
1783                                 result[t][4] = (rtl_get_bbreg(hw,
1784                                                       0xeb4,
1785                                                       MASKDWORD) &
1786                                                 0x3FF0000) >> 16;
1787                                 result[t][5] =
1788                                     (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
1789                                      0x3FF0000) >> 16;
1790                                 result[t][6] =
1791                                     (rtl_get_bbreg(hw, 0xec4, MASKDWORD) &
1792                                      0x3FF0000) >> 16;
1793                                 result[t][7] =
1794                                     (rtl_get_bbreg(hw, 0xecc, MASKDWORD) &
1795                                      0x3FF0000) >> 16;
1796                                 break;
1797                         } else if (i == (retrycount - 1) && pathb_ok == 0x01) {
1798                                 result[t][4] = (rtl_get_bbreg(hw,
1799                                                       0xeb4,
1800                                                       MASKDWORD) &
1801                                                 0x3FF0000) >> 16;
1802                         }
1803                         result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
1804                                         0x3FF0000) >> 16;
1805                 }
1806         }
1807         rtl_set_bbreg(hw, 0xc04, MASKDWORD, rtlphy->reg_c04);
1808         rtl_set_bbreg(hw, 0x874, MASKDWORD, rtlphy->reg_874);
1809         rtl_set_bbreg(hw, 0xc08, MASKDWORD, rtlphy->reg_c08);
1810         rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0);
1811         rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00032ed3);
1812         if (is2t)
1813                 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00032ed3);
1814         if (t != 0) {
1815                 if (!rtlphy->b_rfpi_enable)
1816                         _rtl92c_phy_pi_mode_switch(hw, false);
1817                 _rtl92c_phy_reload_adda_registers(hw, adda_reg,
1818                                                   rtlphy->adda_backup, 16);
1819                 _rtl92c_phy_reload_mac_registers(hw, iqk_mac_reg,
1820                                                  rtlphy->iqk_mac_backup);
1821         }
1822 }
1823
1824 static void _rtl92c_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
1825 {
1826         u8 tmpreg;
1827         u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal;
1828         struct rtl_priv *rtlpriv = rtl_priv(hw);
1829
1830         tmpreg = rtl_read_byte(rtlpriv, 0xd03);
1831
1832         if ((tmpreg & 0x70) != 0)
1833                 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F);
1834         else
1835                 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1836
1837         if ((tmpreg & 0x70) != 0) {
1838                 rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS);
1839
1840                 if (is2t)
1841                         rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00,
1842                                                   MASK12BITS);
1843
1844                 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS,
1845                               (rf_a_mode & 0x8FFFF) | 0x10000);
1846
1847                 if (is2t)
1848                         rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
1849                                       (rf_b_mode & 0x8FFFF) | 0x10000);
1850         }
1851         lc_cal = rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS);
1852
1853         rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, lc_cal | 0x08000);
1854
1855         mdelay(100);
1856
1857         if ((tmpreg & 0x70) != 0) {
1858                 rtl_write_byte(rtlpriv, 0xd03, tmpreg);
1859                 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode);
1860
1861                 if (is2t)
1862                         rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
1863                                       rf_b_mode);
1864         } else {
1865                 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
1866         }
1867 }
1868
1869 static void _rtl92c_phy_ap_calibrate(struct ieee80211_hw *hw,
1870                                      char delta, bool is2t)
1871 {
1872         /* This routine is deliberately dummied out for later fixes */
1873 #if 0
1874         struct rtl_priv *rtlpriv = rtl_priv(hw);
1875         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1876         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1877
1878         u32 reg_d[PATH_NUM];
1879         u32 tmpreg, index, offset, path, i, pathbound = PATH_NUM, apkbound;
1880
1881         u32 bb_backup[APK_BB_REG_NUM];
1882         u32 bb_reg[APK_BB_REG_NUM] = {
1883                 0x904, 0xc04, 0x800, 0xc08, 0x874
1884         };
1885         u32 bb_ap_mode[APK_BB_REG_NUM] = {
1886                 0x00000020, 0x00a05430, 0x02040000,
1887                 0x000800e4, 0x00204000
1888         };
1889         u32 bb_normal_ap_mode[APK_BB_REG_NUM] = {
1890                 0x00000020, 0x00a05430, 0x02040000,
1891                 0x000800e4, 0x22204000
1892         };
1893
1894         u32 afe_backup[APK_AFE_REG_NUM];
1895         u32 afe_reg[APK_AFE_REG_NUM] = {
1896                 0x85c, 0xe6c, 0xe70, 0xe74, 0xe78,
1897                 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c,
1898                 0xed0, 0xed4, 0xed8, 0xedc, 0xee0,
1899                 0xeec
1900         };
1901
1902         u32 mac_backup[IQK_MAC_REG_NUM];
1903         u32 mac_reg[IQK_MAC_REG_NUM] = {
1904                 0x522, 0x550, 0x551, 0x040
1905         };
1906
1907         u32 apk_rf_init_value[PATH_NUM][APK_BB_REG_NUM] = {
1908                 {0x0852c, 0x1852c, 0x5852c, 0x1852c, 0x5852c},
1909                 {0x2852e, 0x0852e, 0x3852e, 0x0852e, 0x0852e}
1910         };
1911
1912         u32 apk_normal_rf_init_value[PATH_NUM][APK_BB_REG_NUM] = {
1913                 {0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c},
1914                 {0x0852c, 0x0a52c, 0x5a52c, 0x5a52c, 0x5a52c}
1915         };
1916
1917         u32 apk_rf_value_0[PATH_NUM][APK_BB_REG_NUM] = {
1918                 {0x52019, 0x52014, 0x52013, 0x5200f, 0x5208d},
1919                 {0x5201a, 0x52019, 0x52016, 0x52033, 0x52050}
1920         };
1921
1922         u32 apk_normal_rf_value_0[PATH_NUM][APK_BB_REG_NUM] = {
1923                 {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a},
1924                 {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}
1925         };
1926
1927         u32 afe_on_off[PATH_NUM] = {
1928                 0x04db25a4, 0x0b1b25a4
1929         };
1930
1931         u32 apk_offset[PATH_NUM] = { 0xb68, 0xb6c };
1932
1933         u32 apk_normal_offset[PATH_NUM] = { 0xb28, 0xb98 };
1934
1935         u32 apk_value[PATH_NUM] = { 0x92fc0000, 0x12fc0000 };
1936
1937         u32 apk_normal_value[PATH_NUM] = { 0x92680000, 0x12680000 };
1938
1939         const char apk_delta_mapping[APK_BB_REG_NUM][13] = {
1940                 {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},
1941                 {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},
1942                 {-6, -4, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},
1943                 {-1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6},
1944                 {-11, -9, -7, -5, -3, -1, 0, 0, 0, 0, 0, 0, 0}
1945         };
1946
1947         const u32 apk_normal_setting_value_1[13] = {
1948                 0x01017018, 0xf7ed8f84, 0x1b1a1816, 0x2522201e, 0x322e2b28,
1949                 0x433f3a36, 0x5b544e49, 0x7b726a62, 0xa69a8f84, 0xdfcfc0b3,
1950                 0x12680000, 0x00880000, 0x00880000
1951         };
1952
1953         const u32 apk_normal_setting_value_2[16] = {
1954                 0x01c7021d, 0x01670183, 0x01000123, 0x00bf00e2, 0x008d00a3,
1955                 0x0068007b, 0x004d0059, 0x003a0042, 0x002b0031, 0x001f0025,
1956                 0x0017001b, 0x00110014, 0x000c000f, 0x0009000b, 0x00070008,
1957                 0x00050006
1958         };
1959
1960         const u32 apk_result[PATH_NUM][APK_BB_REG_NUM];
1961
1962         long bb_offset, delta_v, delta_offset;
1963
1964         if (!is2t)
1965                 pathbound = 1;
1966
1967         for (index = 0; index < PATH_NUM; index++) {
1968                 apk_offset[index] = apk_normal_offset[index];
1969                 apk_value[index] = apk_normal_value[index];
1970                 afe_on_off[index] = 0x6fdb25a4;
1971         }
1972
1973         for (index = 0; index < APK_BB_REG_NUM; index++) {
1974                 for (path = 0; path < pathbound; path++) {
1975                         apk_rf_init_value[path][index] =
1976                             apk_normal_rf_init_value[path][index];
1977                         apk_rf_value_0[path][index] =
1978                             apk_normal_rf_value_0[path][index];
1979                 }
1980                 bb_ap_mode[index] = bb_normal_ap_mode[index];
1981
1982                 apkbound = 6;
1983         }
1984
1985         for (index = 0; index < APK_BB_REG_NUM; index++) {
1986                 if (index == 0)
1987                         continue;
1988                 bb_backup[index] = rtl_get_bbreg(hw, bb_reg[index], MASKDWORD);
1989         }
1990
1991         _rtl92c_phy_save_mac_registers(hw, mac_reg, mac_backup);
1992
1993         _rtl92c_phy_save_adda_registers(hw, afe_reg, afe_backup, 16);
1994
1995         for (path = 0; path < pathbound; path++) {
1996                 if (path == RF90_PATH_A) {
1997                         offset = 0xb00;
1998                         for (index = 0; index < 11; index++) {
1999                                 rtl_set_bbreg(hw, offset, MASKDWORD,
2000                                               apk_normal_setting_value_1
2001                                               [index]);
2002
2003                                 offset += 0x04;
2004                         }
2005
2006                         rtl_set_bbreg(hw, 0xb98, MASKDWORD, 0x12680000);
2007
2008                         offset = 0xb68;
2009                         for (; index < 13; index++) {
2010                                 rtl_set_bbreg(hw, offset, MASKDWORD,
2011                                               apk_normal_setting_value_1
2012                                               [index]);
2013
2014                                 offset += 0x04;
2015                         }
2016
2017                         rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x40000000);
2018
2019                         offset = 0xb00;
2020                         for (index = 0; index < 16; index++) {
2021                                 rtl_set_bbreg(hw, offset, MASKDWORD,
2022                                               apk_normal_setting_value_2
2023                                               [index]);
2024
2025                                 offset += 0x04;
2026                         }
2027                         rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x00000000);
2028                 } else if (path == RF90_PATH_B) {
2029                         offset = 0xb70;
2030                         for (index = 0; index < 10; index++) {
2031                                 rtl_set_bbreg(hw, offset, MASKDWORD,
2032                                               apk_normal_setting_value_1
2033                                               [index]);
2034
2035                                 offset += 0x04;
2036                         }
2037                         rtl_set_bbreg(hw, 0xb28, MASKDWORD, 0x12680000);
2038                         rtl_set_bbreg(hw, 0xb98, MASKDWORD, 0x12680000);
2039
2040                         offset = 0xb68;
2041                         index = 11;
2042                         for (; index < 13; index++) {
2043                                 rtl_set_bbreg(hw, offset, MASKDWORD,
2044                                               apk_normal_setting_value_1
2045                                               [index]);
2046
2047                                 offset += 0x04;
2048                         }
2049
2050                         rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x40000000);
2051
2052                         offset = 0xb60;
2053                         for (index = 0; index < 16; index++) {
2054                                 rtl_set_bbreg(hw, offset, MASKDWORD,
2055                                               apk_normal_setting_value_2
2056                                               [index]);
2057
2058                                 offset += 0x04;
2059                         }
2060                         rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x00000000);
2061                 }
2062
2063                 reg_d[path] = rtl_get_rfreg(hw, (enum radio_path)path,
2064                                             0xd, MASKDWORD);
2065
2066                 for (index = 0; index < APK_AFE_REG_NUM; index++)
2067                         rtl_set_bbreg(hw, afe_reg[index], MASKDWORD,
2068                                       afe_on_off[path]);
2069
2070                 if (path == RF90_PATH_A) {
2071                         for (index = 0; index < APK_BB_REG_NUM; index++) {
2072                                 if (index == 0)
2073                                         continue;
2074                                 rtl_set_bbreg(hw, bb_reg[index], MASKDWORD,
2075                                               bb_ap_mode[index]);
2076                         }
2077                 }
2078
2079                 _rtl92c_phy_mac_setting_calibration(hw, mac_reg, mac_backup);
2080
2081                 if (path == 0) {
2082                         rtl_set_rfreg(hw, RF90_PATH_B, 0x0, MASKDWORD, 0x10000);
2083                 } else {
2084                         rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASKDWORD,
2085                                       0x10000);
2086                         rtl_set_rfreg(hw, RF90_PATH_A, 0x10, MASKDWORD,
2087                                       0x1000f);
2088                         rtl_set_rfreg(hw, RF90_PATH_A, 0x11, MASKDWORD,
2089                                       0x20103);
2090                 }
2091
2092                 delta_offset = ((delta + 14) / 2);
2093                 if (delta_offset < 0)
2094                         delta_offset = 0;
2095                 else if (delta_offset > 12)
2096                         delta_offset = 12;
2097
2098                 for (index = 0; index < APK_BB_REG_NUM; index++) {
2099                         if (index != 1)
2100                                 continue;
2101
2102                         tmpreg = apk_rf_init_value[path][index];
2103
2104                         if (!rtlefuse->b_apk_thermalmeterignore) {
2105                                 bb_offset = (tmpreg & 0xF0000) >> 16;
2106
2107                                 if (!(tmpreg & BIT(15)))
2108                                         bb_offset = -bb_offset;
2109
2110                                 delta_v =
2111                                     apk_delta_mapping[index][delta_offset];
2112
2113                                 bb_offset += delta_v;
2114
2115                                 if (bb_offset < 0) {
2116                                         tmpreg = tmpreg & (~BIT(15));
2117                                         bb_offset = -bb_offset;
2118                                 } else {
2119                                         tmpreg = tmpreg | BIT(15);
2120                                 }
2121
2122                                 tmpreg =
2123                                     (tmpreg & 0xFFF0FFFF) | (bb_offset << 16);
2124                         }
2125
2126                         rtl_set_rfreg(hw, (enum radio_path)path, 0xc,
2127                                       MASKDWORD, 0x8992e);
2128                         rtl_set_rfreg(hw, (enum radio_path)path, 0x0,
2129                                       MASKDWORD, apk_rf_value_0[path][index]);
2130                         rtl_set_rfreg(hw, (enum radio_path)path, 0xd,
2131                                       MASKDWORD, tmpreg);
2132
2133                         i = 0;
2134                         do {
2135                                 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80000000);
2136                                 rtl_set_bbreg(hw, apk_offset[path],
2137                                               MASKDWORD, apk_value[0]);
2138                                 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2139                                         ("PHY_APCalibrate() offset 0x%x "
2140                                          "value 0x%x\n",
2141                                          apk_offset[path],
2142                                          rtl_get_bbreg(hw, apk_offset[path],
2143                                                        MASKDWORD)));
2144
2145                                 mdelay(3);
2146
2147                                 rtl_set_bbreg(hw, apk_offset[path],
2148                                               MASKDWORD, apk_value[1]);
2149                                 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2150                                         ("PHY_APCalibrate() offset 0x%x "
2151                                          "value 0x%x\n",
2152                                          apk_offset[path],
2153                                          rtl_get_bbreg(hw, apk_offset[path],
2154                                                        MASKDWORD)));
2155
2156                                 mdelay(20);
2157
2158                                 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x00000000);
2159
2160                                 if (path == RF90_PATH_A)
2161                                         tmpreg = rtl_get_bbreg(hw, 0xbd8,
2162                                                                0x03E00000);
2163                                 else
2164                                         tmpreg = rtl_get_bbreg(hw, 0xbd8,
2165                                                                0xF8000000);
2166
2167                                 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2168                                         ("PHY_APCalibrate() offset "
2169                                          "0xbd8[25:21] %x\n", tmpreg));
2170
2171                                 i++;
2172
2173                         } while (tmpreg > apkbound && i < 4);
2174
2175                         apk_result[path][index] = tmpreg;
2176                 }
2177         }
2178
2179         _rtl92c_phy_reload_mac_registers(hw, mac_reg, mac_backup);
2180
2181         for (index = 0; index < APK_BB_REG_NUM; index++) {
2182                 if (index == 0)
2183                         continue;
2184                 rtl_set_bbreg(hw, bb_reg[index], MASKDWORD, bb_backup[index]);
2185         }
2186
2187         _rtl92c_phy_reload_adda_registers(hw, afe_reg, afe_backup, 16);
2188
2189         for (path = 0; path < pathbound; path++) {
2190                 rtl_set_rfreg(hw, (enum radio_path)path, 0xd,
2191                               MASKDWORD, reg_d[path]);
2192
2193                 if (path == RF90_PATH_B) {
2194                         rtl_set_rfreg(hw, RF90_PATH_A, 0x10, MASKDWORD,
2195                                       0x1000f);
2196                         rtl_set_rfreg(hw, RF90_PATH_A, 0x11, MASKDWORD,
2197                                       0x20101);
2198                 }
2199
2200                 if (apk_result[path][1] > 6)
2201                         apk_result[path][1] = 6;
2202         }
2203
2204         for (path = 0; path < pathbound; path++) {
2205                 rtl_set_rfreg(hw, (enum radio_path)path, 0x3, MASKDWORD,
2206                               ((apk_result[path][1] << 15) |
2207                                (apk_result[path][1] << 10) |
2208                                (apk_result[path][1] << 5) |
2209                                apk_result[path][1]));
2210
2211                 if (path == RF90_PATH_A)
2212                         rtl_set_rfreg(hw, (enum radio_path)path, 0x4, MASKDWORD,
2213                                       ((apk_result[path][1] << 15) |
2214                                        (apk_result[path][1] << 10) |
2215                                        (0x00 << 5) | 0x05));
2216                 else
2217                         rtl_set_rfreg(hw, (enum radio_path)path, 0x4, MASKDWORD,
2218                                       ((apk_result[path][1] << 15) |
2219                                        (apk_result[path][1] << 10) |
2220                                        (0x02 << 5) | 0x05));
2221
2222                 rtl_set_rfreg(hw, (enum radio_path)path, 0xe, MASKDWORD,
2223                               ((0x08 << 15) | (0x08 << 10) | (0x08 << 5) |
2224                                0x08));
2225
2226         }
2227
2228         rtlphy->b_apk_done = true;
2229 #endif
2230 }
2231
2232 static void _rtl92c_phy_set_rfpath_switch(struct ieee80211_hw *hw,
2233                                           bool bmain, bool is2t)
2234 {
2235         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2236
2237         if (is_hal_stop(rtlhal)) {
2238                 rtl_set_bbreg(hw, REG_LEDCFG0, BIT(23), 0x01);
2239                 rtl_set_bbreg(hw, rFPGA0_XAB_RFPARAMETER, BIT(13), 0x01);
2240         }
2241         if (is2t) {
2242                 if (bmain)
2243                         rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
2244                                       BIT(5) | BIT(6), 0x1);
2245                 else
2246                         rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
2247                                       BIT(5) | BIT(6), 0x2);
2248         } else {
2249                 if (bmain)
2250                         rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300, 0x2);
2251                 else
2252                         rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300, 0x1);
2253
2254         }
2255 }
2256
2257 #undef IQK_ADDA_REG_NUM
2258 #undef IQK_DELAY_TIME
2259
2260 void rtl92c_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery)
2261 {
2262         struct rtl_priv *rtlpriv = rtl_priv(hw);
2263         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2264         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2265
2266         long result[4][8];
2267         u8 i, final_candidate;
2268         bool b_patha_ok, b_pathb_ok;
2269         long reg_e94, reg_e9c, reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4,
2270             reg_ecc, reg_tmp = 0;
2271         bool is12simular, is13simular, is23simular;
2272         bool b_start_conttx = false, b_singletone = false;
2273         u32 iqk_bb_reg[10] = {
2274                 ROFDM0_XARXIQIMBALANCE,
2275                 ROFDM0_XBRXIQIMBALANCE,
2276                 ROFDM0_ECCATHRESHOLD,
2277                 ROFDM0_AGCRSSITABLE,
2278                 ROFDM0_XATXIQIMBALANCE,
2279                 ROFDM0_XBTXIQIMBALANCE,
2280                 ROFDM0_XCTXIQIMBALANCE,
2281                 ROFDM0_XCTXAFE,
2282                 ROFDM0_XDTXAFE,
2283                 ROFDM0_RXIQEXTANTA
2284         };
2285
2286         if (b_recovery) {
2287                 _rtl92c_phy_reload_adda_registers(hw,
2288                                                   iqk_bb_reg,
2289                                                   rtlphy->iqk_bb_backup, 10);
2290                 return;
2291         }
2292         if (b_start_conttx || b_singletone)
2293                 return;
2294         for (i = 0; i < 8; i++) {
2295                 result[0][i] = 0;
2296                 result[1][i] = 0;
2297                 result[2][i] = 0;
2298                 result[3][i] = 0;
2299         }
2300         final_candidate = 0xff;
2301         b_patha_ok = false;
2302         b_pathb_ok = false;
2303         is12simular = false;
2304         is23simular = false;
2305         is13simular = false;
2306         for (i = 0; i < 3; i++) {
2307                 if (IS_92C_SERIAL(rtlhal->version))
2308                         _rtl92c_phy_iq_calibrate(hw, result, i, true);
2309                 else
2310                         _rtl92c_phy_iq_calibrate(hw, result, i, false);
2311                 if (i == 1) {
2312                         is12simular = _rtl92c_phy_simularity_compare(hw,
2313                                                                      result, 0,
2314                                                                      1);
2315                         if (is12simular) {
2316                                 final_candidate = 0;
2317                                 break;
2318                         }
2319                 }
2320                 if (i == 2) {
2321                         is13simular = _rtl92c_phy_simularity_compare(hw,
2322                                                                      result, 0,
2323                                                                      2);
2324                         if (is13simular) {
2325                                 final_candidate = 0;
2326                                 break;
2327                         }
2328                         is23simular = _rtl92c_phy_simularity_compare(hw,
2329                                                                      result, 1,
2330                                                                      2);
2331                         if (is23simular)
2332                                 final_candidate = 1;
2333                         else {
2334                                 for (i = 0; i < 8; i++)
2335                                         reg_tmp += result[3][i];
2336
2337                                 if (reg_tmp != 0)
2338                                         final_candidate = 3;
2339                                 else
2340                                         final_candidate = 0xFF;
2341                         }
2342                 }
2343         }
2344         for (i = 0; i < 4; i++) {
2345                 reg_e94 = result[i][0];
2346                 reg_e9c = result[i][1];
2347                 reg_ea4 = result[i][2];
2348                 reg_eac = result[i][3];
2349                 reg_eb4 = result[i][4];
2350                 reg_ebc = result[i][5];
2351                 reg_ec4 = result[i][6];
2352                 reg_ecc = result[i][7];
2353         }
2354         if (final_candidate != 0xff) {
2355                 rtlphy->reg_e94 = reg_e94 = result[final_candidate][0];
2356                 rtlphy->reg_e9c = reg_e9c = result[final_candidate][1];
2357                 reg_ea4 = result[final_candidate][2];
2358                 reg_eac = result[final_candidate][3];
2359                 rtlphy->reg_eb4 = reg_eb4 = result[final_candidate][4];
2360                 rtlphy->reg_ebc = reg_ebc = result[final_candidate][5];
2361                 reg_ec4 = result[final_candidate][6];
2362                 reg_ecc = result[final_candidate][7];
2363                 b_patha_ok = b_pathb_ok = true;
2364         } else {
2365                 rtlphy->reg_e94 = rtlphy->reg_eb4 = 0x100;
2366                 rtlphy->reg_e9c = rtlphy->reg_ebc = 0x0;
2367         }
2368         if (reg_e94 != 0) /*&&(reg_ea4 != 0) */
2369                 _rtl92c_phy_path_a_fill_iqk_matrix(hw, b_patha_ok, result,
2370                                                    final_candidate,
2371                                                    (reg_ea4 == 0));
2372         if (IS_92C_SERIAL(rtlhal->version)) {
2373                 if (reg_eb4 != 0) /*&&(reg_ec4 != 0) */
2374                         _rtl92c_phy_path_b_fill_iqk_matrix(hw, b_pathb_ok,
2375                                                            result,
2376                                                            final_candidate,
2377                                                            (reg_ec4 == 0));
2378         }
2379         _rtl92c_phy_save_adda_registers(hw, iqk_bb_reg,
2380                                         rtlphy->iqk_bb_backup, 10);
2381 }
2382
2383 void rtl92c_phy_lc_calibrate(struct ieee80211_hw *hw)
2384 {
2385         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2386         bool b_start_conttx = false, b_singletone = false;
2387
2388         if (b_start_conttx || b_singletone)
2389                 return;
2390         if (IS_92C_SERIAL(rtlhal->version))
2391                 _rtl92c_phy_lc_calibrate(hw, true);
2392         else
2393                 _rtl92c_phy_lc_calibrate(hw, false);
2394 }
2395
2396 void rtl92c_phy_ap_calibrate(struct ieee80211_hw *hw, char delta)
2397 {
2398         struct rtl_priv *rtlpriv = rtl_priv(hw);
2399         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2400         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2401
2402         if (rtlphy->b_apk_done)
2403                 return;
2404         if (IS_92C_SERIAL(rtlhal->version))
2405                 _rtl92c_phy_ap_calibrate(hw, delta, true);
2406         else
2407                 _rtl92c_phy_ap_calibrate(hw, delta, false);
2408 }
2409
2410 void rtl92c_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain)
2411 {
2412         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2413
2414         if (IS_92C_SERIAL(rtlhal->version))
2415                 _rtl92c_phy_set_rfpath_switch(hw, bmain, true);
2416         else
2417                 _rtl92c_phy_set_rfpath_switch(hw, bmain, false);
2418 }
2419
2420 bool rtl92c_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
2421 {
2422         struct rtl_priv *rtlpriv = rtl_priv(hw);
2423         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2424         bool b_postprocessing = false;
2425
2426         RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2427                  ("-->IO Cmd(%#x), set_io_inprogress(%d)\n",
2428                   iotype, rtlphy->set_io_inprogress));
2429         do {
2430                 switch (iotype) {
2431                 case IO_CMD_RESUME_DM_BY_SCAN:
2432                         RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2433                                  ("[IO CMD] Resume DM after scan.\n"));
2434                         b_postprocessing = true;
2435                         break;
2436                 case IO_CMD_PAUSE_DM_BY_SCAN:
2437                         RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2438                                  ("[IO CMD] Pause DM before scan.\n"));
2439                         b_postprocessing = true;
2440                         break;
2441                 default:
2442                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2443                                  ("switch case not process\n"));
2444                         break;
2445                 }
2446         } while (false);
2447         if (b_postprocessing && !rtlphy->set_io_inprogress) {
2448                 rtlphy->set_io_inprogress = true;
2449                 rtlphy->current_io_type = iotype;
2450         } else {
2451                 return false;
2452         }
2453         rtl92c_phy_set_io(hw);
2454         RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, ("<--IO Type(%#x)\n", iotype));
2455         return true;
2456 }
2457
2458 void rtl92c_phy_set_io(struct ieee80211_hw *hw)
2459 {
2460         struct rtl_priv *rtlpriv = rtl_priv(hw);
2461         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2462
2463         RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2464                  ("--->Cmd(%#x), set_io_inprogress(%d)\n",
2465                   rtlphy->current_io_type, rtlphy->set_io_inprogress));
2466         switch (rtlphy->current_io_type) {
2467         case IO_CMD_RESUME_DM_BY_SCAN:
2468                 dm_digtable.cur_igvalue = rtlphy->initgain_backup.xaagccore1;
2469                 rtl92c_dm_write_dig(hw);
2470                 rtl92c_phy_set_txpower_level(hw, rtlphy->current_channel);
2471                 break;
2472         case IO_CMD_PAUSE_DM_BY_SCAN:
2473                 rtlphy->initgain_backup.xaagccore1 = dm_digtable.cur_igvalue;
2474                 dm_digtable.cur_igvalue = 0x17;
2475                 rtl92c_dm_write_dig(hw);
2476                 break;
2477         default:
2478                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2479                          ("switch case not process\n"));
2480                 break;
2481         }
2482         rtlphy->set_io_inprogress = false;
2483         RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2484                  ("<---(%#x)\n", rtlphy->current_io_type));
2485 }
2486
2487 void rtl92ce_phy_set_rf_on(struct ieee80211_hw *hw)
2488 {
2489         struct rtl_priv *rtlpriv = rtl_priv(hw);
2490
2491         rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
2492         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
2493         rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
2494         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
2495         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
2496         rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
2497 }
2498
2499 static void _rtl92ce_phy_set_rf_sleep(struct ieee80211_hw *hw)
2500 {
2501         u32 u4b_tmp;
2502         u8 delay = 5;
2503         struct rtl_priv *rtlpriv = rtl_priv(hw);
2504
2505         rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
2506         rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
2507         rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
2508         u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
2509         while (u4b_tmp != 0 && delay > 0) {
2510                 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0);
2511                 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
2512                 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
2513                 u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
2514                 delay--;
2515         }
2516         if (delay == 0) {
2517                 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
2518                 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
2519                 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
2520                 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
2521                 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
2522                          ("Switch RF timeout !!!.\n"));
2523                 return;
2524         }
2525         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
2526         rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22);
2527 }
2528
2529 static bool _rtl92ce_phy_set_rf_power_state(struct ieee80211_hw *hw,
2530                                             enum rf_pwrstate rfpwr_state)
2531 {
2532         struct rtl_priv *rtlpriv = rtl_priv(hw);
2533         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2534         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2535         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2536         bool bresult = true;
2537         u8 i, queue_id;
2538         struct rtl8192_tx_ring *ring = NULL;
2539
2540         ppsc->set_rfpowerstate_inprogress = true;
2541         switch (rfpwr_state) {
2542         case ERFON:{
2543                         if ((ppsc->rfpwr_state == ERFOFF) &&
2544                             RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
2545                                 bool rtstatus;
2546                                 u32 InitializeCount = 0;
2547                                 do {
2548                                         InitializeCount++;
2549                                         RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2550                                                  ("IPS Set eRf nic enable\n"));
2551                                         rtstatus = rtl_ps_enable_nic(hw);
2552                                 } while ((rtstatus != true)
2553                                          && (InitializeCount < 10));
2554                                 RT_CLEAR_PS_LEVEL(ppsc,
2555                                                   RT_RF_OFF_LEVL_HALT_NIC);
2556                         } else {
2557                                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2558                                          ("Set ERFON sleeped:%d ms\n",
2559                                           jiffies_to_msecs(jiffies -
2560                                                    ppsc->
2561                                                    last_sleep_jiffies)));
2562                                 ppsc->last_awake_jiffies = jiffies;
2563                                 rtl92ce_phy_set_rf_on(hw);
2564                         }
2565                         if (mac->link_state == MAC80211_LINKED) {
2566                                 rtlpriv->cfg->ops->led_control(hw,
2567                                                                LED_CTL_LINK);
2568                         } else {
2569                                 rtlpriv->cfg->ops->led_control(hw,
2570                                                                LED_CTL_NO_LINK);
2571                         }
2572                         break;
2573                 }
2574         case ERFOFF:{
2575                         for (queue_id = 0, i = 0;
2576                              queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
2577                                 ring = &pcipriv->dev.tx_ring[queue_id];
2578                                 if (skb_queue_len(&ring->queue) == 0 ||
2579                                     queue_id == BEACON_QUEUE) {
2580                                         queue_id++;
2581                                         continue;
2582                                 } else {
2583                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2584                                                  ("eRf Off/Sleep: %d times "
2585                                                   "TcbBusyQueue[%d] "
2586                                                   "=%d before doze!\n", (i + 1),
2587                                                   queue_id,
2588                                                   skb_queue_len(&ring->queue)));
2589                                         udelay(10);
2590                                         i++;
2591                                 }
2592                                 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
2593                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2594                                                  ("\nERFOFF: %d times "
2595                                                   "TcbBusyQueue[%d] = %d !\n",
2596                                                   MAX_DOZE_WAITING_TIMES_9x,
2597                                                   queue_id,
2598                                                   skb_queue_len(&ring->queue)));
2599                                         break;
2600                                 }
2601                         }
2602                         if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
2603                                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2604                                          ("IPS Set eRf nic disable\n"));
2605                                 rtl_ps_disable_nic(hw);
2606                                 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2607                         } else {
2608                                 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) {
2609                                         rtlpriv->cfg->ops->led_control(hw,
2610                                                                LED_CTL_NO_LINK);
2611                                 } else {
2612                                         rtlpriv->cfg->ops->led_control(hw,
2613                                                              LED_CTL_POWER_OFF);
2614                                 }
2615                         }
2616                         break;
2617                 }
2618         case ERFSLEEP:{
2619                         if (ppsc->rfpwr_state == ERFOFF)
2620                                 break;
2621                         for (queue_id = 0, i = 0;
2622                              queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
2623                                 ring = &pcipriv->dev.tx_ring[queue_id];
2624                                 if (skb_queue_len(&ring->queue) == 0) {
2625                                         queue_id++;
2626                                         continue;
2627                                 } else {
2628                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2629                                                  ("eRf Off/Sleep: %d times "
2630                                                   "TcbBusyQueue[%d] =%d before "
2631                                                   "doze!\n", (i + 1), queue_id,
2632                                                   skb_queue_len(&ring->queue)));
2633                                         udelay(10);
2634                                         i++;
2635                                 }
2636                                 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
2637                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2638                                                  ("\n ERFSLEEP: %d times "
2639                                                   "TcbBusyQueue[%d] = %d !\n",
2640                                                   MAX_DOZE_WAITING_TIMES_9x,
2641                                                   queue_id,
2642                                                   skb_queue_len(&ring->queue)));
2643                                         break;
2644                                 }
2645                         }
2646                         RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2647                                  ("Set ERFSLEEP awaked:%d ms\n",
2648                                   jiffies_to_msecs(jiffies -
2649                                                    ppsc->last_awake_jiffies)));
2650                         ppsc->last_sleep_jiffies = jiffies;
2651                         _rtl92ce_phy_set_rf_sleep(hw);
2652                         break;
2653                 }
2654         default:
2655                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2656                          ("switch case not process\n"));
2657                 bresult = false;
2658                 break;
2659         }
2660         if (bresult)
2661                 ppsc->rfpwr_state = rfpwr_state;
2662         ppsc->set_rfpowerstate_inprogress = false;
2663         return bresult;
2664 }
2665
2666 bool rtl92c_phy_set_rf_power_state(struct ieee80211_hw *hw,
2667                                    enum rf_pwrstate rfpwr_state)
2668 {
2669         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2670         bool bresult = false;
2671
2672         if (rfpwr_state == ppsc->rfpwr_state)
2673                 return bresult;
2674         bresult = _rtl92ce_phy_set_rf_power_state(hw, rfpwr_state);
2675         return bresult;
2676 }