1 /******************************************************************************
3 * Copyright(c) 2009-2010 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
26 * Larry Finger <Larry.Finger@lwfinger.net>
28 *****************************************************************************/
37 static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = {
44 static const u8 ac_to_hwq[] = {
51 static u8 _rtl_mac_to_hwqueue(struct ieee80211_hw *hw,
54 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
55 __le16 fc = rtl_get_fc(skb);
56 u8 queue_index = skb_get_queue_mapping(skb);
58 if (unlikely(ieee80211_is_beacon(fc)))
60 if (ieee80211_is_mgmt(fc))
62 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
63 if (ieee80211_is_nullfunc(fc))
66 return ac_to_hwq[queue_index];
69 /* Update PCI dependent default settings*/
70 static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw)
72 struct rtl_priv *rtlpriv = rtl_priv(hw);
73 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
74 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
75 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
76 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
79 ppsc->reg_rfps_level = 0;
80 ppsc->support_aspm = 0;
82 /*Update PCI ASPM setting */
83 ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm;
84 switch (rtlpci->const_pci_aspm) {
90 /*ASPM dynamically enabled/disable. */
91 ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM;
95 /*ASPM with Clock Req dynamically enabled/disable. */
96 ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM |
97 RT_RF_OFF_LEVL_CLK_REQ);
102 * Always enable ASPM and Clock Req
103 * from initialization to halt.
105 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM);
106 ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM |
107 RT_RF_OFF_LEVL_CLK_REQ);
112 * Always enable ASPM without Clock Req
113 * from initialization to halt.
115 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM |
116 RT_RF_OFF_LEVL_CLK_REQ);
117 ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM;
121 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
123 /*Update Radio OFF setting */
124 switch (rtlpci->const_hwsw_rfoff_d3) {
126 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
127 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
131 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
132 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
133 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
137 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3;
141 /*Set HW definition to determine if it supports ASPM. */
142 switch (rtlpci->const_support_pciaspm) {
144 /*Not support ASPM. */
145 bool support_aspm = false;
146 ppsc->support_aspm = support_aspm;
151 bool support_aspm = true;
152 bool support_backdoor = true;
153 ppsc->support_aspm = support_aspm;
155 /*if (priv->oem_id == RT_CID_TOSHIBA &&
156 !priv->ndis_adapter.amd_l1_patch)
157 support_backdoor = false; */
159 ppsc->support_backdoor = support_backdoor;
164 /*ASPM value set by chipset. */
165 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) {
166 bool support_aspm = true;
167 ppsc->support_aspm = support_aspm;
171 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
172 ("switch case not process\n"));
176 /* toshiba aspm issue, toshiba will set aspm selfly
177 * so we should not set aspm in driver */
178 pci_read_config_byte(rtlpci->pdev, 0x80, &init_aspm);
179 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8192SE &&
181 ppsc->support_aspm = false;
184 static bool _rtl_pci_platform_switch_device_pci_aspm(
185 struct ieee80211_hw *hw,
188 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
189 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
191 if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE)
194 pci_write_config_byte(rtlpci->pdev, 0x80, value);
199 /*When we set 0x01 to enable clk request. Set 0x0 to disable clk req.*/
200 static bool _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u8 value)
202 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
203 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
205 pci_write_config_byte(rtlpci->pdev, 0x81, value);
207 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
213 /*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/
214 static void rtl_pci_disable_aspm(struct ieee80211_hw *hw)
216 struct rtl_priv *rtlpriv = rtl_priv(hw);
217 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
218 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
219 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
220 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
221 u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
222 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
223 /*Retrieve original configuration settings. */
224 u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg;
225 u16 pcibridge_linkctrlreg = pcipriv->ndis_adapter.
226 pcibridge_linkctrlreg;
230 if (!ppsc->support_aspm)
233 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
234 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
235 ("PCI(Bridge) UNKNOWN.\n"));
240 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
241 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
242 _rtl_pci_switch_clk_req(hw, 0x0);
245 /*for promising device will in L0 state after an I/O. */
246 pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b);
248 /*Set corresponding value. */
249 aspmlevel |= BIT(0) | BIT(1);
250 linkctrl_reg &= ~aspmlevel;
251 pcibridge_linkctrlreg &= ~(BIT(0) | BIT(1));
253 _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg);
256 /*4 Disable Pci Bridge ASPM */
257 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
258 pcicfg_addrport + (num4bytes << 2));
259 rtl_pci_raw_write_port_uchar(PCI_CONF_DATA, pcibridge_linkctrlreg);
265 *Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for
266 *power saving We should follow the sequence to enable
267 *RTL8192SE first then enable Pci Bridge ASPM
268 *or the system will show bluescreen.
270 static void rtl_pci_enable_aspm(struct ieee80211_hw *hw)
272 struct rtl_priv *rtlpriv = rtl_priv(hw);
273 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
274 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
275 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
276 u8 pcibridge_busnum = pcipriv->ndis_adapter.pcibridge_busnum;
277 u8 pcibridge_devnum = pcipriv->ndis_adapter.pcibridge_devnum;
278 u8 pcibridge_funcnum = pcipriv->ndis_adapter.pcibridge_funcnum;
279 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
280 u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
281 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
283 u8 u_pcibridge_aspmsetting;
284 u8 u_device_aspmsetting;
286 if (!ppsc->support_aspm)
289 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
290 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
291 ("PCI(Bridge) UNKNOWN.\n"));
295 /*4 Enable Pci Bridge ASPM */
296 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
297 pcicfg_addrport + (num4bytes << 2));
299 u_pcibridge_aspmsetting =
300 pcipriv->ndis_adapter.pcibridge_linkctrlreg |
301 rtlpci->const_hostpci_aspm_setting;
303 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL)
304 u_pcibridge_aspmsetting &= ~BIT(0);
306 rtl_pci_raw_write_port_uchar(PCI_CONF_DATA, u_pcibridge_aspmsetting);
308 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
309 ("PlatformEnableASPM():PciBridge busnumber[%x], "
310 "DevNumbe[%x], funcnumber[%x], Write reg[%x] = %x\n",
311 pcibridge_busnum, pcibridge_devnum, pcibridge_funcnum,
312 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10),
313 u_pcibridge_aspmsetting));
317 /*Get ASPM level (with/without Clock Req) */
318 aspmlevel = rtlpci->const_devicepci_aspm_setting;
319 u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg;
321 /*_rtl_pci_platform_switch_device_pci_aspm(dev,*/
322 /*(priv->ndis_adapter.linkctrl_reg | ASPMLevel)); */
324 u_device_aspmsetting |= aspmlevel;
326 _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting);
328 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
329 _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level &
330 RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0);
331 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
336 static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw)
338 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
339 u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
345 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
346 pcicfg_addrport + 0xE0);
347 rtl_pci_raw_write_port_uchar(PCI_CONF_DATA, 0xA0);
349 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
350 pcicfg_addrport + 0xE0);
351 rtl_pci_raw_read_port_uchar(PCI_CONF_DATA, &offset_e0);
353 if (offset_e0 == 0xA0) {
354 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
355 pcicfg_addrport + 0xE4);
356 rtl_pci_raw_read_port_ulong(PCI_CONF_DATA, &offset_e4);
357 if (offset_e4 & BIT(23))
364 static void rtl_pci_get_linkcontrol_field(struct ieee80211_hw *hw)
366 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
367 u8 capabilityoffset = pcipriv->ndis_adapter.pcibridge_pciehdr_offset;
368 u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
372 num4bbytes = (capabilityoffset + 0x10) / 4;
374 /*Read Link Control Register */
375 rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
376 pcicfg_addrport + (num4bbytes << 2));
377 rtl_pci_raw_read_port_uchar(PCI_CONF_DATA, &linkctrl_reg);
379 pcipriv->ndis_adapter.pcibridge_linkctrlreg = linkctrl_reg;
382 static void rtl_pci_parse_configuration(struct pci_dev *pdev,
383 struct ieee80211_hw *hw)
385 struct rtl_priv *rtlpriv = rtl_priv(hw);
386 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
392 /*Link Control Register */
393 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
394 pci_read_config_byte(pdev, pos + PCI_EXP_LNKCTL, &linkctrl_reg);
395 pcipriv->ndis_adapter.linkctrl_reg = linkctrl_reg;
397 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
398 ("Link Control Register =%x\n",
399 pcipriv->ndis_adapter.linkctrl_reg));
401 pci_read_config_byte(pdev, 0x98, &tmp);
403 pci_write_config_byte(pdev, 0x98, tmp);
406 pci_write_config_byte(pdev, 0x70f, tmp);
409 static void rtl_pci_init_aspm(struct ieee80211_hw *hw)
411 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
413 _rtl_pci_update_default_setting(hw);
415 if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) {
416 /*Always enable ASPM & Clock Req. */
417 rtl_pci_enable_aspm(hw);
418 RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM);
423 static void _rtl_pci_io_handler_init(struct device *dev,
424 struct ieee80211_hw *hw)
426 struct rtl_priv *rtlpriv = rtl_priv(hw);
428 rtlpriv->io.dev = dev;
430 rtlpriv->io.write8_async = pci_write8_async;
431 rtlpriv->io.write16_async = pci_write16_async;
432 rtlpriv->io.write32_async = pci_write32_async;
434 rtlpriv->io.read8_sync = pci_read8_sync;
435 rtlpriv->io.read16_sync = pci_read16_sync;
436 rtlpriv->io.read32_sync = pci_read32_sync;
440 static void _rtl_pci_io_handler_release(struct ieee80211_hw *hw)
444 static bool _rtl_update_earlymode_info(struct ieee80211_hw *hw,
445 struct sk_buff *skb, struct rtl_tcb_desc *tcb_desc, u8 tid)
447 struct rtl_priv *rtlpriv = rtl_priv(hw);
448 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
449 u8 additionlen = FCS_LEN;
450 struct sk_buff *next_skb;
452 /* here open is 4, wep/tkip is 8, aes is 12*/
453 if (info->control.hw_key)
454 additionlen += info->control.hw_key->icv_len;
456 /* The most skb num is 6 */
457 tcb_desc->empkt_num = 0;
458 spin_lock_bh(&rtlpriv->locks.waitq_lock);
459 skb_queue_walk(&rtlpriv->mac80211.skb_waitq[tid], next_skb) {
460 struct ieee80211_tx_info *next_info;
462 next_info = IEEE80211_SKB_CB(next_skb);
463 if (next_info->flags & IEEE80211_TX_CTL_AMPDU) {
464 tcb_desc->empkt_len[tcb_desc->empkt_num] =
465 next_skb->len + additionlen;
466 tcb_desc->empkt_num++;
471 if (skb_queue_is_last(&rtlpriv->mac80211.skb_waitq[tid],
475 if (tcb_desc->empkt_num >= 5)
478 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
483 /* just for early mode now */
484 static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw)
486 struct rtl_priv *rtlpriv = rtl_priv(hw);
487 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
488 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
489 struct sk_buff *skb = NULL;
490 struct ieee80211_tx_info *info = NULL;
491 int tid; /* should be int */
493 if (!rtlpriv->rtlhal.earlymode_enable)
496 /* we juse use em for BE/BK/VI/VO */
497 for (tid = 7; tid >= 0; tid--) {
498 u8 hw_queue = ac_to_hwq[rtl_tid_to_ac(hw, tid)];
499 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
500 while (!mac->act_scanning &&
501 rtlpriv->psc.rfpwr_state == ERFON) {
502 struct rtl_tcb_desc tcb_desc;
503 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
505 spin_lock_bh(&rtlpriv->locks.waitq_lock);
506 if (!skb_queue_empty(&mac->skb_waitq[tid]) &&
507 (ring->entries - skb_queue_len(&ring->queue) > 5)) {
508 skb = skb_dequeue(&mac->skb_waitq[tid]);
510 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
513 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
515 /* Some macaddr can't do early mode. like
516 * multicast/broadcast/no_qos data */
517 info = IEEE80211_SKB_CB(skb);
518 if (info->flags & IEEE80211_TX_CTL_AMPDU)
519 _rtl_update_earlymode_info(hw, skb,
522 rtlpriv->intf_ops->adapter_tx(hw, skb, &tcb_desc);
528 static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio)
530 struct rtl_priv *rtlpriv = rtl_priv(hw);
531 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
533 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
535 while (skb_queue_len(&ring->queue)) {
536 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
538 struct ieee80211_tx_info *info;
542 u8 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) entry, true,
546 *beacon packet will only use the first
547 *descriptor defautly,and the own may not
548 *be cleared by the hardware
552 ring->idx = (ring->idx + 1) % ring->entries;
554 skb = __skb_dequeue(&ring->queue);
555 pci_unmap_single(rtlpci->pdev,
557 get_desc((u8 *) entry, true,
558 HW_DESC_TXBUFF_ADDR),
559 skb->len, PCI_DMA_TODEVICE);
561 /* remove early mode header */
562 if (rtlpriv->rtlhal.earlymode_enable)
563 skb_pull(skb, EM_HDR_LEN);
565 RT_TRACE(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE,
566 ("new ring->idx:%d, "
567 "free: skb_queue_len:%d, free: seq:%x\n",
569 skb_queue_len(&ring->queue),
570 *(u16 *) (skb->data + 22)));
572 if (prio == TXCMD_QUEUE) {
578 /* for sw LPS, just after NULL skb send out, we can
579 * sure AP kown we are sleeped, our we should not let
581 fc = rtl_get_fc(skb);
582 if (ieee80211_is_nullfunc(fc)) {
583 if (ieee80211_has_pm(fc)) {
584 rtlpriv->mac80211.offchan_deley = true;
585 rtlpriv->psc.state_inap = 1;
587 rtlpriv->psc.state_inap = 0;
591 /* update tid tx pkt num */
592 tid = rtl_get_tid(skb);
594 rtlpriv->link_info.tidtx_inperiod[tid]++;
596 info = IEEE80211_SKB_CB(skb);
597 ieee80211_tx_info_clear_status(info);
599 info->flags |= IEEE80211_TX_STAT_ACK;
600 /*info->status.rates[0].count = 1; */
602 ieee80211_tx_status_irqsafe(hw, skb);
604 if ((ring->entries - skb_queue_len(&ring->queue))
607 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
608 ("more desc left, wake"
609 "skb_queue@%d,ring->idx = %d,"
610 "skb_queue_len = 0x%d\n",
612 skb_queue_len(&ring->queue)));
614 ieee80211_wake_queue(hw,
615 skb_get_queue_mapping
622 if (((rtlpriv->link_info.num_rx_inperiod +
623 rtlpriv->link_info.num_tx_inperiod) > 8) ||
624 (rtlpriv->link_info.num_rx_inperiod > 2)) {
629 static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw)
631 struct rtl_priv *rtlpriv = rtl_priv(hw);
632 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
633 int rx_queue_idx = RTL_PCI_RX_MPDU_QUEUE;
635 struct ieee80211_rx_status rx_status = { 0 };
636 unsigned int count = rtlpci->rxringcount;
640 bool unicast = false;
642 struct rtl_stats stats = {
651 struct rtl_rx_desc *pdesc = &rtlpci->rx_ring[rx_queue_idx].desc[
652 rtlpci->rx_ring[rx_queue_idx].idx];
654 struct sk_buff *skb = rtlpci->rx_ring[rx_queue_idx].rx_buf[
655 rtlpci->rx_ring[rx_queue_idx].idx];
657 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
661 /*wait data to be filled by hardware */
664 struct ieee80211_hdr *hdr;
666 struct sk_buff *new_skb = NULL;
668 rtlpriv->cfg->ops->query_rx_desc(hw, &stats,
672 skb_put(skb, rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
676 stats.rx_drvinfo_size + stats.rx_bufshift);
679 *NOTICE This can not be use for mac80211,
680 *this is done in mac80211 code,
681 *if you done here sec DHCP will fail
682 *skb_trim(skb, skb->len - 4);
685 hdr = rtl_get_hdr(skb);
686 fc = rtl_get_fc(skb);
688 /* try for new buffer - if allocation fails, drop
689 * frame and reuse old buffer
691 new_skb = dev_alloc_skb(rtlpci->rxbuffersize);
692 if (unlikely(!new_skb)) {
693 RT_TRACE(rtlpriv, (COMP_INTR | COMP_RECV),
695 ("can't alloc skb for rx\n"));
698 pci_unmap_single(rtlpci->pdev,
699 *((dma_addr_t *) skb->cb),
700 rtlpci->rxbuffersize,
703 if (!stats.crc || !stats.hwerror) {
704 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status,
707 if (is_broadcast_ether_addr(hdr->addr1)) {
709 } else if (is_multicast_ether_addr(hdr->addr1)) {
713 rtlpriv->stats.rxbytesunicast +=
717 rtl_is_special_data(hw, skb, false);
719 if (ieee80211_is_data(fc)) {
720 rtlpriv->cfg->ops->led_control(hw,
729 rtl_swlps_beacon(hw, (void *)skb->data,
731 rtl_recognize_peer(hw, (void *)skb->data,
733 if ((rtlpriv->mac80211.opmode ==
734 NL80211_IFTYPE_AP) &&
735 (rtlpriv->rtlhal.current_bandtype ==
737 (ieee80211_is_beacon(fc) ||
738 ieee80211_is_probe_resp(fc))) {
739 dev_kfree_skb_any(skb);
741 if (unlikely(!rtl_action_proc(hw, skb,
743 dev_kfree_skb_any(skb);
745 struct sk_buff *uskb = NULL;
747 uskb = dev_alloc_skb(skb->len
749 memcpy(IEEE80211_SKB_RXCB(uskb),
752 pdata = (u8 *)skb_put(uskb,
754 memcpy(pdata, skb->data,
756 dev_kfree_skb_any(skb);
758 ieee80211_rx_irqsafe(hw, uskb);
762 dev_kfree_skb_any(skb);
765 if (((rtlpriv->link_info.num_rx_inperiod +
766 rtlpriv->link_info.num_tx_inperiod) > 8) ||
767 (rtlpriv->link_info.num_rx_inperiod > 2)) {
773 rtlpci->rx_ring[rx_queue_idx].rx_buf[rtlpci->
777 *((dma_addr_t *) skb->cb) =
778 pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
779 rtlpci->rxbuffersize,
784 bufferaddress = (*((dma_addr_t *)skb->cb));
786 rtlpriv->cfg->ops->set_desc((u8 *) pdesc, false,
788 (u8 *)&bufferaddress);
789 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false, HW_DESC_RXOWN,
791 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false,
793 (u8 *)&rtlpci->rxbuffersize);
795 if (rtlpci->rx_ring[rx_queue_idx].idx ==
796 rtlpci->rxringcount - 1)
797 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false,
801 rtlpci->rx_ring[rx_queue_idx].idx =
802 (rtlpci->rx_ring[rx_queue_idx].idx + 1) %
808 static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id)
810 struct ieee80211_hw *hw = dev_id;
811 struct rtl_priv *rtlpriv = rtl_priv(hw);
812 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
813 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
818 if (rtlpci->irq_enabled == 0)
821 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
823 /*read ISR: 4/8bytes */
824 rtlpriv->cfg->ops->interrupt_recognized(hw, &inta, &intb);
826 /*Shared IRQ or HW disappared */
827 if (!inta || inta == 0xffff)
830 /*<1> beacon related */
831 if (inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK]) {
832 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
833 ("beacon ok interrupt!\n"));
836 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TBDER])) {
837 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
838 ("beacon err interrupt!\n"));
841 if (inta & rtlpriv->cfg->maps[RTL_IMR_BDOK]) {
842 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
843 ("beacon interrupt!\n"));
846 if (inta & rtlpriv->cfg->maps[RTL_IMR_BcnInt]) {
847 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
848 ("prepare beacon for interrupt!\n"));
849 tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet);
853 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TXFOVW]))
854 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, ("IMR_TXFOVW!\n"));
856 if (inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) {
857 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
858 ("Manage ok interrupt!\n"));
859 _rtl_pci_tx_isr(hw, MGNT_QUEUE);
862 if (inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) {
863 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
864 ("HIGH_QUEUE ok interrupt!\n"));
865 _rtl_pci_tx_isr(hw, HIGH_QUEUE);
868 if (inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) {
869 rtlpriv->link_info.num_tx_inperiod++;
871 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
872 ("BK Tx OK interrupt!\n"));
873 _rtl_pci_tx_isr(hw, BK_QUEUE);
876 if (inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) {
877 rtlpriv->link_info.num_tx_inperiod++;
879 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
880 ("BE TX OK interrupt!\n"));
881 _rtl_pci_tx_isr(hw, BE_QUEUE);
884 if (inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) {
885 rtlpriv->link_info.num_tx_inperiod++;
887 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
888 ("VI TX OK interrupt!\n"));
889 _rtl_pci_tx_isr(hw, VI_QUEUE);
892 if (inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) {
893 rtlpriv->link_info.num_tx_inperiod++;
895 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
896 ("Vo TX OK interrupt!\n"));
897 _rtl_pci_tx_isr(hw, VO_QUEUE);
900 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) {
901 if (inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) {
902 rtlpriv->link_info.num_tx_inperiod++;
904 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
905 ("CMD TX OK interrupt!\n"));
906 _rtl_pci_tx_isr(hw, TXCMD_QUEUE);
911 if (inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) {
912 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, ("Rx ok interrupt!\n"));
913 _rtl_pci_rx_interrupt(hw);
916 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) {
917 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
918 ("rx descriptor unavailable!\n"));
919 _rtl_pci_rx_interrupt(hw);
922 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) {
923 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, ("rx overflow !\n"));
924 _rtl_pci_rx_interrupt(hw);
927 if (rtlpriv->rtlhal.earlymode_enable)
928 tasklet_schedule(&rtlpriv->works.irq_tasklet);
930 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
934 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
938 static void _rtl_pci_irq_tasklet(struct ieee80211_hw *hw)
940 _rtl_pci_tx_chk_waitq(hw);
943 static void _rtl_pci_prepare_bcn_tasklet(struct ieee80211_hw *hw)
945 struct rtl_priv *rtlpriv = rtl_priv(hw);
946 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
947 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
948 struct rtl8192_tx_ring *ring = NULL;
949 struct ieee80211_hdr *hdr = NULL;
950 struct ieee80211_tx_info *info = NULL;
951 struct sk_buff *pskb = NULL;
952 struct rtl_tx_desc *pdesc = NULL;
953 struct rtl_tcb_desc tcb_desc;
956 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
957 ring = &rtlpci->tx_ring[BEACON_QUEUE];
958 pskb = __skb_dequeue(&ring->queue);
962 /*NB: the beacon data buffer must be 32-bit aligned. */
963 pskb = ieee80211_beacon_get(hw, mac->vif);
966 hdr = rtl_get_hdr(pskb);
967 info = IEEE80211_SKB_CB(pskb);
968 pdesc = &ring->desc[0];
969 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *) pdesc,
970 info, pskb, BEACON_QUEUE, &tcb_desc);
972 __skb_queue_tail(&ring->queue, pskb);
974 rtlpriv->cfg->ops->set_desc((u8 *) pdesc, true, HW_DESC_OWN,
980 static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw)
982 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
985 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
986 rtlpci->txringcount[i] = RT_TXDESC_NUM;
989 *we just alloc 2 desc for beacon queue,
990 *because we just need first desc in hw beacon.
992 rtlpci->txringcount[BEACON_QUEUE] = 2;
995 *BE queue need more descriptor for performance
996 *consideration or, No more tx desc will happen,
997 *and may cause mac80211 mem leakage.
999 rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE;
1001 rtlpci->rxbuffersize = 9100; /*2048/1024; */
1002 rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT; /*64; */
1005 static void _rtl_pci_init_struct(struct ieee80211_hw *hw,
1006 struct pci_dev *pdev)
1008 struct rtl_priv *rtlpriv = rtl_priv(hw);
1009 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1010 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1011 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1013 rtlpci->up_first_time = true;
1014 rtlpci->being_init_adapter = false;
1017 rtlpci->pdev = pdev;
1019 /*Tx/Rx related var */
1020 _rtl_pci_init_trx_var(hw);
1022 /*IBSS*/ mac->beacon_interval = 100;
1025 mac->min_space_cfg = 0;
1026 mac->max_mss_density = 0;
1027 /*set sane AMPDU defaults */
1028 mac->current_ampdu_density = 7;
1029 mac->current_ampdu_factor = 3;
1032 rtlpci->acm_method = eAcmWay2_SW;
1035 tasklet_init(&rtlpriv->works.irq_tasklet,
1036 (void (*)(unsigned long))_rtl_pci_irq_tasklet,
1038 tasklet_init(&rtlpriv->works.irq_prepare_bcn_tasklet,
1039 (void (*)(unsigned long))_rtl_pci_prepare_bcn_tasklet,
1043 static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw,
1044 unsigned int prio, unsigned int entries)
1046 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1047 struct rtl_priv *rtlpriv = rtl_priv(hw);
1048 struct rtl_tx_desc *ring;
1050 u32 nextdescaddress;
1053 ring = pci_alloc_consistent(rtlpci->pdev,
1054 sizeof(*ring) * entries, &dma);
1056 if (!ring || (unsigned long)ring & 0xFF) {
1057 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1058 ("Cannot allocate TX ring (prio = %d)\n", prio));
1062 memset(ring, 0, sizeof(*ring) * entries);
1063 rtlpci->tx_ring[prio].desc = ring;
1064 rtlpci->tx_ring[prio].dma = dma;
1065 rtlpci->tx_ring[prio].idx = 0;
1066 rtlpci->tx_ring[prio].entries = entries;
1067 skb_queue_head_init(&rtlpci->tx_ring[prio].queue);
1069 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1070 ("queue:%d, ring_addr:%p\n", prio, ring));
1072 for (i = 0; i < entries; i++) {
1073 nextdescaddress = (u32) dma +
1074 ((i + 1) % entries) *
1077 rtlpriv->cfg->ops->set_desc((u8 *)&(ring[i]),
1078 true, HW_DESC_TX_NEXTDESC_ADDR,
1079 (u8 *)&nextdescaddress);
1085 static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw)
1087 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1088 struct rtl_priv *rtlpriv = rtl_priv(hw);
1089 struct rtl_rx_desc *entry = NULL;
1090 int i, rx_queue_idx;
1094 *rx_queue_idx 0:RX_MPDU_QUEUE
1095 *rx_queue_idx 1:RX_CMD_QUEUE
1097 for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1099 rtlpci->rx_ring[rx_queue_idx].desc =
1100 pci_alloc_consistent(rtlpci->pdev,
1101 sizeof(*rtlpci->rx_ring[rx_queue_idx].
1102 desc) * rtlpci->rxringcount,
1103 &rtlpci->rx_ring[rx_queue_idx].dma);
1105 if (!rtlpci->rx_ring[rx_queue_idx].desc ||
1106 (unsigned long)rtlpci->rx_ring[rx_queue_idx].desc & 0xFF) {
1107 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1108 ("Cannot allocate RX ring\n"));
1112 memset(rtlpci->rx_ring[rx_queue_idx].desc, 0,
1113 sizeof(*rtlpci->rx_ring[rx_queue_idx].desc) *
1114 rtlpci->rxringcount);
1116 rtlpci->rx_ring[rx_queue_idx].idx = 0;
1118 /* If amsdu_8k is disabled, set buffersize to 4096. This
1119 * change will reduce memory fragmentation.
1121 if (rtlpci->rxbuffersize > 4096 &&
1122 rtlpriv->rtlhal.disable_amsdu_8k)
1123 rtlpci->rxbuffersize = 4096;
1125 for (i = 0; i < rtlpci->rxringcount; i++) {
1126 struct sk_buff *skb =
1127 dev_alloc_skb(rtlpci->rxbuffersize);
1131 entry = &rtlpci->rx_ring[rx_queue_idx].desc[i];
1133 /*skb->dev = dev; */
1135 rtlpci->rx_ring[rx_queue_idx].rx_buf[i] = skb;
1138 *just set skb->cb to mapping addr
1139 *for pci_unmap_single use
1141 *((dma_addr_t *) skb->cb) =
1142 pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
1143 rtlpci->rxbuffersize,
1144 PCI_DMA_FROMDEVICE);
1146 bufferaddress = (*((dma_addr_t *)skb->cb));
1147 rtlpriv->cfg->ops->set_desc((u8 *)entry, false,
1148 HW_DESC_RXBUFF_ADDR,
1149 (u8 *)&bufferaddress);
1150 rtlpriv->cfg->ops->set_desc((u8 *)entry, false,
1154 rtlpriv->cfg->ops->set_desc((u8 *) entry, false,
1159 rtlpriv->cfg->ops->set_desc((u8 *) entry, false,
1160 HW_DESC_RXERO, (u8 *)&tmp_one);
1165 static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw,
1168 struct rtl_priv *rtlpriv = rtl_priv(hw);
1169 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1170 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
1172 while (skb_queue_len(&ring->queue)) {
1173 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
1174 struct sk_buff *skb = __skb_dequeue(&ring->queue);
1176 pci_unmap_single(rtlpci->pdev,
1178 ops->get_desc((u8 *) entry, true,
1179 HW_DESC_TXBUFF_ADDR),
1180 skb->len, PCI_DMA_TODEVICE);
1182 ring->idx = (ring->idx + 1) % ring->entries;
1185 pci_free_consistent(rtlpci->pdev,
1186 sizeof(*ring->desc) * ring->entries,
1187 ring->desc, ring->dma);
1191 static void _rtl_pci_free_rx_ring(struct rtl_pci *rtlpci)
1193 int i, rx_queue_idx;
1195 /*rx_queue_idx 0:RX_MPDU_QUEUE */
1196 /*rx_queue_idx 1:RX_CMD_QUEUE */
1197 for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1199 for (i = 0; i < rtlpci->rxringcount; i++) {
1200 struct sk_buff *skb =
1201 rtlpci->rx_ring[rx_queue_idx].rx_buf[i];
1205 pci_unmap_single(rtlpci->pdev,
1206 *((dma_addr_t *) skb->cb),
1207 rtlpci->rxbuffersize,
1208 PCI_DMA_FROMDEVICE);
1212 pci_free_consistent(rtlpci->pdev,
1213 sizeof(*rtlpci->rx_ring[rx_queue_idx].
1214 desc) * rtlpci->rxringcount,
1215 rtlpci->rx_ring[rx_queue_idx].desc,
1216 rtlpci->rx_ring[rx_queue_idx].dma);
1217 rtlpci->rx_ring[rx_queue_idx].desc = NULL;
1221 static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw)
1223 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1227 ret = _rtl_pci_init_rx_ring(hw);
1231 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1232 ret = _rtl_pci_init_tx_ring(hw, i,
1233 rtlpci->txringcount[i]);
1235 goto err_free_rings;
1241 _rtl_pci_free_rx_ring(rtlpci);
1243 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1244 if (rtlpci->tx_ring[i].desc)
1245 _rtl_pci_free_tx_ring(hw, i);
1250 static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw)
1252 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1256 _rtl_pci_free_rx_ring(rtlpci);
1259 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1260 _rtl_pci_free_tx_ring(hw, i);
1265 int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw)
1267 struct rtl_priv *rtlpriv = rtl_priv(hw);
1268 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1269 int i, rx_queue_idx;
1270 unsigned long flags;
1273 /*rx_queue_idx 0:RX_MPDU_QUEUE */
1274 /*rx_queue_idx 1:RX_CMD_QUEUE */
1275 for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1278 *force the rx_ring[RX_MPDU_QUEUE/
1279 *RX_CMD_QUEUE].idx to the first one
1281 if (rtlpci->rx_ring[rx_queue_idx].desc) {
1282 struct rtl_rx_desc *entry = NULL;
1284 for (i = 0; i < rtlpci->rxringcount; i++) {
1285 entry = &rtlpci->rx_ring[rx_queue_idx].desc[i];
1286 rtlpriv->cfg->ops->set_desc((u8 *) entry,
1291 rtlpci->rx_ring[rx_queue_idx].idx = 0;
1296 *after reset, release previous pending packet,
1297 *and force the tx idx to the first one
1299 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1300 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1301 if (rtlpci->tx_ring[i].desc) {
1302 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i];
1304 while (skb_queue_len(&ring->queue)) {
1305 struct rtl_tx_desc *entry =
1306 &ring->desc[ring->idx];
1307 struct sk_buff *skb =
1308 __skb_dequeue(&ring->queue);
1310 pci_unmap_single(rtlpci->pdev,
1315 HW_DESC_TXBUFF_ADDR),
1316 skb->len, PCI_DMA_TODEVICE);
1318 ring->idx = (ring->idx + 1) % ring->entries;
1324 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1329 static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw,
1330 struct sk_buff *skb)
1332 struct rtl_priv *rtlpriv = rtl_priv(hw);
1333 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1334 struct ieee80211_sta *sta = info->control.sta;
1335 struct rtl_sta_info *sta_entry = NULL;
1336 u8 tid = rtl_get_tid(skb);
1340 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1342 if (!rtlpriv->rtlhal.earlymode_enable)
1344 if (sta_entry->tids[tid].agg.agg_state != RTL_AGG_OPERATIONAL)
1346 if (_rtl_mac_to_hwqueue(hw, skb) > VO_QUEUE)
1351 /* maybe every tid should be checked */
1352 if (!rtlpriv->link_info.higher_busytxtraffic[tid])
1355 spin_lock_bh(&rtlpriv->locks.waitq_lock);
1356 skb_queue_tail(&rtlpriv->mac80211.skb_waitq[tid], skb);
1357 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
1362 static int rtl_pci_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
1363 struct rtl_tcb_desc *ptcb_desc)
1365 struct rtl_priv *rtlpriv = rtl_priv(hw);
1366 struct rtl_sta_info *sta_entry = NULL;
1367 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1368 struct ieee80211_sta *sta = info->control.sta;
1369 struct rtl8192_tx_ring *ring;
1370 struct rtl_tx_desc *pdesc;
1372 u8 hw_queue = _rtl_mac_to_hwqueue(hw, skb);
1373 unsigned long flags;
1374 struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
1375 __le16 fc = rtl_get_fc(skb);
1376 u8 *pda_addr = hdr->addr1;
1377 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1384 if (ieee80211_is_auth(fc)) {
1385 RT_TRACE(rtlpriv, COMP_SEND, DBG_DMESG, ("MAC80211_LINKING\n"));
1389 if (rtlpriv->psc.sw_ps_enabled) {
1390 if (ieee80211_is_data(fc) && !ieee80211_is_nullfunc(fc) &&
1391 !ieee80211_has_pm(fc))
1392 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1395 rtl_action_proc(hw, skb, true);
1397 if (is_multicast_ether_addr(pda_addr))
1398 rtlpriv->stats.txbytesmulticast += skb->len;
1399 else if (is_broadcast_ether_addr(pda_addr))
1400 rtlpriv->stats.txbytesbroadcast += skb->len;
1402 rtlpriv->stats.txbytesunicast += skb->len;
1404 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1405 ring = &rtlpci->tx_ring[hw_queue];
1406 if (hw_queue != BEACON_QUEUE)
1407 idx = (ring->idx + skb_queue_len(&ring->queue)) %
1412 pdesc = &ring->desc[idx];
1413 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
1416 if ((own == 1) && (hw_queue != BEACON_QUEUE)) {
1417 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1418 ("No more TX desc@%d, ring->idx = %d,"
1419 "idx = %d, skb_queue_len = 0x%d\n",
1420 hw_queue, ring->idx, idx,
1421 skb_queue_len(&ring->queue)));
1423 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1427 if (ieee80211_is_data_qos(fc)) {
1428 tid = rtl_get_tid(skb);
1430 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1431 seq_number = (le16_to_cpu(hdr->seq_ctrl) &
1432 IEEE80211_SCTL_SEQ) >> 4;
1435 if (!ieee80211_has_morefrags(hdr->frame_control))
1436 sta_entry->tids[tid].seq_number = seq_number;
1440 if (ieee80211_is_data(fc))
1441 rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX);
1443 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
1444 info, skb, hw_queue, ptcb_desc);
1446 __skb_queue_tail(&ring->queue, skb);
1448 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, true,
1449 HW_DESC_OWN, (u8 *)&temp_one);
1452 if ((ring->entries - skb_queue_len(&ring->queue)) < 2 &&
1453 hw_queue != BEACON_QUEUE) {
1455 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
1456 ("less desc left, stop skb_queue@%d, "
1458 "idx = %d, skb_queue_len = 0x%d\n",
1459 hw_queue, ring->idx, idx,
1460 skb_queue_len(&ring->queue)));
1462 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
1465 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1467 rtlpriv->cfg->ops->tx_polling(hw, hw_queue);
1472 static void rtl_pci_flush(struct ieee80211_hw *hw, bool drop)
1474 struct rtl_priv *rtlpriv = rtl_priv(hw);
1475 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1476 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1479 struct rtl8192_tx_ring *ring;
1481 for (queue_id = RTL_PCI_MAX_TX_QUEUE_COUNT - 1; queue_id >= 0;) {
1483 ring = &pcipriv->dev.tx_ring[queue_id];
1484 queue_len = skb_queue_len(&ring->queue);
1485 if (queue_len == 0 || queue_id == BEACON_QUEUE ||
1486 queue_id == TXCMD_QUEUE) {
1494 /* we just wait 1s for all queues */
1495 if (rtlpriv->psc.rfpwr_state == ERFOFF ||
1496 is_hal_stop(rtlhal) || i >= 200)
1501 static void rtl_pci_deinit(struct ieee80211_hw *hw)
1503 struct rtl_priv *rtlpriv = rtl_priv(hw);
1504 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1506 _rtl_pci_deinit_trx_ring(hw);
1508 synchronize_irq(rtlpci->pdev->irq);
1509 tasklet_kill(&rtlpriv->works.irq_tasklet);
1511 flush_workqueue(rtlpriv->works.rtl_wq);
1512 destroy_workqueue(rtlpriv->works.rtl_wq);
1516 static int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev)
1518 struct rtl_priv *rtlpriv = rtl_priv(hw);
1521 _rtl_pci_init_struct(hw, pdev);
1523 err = _rtl_pci_init_trx_ring(hw);
1525 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1526 ("tx ring initialization failed"));
1533 static int rtl_pci_start(struct ieee80211_hw *hw)
1535 struct rtl_priv *rtlpriv = rtl_priv(hw);
1536 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1537 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1538 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1542 rtl_pci_reset_trx_ring(hw);
1544 rtlpci->driver_is_goingto_unload = false;
1545 err = rtlpriv->cfg->ops->hw_init(hw);
1547 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1548 ("Failed to config hardware!\n"));
1552 rtlpriv->cfg->ops->enable_interrupt(hw);
1553 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("enable_interrupt OK\n"));
1555 rtl_init_rx_config(hw);
1557 /*should after adapter start and interrupt enable. */
1558 set_hal_start(rtlhal);
1560 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1562 rtlpci->up_first_time = false;
1564 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("OK\n"));
1568 static void rtl_pci_stop(struct ieee80211_hw *hw)
1570 struct rtl_priv *rtlpriv = rtl_priv(hw);
1571 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1572 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1573 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1574 unsigned long flags;
1575 u8 RFInProgressTimeOut = 0;
1578 *should before disable interrrupt&adapter
1579 *and will do it immediately.
1581 set_hal_stop(rtlhal);
1583 rtlpriv->cfg->ops->disable_interrupt(hw);
1585 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1586 while (ppsc->rfchange_inprogress) {
1587 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1588 if (RFInProgressTimeOut > 100) {
1589 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1593 RFInProgressTimeOut++;
1594 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1596 ppsc->rfchange_inprogress = true;
1597 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1599 rtlpci->driver_is_goingto_unload = true;
1600 rtlpriv->cfg->ops->hw_disable(hw);
1601 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1603 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1604 ppsc->rfchange_inprogress = false;
1605 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1607 rtl_pci_enable_aspm(hw);
1610 static bool _rtl_pci_find_adapter(struct pci_dev *pdev,
1611 struct ieee80211_hw *hw)
1613 struct rtl_priv *rtlpriv = rtl_priv(hw);
1614 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1615 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1616 struct pci_dev *bridge_pdev = pdev->bus->self;
1623 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
1624 venderid = pdev->vendor;
1625 deviceid = pdev->device;
1626 pci_read_config_byte(pdev, 0x8, &revisionid);
1627 pci_read_config_word(pdev, 0x3C, &irqline);
1629 if (deviceid == RTL_PCI_8192_DID ||
1630 deviceid == RTL_PCI_0044_DID ||
1631 deviceid == RTL_PCI_0047_DID ||
1632 deviceid == RTL_PCI_8192SE_DID ||
1633 deviceid == RTL_PCI_8174_DID ||
1634 deviceid == RTL_PCI_8173_DID ||
1635 deviceid == RTL_PCI_8172_DID ||
1636 deviceid == RTL_PCI_8171_DID) {
1637 switch (revisionid) {
1638 case RTL_PCI_REVISION_ID_8192PCIE:
1639 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1640 ("8192 PCI-E is found - "
1641 "vid/did=%x/%x\n", venderid, deviceid));
1642 rtlhal->hw_type = HARDWARE_TYPE_RTL8192E;
1644 case RTL_PCI_REVISION_ID_8192SE:
1645 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1646 ("8192SE is found - "
1647 "vid/did=%x/%x\n", venderid, deviceid));
1648 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1651 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1652 ("Err: Unknown device - "
1653 "vid/did=%x/%x\n", venderid, deviceid));
1654 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1658 } else if (deviceid == RTL_PCI_8192CET_DID ||
1659 deviceid == RTL_PCI_8192CE_DID ||
1660 deviceid == RTL_PCI_8191CE_DID ||
1661 deviceid == RTL_PCI_8188CE_DID) {
1662 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE;
1663 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1664 ("8192C PCI-E is found - "
1665 "vid/did=%x/%x\n", venderid, deviceid));
1666 } else if (deviceid == RTL_PCI_8192DE_DID ||
1667 deviceid == RTL_PCI_8192DE_DID2) {
1668 rtlhal->hw_type = HARDWARE_TYPE_RTL8192DE;
1669 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1670 ("8192D PCI-E is found - "
1671 "vid/did=%x/%x\n", venderid, deviceid));
1673 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1674 ("Err: Unknown device -"
1675 " vid/did=%x/%x\n", venderid, deviceid));
1677 rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE;
1680 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) {
1681 if (revisionid == 0 || revisionid == 1) {
1682 if (revisionid == 0) {
1683 RT_TRACE(rtlpriv, COMP_INIT,
1684 DBG_LOUD, ("Find 92DE MAC0.\n"));
1685 rtlhal->interfaceindex = 0;
1686 } else if (revisionid == 1) {
1687 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1688 ("Find 92DE MAC1.\n"));
1689 rtlhal->interfaceindex = 1;
1692 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1693 ("Unknown device - "
1694 "VendorID/DeviceID=%x/%x, Revision=%x\n",
1695 venderid, deviceid, revisionid));
1696 rtlhal->interfaceindex = 0;
1700 pcipriv->ndis_adapter.busnumber = pdev->bus->number;
1701 pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn);
1702 pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn);
1704 /*find bridge info */
1705 pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor;
1706 for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) {
1707 if (bridge_pdev->vendor == pcibridge_vendors[tmp]) {
1708 pcipriv->ndis_adapter.pcibridge_vendor = tmp;
1709 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1710 ("Pci Bridge Vendor is found index: %d\n",
1716 if (pcipriv->ndis_adapter.pcibridge_vendor !=
1717 PCI_BRIDGE_VENDOR_UNKNOWN) {
1718 pcipriv->ndis_adapter.pcibridge_busnum =
1719 bridge_pdev->bus->number;
1720 pcipriv->ndis_adapter.pcibridge_devnum =
1721 PCI_SLOT(bridge_pdev->devfn);
1722 pcipriv->ndis_adapter.pcibridge_funcnum =
1723 PCI_FUNC(bridge_pdev->devfn);
1724 pcipriv->ndis_adapter.pcicfg_addrport =
1725 (pcipriv->ndis_adapter.pcibridge_busnum << 16) |
1726 (pcipriv->ndis_adapter.pcibridge_devnum << 11) |
1727 (pcipriv->ndis_adapter.pcibridge_funcnum << 8) | (1 << 31);
1728 pcipriv->ndis_adapter.pcibridge_pciehdr_offset =
1729 pci_pcie_cap(bridge_pdev);
1730 pcipriv->ndis_adapter.num4bytes =
1731 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10) / 4;
1733 rtl_pci_get_linkcontrol_field(hw);
1735 if (pcipriv->ndis_adapter.pcibridge_vendor ==
1736 PCI_BRIDGE_VENDOR_AMD) {
1737 pcipriv->ndis_adapter.amd_l1_patch =
1738 rtl_pci_get_amd_l1_patch(hw);
1742 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1743 ("pcidev busnumber:devnumber:funcnumber:"
1744 "vendor:link_ctl %d:%d:%d:%x:%x\n",
1745 pcipriv->ndis_adapter.busnumber,
1746 pcipriv->ndis_adapter.devnumber,
1747 pcipriv->ndis_adapter.funcnumber,
1748 pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg));
1750 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1751 ("pci_bridge busnumber:devnumber:funcnumber:vendor:"
1752 "pcie_cap:link_ctl_reg:amd %d:%d:%d:%x:%x:%x:%x\n",
1753 pcipriv->ndis_adapter.pcibridge_busnum,
1754 pcipriv->ndis_adapter.pcibridge_devnum,
1755 pcipriv->ndis_adapter.pcibridge_funcnum,
1756 pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor],
1757 pcipriv->ndis_adapter.pcibridge_pciehdr_offset,
1758 pcipriv->ndis_adapter.pcibridge_linkctrlreg,
1759 pcipriv->ndis_adapter.amd_l1_patch));
1761 rtl_pci_parse_configuration(pdev, hw);
1766 int __devinit rtl_pci_probe(struct pci_dev *pdev,
1767 const struct pci_device_id *id)
1769 struct ieee80211_hw *hw = NULL;
1771 struct rtl_priv *rtlpriv = NULL;
1772 struct rtl_pci_priv *pcipriv = NULL;
1773 struct rtl_pci *rtlpci;
1774 unsigned long pmem_start, pmem_len, pmem_flags;
1777 err = pci_enable_device(pdev);
1780 ("%s : Cannot enable new PCI device\n",
1785 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
1786 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
1787 RT_ASSERT(false, ("Unable to obtain 32bit DMA "
1788 "for consistent allocations\n"));
1789 pci_disable_device(pdev);
1794 pci_set_master(pdev);
1796 hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) +
1797 sizeof(struct rtl_priv), &rtl_ops);
1800 ("%s : ieee80211 alloc failed\n", pci_name(pdev)));
1805 SET_IEEE80211_DEV(hw, &pdev->dev);
1806 pci_set_drvdata(pdev, hw);
1809 pcipriv = (void *)rtlpriv->priv;
1810 pcipriv->dev.pdev = pdev;
1812 /* init cfg & intf_ops */
1813 rtlpriv->rtlhal.interface = INTF_PCI;
1814 rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data);
1815 rtlpriv->intf_ops = &rtl_pci_ops;
1818 *init dbgp flags before all
1819 *other functions, because we will
1820 *use it in other funtions like
1821 *RT_TRACE/RT_PRINT/RTL_PRINT_DATA
1822 *you can not use these macro
1825 rtl_dbgp_flag_init(hw);
1828 err = pci_request_regions(pdev, KBUILD_MODNAME);
1830 RT_ASSERT(false, ("Can't obtain PCI resources\n"));
1834 pmem_start = pci_resource_start(pdev, rtlpriv->cfg->bar_id);
1835 pmem_len = pci_resource_len(pdev, rtlpriv->cfg->bar_id);
1836 pmem_flags = pci_resource_flags(pdev, rtlpriv->cfg->bar_id);
1838 /*shared mem start */
1839 rtlpriv->io.pci_mem_start =
1840 (unsigned long)pci_iomap(pdev,
1841 rtlpriv->cfg->bar_id, pmem_len);
1842 if (rtlpriv->io.pci_mem_start == 0) {
1843 RT_ASSERT(false, ("Can't map PCI mem\n"));
1847 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1848 ("mem mapped space: start: 0x%08lx len:%08lx "
1849 "flags:%08lx, after map:0x%08lx\n",
1850 pmem_start, pmem_len, pmem_flags,
1851 rtlpriv->io.pci_mem_start));
1853 /* Disable Clk Request */
1854 pci_write_config_byte(pdev, 0x81, 0);
1856 pci_write_config_byte(pdev, 0x44, 0);
1857 pci_write_config_byte(pdev, 0x04, 0x06);
1858 pci_write_config_byte(pdev, 0x04, 0x07);
1861 _rtl_pci_find_adapter(pdev, hw);
1863 /* Init IO handler */
1864 _rtl_pci_io_handler_init(&pdev->dev, hw);
1866 /*like read eeprom and so on */
1867 rtlpriv->cfg->ops->read_eeprom_info(hw);
1869 if (rtlpriv->cfg->ops->init_sw_vars(hw)) {
1870 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1871 ("Can't init_sw_vars.\n"));
1875 rtlpriv->cfg->ops->init_sw_leds(hw);
1878 rtl_pci_init_aspm(hw);
1880 /* Init mac80211 sw */
1881 err = rtl_init_core(hw);
1883 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1884 ("Can't allocate sw for mac80211.\n"));
1889 err = !rtl_pci_init(hw, pdev);
1891 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1892 ("Failed to init PCI.\n"));
1896 err = ieee80211_register_hw(hw);
1898 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1899 ("Can't register mac80211 hw.\n"));
1902 rtlpriv->mac80211.mac80211_registered = 1;
1905 err = sysfs_create_group(&pdev->dev.kobj, &rtl_attribute_group);
1907 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1908 ("failed to create sysfs device attributes\n"));
1913 rtl_init_rfkill(hw);
1915 rtlpci = rtl_pcidev(pcipriv);
1916 err = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
1917 IRQF_SHARED, KBUILD_MODNAME, hw);
1919 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1920 ("%s: failed to register IRQ handler\n",
1921 wiphy_name(hw->wiphy)));
1924 rtlpci->irq_alloc = 1;
1927 set_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
1931 pci_set_drvdata(pdev, NULL);
1932 rtl_deinit_core(hw);
1933 _rtl_pci_io_handler_release(hw);
1934 ieee80211_free_hw(hw);
1936 if (rtlpriv->io.pci_mem_start != 0)
1937 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
1940 pci_release_regions(pdev);
1944 pci_disable_device(pdev);
1949 EXPORT_SYMBOL(rtl_pci_probe);
1951 void rtl_pci_disconnect(struct pci_dev *pdev)
1953 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
1954 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1955 struct rtl_priv *rtlpriv = rtl_priv(hw);
1956 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
1957 struct rtl_mac *rtlmac = rtl_mac(rtlpriv);
1959 clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
1961 sysfs_remove_group(&pdev->dev.kobj, &rtl_attribute_group);
1963 /*ieee80211_unregister_hw will call ops_stop */
1964 if (rtlmac->mac80211_registered == 1) {
1965 ieee80211_unregister_hw(hw);
1966 rtlmac->mac80211_registered = 0;
1968 rtl_deinit_deferred_work(hw);
1969 rtlpriv->intf_ops->adapter_stop(hw);
1973 rtl_deinit_rfkill(hw);
1976 rtl_deinit_core(hw);
1977 _rtl_pci_io_handler_release(hw);
1978 rtlpriv->cfg->ops->deinit_sw_vars(hw);
1980 if (rtlpci->irq_alloc) {
1981 free_irq(rtlpci->pdev->irq, hw);
1982 rtlpci->irq_alloc = 0;
1985 if (rtlpriv->io.pci_mem_start != 0) {
1986 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
1987 pci_release_regions(pdev);
1990 pci_disable_device(pdev);
1992 rtl_pci_disable_aspm(hw);
1994 pci_set_drvdata(pdev, NULL);
1996 ieee80211_free_hw(hw);
1998 EXPORT_SYMBOL(rtl_pci_disconnect);
2000 /***************************************
2001 kernel pci power state define:
2002 PCI_D0 ((pci_power_t __force) 0)
2003 PCI_D1 ((pci_power_t __force) 1)
2004 PCI_D2 ((pci_power_t __force) 2)
2005 PCI_D3hot ((pci_power_t __force) 3)
2006 PCI_D3cold ((pci_power_t __force) 4)
2007 PCI_UNKNOWN ((pci_power_t __force) 5)
2009 This function is called when system
2010 goes into suspend state mac80211 will
2011 call rtl_mac_stop() from the mac80211
2012 suspend function first, So there is
2013 no need to call hw_disable here.
2014 ****************************************/
2015 int rtl_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2017 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2018 struct rtl_priv *rtlpriv = rtl_priv(hw);
2020 rtlpriv->cfg->ops->hw_suspend(hw);
2021 rtl_deinit_rfkill(hw);
2023 pci_save_state(pdev);
2024 pci_disable_device(pdev);
2025 pci_set_power_state(pdev, PCI_D3hot);
2028 EXPORT_SYMBOL(rtl_pci_suspend);
2030 int rtl_pci_resume(struct pci_dev *pdev)
2033 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2034 struct rtl_priv *rtlpriv = rtl_priv(hw);
2036 pci_set_power_state(pdev, PCI_D0);
2037 ret = pci_enable_device(pdev);
2039 RT_ASSERT(false, ("ERR: <======\n"));
2043 pci_restore_state(pdev);
2045 rtlpriv->cfg->ops->hw_resume(hw);
2046 rtl_init_rfkill(hw);
2049 EXPORT_SYMBOL(rtl_pci_resume);
2051 struct rtl_intf_ops rtl_pci_ops = {
2052 .read_efuse_byte = read_efuse_byte,
2053 .adapter_start = rtl_pci_start,
2054 .adapter_stop = rtl_pci_stop,
2055 .adapter_tx = rtl_pci_tx,
2056 .flush = rtl_pci_flush,
2057 .reset_trx_ring = rtl_pci_reset_trx_ring,
2058 .waitq_insert = rtl_pci_tx_chk_waitq_insert,
2060 .disable_aspm = rtl_pci_disable_aspm,
2061 .enable_aspm = rtl_pci_enable_aspm,