drivers/net/wireless/rt2x00/rt2800usb.c

   1 /*
   2         Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt2800usb
  23         Abstract: rt2800usb device specific routines.
  24         Supported chipsets: RT2800U.
  25  */
  26
  27 #include <linux/crc-ccitt.h>
  28 #include <linux/delay.h>
  29 #include <linux/etherdevice.h>
  30 #include <linux/init.h>
  31 #include <linux/kernel.h>
  32 #include <linux/module.h>
  33 #include <linux/usb.h>
  34
  35 #include "rt2x00.h"
  36 #include "rt2x00usb.h"
  37 #include "rt2800usb.h"
  38
  39 /*
  40  * Allow hardware encryption to be disabled.
  41  */
  42 static int modparam_nohwcrypt = 1;
  43 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
  44 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  45
  46 /*
  47  * Register access.
  48  * All access to the CSR registers will go through the methods
  49  * rt2x00usb_register_read and rt2x00usb_register_write.
  50  * BBP and RF register require indirect register access,
  51  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  52  * These indirect registers work with busy bits,
  53  * and we will try maximal REGISTER_BUSY_COUNT times to access
  54  * the register while taking a REGISTER_BUSY_DELAY us delay
  55  * between each attampt. When the busy bit is still set at that time,
  56  * the access attempt is considered to have failed,
  57  * and we will print an error.
  58  * The _lock versions must be used if you already hold the csr_mutex
  59  */
  60 #define WAIT_FOR_BBP(__dev, __reg) \
  61         rt2x00usb_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
  62 #define WAIT_FOR_RFCSR(__dev, __reg) \
  63         rt2x00usb_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
  64 #define WAIT_FOR_RF(__dev, __reg) \
  65         rt2x00usb_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
  66 #define WAIT_FOR_MCU(__dev, __reg) \
  67         rt2x00usb_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  68                                H2M_MAILBOX_CSR_OWNER, (__reg))
  69
  70 static void rt2800usb_bbp_write(struct rt2x00_dev *rt2x00dev,
  71                                 const unsigned int word, const u8 value)
  72 {
  73         u32 reg;
  74
  75         mutex_lock(&rt2x00dev->csr_mutex);
  76
  77         /*
  78          * Wait until the BBP becomes available, afterwards we
  79          * can safely write the new data into the register.
  80          */
  81         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  82                 reg = 0;
  83                 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
  84                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
  85                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
  86                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
  87
  88                 rt2x00usb_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
  89         }
  90
  91         mutex_unlock(&rt2x00dev->csr_mutex);
  92 }
  93
  94 static void rt2800usb_bbp_read(struct rt2x00_dev *rt2x00dev,
  95                                const unsigned int word, u8 *value)
  96 {
  97         u32 reg;
  98
  99         mutex_lock(&rt2x00dev->csr_mutex);
 100
 101         /*
 102          * Wait until the BBP becomes available, afterwards we
 103          * can safely write the read request into the register.
 104          * After the data has been written, we wait until hardware
 105          * returns the correct value, if at any time the register
 106          * doesn't become available in time, reg will be 0xffffffff
 107          * which means we return 0xff to the caller.
 108          */
 109         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 110                 reg = 0;
 111                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 112                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 113                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
 114
 115                 rt2x00usb_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 116
 117                 WAIT_FOR_BBP(rt2x00dev, &reg);
 118         }
 119
 120         *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
 121
 122         mutex_unlock(&rt2x00dev->csr_mutex);
 123 }
 124
 125 static void rt2800usb_rfcsr_write(struct rt2x00_dev *rt2x00dev,
 126                                   const unsigned int word, const u8 value)
 127 {
 128         u32 reg;
 129
 130         mutex_lock(&rt2x00dev->csr_mutex);
 131
 132         /*
 133          * Wait until the RFCSR becomes available, afterwards we
 134          * can safely write the new data into the register.
 135          */
 136         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 137                 reg = 0;
 138                 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
 139                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 140                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
 141                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 142
 143                 rt2x00usb_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 144         }
 145
 146         mutex_unlock(&rt2x00dev->csr_mutex);
 147 }
 148
 149 static void rt2800usb_rfcsr_read(struct rt2x00_dev *rt2x00dev,
 150                                  const unsigned int word, u8 *value)
 151 {
 152         u32 reg;
 153
 154         mutex_lock(&rt2x00dev->csr_mutex);
 155
 156         /*
 157          * Wait until the RFCSR becomes available, afterwards we
 158          * can safely write the read request into the register.
 159          * After the data has been written, we wait until hardware
 160          * returns the correct value, if at any time the register
 161          * doesn't become available in time, reg will be 0xffffffff
 162          * which means we return 0xff to the caller.
 163          */
 164         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 165                 reg = 0;
 166                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 167                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
 168                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 169
 170                 rt2x00usb_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 171
 172                 WAIT_FOR_RFCSR(rt2x00dev, &reg);
 173         }
 174
 175         *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
 176
 177         mutex_unlock(&rt2x00dev->csr_mutex);
 178 }
 179
 180 static void rt2800usb_rf_write(struct rt2x00_dev *rt2x00dev,
 181                                const unsigned int word, const u32 value)
 182 {
 183         u32 reg;
 184
 185         mutex_lock(&rt2x00dev->csr_mutex);
 186
 187         /*
 188          * Wait until the RF becomes available, afterwards we
 189          * can safely write the new data into the register.
 190          */
 191         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 192                 reg = 0;
 193                 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
 194                 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
 195                 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
 196                 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
 197
 198                 rt2x00usb_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
 199                 rt2x00_rf_write(rt2x00dev, word, value);
 200         }
 201
 202         mutex_unlock(&rt2x00dev->csr_mutex);
 203 }
 204
 205 static void rt2800usb_mcu_request(struct rt2x00_dev *rt2x00dev,
 206                                   const u8 command, const u8 token,
 207                                   const u8 arg0, const u8 arg1)
 208 {
 209         u32 reg;
 210
 211         mutex_lock(&rt2x00dev->csr_mutex);
 212
 213         /*
 214          * Wait until the MCU becomes available, afterwards we
 215          * can safely write the new data into the register.
 216          */
 217         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 218                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 219                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 220                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 221                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 222                 rt2x00usb_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
 223
 224                 reg = 0;
 225                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 226                 rt2x00usb_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
 227         }
 228
 229         mutex_unlock(&rt2x00dev->csr_mutex);
 230 }
 231
 232 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 233 static const struct rt2x00debug rt2800usb_rt2x00debug = {
 234         .owner  = THIS_MODULE,
 235         .csr    = {
 236                 .read           = rt2x00usb_register_read,
 237                 .write          = rt2x00usb_register_write,
 238                 .flags          = RT2X00DEBUGFS_OFFSET,
 239                 .word_base      = CSR_REG_BASE,
 240                 .word_size      = sizeof(u32),
 241                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 242         },
 243         .eeprom = {
 244                 .read           = rt2x00_eeprom_read,
 245                 .write          = rt2x00_eeprom_write,
 246                 .word_base      = EEPROM_BASE,
 247                 .word_size      = sizeof(u16),
 248                 .word_count     = EEPROM_SIZE / sizeof(u16),
 249         },
 250         .bbp    = {
 251                 .read           = rt2800usb_bbp_read,
 252                 .write          = rt2800usb_bbp_write,
 253                 .word_base      = BBP_BASE,
 254                 .word_size      = sizeof(u8),
 255                 .word_count     = BBP_SIZE / sizeof(u8),
 256         },
 257         .rf     = {
 258                 .read           = rt2x00_rf_read,
 259                 .write          = rt2800usb_rf_write,
 260                 .word_base      = RF_BASE,
 261                 .word_size      = sizeof(u32),
 262                 .word_count     = RF_SIZE / sizeof(u32),
 263         },
 264 };
 265 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 266
 267 static int rt2800usb_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 268 {
 269         u32 reg;
 270
 271         rt2x00usb_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
 272         return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
 273 }
 274
 275 #ifdef CONFIG_RT2X00_LIB_LEDS
 276 static void rt2800usb_brightness_set(struct led_classdev *led_cdev,
 277                                      enum led_brightness brightness)
 278 {
 279         struct rt2x00_led *led =
 280             container_of(led_cdev, struct rt2x00_led, led_dev);
 281         unsigned int enabled = brightness != LED_OFF;
 282         unsigned int bg_mode =
 283             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 284         unsigned int polarity =
 285                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 286                                    EEPROM_FREQ_LED_POLARITY);
 287         unsigned int ledmode =
 288                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 289                                    EEPROM_FREQ_LED_MODE);
 290
 291         if (led->type == LED_TYPE_RADIO) {
 292                 rt2800usb_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 293                                       enabled ? 0x20 : 0);
 294         } else if (led->type == LED_TYPE_ASSOC) {
 295                 rt2800usb_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 296                                       enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
 297         } else if (led->type == LED_TYPE_QUALITY) {
 298                 /*
 299                  * The brightness is divided into 6 levels (0 - 5),
 300                  * The specs tell us the following levels:
 301                  *      0, 1 ,3, 7, 15, 31
 302                  * to determine the level in a simple way we can simply
 303                  * work with bitshifting:
 304                  *      (1 << level) - 1
 305                  */
 306                 rt2800usb_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
 307                                       (1 << brightness / (LED_FULL / 6)) - 1,
 308                                       polarity);
 309         }
 310 }
 311
 312 static int rt2800usb_blink_set(struct led_classdev *led_cdev,
 313                                unsigned long *delay_on,
 314                                unsigned long *delay_off)
 315 {
 316         struct rt2x00_led *led =
 317             container_of(led_cdev, struct rt2x00_led, led_dev);
 318         u32 reg;
 319
 320         rt2x00usb_register_read(led->rt2x00dev, LED_CFG, &reg);
 321         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
 322         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
 323         rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
 324         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
 325         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 12);
 326         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
 327         rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
 328         rt2x00usb_register_write(led->rt2x00dev, LED_CFG, reg);
 329
 330         return 0;
 331 }
 332
 333 static void rt2800usb_init_led(struct rt2x00_dev *rt2x00dev,
 334                                struct rt2x00_led *led,
 335                                enum led_type type)
 336 {
 337         led->rt2x00dev = rt2x00dev;
 338         led->type = type;
 339         led->led_dev.brightness_set = rt2800usb_brightness_set;
 340         led->led_dev.blink_set = rt2800usb_blink_set;
 341         led->flags = LED_INITIALIZED;
 342 }
 343 #endif /* CONFIG_RT2X00_LIB_LEDS */
 344
 345 /*
 346  * Configuration handlers.
 347  */
 348 static void rt2800usb_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
 349                                        struct rt2x00lib_crypto *crypto,
 350                                        struct ieee80211_key_conf *key)
 351 {
 352         struct mac_wcid_entry wcid_entry;
 353         struct mac_iveiv_entry iveiv_entry;
 354         u32 offset;
 355         u32 reg;
 356
 357         offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
 358
 359         rt2x00usb_register_read(rt2x00dev, offset, &reg);
 360         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
 361                            !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
 362         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
 363                            (crypto->cmd == SET_KEY) * crypto->cipher);
 364         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
 365                            (crypto->cmd == SET_KEY) * crypto->bssidx);
 366         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
 367         rt2x00usb_register_write(rt2x00dev, offset, reg);
 368
 369         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
 370
 371         memset(&iveiv_entry, 0, sizeof(iveiv_entry));
 372         if ((crypto->cipher == CIPHER_TKIP) ||
 373             (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
 374             (crypto->cipher == CIPHER_AES))
 375                 iveiv_entry.iv[3] |= 0x20;
 376         iveiv_entry.iv[3] |= key->keyidx << 6;
 377         rt2x00usb_register_multiwrite(rt2x00dev, offset,
 378                                       &iveiv_entry, sizeof(iveiv_entry));
 379
 380         offset = MAC_WCID_ENTRY(key->hw_key_idx);
 381
 382         memset(&wcid_entry, 0, sizeof(wcid_entry));
 383         if (crypto->cmd == SET_KEY)
 384                 memcpy(&wcid_entry, crypto->address, ETH_ALEN);
 385         rt2x00usb_register_multiwrite(rt2x00dev, offset,
 386                                       &wcid_entry, sizeof(wcid_entry));
 387 }
 388
 389 static int rt2800usb_config_shared_key(struct rt2x00_dev *rt2x00dev,
 390                                        struct rt2x00lib_crypto *crypto,
 391                                        struct ieee80211_key_conf *key)
 392 {
 393         struct hw_key_entry key_entry;
 394         struct rt2x00_field32 field;
 395         int timeout;
 396         u32 offset;
 397         u32 reg;
 398
 399         if (crypto->cmd == SET_KEY) {
 400                 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
 401
 402                 memcpy(key_entry.key, crypto->key,
 403                        sizeof(key_entry.key));
 404                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 405                        sizeof(key_entry.tx_mic));
 406                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 407                        sizeof(key_entry.rx_mic));
 408
 409                 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
 410                 timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
 411                 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
 412                                                     USB_VENDOR_REQUEST_OUT,
 413                                                     offset, &key_entry,
 414                                                     sizeof(key_entry),
 415                                                     timeout);
 416         }
 417
 418         /*
 419          * The cipher types are stored over multiple registers
 420          * starting with SHARED_KEY_MODE_BASE each word will have
 421          * 32 bits and contains the cipher types for 2 bssidx each.
 422          * Using the correct defines correctly will cause overhead,
 423          * so just calculate the correct offset.
 424          */
 425         field.bit_offset = 4 * (key->hw_key_idx % 8);
 426         field.bit_mask = 0x7 << field.bit_offset;
 427
 428         offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
 429
 430         rt2x00usb_register_read(rt2x00dev, offset, &reg);
 431         rt2x00_set_field32(&reg, field,
 432                            (crypto->cmd == SET_KEY) * crypto->cipher);
 433         rt2x00usb_register_write(rt2x00dev, offset, reg);
 434
 435         /*
 436          * Update WCID information
 437          */
 438         rt2800usb_config_wcid_attr(rt2x00dev, crypto, key);
 439
 440         return 0;
 441 }
 442
 443 static int rt2800usb_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
 444                                          struct rt2x00lib_crypto *crypto,
 445                                          struct ieee80211_key_conf *key)
 446 {
 447         struct hw_key_entry key_entry;
 448         int timeout;
 449         u32 offset;
 450
 451         if (crypto->cmd == SET_KEY) {
 452                 /*
 453                  * 1 pairwise key is possible per AID, this means that the AID
 454                  * equals our hw_key_idx. Make sure the WCID starts _after_ the
 455                  * last possible shared key entry.
 456                  */
 457                 if (crypto->aid > (256 - 32))
 458                         return -ENOSPC;
 459
 460                 key->hw_key_idx = 32 + crypto->aid;
 461
 462                 memcpy(key_entry.key, crypto->key,
 463                        sizeof(key_entry.key));
 464                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 465                        sizeof(key_entry.tx_mic));
 466                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 467                        sizeof(key_entry.rx_mic));
 468
 469                 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
 470                 timeout = REGISTER_TIMEOUT32(sizeof(key_entry));
 471                 rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
 472                                                     USB_VENDOR_REQUEST_OUT,
 473                                                     offset, &key_entry,
 474                                                     sizeof(key_entry),
 475                                                     timeout);
 476         }
 477
 478         /*
 479          * Update WCID information
 480          */
 481         rt2800usb_config_wcid_attr(rt2x00dev, crypto, key);
 482
 483         return 0;
 484 }
 485
 486 static void rt2800usb_config_filter(struct rt2x00_dev *rt2x00dev,
 487                                     const unsigned int filter_flags)
 488 {
 489         u32 reg;
 490
 491         /*
 492          * Start configuration steps.
 493          * Note that the version error will always be dropped
 494          * and broadcast frames will always be accepted since
 495          * there is no filter for it at this time.
 496          */
 497         rt2x00usb_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
 498         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
 499                            !(filter_flags & FIF_FCSFAIL));
 500         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
 501                            !(filter_flags & FIF_PLCPFAIL));
 502         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
 503                            !(filter_flags & FIF_PROMISC_IN_BSS));
 504         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
 505         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
 506         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
 507                            !(filter_flags & FIF_ALLMULTI));
 508         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
 509         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
 510         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
 511                            !(filter_flags & FIF_CONTROL));
 512         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
 513                            !(filter_flags & FIF_CONTROL));
 514         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
 515                            !(filter_flags & FIF_CONTROL));
 516         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
 517                            !(filter_flags & FIF_CONTROL));
 518         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
 519                            !(filter_flags & FIF_CONTROL));
 520         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
 521                            !(filter_flags & FIF_PSPOLL));
 522         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
 523         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
 524         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
 525                            !(filter_flags & FIF_CONTROL));
 526         rt2x00usb_register_write(rt2x00dev, RX_FILTER_CFG, reg);
 527 }
 528
 529 static void rt2800usb_config_intf(struct rt2x00_dev *rt2x00dev,
 530                                   struct rt2x00_intf *intf,
 531                                   struct rt2x00intf_conf *conf,
 532                                   const unsigned int flags)
 533 {
 534         unsigned int beacon_base;
 535         u32 reg;
 536
 537         if (flags & CONFIG_UPDATE_TYPE) {
 538                 /*
 539                  * Clear current synchronisation setup.
 540                  * For the Beacon base registers we only need to clear
 541                  * the first byte since that byte contains the VALID and OWNER
 542                  * bits which (when set to 0) will invalidate the entire beacon.
 543                  */
 544                 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
 545                 rt2x00usb_register_write(rt2x00dev, beacon_base, 0);
 546
 547                 /*
 548                  * Enable synchronisation.
 549                  */
 550                 rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 551                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
 552                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
 553                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
 554                 rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 555         }
 556
 557         if (flags & CONFIG_UPDATE_MAC) {
 558                 reg = le32_to_cpu(conf->mac[1]);
 559                 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
 560                 conf->mac[1] = cpu_to_le32(reg);
 561
 562                 rt2x00usb_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
 563                                               conf->mac, sizeof(conf->mac));
 564         }
 565
 566         if (flags & CONFIG_UPDATE_BSSID) {
 567                 reg = le32_to_cpu(conf->bssid[1]);
 568                 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
 569                 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
 570                 conf->bssid[1] = cpu_to_le32(reg);
 571
 572                 rt2x00usb_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
 573                                               conf->bssid, sizeof(conf->bssid));
 574         }
 575 }
 576
 577 static void rt2800usb_config_erp(struct rt2x00_dev *rt2x00dev,
 578                                  struct rt2x00lib_erp *erp)
 579 {
 580         u32 reg;
 581
 582         rt2x00usb_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
 583         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 0x20);
 584         rt2x00usb_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
 585
 586         rt2x00usb_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
 587         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
 588                            !!erp->short_preamble);
 589         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
 590                            !!erp->short_preamble);
 591         rt2x00usb_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
 592
 593         rt2x00usb_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
 594         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
 595                            erp->cts_protection ? 2 : 0);
 596         rt2x00usb_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
 597
 598         rt2x00usb_register_write(rt2x00dev, LEGACY_BASIC_RATE,
 599                                  erp->basic_rates);
 600         rt2x00usb_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
 601
 602         rt2x00usb_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
 603         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
 604         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
 605         rt2x00usb_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
 606
 607         rt2x00usb_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
 608         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
 609         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
 610         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
 611         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
 612         rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
 613         rt2x00usb_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
 614
 615         rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 616         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
 617                            erp->beacon_int * 16);
 618         rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 619 }
 620
 621 static void rt2800usb_config_ant(struct rt2x00_dev *rt2x00dev,
 622                                  struct antenna_setup *ant)
 623 {
 624         u8 r1;
 625         u8 r3;
 626
 627         rt2800usb_bbp_read(rt2x00dev, 1, &r1);
 628         rt2800usb_bbp_read(rt2x00dev, 3, &r3);
 629
 630         /*
 631          * Configure the TX antenna.
 632          */
 633         switch ((int)ant->tx) {
 634         case 1:
 635                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
 636                 break;
 637         case 2:
 638                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
 639                 break;
 640         case 3:
 641                 /* Do nothing */
 642                 break;
 643         }
 644
 645         /*
 646          * Configure the RX antenna.
 647          */
 648         switch ((int)ant->rx) {
 649         case 1:
 650                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
 651                 break;
 652         case 2:
 653                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
 654                 break;
 655         case 3:
 656                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
 657                 break;
 658         }
 659
 660         rt2800usb_bbp_write(rt2x00dev, 3, r3);
 661         rt2800usb_bbp_write(rt2x00dev, 1, r1);
 662 }
 663
 664 static void rt2800usb_config_lna_gain(struct rt2x00_dev *rt2x00dev,
 665                                       struct rt2x00lib_conf *libconf)
 666 {
 667         u16 eeprom;
 668         short lna_gain;
 669
 670         if (libconf->rf.channel <= 14) {
 671                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
 672                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
 673         } else if (libconf->rf.channel <= 64) {
 674                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
 675                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
 676         } else if (libconf->rf.channel <= 128) {
 677                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
 678                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
 679         } else {
 680                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
 681                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
 682         }
 683
 684         rt2x00dev->lna_gain = lna_gain;
 685 }
 686
 687 static void rt2800usb_config_channel_rt2x(struct rt2x00_dev *rt2x00dev,
 688                                           struct ieee80211_conf *conf,
 689                                           struct rf_channel *rf,
 690                                           struct channel_info *info)
 691 {
 692         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
 693
 694         if (rt2x00dev->default_ant.tx == 1)
 695                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
 696
 697         if (rt2x00dev->default_ant.rx == 1) {
 698                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
 699                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
 700         } else if (rt2x00dev->default_ant.rx == 2)
 701                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
 702
 703         if (rf->channel > 14) {
 704                 /*
 705                  * When TX power is below 0, we should increase it by 7 to
 706                  * make it a positive value (Minumum value is -7).
 707                  * However this means that values between 0 and 7 have
 708                  * double meaning, and we should set a 7DBm boost flag.
 709                  */
 710                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
 711                                    (info->tx_power1 >= 0));
 712
 713                 if (info->tx_power1 < 0)
 714                         info->tx_power1 += 7;
 715
 716                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
 717                                    TXPOWER_A_TO_DEV(info->tx_power1));
 718
 719                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
 720                                    (info->tx_power2 >= 0));
 721
 722                 if (info->tx_power2 < 0)
 723                         info->tx_power2 += 7;
 724
 725                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
 726                                    TXPOWER_A_TO_DEV(info->tx_power2));
 727         } else {
 728                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
 729                                    TXPOWER_G_TO_DEV(info->tx_power1));
 730                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
 731                                    TXPOWER_G_TO_DEV(info->tx_power2));
 732         }
 733
 734         rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
 735
 736         rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
 737         rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
 738         rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 739         rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
 740
 741         udelay(200);
 742
 743         rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
 744         rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
 745         rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
 746         rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
 747
 748         udelay(200);
 749
 750         rt2800usb_rf_write(rt2x00dev, 1, rf->rf1);
 751         rt2800usb_rf_write(rt2x00dev, 2, rf->rf2);
 752         rt2800usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 753         rt2800usb_rf_write(rt2x00dev, 4, rf->rf4);
 754 }
 755
 756 static void rt2800usb_config_channel_rt3x(struct rt2x00_dev *rt2x00dev,
 757                                           struct ieee80211_conf *conf,
 758                                           struct rf_channel *rf,
 759                                           struct channel_info *info)
 760 {
 761         u8 rfcsr;
 762
 763         rt2800usb_rfcsr_write(rt2x00dev, 2, rf->rf1);
 764         rt2800usb_rfcsr_write(rt2x00dev, 2, rf->rf3);
 765
 766         rt2800usb_rfcsr_read(rt2x00dev, 6, &rfcsr);
 767         rt2x00_set_field8(&rfcsr, RFCSR6_R, rf->rf2);
 768         rt2800usb_rfcsr_write(rt2x00dev, 6, rfcsr);
 769
 770         rt2800usb_rfcsr_read(rt2x00dev, 12, &rfcsr);
 771         rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
 772                           TXPOWER_G_TO_DEV(info->tx_power1));
 773         rt2800usb_rfcsr_write(rt2x00dev, 12, rfcsr);
 774
 775         rt2800usb_rfcsr_read(rt2x00dev, 23, &rfcsr);
 776         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
 777         rt2800usb_rfcsr_write(rt2x00dev, 23, rfcsr);
 778
 779         rt2800usb_rfcsr_write(rt2x00dev, 24,
 780                               rt2x00dev->calibration[conf_is_ht40(conf)]);
 781
 782         rt2800usb_rfcsr_read(rt2x00dev, 23, &rfcsr);
 783         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
 784         rt2800usb_rfcsr_write(rt2x00dev, 23, rfcsr);
 785 }
 786
 787 static void rt2800usb_config_channel(struct rt2x00_dev *rt2x00dev,
 788                                      struct ieee80211_conf *conf,
 789                                      struct rf_channel *rf,
 790                                      struct channel_info *info)
 791 {
 792         u32 reg;
 793         unsigned int tx_pin;
 794         u8 bbp;
 795
 796         if (rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
 797                 rt2800usb_config_channel_rt2x(rt2x00dev, conf, rf, info);
 798         else
 799                 rt2800usb_config_channel_rt3x(rt2x00dev, conf, rf, info);
 800
 801         /*
 802          * Change BBP settings
 803          */
 804         rt2800usb_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
 805         rt2800usb_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
 806         rt2800usb_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
 807         rt2800usb_bbp_write(rt2x00dev, 86, 0);
 808
 809         if (rf->channel <= 14) {
 810                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
 811                         rt2800usb_bbp_write(rt2x00dev, 82, 0x62);
 812                         rt2800usb_bbp_write(rt2x00dev, 75, 0x46);
 813                 } else {
 814                         rt2800usb_bbp_write(rt2x00dev, 82, 0x84);
 815                         rt2800usb_bbp_write(rt2x00dev, 75, 0x50);
 816                 }
 817         } else {
 818                 rt2800usb_bbp_write(rt2x00dev, 82, 0xf2);
 819
 820                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
 821                         rt2800usb_bbp_write(rt2x00dev, 75, 0x46);
 822                 else
 823                         rt2800usb_bbp_write(rt2x00dev, 75, 0x50);
 824         }
 825
 826         rt2x00usb_register_read(rt2x00dev, TX_BAND_CFG, &reg);
 827         rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_PLUS, conf_is_ht40_plus(conf));
 828         rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
 829         rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
 830         rt2x00usb_register_write(rt2x00dev, TX_BAND_CFG, reg);
 831
 832         tx_pin = 0;
 833
 834         /* Turn on unused PA or LNA when not using 1T or 1R */
 835         if (rt2x00dev->default_ant.tx != 1) {
 836                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
 837                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
 838         }
 839
 840         /* Turn on unused PA or LNA when not using 1T or 1R */
 841         if (rt2x00dev->default_ant.rx != 1) {
 842                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
 843                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
 844         }
 845
 846         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
 847         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
 848         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
 849         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
 850         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
 851         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
 852
 853         rt2x00usb_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
 854
 855         rt2800usb_bbp_read(rt2x00dev, 4, &bbp);
 856         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
 857         rt2800usb_bbp_write(rt2x00dev, 4, bbp);
 858
 859         rt2800usb_bbp_read(rt2x00dev, 3, &bbp);
 860         rt2x00_set_field8(&bbp, BBP3_HT40_PLUS, conf_is_ht40_plus(conf));
 861         rt2800usb_bbp_write(rt2x00dev, 3, bbp);
 862
 863         if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
 864                 if (conf_is_ht40(conf)) {
 865                         rt2800usb_bbp_write(rt2x00dev, 69, 0x1a);
 866                         rt2800usb_bbp_write(rt2x00dev, 70, 0x0a);
 867                         rt2800usb_bbp_write(rt2x00dev, 73, 0x16);
 868                 } else {
 869                         rt2800usb_bbp_write(rt2x00dev, 69, 0x16);
 870                         rt2800usb_bbp_write(rt2x00dev, 70, 0x08);
 871                         rt2800usb_bbp_write(rt2x00dev, 73, 0x11);
 872                 }
 873         }
 874
 875         msleep(1);
 876 }
 877
 878 static void rt2800usb_config_txpower(struct rt2x00_dev *rt2x00dev,
 879                                      const int txpower)
 880 {
 881         u32 reg;
 882         u32 value = TXPOWER_G_TO_DEV(txpower);
 883         u8 r1;
 884
 885         rt2800usb_bbp_read(rt2x00dev, 1, &r1);
 886         rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
 887         rt2800usb_bbp_write(rt2x00dev, 1, r1);
 888
 889         rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
 890         rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
 891         rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
 892         rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
 893         rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
 894         rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
 895         rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
 896         rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
 897         rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
 898         rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
 899
 900         rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
 901         rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
 902         rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
 903         rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
 904         rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
 905         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
 906         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
 907         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
 908         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
 909         rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
 910
 911         rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
 912         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
 913         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
 914         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
 915         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
 916         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
 917         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
 918         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
 919         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
 920         rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
 921
 922         rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
 923         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
 924         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
 925         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
 926         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
 927         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
 928         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
 929         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
 930         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
 931         rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
 932
 933         rt2x00usb_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
 934         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
 935         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
 936         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
 937         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
 938         rt2x00usb_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
 939 }
 940
 941 static void rt2800usb_config_retry_limit(struct rt2x00_dev *rt2x00dev,
 942                                          struct rt2x00lib_conf *libconf)
 943 {
 944         u32 reg;
 945
 946         rt2x00usb_register_read(rt2x00dev, TX_RTY_CFG, &reg);
 947         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
 948                            libconf->conf->short_frame_max_tx_count);
 949         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
 950                            libconf->conf->long_frame_max_tx_count);
 951         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
 952         rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
 953         rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
 954         rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
 955         rt2x00usb_register_write(rt2x00dev, TX_RTY_CFG, reg);
 956 }
 957
 958 static void rt2800usb_config_ps(struct rt2x00_dev *rt2x00dev,
 959                                 struct rt2x00lib_conf *libconf)
 960 {
 961         enum dev_state state =
 962             (libconf->conf->flags & IEEE80211_CONF_PS) ?
 963                 STATE_SLEEP : STATE_AWAKE;
 964         u32 reg;
 965
 966         if (state == STATE_SLEEP) {
 967                 rt2x00usb_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
 968
 969                 rt2x00usb_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
 970                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
 971                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
 972                                    libconf->conf->listen_interval - 1);
 973                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
 974                 rt2x00usb_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
 975
 976                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
 977         } else {
 978                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
 979
 980                 rt2x00usb_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
 981                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
 982                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
 983                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
 984                 rt2x00usb_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
 985         }
 986 }
 987
 988 static void rt2800usb_config(struct rt2x00_dev *rt2x00dev,
 989                              struct rt2x00lib_conf *libconf,
 990                              const unsigned int flags)
 991 {
 992         /* Always recalculate LNA gain before changing configuration */
 993         rt2800usb_config_lna_gain(rt2x00dev, libconf);
 994
 995         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
 996                 rt2800usb_config_channel(rt2x00dev, libconf->conf,
 997                                          &libconf->rf, &libconf->channel);
 998         if (flags & IEEE80211_CONF_CHANGE_POWER)
 999                 rt2800usb_config_txpower(rt2x00dev, libconf->conf->power_level);
1000         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1001                 rt2800usb_config_retry_limit(rt2x00dev, libconf);
1002         if (flags & IEEE80211_CONF_CHANGE_PS)
1003                 rt2800usb_config_ps(rt2x00dev, libconf);
1004 }
1005
1006 /*
1007  * Link tuning
1008  */
1009 static void rt2800usb_link_stats(struct rt2x00_dev *rt2x00dev,
1010                                  struct link_qual *qual)
1011 {
1012         u32 reg;
1013
1014         /*
1015          * Update FCS error count from register.
1016          */
1017         rt2x00usb_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1018         qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1019 }
1020
1021 static u8 rt2800usb_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1022 {
1023         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1024                 if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION)
1025                         return 0x1c + (2 * rt2x00dev->lna_gain);
1026                 else
1027                         return 0x2e + rt2x00dev->lna_gain;
1028         }
1029
1030         if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1031                 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1032         else
1033                 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1034 }
1035
1036 static inline void rt2800usb_set_vgc(struct rt2x00_dev *rt2x00dev,
1037                                      struct link_qual *qual, u8 vgc_level)
1038 {
1039         if (qual->vgc_level != vgc_level) {
1040                 rt2800usb_bbp_write(rt2x00dev, 66, vgc_level);
1041                 qual->vgc_level = vgc_level;
1042                 qual->vgc_level_reg = vgc_level;
1043         }
1044 }
1045
1046 static void rt2800usb_reset_tuner(struct rt2x00_dev *rt2x00dev,
1047                                   struct link_qual *qual)
1048 {
1049         rt2800usb_set_vgc(rt2x00dev, qual,
1050                           rt2800usb_get_default_vgc(rt2x00dev));
1051 }
1052
1053 static void rt2800usb_link_tuner(struct rt2x00_dev *rt2x00dev,
1054                                  struct link_qual *qual, const u32 count)
1055 {
1056         if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION)
1057                 return;
1058
1059         /*
1060          * When RSSI is better then -80 increase VGC level with 0x10
1061          */
1062         rt2800usb_set_vgc(rt2x00dev, qual,
1063                           rt2800usb_get_default_vgc(rt2x00dev) +
1064                           ((qual->rssi > -80) * 0x10));
1065 }
1066
1067 /*
1068  * Firmware functions
1069  */
1070 static char *rt2800usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1071 {
1072         return FIRMWARE_RT2870;
1073 }
1074
1075 static bool rt2800usb_check_crc(const u8 *data, const size_t len)
1076 {
1077         u16 fw_crc;
1078         u16 crc;
1079
1080         /*
1081          * The last 2 bytes in the firmware array are the crc checksum itself,
1082          * this means that we should never pass those 2 bytes to the crc
1083          * algorithm.
1084          */
1085         fw_crc = (data[len - 2] << 8 | data[len - 1]);
1086
1087         /*
1088          * Use the crc ccitt algorithm.
1089          * This will return the same value as the legacy driver which
1090          * used bit ordering reversion on the both the firmware bytes
1091          * before input input as well as on the final output.
1092          * Obviously using crc ccitt directly is much more efficient.
1093          */
1094         crc = crc_ccitt(~0, data, len - 2);
1095
1096         /*
1097          * There is a small difference between the crc-itu-t + bitrev and
1098          * the crc-ccitt crc calculation. In the latter method the 2 bytes
1099          * will be swapped, use swab16 to convert the crc to the correct
1100          * value.
1101          */
1102         crc = swab16(crc);
1103
1104         return fw_crc == crc;
1105 }
1106
1107 static int rt2800usb_check_firmware(struct rt2x00_dev *rt2x00dev,
1108                                     const u8 *data, const size_t len)
1109 {
1110         u16 chipset = (rt2x00_rev(&rt2x00dev->chip) >> 16) & 0xffff;
1111         size_t offset = 0;
1112
1113         /*
1114          * Firmware files:
1115          * There are 2 variations of the rt2870 firmware.
1116          * a) size: 4kb
1117          * b) size: 8kb
1118          * Note that (b) contains 2 seperate firmware blobs of 4k
1119          * within the file. The first blob is the same firmware as (a),
1120          * but the second blob is for the additional chipsets.
1121          */
1122         if (len != 4096 && len != 8192)
1123                 return FW_BAD_LENGTH;
1124
1125         /*
1126          * Check if we need the upper 4kb firmware data or not.
1127          */
1128         if ((len == 4096) &&
1129             (chipset != 0x2860) &&
1130             (chipset != 0x2872) &&
1131             (chipset != 0x3070))
1132                 return FW_BAD_VERSION;
1133
1134         /*
1135          * 8kb firmware files must be checked as if it were
1136          * 2 seperate firmware files.
1137          */
1138         while (offset < len) {
1139                 if (!rt2800usb_check_crc(data + offset, 4096))
1140                         return FW_BAD_CRC;
1141
1142                 offset += 4096;
1143         }
1144
1145         return FW_OK;
1146 }
1147
1148 static int rt2800usb_load_firmware(struct rt2x00_dev *rt2x00dev,
1149                                    const u8 *data, const size_t len)
1150 {
1151         unsigned int i;
1152         int status;
1153         u32 reg;
1154         u32 offset;
1155         u32 length;
1156         u16 chipset = (rt2x00_rev(&rt2x00dev->chip) >> 16) & 0xffff;
1157
1158         /*
1159          * Check which section of the firmware we need.
1160          */
1161         if ((chipset == 0x2860) ||
1162             (chipset == 0x2872) ||
1163             (chipset == 0x3070)) {
1164                 offset = 0;
1165                 length = 4096;
1166         } else {
1167                 offset = 4096;
1168                 length = 4096;
1169         }
1170
1171         /*
1172          * Wait for stable hardware.
1173          */
1174         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1175                 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1176                 if (reg && reg != ~0)
1177                         break;
1178                 msleep(1);
1179         }
1180
1181         if (i == REGISTER_BUSY_COUNT) {
1182                 ERROR(rt2x00dev, "Unstable hardware.\n");
1183                 return -EBUSY;
1184         }
1185
1186         /*
1187          * Write firmware to device.
1188          */
1189         rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
1190                                             USB_VENDOR_REQUEST_OUT,
1191                                             FIRMWARE_IMAGE_BASE,
1192                                             data + offset, length,
1193                                             REGISTER_TIMEOUT32(length));
1194
1195         rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
1196         rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
1197
1198         /*
1199          * Send firmware request to device to load firmware,
1200          * we need to specify a long timeout time.
1201          */
1202         status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
1203                                              0, USB_MODE_FIRMWARE,
1204                                              REGISTER_TIMEOUT_FIRMWARE);
1205         if (status < 0) {
1206                 ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
1207                 return status;
1208         }
1209
1210         msleep(10);
1211         rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1212
1213         /*
1214          * Send signal to firmware during boot time.
1215          */
1216         rt2800usb_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);
1217
1218         if ((chipset == 0x3070) ||
1219             (chipset == 0x3071) ||
1220             (chipset == 0x3572)) {
1221                 udelay(200);
1222                 rt2800usb_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
1223                 udelay(10);
1224         }
1225
1226         /*
1227          * Wait for device to stabilize.
1228          */
1229         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1230                 rt2x00usb_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1231                 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
1232                         break;
1233                 msleep(1);
1234         }
1235
1236         if (i == REGISTER_BUSY_COUNT) {
1237                 ERROR(rt2x00dev, "PBF system register not ready.\n");
1238                 return -EBUSY;
1239         }
1240
1241         /*
1242          * Initialize firmware.
1243          */
1244         rt2x00usb_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1245         rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1246         msleep(1);
1247
1248         return 0;
1249 }
1250
1251 /*
1252  * Initialization functions.
1253  */
1254 static int rt2800usb_init_registers(struct rt2x00_dev *rt2x00dev)
1255 {
1256         u32 reg;
1257         unsigned int i;
1258
1259         /*
1260          * Wait untill BBP and RF are ready.
1261          */
1262         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1263                 rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
1264                 if (reg && reg != ~0)
1265                         break;
1266                 msleep(1);
1267         }
1268
1269         if (i == REGISTER_BUSY_COUNT) {
1270                 ERROR(rt2x00dev, "Unstable hardware.\n");
1271                 return -EBUSY;
1272         }
1273
1274         rt2x00usb_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1275         rt2x00usb_register_write(rt2x00dev, PBF_SYS_CTRL, reg & ~0x00002000);
1276
1277         rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1278         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1279         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1280         rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1281
1282         rt2x00usb_register_write(rt2x00dev, USB_DMA_CFG, 0x00000000);
1283
1284         rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
1285                                     USB_MODE_RESET, REGISTER_TIMEOUT);
1286
1287         rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1288
1289         rt2x00usb_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1290         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1291         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1292         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1293         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1294         rt2x00usb_register_write(rt2x00dev, BCN_OFFSET0, reg);
1295
1296         rt2x00usb_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1297         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1298         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1299         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1300         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1301         rt2x00usb_register_write(rt2x00dev, BCN_OFFSET1, reg);
1302
1303         rt2x00usb_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1304         rt2x00usb_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1305
1306         rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1307
1308         rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1309         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1310         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1311         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1312         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1313         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1314         rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1315         rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1316
1317         if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
1318                 rt2x00usb_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1319                 rt2x00usb_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1320                 rt2x00usb_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1321         } else {
1322                 rt2x00usb_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1323                 rt2x00usb_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1324         }
1325
1326         rt2x00usb_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1327         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1328         rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1329         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1330         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1331         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1332         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1333         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1334         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1335         rt2x00usb_register_write(rt2x00dev, TX_LINK_CFG, reg);
1336
1337         rt2x00usb_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1338         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1339         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1340         rt2x00usb_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1341
1342         rt2x00usb_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1343         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1344         if (rt2x00_rev(&rt2x00dev->chip) >= RT2880E_VERSION &&
1345             rt2x00_rev(&rt2x00dev->chip) < RT3070_VERSION)
1346                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1347         else
1348                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1349         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1350         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1351         rt2x00usb_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1352
1353         rt2x00usb_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1354
1355         rt2x00usb_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1356         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1357         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1358         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1359         rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1360         rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1361         rt2x00usb_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1362
1363         rt2x00usb_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1364         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 8);
1365         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1366         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1367         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1368         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1369         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1370         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1371         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1372         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1373         rt2x00usb_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1374
1375         rt2x00usb_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1376         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 8);
1377         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1378         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1379         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1380         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1381         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1382         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1383         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1384         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1385         rt2x00usb_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1386
1387         rt2x00usb_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1388         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1389         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1390         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1391         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1392         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1393         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1394         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1395         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1396         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1397         rt2x00usb_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1398
1399         rt2x00usb_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1400         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1401         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
1402         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1403         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1404         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1405         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1406         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1407         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1408         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1409         rt2x00usb_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1410
1411         rt2x00usb_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1412         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1413         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1414         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1415         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1416         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1417         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1418         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1419         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1420         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1421         rt2x00usb_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1422
1423         rt2x00usb_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1424         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1425         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1426         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1427         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1428         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1429         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1430         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1431         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1432         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1433         rt2x00usb_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1434
1435         rt2x00usb_register_write(rt2x00dev, PBF_CFG, 0xf40006);
1436
1437         rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1438         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1439         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1440         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1441         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1442         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
1443         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
1444         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
1445         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
1446         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
1447         rt2x00usb_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1448
1449         rt2x00usb_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1450         rt2x00usb_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1451
1452         rt2x00usb_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1453         rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1454         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1455                            IEEE80211_MAX_RTS_THRESHOLD);
1456         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1457         rt2x00usb_register_write(rt2x00dev, TX_RTS_CFG, reg);
1458
1459         rt2x00usb_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1460         rt2x00usb_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1461
1462         /*
1463          * ASIC will keep garbage value after boot, clear encryption keys.
1464          */
1465         for (i = 0; i < 4; i++)
1466                 rt2x00usb_register_write(rt2x00dev,
1467                                          SHARED_KEY_MODE_ENTRY(i), 0);
1468
1469         for (i = 0; i < 256; i++) {
1470                 u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1471                 rt2x00usb_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1472                                               wcid, sizeof(wcid));
1473
1474                 rt2x00usb_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1475                 rt2x00usb_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1476         }
1477
1478         /*
1479          * Clear all beacons
1480          * For the Beacon base registers we only need to clear
1481          * the first byte since that byte contains the VALID and OWNER
1482          * bits which (when set to 0) will invalidate the entire beacon.
1483          */
1484         rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1485         rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1486         rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1487         rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1488         rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1489         rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1490         rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1491         rt2x00usb_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1492
1493         rt2x00usb_register_read(rt2x00dev, USB_CYC_CFG, &reg);
1494         rt2x00_set_field32(&reg, USB_CYC_CFG_CLOCK_CYCLE, 30);
1495         rt2x00usb_register_write(rt2x00dev, USB_CYC_CFG, reg);
1496
1497         rt2x00usb_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1498         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1499         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1500         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1501         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1502         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1503         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1504         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1505         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1506         rt2x00usb_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1507
1508         rt2x00usb_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1509         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1510         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1511         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1512         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1513         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1514         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1515         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1516         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1517         rt2x00usb_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1518
1519         rt2x00usb_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1520         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1521         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1522         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
1523         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
1524         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
1525         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
1526         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
1527         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
1528         rt2x00usb_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1529
1530         rt2x00usb_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1531         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1532         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1533         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1534         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1535         rt2x00usb_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1536
1537         /*
1538          * We must clear the error counters.
1539          * These registers are cleared on read,
1540          * so we may pass a useless variable to store the value.
1541          */
1542         rt2x00usb_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1543         rt2x00usb_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1544         rt2x00usb_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1545         rt2x00usb_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1546         rt2x00usb_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1547         rt2x00usb_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1548
1549         return 0;
1550 }
1551
1552 static int rt2800usb_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1553 {
1554         unsigned int i;
1555         u32 reg;
1556
1557         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1558                 rt2x00usb_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1559                 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1560                         return 0;
1561
1562                 udelay(REGISTER_BUSY_DELAY);
1563         }
1564
1565         ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1566         return -EACCES;
1567 }
1568
1569 static int rt2800usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1570 {
1571         unsigned int i;
1572         u8 value;
1573
1574         /*
1575          * BBP was enabled after firmware was loaded,
1576          * but we need to reactivate it now.
1577          */
1578         rt2x00usb_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1579         rt2x00usb_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1580         msleep(1);
1581
1582         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1583                 rt2800usb_bbp_read(rt2x00dev, 0, &value);
1584                 if ((value != 0xff) && (value != 0x00))
1585                         return 0;
1586                 udelay(REGISTER_BUSY_DELAY);
1587         }
1588
1589         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1590         return -EACCES;
1591 }
1592
1593 static int rt2800usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1594 {
1595         unsigned int i;
1596         u16 eeprom;
1597         u8 reg_id;
1598         u8 value;
1599
1600         if (unlikely(rt2800usb_wait_bbp_rf_ready(rt2x00dev) ||
1601                      rt2800usb_wait_bbp_ready(rt2x00dev)))
1602                 return -EACCES;
1603
1604         rt2800usb_bbp_write(rt2x00dev, 65, 0x2c);
1605         rt2800usb_bbp_write(rt2x00dev, 66, 0x38);
1606         rt2800usb_bbp_write(rt2x00dev, 69, 0x12);
1607         rt2800usb_bbp_write(rt2x00dev, 70, 0x0a);
1608         rt2800usb_bbp_write(rt2x00dev, 73, 0x10);
1609         rt2800usb_bbp_write(rt2x00dev, 81, 0x37);
1610         rt2800usb_bbp_write(rt2x00dev, 82, 0x62);
1611         rt2800usb_bbp_write(rt2x00dev, 83, 0x6a);
1612         rt2800usb_bbp_write(rt2x00dev, 84, 0x99);
1613         rt2800usb_bbp_write(rt2x00dev, 86, 0x00);
1614         rt2800usb_bbp_write(rt2x00dev, 91, 0x04);
1615         rt2800usb_bbp_write(rt2x00dev, 92, 0x00);
1616         rt2800usb_bbp_write(rt2x00dev, 103, 0x00);
1617         rt2800usb_bbp_write(rt2x00dev, 105, 0x05);
1618
1619         if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
1620                 rt2800usb_bbp_write(rt2x00dev, 69, 0x16);
1621                 rt2800usb_bbp_write(rt2x00dev, 73, 0x12);
1622         }
1623
1624         if (rt2x00_rev(&rt2x00dev->chip) > RT2860D_VERSION) {
1625                 rt2800usb_bbp_write(rt2x00dev, 84, 0x19);
1626         }
1627
1628         if (rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
1629                 rt2800usb_bbp_write(rt2x00dev, 70, 0x0a);
1630                 rt2800usb_bbp_write(rt2x00dev, 84, 0x99);
1631                 rt2800usb_bbp_write(rt2x00dev, 105, 0x05);
1632         }
1633
1634         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1635                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1636
1637                 if (eeprom != 0xffff && eeprom != 0x0000) {
1638                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1639                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1640                         rt2800usb_bbp_write(rt2x00dev, reg_id, value);
1641                 }
1642         }
1643
1644         return 0;
1645 }
1646
1647 static u8 rt2800usb_init_rx_filter(struct rt2x00_dev *rt2x00dev,
1648                                    bool bw40, u8 rfcsr24, u8 filter_target)
1649 {
1650         unsigned int i;
1651         u8 bbp;
1652         u8 rfcsr;
1653         u8 passband;
1654         u8 stopband;
1655         u8 overtuned = 0;
1656
1657         rt2800usb_rfcsr_write(rt2x00dev, 24, rfcsr24);
1658
1659         rt2800usb_bbp_read(rt2x00dev, 4, &bbp);
1660         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
1661         rt2800usb_bbp_write(rt2x00dev, 4, bbp);
1662
1663         rt2800usb_rfcsr_read(rt2x00dev, 22, &rfcsr);
1664         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
1665         rt2800usb_rfcsr_write(rt2x00dev, 22, rfcsr);
1666
1667         /*
1668          * Set power & frequency of passband test tone
1669          */
1670         rt2800usb_bbp_write(rt2x00dev, 24, 0);
1671
1672         for (i = 0; i < 100; i++) {
1673                 rt2800usb_bbp_write(rt2x00dev, 25, 0x90);
1674                 msleep(1);
1675
1676                 rt2800usb_bbp_read(rt2x00dev, 55, &passband);
1677                 if (passband)
1678                         break;
1679         }
1680
1681         /*
1682          * Set power & frequency of stopband test tone
1683          */
1684         rt2800usb_bbp_write(rt2x00dev, 24, 0x06);
1685
1686         for (i = 0; i < 100; i++) {
1687                 rt2800usb_bbp_write(rt2x00dev, 25, 0x90);
1688                 msleep(1);
1689
1690                 rt2800usb_bbp_read(rt2x00dev, 55, &stopband);
1691
1692                 if ((passband - stopband) <= filter_target) {
1693                         rfcsr24++;
1694                         overtuned += ((passband - stopband) == filter_target);
1695                 } else
1696                         break;
1697
1698                 rt2800usb_rfcsr_write(rt2x00dev, 24, rfcsr24);
1699         }
1700
1701         rfcsr24 -= !!overtuned;
1702
1703         rt2800usb_rfcsr_write(rt2x00dev, 24, rfcsr24);
1704         return rfcsr24;
1705 }
1706
1707 static int rt2800usb_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1708 {
1709         u8 rfcsr;
1710         u8 bbp;
1711
1712         if (rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
1713                 return 0;
1714
1715         /*
1716          * Init RF calibration.
1717          */
1718         rt2800usb_rfcsr_read(rt2x00dev, 30, &rfcsr);
1719         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1720         rt2800usb_rfcsr_write(rt2x00dev, 30, rfcsr);
1721         msleep(1);
1722         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1723         rt2800usb_rfcsr_write(rt2x00dev, 30, rfcsr);
1724
1725         rt2800usb_rfcsr_write(rt2x00dev, 4, 0x40);
1726         rt2800usb_rfcsr_write(rt2x00dev, 5, 0x03);
1727         rt2800usb_rfcsr_write(rt2x00dev, 6, 0x02);
1728         rt2800usb_rfcsr_write(rt2x00dev, 7, 0x70);
1729         rt2800usb_rfcsr_write(rt2x00dev, 9, 0x0f);
1730         rt2800usb_rfcsr_write(rt2x00dev, 10, 0x71);
1731         rt2800usb_rfcsr_write(rt2x00dev, 11, 0x21);
1732         rt2800usb_rfcsr_write(rt2x00dev, 12, 0x7b);
1733         rt2800usb_rfcsr_write(rt2x00dev, 14, 0x90);
1734         rt2800usb_rfcsr_write(rt2x00dev, 15, 0x58);
1735         rt2800usb_rfcsr_write(rt2x00dev, 16, 0xb3);
1736         rt2800usb_rfcsr_write(rt2x00dev, 17, 0x92);
1737         rt2800usb_rfcsr_write(rt2x00dev, 18, 0x2c);
1738         rt2800usb_rfcsr_write(rt2x00dev, 19, 0x02);
1739         rt2800usb_rfcsr_write(rt2x00dev, 20, 0xba);
1740         rt2800usb_rfcsr_write(rt2x00dev, 21, 0xdb);
1741         rt2800usb_rfcsr_write(rt2x00dev, 24, 0x16);
1742         rt2800usb_rfcsr_write(rt2x00dev, 25, 0x01);
1743         rt2800usb_rfcsr_write(rt2x00dev, 27, 0x03);
1744         rt2800usb_rfcsr_write(rt2x00dev, 29, 0x1f);
1745
1746         /*
1747          * Set RX Filter calibration for 20MHz and 40MHz
1748          */
1749         rt2x00dev->calibration[0] =
1750             rt2800usb_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
1751         rt2x00dev->calibration[1] =
1752             rt2800usb_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
1753
1754         /*
1755          * Set back to initial state
1756          */
1757         rt2800usb_bbp_write(rt2x00dev, 24, 0);
1758
1759         rt2800usb_rfcsr_read(rt2x00dev, 22, &rfcsr);
1760         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
1761         rt2800usb_rfcsr_write(rt2x00dev, 22, rfcsr);
1762
1763         /*
1764          * set BBP back to BW20
1765          */
1766         rt2800usb_bbp_read(rt2x00dev, 4, &bbp);
1767         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
1768         rt2800usb_bbp_write(rt2x00dev, 4, bbp);
1769
1770         return 0;
1771 }
1772
1773 /*
1774  * Device state switch handlers.
1775  */
1776 static void rt2800usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1777                                 enum dev_state state)
1778 {
1779         u32 reg;
1780
1781         rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1782         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
1783                            (state == STATE_RADIO_RX_ON) ||
1784                            (state == STATE_RADIO_RX_ON_LINK));
1785         rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1786 }
1787
1788 static int rt2800usb_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
1789 {
1790         unsigned int i;
1791         u32 reg;
1792
1793         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1794                 rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1795                 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
1796                     !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
1797                         return 0;
1798
1799                 msleep(1);
1800         }
1801
1802         ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
1803         return -EACCES;
1804 }
1805
1806 static int rt2800usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1807 {
1808         u32 reg;
1809         u16 word;
1810
1811         /*
1812          * Initialize all registers.
1813          */
1814         if (unlikely(rt2800usb_wait_wpdma_ready(rt2x00dev) ||
1815                      rt2800usb_init_registers(rt2x00dev) ||
1816                      rt2800usb_init_bbp(rt2x00dev) ||
1817                      rt2800usb_init_rfcsr(rt2x00dev)))
1818                 return -EIO;
1819
1820         rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1821         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
1822         rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1823
1824         udelay(50);
1825
1826         rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1827         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1828         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
1829         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
1830         rt2x00usb_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1831
1832
1833         rt2x00usb_register_read(rt2x00dev, USB_DMA_CFG, &reg);
1834         rt2x00_set_field32(&reg, USB_DMA_CFG_PHY_CLEAR, 0);
1835         /* Don't use bulk in aggregation when working with USB 1.1 */
1836         rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_EN,
1837                            (rt2x00dev->rx->usb_maxpacket == 512));
1838         rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_TIMEOUT, 128);
1839         /*
1840          * Total room for RX frames in kilobytes, PBF might still exceed
1841          * this limit so reduce the number to prevent errors.
1842          */
1843         rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_LIMIT,
1844                            ((RX_ENTRIES * DATA_FRAME_SIZE) / 1024) - 3);
1845         rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_EN, 1);
1846         rt2x00_set_field32(&reg, USB_DMA_CFG_TX_BULK_EN, 1);
1847         rt2x00usb_register_write(rt2x00dev, USB_DMA_CFG, reg);
1848
1849         rt2x00usb_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1850         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
1851         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
1852         rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1853
1854         /*
1855          * Initialize LED control
1856          */
1857         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
1858         rt2800usb_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
1859                               word & 0xff, (word >> 8) & 0xff);
1860
1861         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
1862         rt2800usb_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
1863                               word & 0xff, (word >> 8) & 0xff);
1864
1865         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
1866         rt2800usb_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
1867                               word & 0xff, (word >> 8) & 0xff);
1868
1869         return 0;
1870 }
1871
1872 static void rt2800usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1873 {
1874         u32 reg;
1875
1876         rt2x00usb_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1877         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1878         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1879         rt2x00usb_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1880
1881         rt2x00usb_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
1882         rt2x00usb_register_write(rt2x00dev, PWR_PIN_CFG, 0);
1883         rt2x00usb_register_write(rt2x00dev, TX_PIN_CFG, 0);
1884
1885         /* Wait for DMA, ignore error */
1886         rt2800usb_wait_wpdma_ready(rt2x00dev);
1887
1888         rt2x00usb_disable_radio(rt2x00dev);
1889 }
1890
1891 static int rt2800usb_set_state(struct rt2x00_dev *rt2x00dev,
1892                                enum dev_state state)
1893 {
1894         if (state == STATE_AWAKE)
1895                 rt2800usb_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
1896         else
1897                 rt2800usb_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
1898
1899         return 0;
1900 }
1901
1902 static int rt2800usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1903                                       enum dev_state state)
1904 {
1905         int retval = 0;
1906
1907         switch (state) {
1908         case STATE_RADIO_ON:
1909                 /*
1910                  * Before the radio can be enabled, the device first has
1911                  * to be woken up. After that it needs a bit of time
1912                  * to be fully awake and then the radio can be enabled.
1913                  */
1914                 rt2800usb_set_state(rt2x00dev, STATE_AWAKE);
1915                 msleep(1);
1916                 retval = rt2800usb_enable_radio(rt2x00dev);
1917                 break;
1918         case STATE_RADIO_OFF:
1919                 /*
1920                  * After the radio has been disabled, the device should
1921                  * be put to sleep for powersaving.
1922                  */
1923                 rt2800usb_disable_radio(rt2x00dev);
1924                 rt2800usb_set_state(rt2x00dev, STATE_SLEEP);
1925                 break;
1926         case STATE_RADIO_RX_ON:
1927         case STATE_RADIO_RX_ON_LINK:
1928         case STATE_RADIO_RX_OFF:
1929         case STATE_RADIO_RX_OFF_LINK:
1930                 rt2800usb_toggle_rx(rt2x00dev, state);
1931                 break;
1932         case STATE_RADIO_IRQ_ON:
1933         case STATE_RADIO_IRQ_OFF:
1934                 /* No support, but no error either */
1935                 break;
1936         case STATE_DEEP_SLEEP:
1937         case STATE_SLEEP:
1938         case STATE_STANDBY:
1939         case STATE_AWAKE:
1940                 retval = rt2800usb_set_state(rt2x00dev, state);
1941                 break;
1942         default:
1943                 retval = -ENOTSUPP;
1944                 break;
1945         }
1946
1947         if (unlikely(retval))
1948                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1949                       state, retval);
1950
1951         return retval;
1952 }
1953
1954 /*
1955  * TX descriptor initialization
1956  */
1957 static void rt2800usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1958                                     struct sk_buff *skb,
1959                                     struct txentry_desc *txdesc)
1960 {
1961         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1962         __le32 *txi = skbdesc->desc;
1963         __le32 *txwi = &txi[TXINFO_DESC_SIZE / sizeof(__le32)];
1964         u32 word;
1965
1966         /*
1967          * Initialize TX Info descriptor
1968          */
1969         rt2x00_desc_read(txwi, 0, &word);
1970         rt2x00_set_field32(&word, TXWI_W0_FRAG,
1971                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1972         rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
1973         rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
1974         rt2x00_set_field32(&word, TXWI_W0_TS,
1975                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1976         rt2x00_set_field32(&word, TXWI_W0_AMPDU,
1977                            test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
1978         rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
1979         rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->ifs);
1980         rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
1981         rt2x00_set_field32(&word, TXWI_W0_BW,
1982                            test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
1983         rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
1984                            test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
1985         rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
1986         rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
1987         rt2x00_desc_write(txwi, 0, word);
1988
1989         rt2x00_desc_read(txwi, 1, &word);
1990         rt2x00_set_field32(&word, TXWI_W1_ACK,
1991                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1992         rt2x00_set_field32(&word, TXWI_W1_NSEQ,
1993                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
1994         rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
1995         rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
1996                            test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
1997                            txdesc->key_idx : 0xff);
1998         rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
1999                            skb->len - txdesc->l2pad);
2000         rt2x00_set_field32(&word, TXWI_W1_PACKETID,
2001                            skbdesc->entry->queue->qid + 1);
2002         rt2x00_desc_write(txwi, 1, word);
2003
2004         /*
2005          * Always write 0 to IV/EIV fields, hardware will insert the IV
2006          * from the IVEIV register when TXINFO_W0_WIV is set to 0.
2007          * When TXINFO_W0_WIV is set to 1 it will use the IV data
2008          * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
2009          * crypto entry in the registers should be used to encrypt the frame.
2010          */
2011         _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
2012         _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
2013
2014         /*
2015          * Initialize TX descriptor
2016          */
2017         rt2x00_desc_read(txi, 0, &word);
2018         rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_TX_PKT_LEN,
2019                            skb->len + TXWI_DESC_SIZE);
2020         rt2x00_set_field32(&word, TXINFO_W0_WIV,
2021                            !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
2022         rt2x00_set_field32(&word, TXINFO_W0_QSEL, 2);
2023         rt2x00_set_field32(&word, TXINFO_W0_SW_USE_LAST_ROUND, 0);
2024         rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_NEXT_VALID, 0);
2025         rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_TX_BURST,
2026                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
2027         rt2x00_desc_write(txi, 0, word);
2028 }
2029
2030 /*
2031  * TX data initialization
2032  */
2033 static void rt2800usb_write_beacon(struct queue_entry *entry)
2034 {
2035         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2036         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
2037         unsigned int beacon_base;
2038         u32 reg;
2039
2040         /*
2041          * Add the descriptor in front of the skb.
2042          */
2043         skb_push(entry->skb, entry->queue->desc_size);
2044         memcpy(entry->skb->data, skbdesc->desc, skbdesc->desc_len);
2045         skbdesc->desc = entry->skb->data;
2046
2047         /*
2048          * Disable beaconing while we are reloading the beacon data,
2049          * otherwise we might be sending out invalid data.
2050          */
2051         rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2052         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
2053         rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2054
2055         /*
2056          * Write entire beacon with descriptor to register.
2057          */
2058         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
2059         rt2x00usb_vendor_request_large_buff(rt2x00dev, USB_MULTI_WRITE,
2060                                             USB_VENDOR_REQUEST_OUT, beacon_base,
2061                                             entry->skb->data, entry->skb->len,
2062                                             REGISTER_TIMEOUT32(entry->skb->len));
2063
2064         /*
2065          * Clean up the beacon skb.
2066          */
2067         dev_kfree_skb(entry->skb);
2068         entry->skb = NULL;
2069 }
2070
2071 static int rt2800usb_get_tx_data_len(struct queue_entry *entry)
2072 {
2073         int length;
2074
2075         /*
2076          * The length _must_ include 4 bytes padding,
2077          * it should always be multiple of 4,
2078          * but it must _not_ be a multiple of the USB packet size.
2079          */
2080         length = roundup(entry->skb->len + 4, 4);
2081         length += (4 * !(length % entry->queue->usb_maxpacket));
2082
2083         return length;
2084 }
2085
2086 static void rt2800usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
2087                                     const enum data_queue_qid queue)
2088 {
2089         u32 reg;
2090
2091         if (queue != QID_BEACON) {
2092                 rt2x00usb_kick_tx_queue(rt2x00dev, queue);
2093                 return;
2094         }
2095
2096         rt2x00usb_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2097         if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
2098                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
2099                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
2100                 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
2101                 rt2x00usb_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2102         }
2103 }
2104
2105 /*
2106  * RX control handlers
2107  */
2108 static void rt2800usb_fill_rxdone(struct queue_entry *entry,
2109                                   struct rxdone_entry_desc *rxdesc)
2110 {
2111         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2112         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
2113         __le32 *rxd = (__le32 *)entry->skb->data;
2114         __le32 *rxwi;
2115         u32 rxd0;
2116         u32 rxwi0;
2117         u32 rxwi1;
2118         u32 rxwi2;
2119         u32 rxwi3;
2120
2121         /*
2122          * Copy descriptor to the skbdesc->desc buffer, making it safe from
2123          * moving of frame data in rt2x00usb.
2124          */
2125         memcpy(skbdesc->desc, rxd, skbdesc->desc_len);
2126         rxd = (__le32 *)skbdesc->desc;
2127         rxwi = &rxd[RXD_DESC_SIZE / sizeof(__le32)];
2128
2129         /*
2130          * It is now safe to read the descriptor on all architectures.
2131          */
2132         rt2x00_desc_read(rxd, 0, &rxd0);
2133         rt2x00_desc_read(rxwi, 0, &rxwi0);
2134         rt2x00_desc_read(rxwi, 1, &rxwi1);
2135         rt2x00_desc_read(rxwi, 2, &rxwi2);
2136         rt2x00_desc_read(rxwi, 3, &rxwi3);
2137
2138         if (rt2x00_get_field32(rxd0, RXD_W0_CRC_ERROR))
2139                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
2140
2141         if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
2142                 rxdesc->cipher = rt2x00_get_field32(rxwi0, RXWI_W0_UDF);
2143                 rxdesc->cipher_status =
2144                     rt2x00_get_field32(rxd0, RXD_W0_CIPHER_ERROR);
2145         }
2146
2147         if (rt2x00_get_field32(rxd0, RXD_W0_DECRYPTED)) {
2148                 /*
2149                  * Hardware has stripped IV/EIV data from 802.11 frame during
2150                  * decryption. Unfortunately the descriptor doesn't contain
2151                  * any fields with the EIV/IV data either, so they can't
2152                  * be restored by rt2x00lib.
2153                  */
2154                 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
2155
2156                 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
2157                         rxdesc->flags |= RX_FLAG_DECRYPTED;
2158                 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
2159                         rxdesc->flags |= RX_FLAG_MMIC_ERROR;
2160         }
2161
2162         if (rt2x00_get_field32(rxd0, RXD_W0_MY_BSS))
2163                 rxdesc->dev_flags |= RXDONE_MY_BSS;
2164
2165         if (rt2x00_get_field32(rxd0, RXD_W0_L2PAD)) {
2166                 rxdesc->dev_flags |= RXDONE_L2PAD;
2167                 skbdesc->flags |= SKBDESC_L2_PADDED;
2168         }
2169
2170         if (rt2x00_get_field32(rxwi1, RXWI_W1_SHORT_GI))
2171                 rxdesc->flags |= RX_FLAG_SHORT_GI;
2172
2173         if (rt2x00_get_field32(rxwi1, RXWI_W1_BW))
2174                 rxdesc->flags |= RX_FLAG_40MHZ;
2175
2176         /*
2177          * Detect RX rate, always use MCS as signal type.
2178          */
2179         rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
2180         rxdesc->rate_mode = rt2x00_get_field32(rxwi1, RXWI_W1_PHYMODE);
2181         rxdesc->signal = rt2x00_get_field32(rxwi1, RXWI_W1_MCS);
2182
2183         /*
2184          * Mask of 0x8 bit to remove the short preamble flag.
2185          */
2186         if (rxdesc->rate_mode == RATE_MODE_CCK)
2187                 rxdesc->signal &= ~0x8;
2188
2189         rxdesc->rssi =
2190             (rt2x00_get_field32(rxwi2, RXWI_W2_RSSI0) +
2191              rt2x00_get_field32(rxwi2, RXWI_W2_RSSI1)) / 2;
2192
2193         rxdesc->noise =
2194             (rt2x00_get_field32(rxwi3, RXWI_W3_SNR0) +
2195              rt2x00_get_field32(rxwi3, RXWI_W3_SNR1)) / 2;
2196
2197         rxdesc->size = rt2x00_get_field32(rxwi0, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
2198
2199         /*
2200          * Remove RXWI descriptor from start of buffer.
2201          */
2202         skb_pull(entry->skb, skbdesc->desc_len);
2203         skb_trim(entry->skb, rxdesc->size);
2204 }
2205
2206 /*
2207  * Device probe functions.
2208  */
2209 static int rt2800usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2210 {
2211         u16 word;
2212         u8 *mac;
2213         u8 default_lna_gain;
2214
2215         rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
2216
2217         /*
2218          * Start validation of the data that has been read.
2219          */
2220         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2221         if (!is_valid_ether_addr(mac)) {
2222                 random_ether_addr(mac);
2223                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
2224         }
2225
2226         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2227         if (word == 0xffff) {
2228                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2229                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
2230                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
2231                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2232                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2233         } else if (rt2x00_rev(&rt2x00dev->chip) < RT2883_VERSION) {
2234                 /*
2235                  * There is a max of 2 RX streams for RT2870 series
2236                  */
2237                 if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
2238                         rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2239                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2240         }
2241
2242         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2243         if (word == 0xffff) {
2244                 rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
2245                 rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
2246                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2247                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2248                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2249                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
2250                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
2251                 rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
2252                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
2253                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
2254                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2255                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2256         }
2257
2258         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2259         if ((word & 0x00ff) == 0x00ff) {
2260                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2261                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2262                                    LED_MODE_TXRX_ACTIVITY);
2263                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2264                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2265                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
2266                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
2267                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
2268                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2269         }
2270
2271         /*
2272          * During the LNA validation we are going to use
2273          * lna0 as correct value. Note that EEPROM_LNA
2274          * is never validated.
2275          */
2276         rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2277         default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2278
2279         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2280         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2281                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2282         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2283                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2284         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2285
2286         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2287         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2288                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2289         if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2290             rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2291                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2292                                    default_lna_gain);
2293         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2294
2295         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2296         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2297                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2298         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2299                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2300         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2301
2302         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2303         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2304                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2305         if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2306             rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2307                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2308                                    default_lna_gain);
2309         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2310
2311         return 0;
2312 }
2313
2314 static int rt2800usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
2315 {
2316         u32 reg;
2317         u16 value;
2318         u16 eeprom;
2319
2320         /*
2321          * Read EEPROM word for configuration.
2322          */
2323         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2324
2325         /*
2326          * Identify RF chipset.
2327          */
2328         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2329         rt2x00usb_register_read(rt2x00dev, MAC_CSR0, &reg);
2330         rt2x00_set_chip(rt2x00dev, RT2870, value, reg);
2331
2332         /*
2333          * The check for rt2860 is not a typo, some rt2870 hardware
2334          * identifies itself as rt2860 in the CSR register.
2335          */
2336         if (!rt2x00_check_rev(&rt2x00dev->chip, 0xfff00000, 0x28600000) &&
2337             !rt2x00_check_rev(&rt2x00dev->chip, 0xfff00000, 0x28700000) &&
2338             !rt2x00_check_rev(&rt2x00dev->chip, 0xfff00000, 0x28800000) &&
2339             !rt2x00_check_rev(&rt2x00dev->chip, 0xffff0000, 0x30700000)) {
2340                 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
2341                 return -ENODEV;
2342         }
2343
2344         if (!rt2x00_rf(&rt2x00dev->chip, RF2820) &&
2345             !rt2x00_rf(&rt2x00dev->chip, RF2850) &&
2346             !rt2x00_rf(&rt2x00dev->chip, RF2720) &&
2347             !rt2x00_rf(&rt2x00dev->chip, RF2750) &&
2348             !rt2x00_rf(&rt2x00dev->chip, RF3020) &&
2349             !rt2x00_rf(&rt2x00dev->chip, RF2020)) {
2350                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2351                 return -ENODEV;
2352         }
2353
2354         /*
2355          * Identify default antenna configuration.
2356          */
2357         rt2x00dev->default_ant.tx =
2358             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH);
2359         rt2x00dev->default_ant.rx =
2360             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH);
2361
2362         /*
2363          * Read frequency offset and RF programming sequence.
2364          */
2365         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2366         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2367
2368         /*
2369          * Read external LNA informations.
2370          */
2371         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2372
2373         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2374                 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2375         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2376                 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2377
2378         /*
2379          * Detect if this device has an hardware controlled radio.
2380          */
2381         if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
2382                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2383
2384         /*
2385          * Store led settings, for correct led behaviour.
2386          */
2387 #ifdef CONFIG_RT2X00_LIB_LEDS
2388         rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2389         rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2390         rt2800usb_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2391
2392         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ,
2393                            &rt2x00dev->led_mcu_reg);
2394 #endif /* CONFIG_RT2X00_LIB_LEDS */
2395
2396         return 0;
2397 }
2398
2399 /*
2400  * RF value list for rt2870
2401  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2402  */
2403 static const struct rf_channel rf_vals[] = {
2404         { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2405         { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2406         { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2407         { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2408         { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2409         { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2410         { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2411         { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2412         { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2413         { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2414         { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2415         { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2416         { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2417         { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2418
2419         /* 802.11 UNI / HyperLan 2 */
2420         { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2421         { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2422         { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2423         { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2424         { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2425         { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2426         { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2427         { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2428         { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2429         { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2430         { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2431         { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2432
2433         /* 802.11 HyperLan 2 */
2434         { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2435         { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
2436         { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
2437         { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
2438         { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2439         { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2440         { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2441         { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2442         { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2443         { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2444         { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2445         { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2446         { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2447         { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2448         { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2449         { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2450
2451         /* 802.11 UNII */
2452         { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2453         { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2454         { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2455         { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2456         { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2457         { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2458         { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2459         { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
2460         { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
2461         { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
2462         { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
2463
2464         /* 802.11 Japan */
2465         { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2466         { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2467         { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2468         { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2469         { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2470         { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2471         { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2472 };
2473
2474 /*
2475  * RF value list for rt3070
2476  * Supports: 2.4 GHz
2477  */
2478 static const struct rf_channel rf_vals_3070[] = {
2479         {1,  241, 2, 2 },
2480         {2,  241, 2, 7 },
2481         {3,  242, 2, 2 },
2482         {4,  242, 2, 7 },
2483         {5,  243, 2, 2 },
2484         {6,  243, 2, 7 },
2485         {7,  244, 2, 2 },
2486         {8,  244, 2, 7 },
2487         {9,  245, 2, 2 },
2488         {10, 245, 2, 7 },
2489         {11, 246, 2, 2 },
2490         {12, 246, 2, 7 },
2491         {13, 247, 2, 2 },
2492         {14, 248, 2, 4 },
2493 };
2494
2495 static int rt2800usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2496 {
2497         struct hw_mode_spec *spec = &rt2x00dev->spec;
2498         struct channel_info *info;
2499         char *tx_power1;
2500         char *tx_power2;
2501         unsigned int i;
2502         u16 eeprom;
2503
2504         /*
2505          * Initialize all hw fields.
2506          */
2507         rt2x00dev->hw->flags =
2508             IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2509             IEEE80211_HW_SIGNAL_DBM |
2510             IEEE80211_HW_SUPPORTS_PS |
2511             IEEE80211_HW_PS_NULLFUNC_STACK;
2512         rt2x00dev->hw->extra_tx_headroom = TXINFO_DESC_SIZE + TXWI_DESC_SIZE;
2513
2514         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2515         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2516                                 rt2x00_eeprom_addr(rt2x00dev,
2517                                                    EEPROM_MAC_ADDR_0));
2518
2519         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2520
2521         /*
2522          * Initialize HT information.
2523          */
2524         spec->ht.ht_supported = true;
2525         spec->ht.cap =
2526             IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
2527             IEEE80211_HT_CAP_GRN_FLD |
2528             IEEE80211_HT_CAP_SGI_20 |
2529             IEEE80211_HT_CAP_SGI_40 |
2530             IEEE80211_HT_CAP_TX_STBC |
2531             IEEE80211_HT_CAP_RX_STBC |
2532             IEEE80211_HT_CAP_PSMP_SUPPORT;
2533         spec->ht.ampdu_factor = 3;
2534         spec->ht.ampdu_density = 4;
2535         spec->ht.mcs.tx_params =
2536             IEEE80211_HT_MCS_TX_DEFINED |
2537             IEEE80211_HT_MCS_TX_RX_DIFF |
2538             ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
2539                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
2540
2541         switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
2542         case 3:
2543                 spec->ht.mcs.rx_mask[2] = 0xff;
2544         case 2:
2545                 spec->ht.mcs.rx_mask[1] = 0xff;
2546         case 1:
2547                 spec->ht.mcs.rx_mask[0] = 0xff;
2548                 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
2549                 break;
2550         }
2551
2552         /*
2553          * Initialize hw_mode information.
2554          */
2555         spec->supported_bands = SUPPORT_BAND_2GHZ;
2556         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2557
2558         if (rt2x00_rf(&rt2x00dev->chip, RF2820) ||
2559             rt2x00_rf(&rt2x00dev->chip, RF2720)) {
2560                 spec->num_channels = 14;
2561                 spec->channels = rf_vals;
2562         } else if (rt2x00_rf(&rt2x00dev->chip, RF2850) ||
2563                    rt2x00_rf(&rt2x00dev->chip, RF2750)) {
2564                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2565                 spec->num_channels = ARRAY_SIZE(rf_vals);
2566                 spec->channels = rf_vals;
2567         } else if (rt2x00_rf(&rt2x00dev->chip, RF3020) ||
2568                    rt2x00_rf(&rt2x00dev->chip, RF2020)) {
2569                 spec->num_channels = ARRAY_SIZE(rf_vals_3070);
2570                 spec->channels = rf_vals_3070;
2571         }
2572
2573         /*
2574          * Create channel information array
2575          */
2576         info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2577         if (!info)
2578                 return -ENOMEM;
2579
2580         spec->channels_info = info;
2581
2582         tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2583         tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2584
2585         for (i = 0; i < 14; i++) {
2586                 info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
2587                 info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
2588         }
2589
2590         if (spec->num_channels > 14) {
2591                 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2592                 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2593
2594                 for (i = 14; i < spec->num_channels; i++) {
2595                         info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
2596                         info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
2597                 }
2598         }
2599
2600         return 0;
2601 }
2602
2603 static int rt2800usb_probe_hw(struct rt2x00_dev *rt2x00dev)
2604 {
2605         int retval;
2606
2607         /*
2608          * Allocate eeprom data.
2609          */
2610         retval = rt2800usb_validate_eeprom(rt2x00dev);
2611         if (retval)
2612                 return retval;
2613
2614         retval = rt2800usb_init_eeprom(rt2x00dev);
2615         if (retval)
2616                 return retval;
2617
2618         /*
2619          * Initialize hw specifications.
2620          */
2621         retval = rt2800usb_probe_hw_mode(rt2x00dev);
2622         if (retval)
2623                 return retval;
2624
2625         /*
2626          * This device has multiple filters for control frames
2627          * and has a separate filter for PS Poll frames.
2628          */
2629         __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
2630         __set_bit(DRIVER_SUPPORT_CONTROL_FILTER_PSPOLL, &rt2x00dev->flags);
2631
2632         /*
2633          * This device requires firmware.
2634          */
2635         __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2636         __set_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags);
2637         if (!modparam_nohwcrypt)
2638                 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2639
2640         /*
2641          * Set the rssi offset.
2642          */
2643         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2644
2645         return 0;
2646 }
2647
2648 /*
2649  * IEEE80211 stack callback functions.
2650  */
2651 static void rt2800usb_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
2652                                    u32 *iv32, u16 *iv16)
2653 {
2654         struct rt2x00_dev *rt2x00dev = hw->priv;
2655         struct mac_iveiv_entry iveiv_entry;
2656         u32 offset;
2657
2658         offset = MAC_IVEIV_ENTRY(hw_key_idx);
2659         rt2x00usb_register_multiread(rt2x00dev, offset,
2660                                       &iveiv_entry, sizeof(iveiv_entry));
2661
2662         memcpy(&iveiv_entry.iv[0], iv16, sizeof(iv16));
2663         memcpy(&iveiv_entry.iv[4], iv32, sizeof(iv32));
2664 }
2665
2666 static int rt2800usb_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2667 {
2668         struct rt2x00_dev *rt2x00dev = hw->priv;
2669         u32 reg;
2670         bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
2671
2672         rt2x00usb_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2673         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
2674         rt2x00usb_register_write(rt2x00dev, TX_RTS_CFG, reg);
2675
2676         rt2x00usb_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2677         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
2678         rt2x00usb_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2679
2680         rt2x00usb_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2681         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
2682         rt2x00usb_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2683
2684         rt2x00usb_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2685         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
2686         rt2x00usb_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2687
2688         rt2x00usb_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2689         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
2690         rt2x00usb_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2691
2692         rt2x00usb_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2693         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
2694         rt2x00usb_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2695
2696         rt2x00usb_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2697         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
2698         rt2x00usb_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2699
2700         return 0;
2701 }
2702
2703 static int rt2800usb_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2704                              const struct ieee80211_tx_queue_params *params)
2705 {
2706         struct rt2x00_dev *rt2x00dev = hw->priv;
2707         struct data_queue *queue;
2708         struct rt2x00_field32 field;
2709         int retval;
2710         u32 reg;
2711         u32 offset;
2712
2713         /*
2714          * First pass the configuration through rt2x00lib, that will
2715          * update the queue settings and validate the input. After that
2716          * we are free to update the registers based on the value
2717          * in the queue parameter.
2718          */
2719         retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2720         if (retval)
2721                 return retval;
2722
2723         /*
2724          * We only need to perform additional register initialization
2725          * for WMM queues/
2726          */
2727         if (queue_idx >= 4)
2728                 return 0;
2729
2730         queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2731
2732         /* Update WMM TXOP register */
2733         offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
2734         field.bit_offset = (queue_idx & 1) * 16;
2735         field.bit_mask = 0xffff << field.bit_offset;
2736
2737         rt2x00usb_register_read(rt2x00dev, offset, &reg);
2738         rt2x00_set_field32(&reg, field, queue->txop);
2739         rt2x00usb_register_write(rt2x00dev, offset, reg);
2740
2741         /* Update WMM registers */
2742         field.bit_offset = queue_idx * 4;
2743         field.bit_mask = 0xf << field.bit_offset;
2744
2745         rt2x00usb_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
2746         rt2x00_set_field32(&reg, field, queue->aifs);
2747         rt2x00usb_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
2748
2749         rt2x00usb_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
2750         rt2x00_set_field32(&reg, field, queue->cw_min);
2751         rt2x00usb_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
2752
2753         rt2x00usb_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
2754         rt2x00_set_field32(&reg, field, queue->cw_max);
2755         rt2x00usb_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
2756
2757         /* Update EDCA registers */
2758         offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
2759
2760         rt2x00usb_register_read(rt2x00dev, offset, &reg);
2761         rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
2762         rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
2763         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
2764         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
2765         rt2x00usb_register_write(rt2x00dev, offset, reg);
2766
2767         return 0;
2768 }
2769
2770 static u64 rt2800usb_get_tsf(struct ieee80211_hw *hw)
2771 {
2772         struct rt2x00_dev *rt2x00dev = hw->priv;
2773         u64 tsf;
2774         u32 reg;
2775
2776         rt2x00usb_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
2777         tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
2778         rt2x00usb_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
2779         tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
2780
2781         return tsf;
2782 }
2783
2784 static const struct ieee80211_ops rt2800usb_mac80211_ops = {
2785         .tx                     = rt2x00mac_tx,
2786         .start                  = rt2x00mac_start,
2787         .stop                   = rt2x00mac_stop,
2788         .add_interface          = rt2x00mac_add_interface,
2789         .remove_interface       = rt2x00mac_remove_interface,
2790         .config                 = rt2x00mac_config,
2791         .configure_filter       = rt2x00mac_configure_filter,
2792         .set_tim                = rt2x00mac_set_tim,
2793         .set_key                = rt2x00mac_set_key,
2794         .get_stats              = rt2x00mac_get_stats,
2795         .get_tkip_seq           = rt2800usb_get_tkip_seq,
2796         .set_rts_threshold      = rt2800usb_set_rts_threshold,
2797         .bss_info_changed       = rt2x00mac_bss_info_changed,
2798         .conf_tx                = rt2800usb_conf_tx,
2799         .get_tx_stats           = rt2x00mac_get_tx_stats,
2800         .get_tsf                = rt2800usb_get_tsf,
2801         .rfkill_poll            = rt2x00mac_rfkill_poll,
2802 };
2803
2804 static const struct rt2x00lib_ops rt2800usb_rt2x00_ops = {
2805         .probe_hw               = rt2800usb_probe_hw,
2806         .get_firmware_name      = rt2800usb_get_firmware_name,
2807         .check_firmware         = rt2800usb_check_firmware,
2808         .load_firmware          = rt2800usb_load_firmware,
2809         .initialize             = rt2x00usb_initialize,
2810         .uninitialize           = rt2x00usb_uninitialize,
2811         .clear_entry            = rt2x00usb_clear_entry,
2812         .set_device_state       = rt2800usb_set_device_state,
2813         .rfkill_poll            = rt2800usb_rfkill_poll,
2814         .link_stats             = rt2800usb_link_stats,
2815         .reset_tuner            = rt2800usb_reset_tuner,
2816         .link_tuner             = rt2800usb_link_tuner,
2817         .write_tx_desc          = rt2800usb_write_tx_desc,
2818         .write_tx_data          = rt2x00usb_write_tx_data,
2819         .write_beacon           = rt2800usb_write_beacon,
2820         .get_tx_data_len        = rt2800usb_get_tx_data_len,
2821         .kick_tx_queue          = rt2800usb_kick_tx_queue,
2822         .kill_tx_queue          = rt2x00usb_kill_tx_queue,
2823         .fill_rxdone            = rt2800usb_fill_rxdone,
2824         .config_shared_key      = rt2800usb_config_shared_key,
2825         .config_pairwise_key    = rt2800usb_config_pairwise_key,
2826         .config_filter          = rt2800usb_config_filter,
2827         .config_intf            = rt2800usb_config_intf,
2828         .config_erp             = rt2800usb_config_erp,
2829         .config_ant             = rt2800usb_config_ant,
2830         .config                 = rt2800usb_config,
2831 };
2832
2833 static const struct data_queue_desc rt2800usb_queue_rx = {
2834         .entry_num              = RX_ENTRIES,
2835         .data_size              = AGGREGATION_SIZE,
2836         .desc_size              = RXD_DESC_SIZE + RXWI_DESC_SIZE,
2837         .priv_size              = sizeof(struct queue_entry_priv_usb),
2838 };
2839
2840 static const struct data_queue_desc rt2800usb_queue_tx = {
2841         .entry_num              = TX_ENTRIES,
2842         .data_size              = AGGREGATION_SIZE,
2843         .desc_size              = TXINFO_DESC_SIZE + TXWI_DESC_SIZE,
2844         .priv_size              = sizeof(struct queue_entry_priv_usb),
2845 };
2846
2847 static const struct data_queue_desc rt2800usb_queue_bcn = {
2848         .entry_num              = 8 * BEACON_ENTRIES,
2849         .data_size              = MGMT_FRAME_SIZE,
2850         .desc_size              = TXINFO_DESC_SIZE + TXWI_DESC_SIZE,
2851         .priv_size              = sizeof(struct queue_entry_priv_usb),
2852 };
2853
2854 static const struct rt2x00_ops rt2800usb_ops = {
2855         .name           = KBUILD_MODNAME,
2856         .max_sta_intf   = 1,
2857         .max_ap_intf    = 8,
2858         .eeprom_size    = EEPROM_SIZE,
2859         .rf_size        = RF_SIZE,
2860         .tx_queues      = NUM_TX_QUEUES,
2861         .rx             = &rt2800usb_queue_rx,
2862         .tx             = &rt2800usb_queue_tx,
2863         .bcn            = &rt2800usb_queue_bcn,
2864         .lib            = &rt2800usb_rt2x00_ops,
2865         .hw             = &rt2800usb_mac80211_ops,
2866 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2867         .debugfs        = &rt2800usb_rt2x00debug,
2868 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2869 };
2870
2871 /*
2872  * rt2800usb module information.
2873  */
2874 static struct usb_device_id rt2800usb_device_table[] = {
2875         /* Abocom */
2876         { USB_DEVICE(0x07b8, 0x2870), USB_DEVICE_DATA(&rt2800usb_ops) },
2877         { USB_DEVICE(0x07b8, 0x2770), USB_DEVICE_DATA(&rt2800usb_ops) },
2878         { USB_DEVICE(0x07b8, 0x3070), USB_DEVICE_DATA(&rt2800usb_ops) },
2879         { USB_DEVICE(0x07b8, 0x3071), USB_DEVICE_DATA(&rt2800usb_ops) },
2880         { USB_DEVICE(0x07b8, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
2881         { USB_DEVICE(0x1482, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
2882         /* AirTies */
2883         { USB_DEVICE(0x1eda, 0x2310), USB_DEVICE_DATA(&rt2800usb_ops) },
2884         /* Amigo */
2885         { USB_DEVICE(0x0e0b, 0x9031), USB_DEVICE_DATA(&rt2800usb_ops) },
2886         { USB_DEVICE(0x0e0b, 0x9041), USB_DEVICE_DATA(&rt2800usb_ops) },
2887         /* Amit */
2888         { USB_DEVICE(0x15c5, 0x0008), USB_DEVICE_DATA(&rt2800usb_ops) },
2889         /* ASUS */
2890         { USB_DEVICE(0x0b05, 0x1731), USB_DEVICE_DATA(&rt2800usb_ops) },
2891         { USB_DEVICE(0x0b05, 0x1732), USB_DEVICE_DATA(&rt2800usb_ops) },
2892         { USB_DEVICE(0x0b05, 0x1742), USB_DEVICE_DATA(&rt2800usb_ops) },
2893         { USB_DEVICE(0x0b05, 0x1760), USB_DEVICE_DATA(&rt2800usb_ops) },
2894         { USB_DEVICE(0x0b05, 0x1761), USB_DEVICE_DATA(&rt2800usb_ops) },
2895         /* AzureWave */
2896         { USB_DEVICE(0x13d3, 0x3247), USB_DEVICE_DATA(&rt2800usb_ops) },
2897         { USB_DEVICE(0x13d3, 0x3262), USB_DEVICE_DATA(&rt2800usb_ops) },
2898         { USB_DEVICE(0x13d3, 0x3273), USB_DEVICE_DATA(&rt2800usb_ops) },
2899         { USB_DEVICE(0x13d3, 0x3284), USB_DEVICE_DATA(&rt2800usb_ops) },
2900         /* Belkin */
2901         { USB_DEVICE(0x050d, 0x8053), USB_DEVICE_DATA(&rt2800usb_ops) },
2902         { USB_DEVICE(0x050d, 0x805c), USB_DEVICE_DATA(&rt2800usb_ops) },
2903         { USB_DEVICE(0x050d, 0x815c), USB_DEVICE_DATA(&rt2800usb_ops) },
2904         { USB_DEVICE(0x050d, 0x825a), USB_DEVICE_DATA(&rt2800usb_ops) },
2905         /* Buffalo */
2906         { USB_DEVICE(0x0411, 0x00e8), USB_DEVICE_DATA(&rt2800usb_ops) },
2907         { USB_DEVICE(0x0411, 0x012e), USB_DEVICE_DATA(&rt2800usb_ops) },
2908         /* Conceptronic */
2909         { USB_DEVICE(0x14b2, 0x3c06), USB_DEVICE_DATA(&rt2800usb_ops) },
2910         { USB_DEVICE(0x14b2, 0x3c07), USB_DEVICE_DATA(&rt2800usb_ops) },
2911         { USB_DEVICE(0x14b2, 0x3c08), USB_DEVICE_DATA(&rt2800usb_ops) },
2912         { USB_DEVICE(0x14b2, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
2913         { USB_DEVICE(0x14b2, 0x3c11), USB_DEVICE_DATA(&rt2800usb_ops) },
2914         { USB_DEVICE(0x14b2, 0x3c12), USB_DEVICE_DATA(&rt2800usb_ops) },
2915         { USB_DEVICE(0x14b2, 0x3c23), USB_DEVICE_DATA(&rt2800usb_ops) },
2916         { USB_DEVICE(0x14b2, 0x3c25), USB_DEVICE_DATA(&rt2800usb_ops) },
2917         { USB_DEVICE(0x14b2, 0x3c27), USB_DEVICE_DATA(&rt2800usb_ops) },
2918         { USB_DEVICE(0x14b2, 0x3c28), USB_DEVICE_DATA(&rt2800usb_ops) },
2919         /* Corega */
2920         { USB_DEVICE(0x07aa, 0x002f), USB_DEVICE_DATA(&rt2800usb_ops) },
2921         { USB_DEVICE(0x07aa, 0x003c), USB_DEVICE_DATA(&rt2800usb_ops) },
2922         { USB_DEVICE(0x07aa, 0x003f), USB_DEVICE_DATA(&rt2800usb_ops) },
2923         { USB_DEVICE(0x18c5, 0x0008), USB_DEVICE_DATA(&rt2800usb_ops) },
2924         { USB_DEVICE(0x18c5, 0x0012), USB_DEVICE_DATA(&rt2800usb_ops) },
2925         /* D-Link */
2926         { USB_DEVICE(0x07d1, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
2927         { USB_DEVICE(0x07d1, 0x3c0a), USB_DEVICE_DATA(&rt2800usb_ops) },
2928         { USB_DEVICE(0x07d1, 0x3c0b), USB_DEVICE_DATA(&rt2800usb_ops) },
2929         { USB_DEVICE(0x07d1, 0x3c0d), USB_DEVICE_DATA(&rt2800usb_ops) },
2930         { USB_DEVICE(0x07d1, 0x3c0e), USB_DEVICE_DATA(&rt2800usb_ops) },
2931         { USB_DEVICE(0x07d1, 0x3c0f), USB_DEVICE_DATA(&rt2800usb_ops) },
2932         { USB_DEVICE(0x07d1, 0x3c11), USB_DEVICE_DATA(&rt2800usb_ops) },
2933         { USB_DEVICE(0x07d1, 0x3c13), USB_DEVICE_DATA(&rt2800usb_ops) },
2934         /* Edimax */
2935         { USB_DEVICE(0x7392, 0x7711), USB_DEVICE_DATA(&rt2800usb_ops) },
2936         { USB_DEVICE(0x7392, 0x7717), USB_DEVICE_DATA(&rt2800usb_ops) },
2937         { USB_DEVICE(0x7392, 0x7718), USB_DEVICE_DATA(&rt2800usb_ops) },
2938         /* Encore */
2939         { USB_DEVICE(0x203d, 0x1480), USB_DEVICE_DATA(&rt2800usb_ops) },
2940         /* EnGenius */
2941         { USB_DEVICE(0X1740, 0x9701), USB_DEVICE_DATA(&rt2800usb_ops) },
2942         { USB_DEVICE(0x1740, 0x9702), USB_DEVICE_DATA(&rt2800usb_ops) },
2943         { USB_DEVICE(0x1740, 0x9703), USB_DEVICE_DATA(&rt2800usb_ops) },
2944         { USB_DEVICE(0x1740, 0x9705), USB_DEVICE_DATA(&rt2800usb_ops) },
2945         { USB_DEVICE(0x1740, 0x9706), USB_DEVICE_DATA(&rt2800usb_ops) },
2946         { USB_DEVICE(0x1740, 0x9801), USB_DEVICE_DATA(&rt2800usb_ops) },
2947         /* Gemtek */
2948         { USB_DEVICE(0x15a9, 0x0010), USB_DEVICE_DATA(&rt2800usb_ops) },
2949         /* Gigabyte */
2950         { USB_DEVICE(0x1044, 0x800b), USB_DEVICE_DATA(&rt2800usb_ops) },
2951         { USB_DEVICE(0x1044, 0x800c), USB_DEVICE_DATA(&rt2800usb_ops) },
2952         { USB_DEVICE(0x1044, 0x800d), USB_DEVICE_DATA(&rt2800usb_ops) },
2953         /* Hawking */
2954         { USB_DEVICE(0x0e66, 0x0001), USB_DEVICE_DATA(&rt2800usb_ops) },
2955         { USB_DEVICE(0x0e66, 0x0003), USB_DEVICE_DATA(&rt2800usb_ops) },
2956         { USB_DEVICE(0x0e66, 0x0009), USB_DEVICE_DATA(&rt2800usb_ops) },
2957         { USB_DEVICE(0x0e66, 0x000b), USB_DEVICE_DATA(&rt2800usb_ops) },
2958         /* I-O DATA */
2959         { USB_DEVICE(0x04bb, 0x0945), USB_DEVICE_DATA(&rt2800usb_ops) },
2960         /* LevelOne */
2961         { USB_DEVICE(0x1740, 0x0605), USB_DEVICE_DATA(&rt2800usb_ops) },
2962         { USB_DEVICE(0x1740, 0x0615), USB_DEVICE_DATA(&rt2800usb_ops) },
2963         /* Linksys */
2964         { USB_DEVICE(0x1737, 0x0070), USB_DEVICE_DATA(&rt2800usb_ops) },
2965         { USB_DEVICE(0x1737, 0x0071), USB_DEVICE_DATA(&rt2800usb_ops) },
2966         { USB_DEVICE(0x1737, 0x0077), USB_DEVICE_DATA(&rt2800usb_ops) },
2967         /* Logitec */
2968         { USB_DEVICE(0x0789, 0x0162), USB_DEVICE_DATA(&rt2800usb_ops) },
2969         { USB_DEVICE(0x0789, 0x0163), USB_DEVICE_DATA(&rt2800usb_ops) },
2970         { USB_DEVICE(0x0789, 0x0164), USB_DEVICE_DATA(&rt2800usb_ops) },
2971         /* Motorola */
2972         { USB_DEVICE(0x100d, 0x9031), USB_DEVICE_DATA(&rt2800usb_ops) },
2973         { USB_DEVICE(0x100d, 0x9032), USB_DEVICE_DATA(&rt2800usb_ops) },
2974         /* Ovislink */
2975         { USB_DEVICE(0x1b75, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
2976         /* Pegatron */
2977         { USB_DEVICE(0x1d4d, 0x0002), USB_DEVICE_DATA(&rt2800usb_ops) },
2978         { USB_DEVICE(0x1d4d, 0x000c), USB_DEVICE_DATA(&rt2800usb_ops) },
2979         { USB_DEVICE(0x1d4d, 0x000e), USB_DEVICE_DATA(&rt2800usb_ops) },
2980         /* Philips */
2981         { USB_DEVICE(0x0471, 0x200f), USB_DEVICE_DATA(&rt2800usb_ops) },
2982         /* Planex */
2983         { USB_DEVICE(0x2019, 0xed06), USB_DEVICE_DATA(&rt2800usb_ops) },
2984         { USB_DEVICE(0x2019, 0xab24), USB_DEVICE_DATA(&rt2800usb_ops) },
2985         { USB_DEVICE(0x2019, 0xab25), USB_DEVICE_DATA(&rt2800usb_ops) },
2986         /* Qcom */
2987         { USB_DEVICE(0x18e8, 0x6259), USB_DEVICE_DATA(&rt2800usb_ops) },
2988         /* Quanta */
2989         { USB_DEVICE(0x1a32, 0x0304), USB_DEVICE_DATA(&rt2800usb_ops) },
2990         /* Ralink */
2991         { USB_DEVICE(0x0db0, 0x3820), USB_DEVICE_DATA(&rt2800usb_ops) },
2992         { USB_DEVICE(0x0db0, 0x6899), USB_DEVICE_DATA(&rt2800usb_ops) },
2993         { USB_DEVICE(0x148f, 0x2070), USB_DEVICE_DATA(&rt2800usb_ops) },
2994         { USB_DEVICE(0x148f, 0x2770), USB_DEVICE_DATA(&rt2800usb_ops) },
2995         { USB_DEVICE(0x148f, 0x2870), USB_DEVICE_DATA(&rt2800usb_ops) },
2996         { USB_DEVICE(0x148f, 0x3070), USB_DEVICE_DATA(&rt2800usb_ops) },
2997         { USB_DEVICE(0x148f, 0x3071), USB_DEVICE_DATA(&rt2800usb_ops) },
2998         { USB_DEVICE(0x148f, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
2999         { USB_DEVICE(0x148f, 0x3572), USB_DEVICE_DATA(&rt2800usb_ops) },
3000         /* Samsung */
3001         { USB_DEVICE(0x04e8, 0x2018), USB_DEVICE_DATA(&rt2800usb_ops) },
3002         /* Siemens */
3003         { USB_DEVICE(0x129b, 0x1828), USB_DEVICE_DATA(&rt2800usb_ops) },
3004         /* Sitecom */
3005         { USB_DEVICE(0x0df6, 0x0017), USB_DEVICE_DATA(&rt2800usb_ops) },
3006         { USB_DEVICE(0x0df6, 0x002b), USB_DEVICE_DATA(&rt2800usb_ops) },
3007         { USB_DEVICE(0x0df6, 0x002c), USB_DEVICE_DATA(&rt2800usb_ops) },
3008         { USB_DEVICE(0x0df6, 0x002d), USB_DEVICE_DATA(&rt2800usb_ops) },
3009         { USB_DEVICE(0x0df6, 0x0039), USB_DEVICE_DATA(&rt2800usb_ops) },
3010         { USB_DEVICE(0x0df6, 0x003b), USB_DEVICE_DATA(&rt2800usb_ops) },
3011         { USB_DEVICE(0x0df6, 0x003c), USB_DEVICE_DATA(&rt2800usb_ops) },
3012         { USB_DEVICE(0x0df6, 0x003d), USB_DEVICE_DATA(&rt2800usb_ops) },
3013         { USB_DEVICE(0x0df6, 0x003e), USB_DEVICE_DATA(&rt2800usb_ops) },
3014         { USB_DEVICE(0x0df6, 0x003f), USB_DEVICE_DATA(&rt2800usb_ops) },
3015         { USB_DEVICE(0x0df6, 0x0040), USB_DEVICE_DATA(&rt2800usb_ops) },
3016         { USB_DEVICE(0x0df6, 0x0042), USB_DEVICE_DATA(&rt2800usb_ops) },
3017         /* SMC */
3018         { USB_DEVICE(0x083a, 0x6618), USB_DEVICE_DATA(&rt2800usb_ops) },
3019         { USB_DEVICE(0x083a, 0x7511), USB_DEVICE_DATA(&rt2800usb_ops) },
3020         { USB_DEVICE(0x083a, 0x7512), USB_DEVICE_DATA(&rt2800usb_ops) },
3021         { USB_DEVICE(0x083a, 0x7522), USB_DEVICE_DATA(&rt2800usb_ops) },
3022         { USB_DEVICE(0x083a, 0x8522), USB_DEVICE_DATA(&rt2800usb_ops) },
3023         { USB_DEVICE(0x083a, 0xa512), USB_DEVICE_DATA(&rt2800usb_ops) },
3024         { USB_DEVICE(0x083a, 0xa618), USB_DEVICE_DATA(&rt2800usb_ops) },
3025         { USB_DEVICE(0x083a, 0xb522), USB_DEVICE_DATA(&rt2800usb_ops) },
3026         { USB_DEVICE(0x083a, 0xc522), USB_DEVICE_DATA(&rt2800usb_ops) },
3027         /* Sparklan */
3028         { USB_DEVICE(0x15a9, 0x0006), USB_DEVICE_DATA(&rt2800usb_ops) },
3029         /* Sweex */
3030         { USB_DEVICE(0x177f, 0x0153), USB_DEVICE_DATA(&rt2800usb_ops) },
3031         { USB_DEVICE(0x177f, 0x0302), USB_DEVICE_DATA(&rt2800usb_ops) },
3032         { USB_DEVICE(0x177f, 0x0313), USB_DEVICE_DATA(&rt2800usb_ops) },
3033         /* U-Media*/
3034         { USB_DEVICE(0x157e, 0x300e), USB_DEVICE_DATA(&rt2800usb_ops) },
3035         /* ZCOM */
3036         { USB_DEVICE(0x0cde, 0x0022), USB_DEVICE_DATA(&rt2800usb_ops) },
3037         { USB_DEVICE(0x0cde, 0x0025), USB_DEVICE_DATA(&rt2800usb_ops) },
3038         /* Zinwell */
3039         { USB_DEVICE(0x5a57, 0x0280), USB_DEVICE_DATA(&rt2800usb_ops) },
3040         { USB_DEVICE(0x5a57, 0x0282), USB_DEVICE_DATA(&rt2800usb_ops) },
3041         { USB_DEVICE(0x5a57, 0x0283), USB_DEVICE_DATA(&rt2800usb_ops) },
3042         { USB_DEVICE(0x5a57, 0x5257), USB_DEVICE_DATA(&rt2800usb_ops) },
3043         /* Zyxel */
3044         { USB_DEVICE(0x0586, 0x3416), USB_DEVICE_DATA(&rt2800usb_ops) },
3045         { USB_DEVICE(0x0586, 0x341a), USB_DEVICE_DATA(&rt2800usb_ops) },
3046         { 0, }
3047 };
3048
3049 MODULE_AUTHOR(DRV_PROJECT);
3050 MODULE_VERSION(DRV_VERSION);
3051 MODULE_DESCRIPTION("Ralink RT2800 USB Wireless LAN driver.");
3052 MODULE_SUPPORTED_DEVICE("Ralink RT2870 USB chipset based cards");
3053 MODULE_DEVICE_TABLE(usb, rt2800usb_device_table);
3054 MODULE_FIRMWARE(FIRMWARE_RT2870);
3055 MODULE_LICENSE("GPL");
3056
3057 static struct usb_driver rt2800usb_driver = {
3058         .name           = KBUILD_MODNAME,
3059         .id_table       = rt2800usb_device_table,
3060         .probe          = rt2x00usb_probe,
3061         .disconnect     = rt2x00usb_disconnect,
3062         .suspend        = rt2x00usb_suspend,
3063         .resume         = rt2x00usb_resume,
3064 };
3065
3066 static int __init rt2800usb_init(void)
3067 {
3068         return usb_register(&rt2800usb_driver);
3069 }
3070
3071 static void __exit rt2800usb_exit(void)
3072 {
3073         usb_deregister(&rt2800usb_driver);
3074 }
3075
3076 module_init(rt2800usb_init);
3077 module_exit(rt2800usb_exit);