drivers/net/wireless/rt2x00/rt2800lib.c

   1 /*
   2         Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
   3         Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
   4         Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
   5         Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
   6
   7         Based on the original rt2800pci.c and rt2800usb.c.
   8           Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
   9           Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
  10           Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
  11           Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
  12           Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
  13           Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
  14           <http://rt2x00.serialmonkey.com>
  15
  16         This program is free software; you can redistribute it and/or modify
  17         it under the terms of the GNU General Public License as published by
  18         the Free Software Foundation; either version 2 of the License, or
  19         (at your option) any later version.
  20
  21         This program is distributed in the hope that it will be useful,
  22         but WITHOUT ANY WARRANTY; without even the implied warranty of
  23         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24         GNU General Public License for more details.
  25
  26         You should have received a copy of the GNU General Public License
  27         along with this program; if not, write to the
  28         Free Software Foundation, Inc.,
  29         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  30  */
  31
  32 /*
  33         Module: rt2800lib
  34         Abstract: rt2800 generic device routines.
  35  */
  36
  37 #include <linux/crc-ccitt.h>
  38 #include <linux/kernel.h>
  39 #include <linux/module.h>
  40 #include <linux/slab.h>
  41
  42 #include "rt2x00.h"
  43 #include "rt2800lib.h"
  44 #include "rt2800.h"
  45
  46 /*
  47  * Register access.
  48  * All access to the CSR registers will go through the methods
  49  * rt2800_register_read and rt2800_register_write.
  50  * BBP and RF register require indirect register access,
  51  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  52  * These indirect registers work with busy bits,
  53  * and we will try maximal REGISTER_BUSY_COUNT times to access
  54  * the register while taking a REGISTER_BUSY_DELAY us delay
  55  * between each attampt. When the busy bit is still set at that time,
  56  * the access attempt is considered to have failed,
  57  * and we will print an error.
  58  * The _lock versions must be used if you already hold the csr_mutex
  59  */
  60 #define WAIT_FOR_BBP(__dev, __reg) \
  61         rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
  62 #define WAIT_FOR_RFCSR(__dev, __reg) \
  63         rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
  64 #define WAIT_FOR_RF(__dev, __reg) \
  65         rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
  66 #define WAIT_FOR_MCU(__dev, __reg) \
  67         rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  68                             H2M_MAILBOX_CSR_OWNER, (__reg))
  69
  70 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
  71 {
  72         /* check for rt2872 on SoC */
  73         if (!rt2x00_is_soc(rt2x00dev) ||
  74             !rt2x00_rt(rt2x00dev, RT2872))
  75                 return false;
  76
  77         /* we know for sure that these rf chipsets are used on rt305x boards */
  78         if (rt2x00_rf(rt2x00dev, RF3020) ||
  79             rt2x00_rf(rt2x00dev, RF3021) ||
  80             rt2x00_rf(rt2x00dev, RF3022))
  81                 return true;
  82
  83         NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n");
  84         return false;
  85 }
  86
  87 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
  88                              const unsigned int word, const u8 value)
  89 {
  90         u32 reg;
  91
  92         mutex_lock(&rt2x00dev->csr_mutex);
  93
  94         /*
  95          * Wait until the BBP becomes available, afterwards we
  96          * can safely write the new data into the register.
  97          */
  98         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  99                 reg = 0;
 100                 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
 101                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 102                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 103                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
 104                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 105
 106                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 107         }
 108
 109         mutex_unlock(&rt2x00dev->csr_mutex);
 110 }
 111
 112 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
 113                             const unsigned int word, u8 *value)
 114 {
 115         u32 reg;
 116
 117         mutex_lock(&rt2x00dev->csr_mutex);
 118
 119         /*
 120          * Wait until the BBP becomes available, afterwards we
 121          * can safely write the read request into the register.
 122          * After the data has been written, we wait until hardware
 123          * returns the correct value, if at any time the register
 124          * doesn't become available in time, reg will be 0xffffffff
 125          * which means we return 0xff to the caller.
 126          */
 127         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 128                 reg = 0;
 129                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 130                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 131                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
 132                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 133
 134                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 135
 136                 WAIT_FOR_BBP(rt2x00dev, &reg);
 137         }
 138
 139         *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
 140
 141         mutex_unlock(&rt2x00dev->csr_mutex);
 142 }
 143
 144 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
 145                                const unsigned int word, const u8 value)
 146 {
 147         u32 reg;
 148
 149         mutex_lock(&rt2x00dev->csr_mutex);
 150
 151         /*
 152          * Wait until the RFCSR becomes available, afterwards we
 153          * can safely write the new data into the register.
 154          */
 155         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 156                 reg = 0;
 157                 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
 158                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 159                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
 160                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 161
 162                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 163         }
 164
 165         mutex_unlock(&rt2x00dev->csr_mutex);
 166 }
 167
 168 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
 169                               const unsigned int word, u8 *value)
 170 {
 171         u32 reg;
 172
 173         mutex_lock(&rt2x00dev->csr_mutex);
 174
 175         /*
 176          * Wait until the RFCSR becomes available, afterwards we
 177          * can safely write the read request into the register.
 178          * After the data has been written, we wait until hardware
 179          * returns the correct value, if at any time the register
 180          * doesn't become available in time, reg will be 0xffffffff
 181          * which means we return 0xff to the caller.
 182          */
 183         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 184                 reg = 0;
 185                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 186                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
 187                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 188
 189                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 190
 191                 WAIT_FOR_RFCSR(rt2x00dev, &reg);
 192         }
 193
 194         *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
 195
 196         mutex_unlock(&rt2x00dev->csr_mutex);
 197 }
 198
 199 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
 200                             const unsigned int word, const u32 value)
 201 {
 202         u32 reg;
 203
 204         mutex_lock(&rt2x00dev->csr_mutex);
 205
 206         /*
 207          * Wait until the RF becomes available, afterwards we
 208          * can safely write the new data into the register.
 209          */
 210         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 211                 reg = 0;
 212                 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
 213                 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
 214                 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
 215                 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
 216
 217                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
 218                 rt2x00_rf_write(rt2x00dev, word, value);
 219         }
 220
 221         mutex_unlock(&rt2x00dev->csr_mutex);
 222 }
 223
 224 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
 225                         const u8 command, const u8 token,
 226                         const u8 arg0, const u8 arg1)
 227 {
 228         u32 reg;
 229
 230         /*
 231          * SOC devices don't support MCU requests.
 232          */
 233         if (rt2x00_is_soc(rt2x00dev))
 234                 return;
 235
 236         mutex_lock(&rt2x00dev->csr_mutex);
 237
 238         /*
 239          * Wait until the MCU becomes available, afterwards we
 240          * can safely write the new data into the register.
 241          */
 242         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 243                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 244                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 245                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 246                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 247                 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
 248
 249                 reg = 0;
 250                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 251                 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
 252         }
 253
 254         mutex_unlock(&rt2x00dev->csr_mutex);
 255 }
 256 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
 257
 258 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
 259 {
 260         unsigned int i = 0;
 261         u32 reg;
 262
 263         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 264                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
 265                 if (reg && reg != ~0)
 266                         return 0;
 267                 msleep(1);
 268         }
 269
 270         ERROR(rt2x00dev, "Unstable hardware.\n");
 271         return -EBUSY;
 272 }
 273 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
 274
 275 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
 276 {
 277         unsigned int i;
 278         u32 reg;
 279
 280         /*
 281          * Some devices are really slow to respond here. Wait a whole second
 282          * before timing out.
 283          */
 284         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 285                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 286                 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
 287                     !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
 288                         return 0;
 289
 290                 msleep(10);
 291         }
 292
 293         ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
 294         return -EACCES;
 295 }
 296 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
 297
 298 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
 299 {
 300         u16 fw_crc;
 301         u16 crc;
 302
 303         /*
 304          * The last 2 bytes in the firmware array are the crc checksum itself,
 305          * this means that we should never pass those 2 bytes to the crc
 306          * algorithm.
 307          */
 308         fw_crc = (data[len - 2] << 8 | data[len - 1]);
 309
 310         /*
 311          * Use the crc ccitt algorithm.
 312          * This will return the same value as the legacy driver which
 313          * used bit ordering reversion on the both the firmware bytes
 314          * before input input as well as on the final output.
 315          * Obviously using crc ccitt directly is much more efficient.
 316          */
 317         crc = crc_ccitt(~0, data, len - 2);
 318
 319         /*
 320          * There is a small difference between the crc-itu-t + bitrev and
 321          * the crc-ccitt crc calculation. In the latter method the 2 bytes
 322          * will be swapped, use swab16 to convert the crc to the correct
 323          * value.
 324          */
 325         crc = swab16(crc);
 326
 327         return fw_crc == crc;
 328 }
 329
 330 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
 331                           const u8 *data, const size_t len)
 332 {
 333         size_t offset = 0;
 334         size_t fw_len;
 335         bool multiple;
 336
 337         /*
 338          * PCI(e) & SOC devices require firmware with a length
 339          * of 8kb. USB devices require firmware files with a length
 340          * of 4kb. Certain USB chipsets however require different firmware,
 341          * which Ralink only provides attached to the original firmware
 342          * file. Thus for USB devices, firmware files have a length
 343          * which is a multiple of 4kb.
 344          */
 345         if (rt2x00_is_usb(rt2x00dev)) {
 346                 fw_len = 4096;
 347                 multiple = true;
 348         } else {
 349                 fw_len = 8192;
 350                 multiple = true;
 351         }
 352
 353         /*
 354          * Validate the firmware length
 355          */
 356         if (len != fw_len && (!multiple || (len % fw_len) != 0))
 357                 return FW_BAD_LENGTH;
 358
 359         /*
 360          * Check if the chipset requires one of the upper parts
 361          * of the firmware.
 362          */
 363         if (rt2x00_is_usb(rt2x00dev) &&
 364             !rt2x00_rt(rt2x00dev, RT2860) &&
 365             !rt2x00_rt(rt2x00dev, RT2872) &&
 366             !rt2x00_rt(rt2x00dev, RT3070) &&
 367             ((len / fw_len) == 1))
 368                 return FW_BAD_VERSION;
 369
 370         /*
 371          * 8kb firmware files must be checked as if it were
 372          * 2 separate firmware files.
 373          */
 374         while (offset < len) {
 375                 if (!rt2800_check_firmware_crc(data + offset, fw_len))
 376                         return FW_BAD_CRC;
 377
 378                 offset += fw_len;
 379         }
 380
 381         return FW_OK;
 382 }
 383 EXPORT_SYMBOL_GPL(rt2800_check_firmware);
 384
 385 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
 386                          const u8 *data, const size_t len)
 387 {
 388         unsigned int i;
 389         u32 reg;
 390
 391         /*
 392          * If driver doesn't wake up firmware here,
 393          * rt2800_load_firmware will hang forever when interface is up again.
 394          */
 395         rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
 396
 397         /*
 398          * Wait for stable hardware.
 399          */
 400         if (rt2800_wait_csr_ready(rt2x00dev))
 401                 return -EBUSY;
 402
 403         if (rt2x00_is_pci(rt2x00dev)) {
 404                 if (rt2x00_rt(rt2x00dev, RT5390)) {
 405                         rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
 406                         rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
 407                         rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
 408                         rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
 409                 }
 410                 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
 411         }
 412
 413         /*
 414          * Disable DMA, will be reenabled later when enabling
 415          * the radio.
 416          */
 417         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 418         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
 419         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
 420         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
 421         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
 422         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
 423         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 424
 425         /*
 426          * Write firmware to the device.
 427          */
 428         rt2800_drv_write_firmware(rt2x00dev, data, len);
 429
 430         /*
 431          * Wait for device to stabilize.
 432          */
 433         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 434                 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
 435                 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
 436                         break;
 437                 msleep(1);
 438         }
 439
 440         if (i == REGISTER_BUSY_COUNT) {
 441                 ERROR(rt2x00dev, "PBF system register not ready.\n");
 442                 return -EBUSY;
 443         }
 444
 445         /*
 446          * Initialize firmware.
 447          */
 448         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
 449         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
 450         msleep(1);
 451
 452         return 0;
 453 }
 454 EXPORT_SYMBOL_GPL(rt2800_load_firmware);
 455
 456 void rt2800_write_tx_data(struct queue_entry *entry,
 457                           struct txentry_desc *txdesc)
 458 {
 459         __le32 *txwi = rt2800_drv_get_txwi(entry);
 460         u32 word;
 461
 462         /*
 463          * Initialize TX Info descriptor
 464          */
 465         rt2x00_desc_read(txwi, 0, &word);
 466         rt2x00_set_field32(&word, TXWI_W0_FRAG,
 467                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
 468         rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
 469                            test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
 470         rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
 471         rt2x00_set_field32(&word, TXWI_W0_TS,
 472                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
 473         rt2x00_set_field32(&word, TXWI_W0_AMPDU,
 474                            test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
 475         rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
 476                            txdesc->u.ht.mpdu_density);
 477         rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
 478         rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
 479         rt2x00_set_field32(&word, TXWI_W0_BW,
 480                            test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
 481         rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
 482                            test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
 483         rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
 484         rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
 485         rt2x00_desc_write(txwi, 0, word);
 486
 487         rt2x00_desc_read(txwi, 1, &word);
 488         rt2x00_set_field32(&word, TXWI_W1_ACK,
 489                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
 490         rt2x00_set_field32(&word, TXWI_W1_NSEQ,
 491                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
 492         rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
 493         rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
 494                            test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
 495                            txdesc->key_idx : 0xff);
 496         rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
 497                            txdesc->length);
 498         rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
 499         rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
 500         rt2x00_desc_write(txwi, 1, word);
 501
 502         /*
 503          * Always write 0 to IV/EIV fields, hardware will insert the IV
 504          * from the IVEIV register when TXD_W3_WIV is set to 0.
 505          * When TXD_W3_WIV is set to 1 it will use the IV data
 506          * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
 507          * crypto entry in the registers should be used to encrypt the frame.
 508          */
 509         _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
 510         _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
 511 }
 512 EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
 513
 514 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
 515 {
 516         int rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
 517         int rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
 518         int rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
 519         u16 eeprom;
 520         u8 offset0;
 521         u8 offset1;
 522         u8 offset2;
 523
 524         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
 525                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
 526                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
 527                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
 528                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
 529                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
 530         } else {
 531                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
 532                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
 533                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
 534                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
 535                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
 536         }
 537
 538         /*
 539          * Convert the value from the descriptor into the RSSI value
 540          * If the value in the descriptor is 0, it is considered invalid
 541          * and the default (extremely low) rssi value is assumed
 542          */
 543         rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
 544         rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
 545         rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
 546
 547         /*
 548          * mac80211 only accepts a single RSSI value. Calculating the
 549          * average doesn't deliver a fair answer either since -60:-60 would
 550          * be considered equally good as -50:-70 while the second is the one
 551          * which gives less energy...
 552          */
 553         rssi0 = max(rssi0, rssi1);
 554         return max(rssi0, rssi2);
 555 }
 556
 557 void rt2800_process_rxwi(struct queue_entry *entry,
 558                          struct rxdone_entry_desc *rxdesc)
 559 {
 560         __le32 *rxwi = (__le32 *) entry->skb->data;
 561         u32 word;
 562
 563         rt2x00_desc_read(rxwi, 0, &word);
 564
 565         rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
 566         rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
 567
 568         rt2x00_desc_read(rxwi, 1, &word);
 569
 570         if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
 571                 rxdesc->flags |= RX_FLAG_SHORT_GI;
 572
 573         if (rt2x00_get_field32(word, RXWI_W1_BW))
 574                 rxdesc->flags |= RX_FLAG_40MHZ;
 575
 576         /*
 577          * Detect RX rate, always use MCS as signal type.
 578          */
 579         rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
 580         rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
 581         rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
 582
 583         /*
 584          * Mask of 0x8 bit to remove the short preamble flag.
 585          */
 586         if (rxdesc->rate_mode == RATE_MODE_CCK)
 587                 rxdesc->signal &= ~0x8;
 588
 589         rt2x00_desc_read(rxwi, 2, &word);
 590
 591         /*
 592          * Convert descriptor AGC value to RSSI value.
 593          */
 594         rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
 595
 596         /*
 597          * Remove RXWI descriptor from start of buffer.
 598          */
 599         skb_pull(entry->skb, RXWI_DESC_SIZE);
 600 }
 601 EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
 602
 603 static bool rt2800_txdone_entry_check(struct queue_entry *entry, u32 reg)
 604 {
 605         __le32 *txwi;
 606         u32 word;
 607         int wcid, ack, pid;
 608         int tx_wcid, tx_ack, tx_pid;
 609
 610         wcid    = rt2x00_get_field32(reg, TX_STA_FIFO_WCID);
 611         ack     = rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED);
 612         pid     = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE);
 613
 614         /*
 615          * This frames has returned with an IO error,
 616          * so the status report is not intended for this
 617          * frame.
 618          */
 619         if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags)) {
 620                 rt2x00lib_txdone_noinfo(entry, TXDONE_FAILURE);
 621                 return false;
 622         }
 623
 624         /*
 625          * Validate if this TX status report is intended for
 626          * this entry by comparing the WCID/ACK/PID fields.
 627          */
 628         txwi = rt2800_drv_get_txwi(entry);
 629
 630         rt2x00_desc_read(txwi, 1, &word);
 631         tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID);
 632         tx_ack  = rt2x00_get_field32(word, TXWI_W1_ACK);
 633         tx_pid  = rt2x00_get_field32(word, TXWI_W1_PACKETID);
 634
 635         if ((wcid != tx_wcid) || (ack != tx_ack) || (pid != tx_pid)) {
 636                 WARNING(entry->queue->rt2x00dev,
 637                         "TX status report missed for queue %d entry %d\n",
 638                 entry->queue->qid, entry->entry_idx);
 639                 rt2x00lib_txdone_noinfo(entry, TXDONE_UNKNOWN);
 640                 return false;
 641         }
 642
 643         return true;
 644 }
 645
 646 void rt2800_txdone_entry(struct queue_entry *entry, u32 status)
 647 {
 648         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 649         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 650         struct txdone_entry_desc txdesc;
 651         u32 word;
 652         u16 mcs, real_mcs;
 653         int aggr, ampdu;
 654         __le32 *txwi;
 655
 656         /*
 657          * Obtain the status about this packet.
 658          */
 659         txdesc.flags = 0;
 660         txwi = rt2800_drv_get_txwi(entry);
 661         rt2x00_desc_read(txwi, 0, &word);
 662
 663         mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
 664         ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
 665
 666         real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
 667         aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
 668
 669         /*
 670          * If a frame was meant to be sent as a single non-aggregated MPDU
 671          * but ended up in an aggregate the used tx rate doesn't correlate
 672          * with the one specified in the TXWI as the whole aggregate is sent
 673          * with the same rate.
 674          *
 675          * For example: two frames are sent to rt2x00, the first one sets
 676          * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
 677          * and requests MCS15. If the hw aggregates both frames into one
 678          * AMDPU the tx status for both frames will contain MCS7 although
 679          * the frame was sent successfully.
 680          *
 681          * Hence, replace the requested rate with the real tx rate to not
 682          * confuse the rate control algortihm by providing clearly wrong
 683          * data.
 684          */
 685         if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
 686                 skbdesc->tx_rate_idx = real_mcs;
 687                 mcs = real_mcs;
 688         }
 689
 690         if (aggr == 1 || ampdu == 1)
 691                 __set_bit(TXDONE_AMPDU, &txdesc.flags);
 692
 693         /*
 694          * Ralink has a retry mechanism using a global fallback
 695          * table. We setup this fallback table to try the immediate
 696          * lower rate for all rates. In the TX_STA_FIFO, the MCS field
 697          * always contains the MCS used for the last transmission, be
 698          * it successful or not.
 699          */
 700         if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
 701                 /*
 702                  * Transmission succeeded. The number of retries is
 703                  * mcs - real_mcs
 704                  */
 705                 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
 706                 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
 707         } else {
 708                 /*
 709                  * Transmission failed. The number of retries is
 710                  * always 7 in this case (for a total number of 8
 711                  * frames sent).
 712                  */
 713                 __set_bit(TXDONE_FAILURE, &txdesc.flags);
 714                 txdesc.retry = rt2x00dev->long_retry;
 715         }
 716
 717         /*
 718          * the frame was retried at least once
 719          * -> hw used fallback rates
 720          */
 721         if (txdesc.retry)
 722                 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
 723
 724         rt2x00lib_txdone(entry, &txdesc);
 725 }
 726 EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
 727
 728 void rt2800_txdone(struct rt2x00_dev *rt2x00dev)
 729 {
 730         struct data_queue *queue;
 731         struct queue_entry *entry;
 732         u32 reg;
 733         u8 pid;
 734         int i;
 735
 736         /*
 737          * TX_STA_FIFO is a stack of X entries, hence read TX_STA_FIFO
 738          * at most X times and also stop processing once the TX_STA_FIFO_VALID
 739          * flag is not set anymore.
 740          *
 741          * The legacy drivers use X=TX_RING_SIZE but state in a comment
 742          * that the TX_STA_FIFO stack has a size of 16. We stick to our
 743          * tx ring size for now.
 744          */
 745         for (i = 0; i < rt2x00dev->ops->tx->entry_num; i++) {
 746                 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &reg);
 747                 if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
 748                         break;
 749
 750                 /*
 751                  * Skip this entry when it contains an invalid
 752                  * queue identication number.
 753                  */
 754                 pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_QUEUE);
 755                 if (pid >= QID_RX)
 756                         continue;
 757
 758                 queue = rt2x00queue_get_tx_queue(rt2x00dev, pid);
 759                 if (unlikely(!queue))
 760                         continue;
 761
 762                 /*
 763                  * Inside each queue, we process each entry in a chronological
 764                  * order. We first check that the queue is not empty.
 765                  */
 766                 entry = NULL;
 767                 while (!rt2x00queue_empty(queue)) {
 768                         entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
 769                         if (rt2800_txdone_entry_check(entry, reg))
 770                                 break;
 771                 }
 772
 773                 if (!entry || rt2x00queue_empty(queue))
 774                         break;
 775
 776                 rt2800_txdone_entry(entry, reg);
 777         }
 778 }
 779 EXPORT_SYMBOL_GPL(rt2800_txdone);
 780
 781 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
 782 {
 783         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 784         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 785         unsigned int beacon_base;
 786         unsigned int padding_len;
 787         u32 orig_reg, reg;
 788
 789         /*
 790          * Disable beaconing while we are reloading the beacon data,
 791          * otherwise we might be sending out invalid data.
 792          */
 793         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 794         orig_reg = reg;
 795         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
 796         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 797
 798         /*
 799          * Add space for the TXWI in front of the skb.
 800          */
 801         skb_push(entry->skb, TXWI_DESC_SIZE);
 802         memset(entry->skb, 0, TXWI_DESC_SIZE);
 803
 804         /*
 805          * Register descriptor details in skb frame descriptor.
 806          */
 807         skbdesc->flags |= SKBDESC_DESC_IN_SKB;
 808         skbdesc->desc = entry->skb->data;
 809         skbdesc->desc_len = TXWI_DESC_SIZE;
 810
 811         /*
 812          * Add the TXWI for the beacon to the skb.
 813          */
 814         rt2800_write_tx_data(entry, txdesc);
 815
 816         /*
 817          * Dump beacon to userspace through debugfs.
 818          */
 819         rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
 820
 821         /*
 822          * Write entire beacon with TXWI and padding to register.
 823          */
 824         padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
 825         if (padding_len && skb_pad(entry->skb, padding_len)) {
 826                 ERROR(rt2x00dev, "Failure padding beacon, aborting\n");
 827                 /* skb freed by skb_pad() on failure */
 828                 entry->skb = NULL;
 829                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
 830                 return;
 831         }
 832
 833         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
 834         rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
 835                                    entry->skb->len + padding_len);
 836
 837         /*
 838          * Enable beaconing again.
 839          */
 840         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
 841         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 842
 843         /*
 844          * Clean up beacon skb.
 845          */
 846         dev_kfree_skb_any(entry->skb);
 847         entry->skb = NULL;
 848 }
 849 EXPORT_SYMBOL_GPL(rt2800_write_beacon);
 850
 851 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
 852                                                 unsigned int beacon_base)
 853 {
 854         int i;
 855
 856         /*
 857          * For the Beacon base registers we only need to clear
 858          * the whole TXWI which (when set to 0) will invalidate
 859          * the entire beacon.
 860          */
 861         for (i = 0; i < TXWI_DESC_SIZE; i += sizeof(__le32))
 862                 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
 863 }
 864
 865 void rt2800_clear_beacon(struct queue_entry *entry)
 866 {
 867         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 868         u32 reg;
 869
 870         /*
 871          * Disable beaconing while we are reloading the beacon data,
 872          * otherwise we might be sending out invalid data.
 873          */
 874         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 875         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
 876         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 877
 878         /*
 879          * Clear beacon.
 880          */
 881         rt2800_clear_beacon_register(rt2x00dev,
 882                                      HW_BEACON_OFFSET(entry->entry_idx));
 883
 884         /*
 885          * Enabled beaconing again.
 886          */
 887         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
 888         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 889 }
 890 EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
 891
 892 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 893 const struct rt2x00debug rt2800_rt2x00debug = {
 894         .owner  = THIS_MODULE,
 895         .csr    = {
 896                 .read           = rt2800_register_read,
 897                 .write          = rt2800_register_write,
 898                 .flags          = RT2X00DEBUGFS_OFFSET,
 899                 .word_base      = CSR_REG_BASE,
 900                 .word_size      = sizeof(u32),
 901                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 902         },
 903         .eeprom = {
 904                 .read           = rt2x00_eeprom_read,
 905                 .write          = rt2x00_eeprom_write,
 906                 .word_base      = EEPROM_BASE,
 907                 .word_size      = sizeof(u16),
 908                 .word_count     = EEPROM_SIZE / sizeof(u16),
 909         },
 910         .bbp    = {
 911                 .read           = rt2800_bbp_read,
 912                 .write          = rt2800_bbp_write,
 913                 .word_base      = BBP_BASE,
 914                 .word_size      = sizeof(u8),
 915                 .word_count     = BBP_SIZE / sizeof(u8),
 916         },
 917         .rf     = {
 918                 .read           = rt2x00_rf_read,
 919                 .write          = rt2800_rf_write,
 920                 .word_base      = RF_BASE,
 921                 .word_size      = sizeof(u32),
 922                 .word_count     = RF_SIZE / sizeof(u32),
 923         },
 924 };
 925 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
 926 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 927
 928 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 929 {
 930         u32 reg;
 931
 932         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
 933         return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
 934 }
 935 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
 936
 937 #ifdef CONFIG_RT2X00_LIB_LEDS
 938 static void rt2800_brightness_set(struct led_classdev *led_cdev,
 939                                   enum led_brightness brightness)
 940 {
 941         struct rt2x00_led *led =
 942             container_of(led_cdev, struct rt2x00_led, led_dev);
 943         unsigned int enabled = brightness != LED_OFF;
 944         unsigned int bg_mode =
 945             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 946         unsigned int polarity =
 947                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 948                                    EEPROM_FREQ_LED_POLARITY);
 949         unsigned int ledmode =
 950                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 951                                    EEPROM_FREQ_LED_MODE);
 952
 953         if (led->type == LED_TYPE_RADIO) {
 954                 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 955                                       enabled ? 0x20 : 0);
 956         } else if (led->type == LED_TYPE_ASSOC) {
 957                 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 958                                       enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
 959         } else if (led->type == LED_TYPE_QUALITY) {
 960                 /*
 961                  * The brightness is divided into 6 levels (0 - 5),
 962                  * The specs tell us the following levels:
 963                  *      0, 1 ,3, 7, 15, 31
 964                  * to determine the level in a simple way we can simply
 965                  * work with bitshifting:
 966                  *      (1 << level) - 1
 967                  */
 968                 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
 969                                       (1 << brightness / (LED_FULL / 6)) - 1,
 970                                       polarity);
 971         }
 972 }
 973
 974 static int rt2800_blink_set(struct led_classdev *led_cdev,
 975                             unsigned long *delay_on, unsigned long *delay_off)
 976 {
 977         struct rt2x00_led *led =
 978             container_of(led_cdev, struct rt2x00_led, led_dev);
 979         u32 reg;
 980
 981         rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
 982         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
 983         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
 984         rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
 985
 986         return 0;
 987 }
 988
 989 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
 990                      struct rt2x00_led *led, enum led_type type)
 991 {
 992         led->rt2x00dev = rt2x00dev;
 993         led->type = type;
 994         led->led_dev.brightness_set = rt2800_brightness_set;
 995         led->led_dev.blink_set = rt2800_blink_set;
 996         led->flags = LED_INITIALIZED;
 997 }
 998 #endif /* CONFIG_RT2X00_LIB_LEDS */
 999
1000 /*
1001  * Configuration handlers.
1002  */
1003 static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
1004                                     struct rt2x00lib_crypto *crypto,
1005                                     struct ieee80211_key_conf *key)
1006 {
1007         struct mac_wcid_entry wcid_entry;
1008         struct mac_iveiv_entry iveiv_entry;
1009         u32 offset;
1010         u32 reg;
1011
1012         offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
1013
1014         if (crypto->cmd == SET_KEY) {
1015                 rt2800_register_read(rt2x00dev, offset, &reg);
1016                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
1017                                    !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
1018                 /*
1019                  * Both the cipher as the BSS Idx numbers are split in a main
1020                  * value of 3 bits, and a extended field for adding one additional
1021                  * bit to the value.
1022                  */
1023                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
1024                                    (crypto->cipher & 0x7));
1025                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
1026                                    (crypto->cipher & 0x8) >> 3);
1027                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
1028                                    (crypto->bssidx & 0x7));
1029                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
1030                                    (crypto->bssidx & 0x8) >> 3);
1031                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
1032                 rt2800_register_write(rt2x00dev, offset, reg);
1033         } else {
1034                 rt2800_register_write(rt2x00dev, offset, 0);
1035         }
1036
1037         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1038
1039         memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1040         if ((crypto->cipher == CIPHER_TKIP) ||
1041             (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1042             (crypto->cipher == CIPHER_AES))
1043                 iveiv_entry.iv[3] |= 0x20;
1044         iveiv_entry.iv[3] |= key->keyidx << 6;
1045         rt2800_register_multiwrite(rt2x00dev, offset,
1046                                       &iveiv_entry, sizeof(iveiv_entry));
1047
1048         offset = MAC_WCID_ENTRY(key->hw_key_idx);
1049
1050         memset(&wcid_entry, 0, sizeof(wcid_entry));
1051         if (crypto->cmd == SET_KEY)
1052                 memcpy(wcid_entry.mac, crypto->address, ETH_ALEN);
1053         rt2800_register_multiwrite(rt2x00dev, offset,
1054                                       &wcid_entry, sizeof(wcid_entry));
1055 }
1056
1057 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1058                              struct rt2x00lib_crypto *crypto,
1059                              struct ieee80211_key_conf *key)
1060 {
1061         struct hw_key_entry key_entry;
1062         struct rt2x00_field32 field;
1063         u32 offset;
1064         u32 reg;
1065
1066         if (crypto->cmd == SET_KEY) {
1067                 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1068
1069                 memcpy(key_entry.key, crypto->key,
1070                        sizeof(key_entry.key));
1071                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1072                        sizeof(key_entry.tx_mic));
1073                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1074                        sizeof(key_entry.rx_mic));
1075
1076                 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1077                 rt2800_register_multiwrite(rt2x00dev, offset,
1078                                               &key_entry, sizeof(key_entry));
1079         }
1080
1081         /*
1082          * The cipher types are stored over multiple registers
1083          * starting with SHARED_KEY_MODE_BASE each word will have
1084          * 32 bits and contains the cipher types for 2 bssidx each.
1085          * Using the correct defines correctly will cause overhead,
1086          * so just calculate the correct offset.
1087          */
1088         field.bit_offset = 4 * (key->hw_key_idx % 8);
1089         field.bit_mask = 0x7 << field.bit_offset;
1090
1091         offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1092
1093         rt2800_register_read(rt2x00dev, offset, &reg);
1094         rt2x00_set_field32(&reg, field,
1095                            (crypto->cmd == SET_KEY) * crypto->cipher);
1096         rt2800_register_write(rt2x00dev, offset, reg);
1097
1098         /*
1099          * Update WCID information
1100          */
1101         rt2800_config_wcid_attr(rt2x00dev, crypto, key);
1102
1103         return 0;
1104 }
1105 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1106
1107 static inline int rt2800_find_pairwise_keyslot(struct rt2x00_dev *rt2x00dev)
1108 {
1109         int idx;
1110         u32 offset, reg;
1111
1112         /*
1113          * Search for the first free pairwise key entry and return the
1114          * corresponding index.
1115          *
1116          * Make sure the WCID starts _after_ the last possible shared key
1117          * entry (>32).
1118          *
1119          * Since parts of the pairwise key table might be shared with
1120          * the beacon frame buffers 6 & 7 we should only write into the
1121          * first 222 entries.
1122          */
1123         for (idx = 33; idx <= 222; idx++) {
1124                 offset = MAC_WCID_ATTR_ENTRY(idx);
1125                 rt2800_register_read(rt2x00dev, offset, &reg);
1126                 if (!reg)
1127                         return idx;
1128         }
1129         return -1;
1130 }
1131
1132 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1133                                struct rt2x00lib_crypto *crypto,
1134                                struct ieee80211_key_conf *key)
1135 {
1136         struct hw_key_entry key_entry;
1137         u32 offset;
1138         int idx;
1139
1140         if (crypto->cmd == SET_KEY) {
1141                 idx = rt2800_find_pairwise_keyslot(rt2x00dev);
1142                 if (idx < 0)
1143                         return -ENOSPC;
1144                 key->hw_key_idx = idx;
1145
1146                 memcpy(key_entry.key, crypto->key,
1147                        sizeof(key_entry.key));
1148                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1149                        sizeof(key_entry.tx_mic));
1150                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1151                        sizeof(key_entry.rx_mic));
1152
1153                 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1154                 rt2800_register_multiwrite(rt2x00dev, offset,
1155                                               &key_entry, sizeof(key_entry));
1156         }
1157
1158         /*
1159          * Update WCID information
1160          */
1161         rt2800_config_wcid_attr(rt2x00dev, crypto, key);
1162
1163         return 0;
1164 }
1165 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1166
1167 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1168                           const unsigned int filter_flags)
1169 {
1170         u32 reg;
1171
1172         /*
1173          * Start configuration steps.
1174          * Note that the version error will always be dropped
1175          * and broadcast frames will always be accepted since
1176          * there is no filter for it at this time.
1177          */
1178         rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1179         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1180                            !(filter_flags & FIF_FCSFAIL));
1181         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1182                            !(filter_flags & FIF_PLCPFAIL));
1183         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1184                            !(filter_flags & FIF_PROMISC_IN_BSS));
1185         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1186         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1187         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1188                            !(filter_flags & FIF_ALLMULTI));
1189         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1190         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1191         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1192                            !(filter_flags & FIF_CONTROL));
1193         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1194                            !(filter_flags & FIF_CONTROL));
1195         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1196                            !(filter_flags & FIF_CONTROL));
1197         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1198                            !(filter_flags & FIF_CONTROL));
1199         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1200                            !(filter_flags & FIF_CONTROL));
1201         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1202                            !(filter_flags & FIF_PSPOLL));
1203         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
1204         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
1205         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1206                            !(filter_flags & FIF_CONTROL));
1207         rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1208 }
1209 EXPORT_SYMBOL_GPL(rt2800_config_filter);
1210
1211 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1212                         struct rt2x00intf_conf *conf, const unsigned int flags)
1213 {
1214         u32 reg;
1215         bool update_bssid = false;
1216
1217         if (flags & CONFIG_UPDATE_TYPE) {
1218                 /*
1219                  * Enable synchronisation.
1220                  */
1221                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1222                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
1223                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1224         }
1225
1226         if (flags & CONFIG_UPDATE_MAC) {
1227                 if (flags & CONFIG_UPDATE_TYPE &&
1228                     conf->sync == TSF_SYNC_AP_NONE) {
1229                         /*
1230                          * The BSSID register has to be set to our own mac
1231                          * address in AP mode.
1232                          */
1233                         memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1234                         update_bssid = true;
1235                 }
1236
1237                 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1238                         reg = le32_to_cpu(conf->mac[1]);
1239                         rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1240                         conf->mac[1] = cpu_to_le32(reg);
1241                 }
1242
1243                 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1244                                               conf->mac, sizeof(conf->mac));
1245         }
1246
1247         if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
1248                 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1249                         reg = le32_to_cpu(conf->bssid[1]);
1250                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1251                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1252                         conf->bssid[1] = cpu_to_le32(reg);
1253                 }
1254
1255                 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1256                                               conf->bssid, sizeof(conf->bssid));
1257         }
1258 }
1259 EXPORT_SYMBOL_GPL(rt2800_config_intf);
1260
1261 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1262                                     struct rt2x00lib_erp *erp)
1263 {
1264         bool any_sta_nongf = !!(erp->ht_opmode &
1265                                 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1266         u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1267         u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1268         u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1269         u32 reg;
1270
1271         /* default protection rate for HT20: OFDM 24M */
1272         mm20_rate = gf20_rate = 0x4004;
1273
1274         /* default protection rate for HT40: duplicate OFDM 24M */
1275         mm40_rate = gf40_rate = 0x4084;
1276
1277         switch (protection) {
1278         case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1279                 /*
1280                  * All STAs in this BSS are HT20/40 but there might be
1281                  * STAs not supporting greenfield mode.
1282                  * => Disable protection for HT transmissions.
1283                  */
1284                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1285
1286                 break;
1287         case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1288                 /*
1289                  * All STAs in this BSS are HT20 or HT20/40 but there
1290                  * might be STAs not supporting greenfield mode.
1291                  * => Protect all HT40 transmissions.
1292                  */
1293                 mm20_mode = gf20_mode = 0;
1294                 mm40_mode = gf40_mode = 2;
1295
1296                 break;
1297         case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1298                 /*
1299                  * Nonmember protection:
1300                  * According to 802.11n we _should_ protect all
1301                  * HT transmissions (but we don't have to).
1302                  *
1303                  * But if cts_protection is enabled we _shall_ protect
1304                  * all HT transmissions using a CCK rate.
1305                  *
1306                  * And if any station is non GF we _shall_ protect
1307                  * GF transmissions.
1308                  *
1309                  * We decide to protect everything
1310                  * -> fall through to mixed mode.
1311                  */
1312         case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1313                 /*
1314                  * Legacy STAs are present
1315                  * => Protect all HT transmissions.
1316                  */
1317                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1318
1319                 /*
1320                  * If erp protection is needed we have to protect HT
1321                  * transmissions with CCK 11M long preamble.
1322                  */
1323                 if (erp->cts_protection) {
1324                         /* don't duplicate RTS/CTS in CCK mode */
1325                         mm20_rate = mm40_rate = 0x0003;
1326                         gf20_rate = gf40_rate = 0x0003;
1327                 }
1328                 break;
1329         };
1330
1331         /* check for STAs not supporting greenfield mode */
1332         if (any_sta_nongf)
1333                 gf20_mode = gf40_mode = 2;
1334
1335         /* Update HT protection config */
1336         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1337         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1338         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1339         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1340
1341         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1342         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1343         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1344         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1345
1346         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1347         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1348         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1349         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1350
1351         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1352         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1353         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1354         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1355 }
1356
1357 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1358                        u32 changed)
1359 {
1360         u32 reg;
1361
1362         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1363                 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1364                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1365                                    !!erp->short_preamble);
1366                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1367                                    !!erp->short_preamble);
1368                 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1369         }
1370
1371         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1372                 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1373                 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1374                                    erp->cts_protection ? 2 : 0);
1375                 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1376         }
1377
1378         if (changed & BSS_CHANGED_BASIC_RATES) {
1379                 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1380                                          erp->basic_rates);
1381                 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1382         }
1383
1384         if (changed & BSS_CHANGED_ERP_SLOT) {
1385                 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1386                 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1387                                    erp->slot_time);
1388                 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1389
1390                 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1391                 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1392                 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1393         }
1394
1395         if (changed & BSS_CHANGED_BEACON_INT) {
1396                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1397                 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1398                                    erp->beacon_int * 16);
1399                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1400         }
1401
1402         if (changed & BSS_CHANGED_HT)
1403                 rt2800_config_ht_opmode(rt2x00dev, erp);
1404 }
1405 EXPORT_SYMBOL_GPL(rt2800_config_erp);
1406
1407 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1408                                      enum antenna ant)
1409 {
1410         u32 reg;
1411         u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1412         u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1413
1414         if (rt2x00_is_pci(rt2x00dev)) {
1415                 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1416                 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1417                 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1418         } else if (rt2x00_is_usb(rt2x00dev))
1419                 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1420                                    eesk_pin, 0);
1421
1422         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
1423         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
1424         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, gpio_bit3);
1425         rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
1426 }
1427
1428 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1429 {
1430         u8 r1;
1431         u8 r3;
1432         u16 eeprom;
1433
1434         rt2800_bbp_read(rt2x00dev, 1, &r1);
1435         rt2800_bbp_read(rt2x00dev, 3, &r3);
1436
1437         /*
1438          * Configure the TX antenna.
1439          */
1440         switch (ant->tx_chain_num) {
1441         case 1:
1442                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1443                 break;
1444         case 2:
1445                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1446                 break;
1447         case 3:
1448                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1449                 break;
1450         }
1451
1452         /*
1453          * Configure the RX antenna.
1454          */
1455         switch (ant->rx_chain_num) {
1456         case 1:
1457                 if (rt2x00_rt(rt2x00dev, RT3070) ||
1458                     rt2x00_rt(rt2x00dev, RT3090) ||
1459                     rt2x00_rt(rt2x00dev, RT3390)) {
1460                         rt2x00_eeprom_read(rt2x00dev,
1461                                            EEPROM_NIC_CONF1, &eeprom);
1462                         if (rt2x00_get_field16(eeprom,
1463                                                 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1464                                 rt2800_set_ant_diversity(rt2x00dev,
1465                                                 rt2x00dev->default_ant.rx);
1466                 }
1467                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1468                 break;
1469         case 2:
1470                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1471                 break;
1472         case 3:
1473                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1474                 break;
1475         }
1476
1477         rt2800_bbp_write(rt2x00dev, 3, r3);
1478         rt2800_bbp_write(rt2x00dev, 1, r1);
1479 }
1480 EXPORT_SYMBOL_GPL(rt2800_config_ant);
1481
1482 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1483                                    struct rt2x00lib_conf *libconf)
1484 {
1485         u16 eeprom;
1486         short lna_gain;
1487
1488         if (libconf->rf.channel <= 14) {
1489                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1490                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1491         } else if (libconf->rf.channel <= 64) {
1492                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1493                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1494         } else if (libconf->rf.channel <= 128) {
1495                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1496                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
1497         } else {
1498                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1499                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
1500         }
1501
1502         rt2x00dev->lna_gain = lna_gain;
1503 }
1504
1505 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1506                                          struct ieee80211_conf *conf,
1507                                          struct rf_channel *rf,
1508                                          struct channel_info *info)
1509 {
1510         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1511
1512         if (rt2x00dev->default_ant.tx_chain_num == 1)
1513                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1514
1515         if (rt2x00dev->default_ant.rx_chain_num == 1) {
1516                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1517                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1518         } else if (rt2x00dev->default_ant.rx_chain_num == 2)
1519                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1520
1521         if (rf->channel > 14) {
1522                 /*
1523                  * When TX power is below 0, we should increase it by 7 to
1524                  * make it a positive value (Minumum value is -7).
1525                  * However this means that values between 0 and 7 have
1526                  * double meaning, and we should set a 7DBm boost flag.
1527                  */
1528                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
1529                                    (info->default_power1 >= 0));
1530
1531                 if (info->default_power1 < 0)
1532                         info->default_power1 += 7;
1533
1534                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
1535
1536                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
1537                                    (info->default_power2 >= 0));
1538
1539                 if (info->default_power2 < 0)
1540                         info->default_power2 += 7;
1541
1542                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
1543         } else {
1544                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1545                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
1546         }
1547
1548         rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1549
1550         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1551         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1552         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1553         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1554
1555         udelay(200);
1556
1557         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1558         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1559         rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1560         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1561
1562         udelay(200);
1563
1564         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1565         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1566         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1567         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1568 }
1569
1570 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1571                                          struct ieee80211_conf *conf,
1572                                          struct rf_channel *rf,
1573                                          struct channel_info *info)
1574 {
1575         u8 rfcsr;
1576
1577         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1578         rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
1579
1580         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1581         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1582         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1583
1584         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1585         rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
1586         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1587
1588         rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1589         rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
1590         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1591
1592         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1593         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1594         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1595
1596         rt2800_rfcsr_write(rt2x00dev, 24,
1597                               rt2x00dev->calibration[conf_is_ht40(conf)]);
1598
1599         rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1600         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1601         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1602 }
1603
1604
1605 #define RT5390_POWER_BOUND     0x27
1606 #define RT5390_FREQ_OFFSET_BOUND       0x5f
1607
1608 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
1609                                          struct ieee80211_conf *conf,
1610                                          struct rf_channel *rf,
1611                                          struct channel_info *info)
1612 {
1613         u8 rfcsr;
1614         u16 eeprom;
1615
1616         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
1617         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
1618         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
1619         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
1620         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
1621
1622         rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
1623         if (info->default_power1 > RT5390_POWER_BOUND)
1624                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, RT5390_POWER_BOUND);
1625         else
1626                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
1627         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
1628
1629         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1630         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
1631         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
1632         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
1633         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
1634         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1635
1636         rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1637         if (rt2x00dev->freq_offset > RT5390_FREQ_OFFSET_BOUND)
1638                 rt2x00_set_field8(&rfcsr, RFCSR17_CODE,
1639                                   RT5390_FREQ_OFFSET_BOUND);
1640         else
1641                 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
1642         rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
1643
1644         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
1645         if (rf->channel <= 14) {
1646                 int idx = rf->channel-1;
1647
1648                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST)) {
1649                         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
1650                                 /* r55/r59 value array of channel 1~14 */
1651                                 static const char r55_bt_rev[] = {0x83, 0x83,
1652                                         0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
1653                                         0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
1654                                 static const char r59_bt_rev[] = {0x0e, 0x0e,
1655                                         0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
1656                                         0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
1657
1658                                 rt2800_rfcsr_write(rt2x00dev, 55,
1659                                                    r55_bt_rev[idx]);
1660                                 rt2800_rfcsr_write(rt2x00dev, 59,
1661                                                    r59_bt_rev[idx]);
1662                         } else {
1663                                 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
1664                                         0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
1665                                         0x88, 0x88, 0x86, 0x85, 0x84};
1666
1667                                 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
1668                         }
1669                 } else {
1670                         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
1671                                 static const char r55_nonbt_rev[] = {0x23, 0x23,
1672                                         0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
1673                                         0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
1674                                 static const char r59_nonbt_rev[] = {0x07, 0x07,
1675                                         0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
1676                                         0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
1677
1678                                 rt2800_rfcsr_write(rt2x00dev, 55,
1679                                                    r55_nonbt_rev[idx]);
1680                                 rt2800_rfcsr_write(rt2x00dev, 59,
1681                                                    r59_nonbt_rev[idx]);
1682                         } else if (rt2x00_rt(rt2x00dev, RT5390)) {
1683                                 static const char r59_non_bt[] = {0x8f, 0x8f,
1684                                         0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
1685                                         0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
1686
1687                                 rt2800_rfcsr_write(rt2x00dev, 59,
1688                                                    r59_non_bt[idx]);
1689                         }
1690                 }
1691         }
1692
1693         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1694         rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
1695         rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
1696         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1697
1698         rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
1699         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1700         rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
1701 }
1702
1703 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
1704                                   struct ieee80211_conf *conf,
1705                                   struct rf_channel *rf,
1706                                   struct channel_info *info)
1707 {
1708         u32 reg;
1709         unsigned int tx_pin;
1710         u8 bbp;
1711
1712         if (rf->channel <= 14) {
1713                 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
1714                 info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2);
1715         } else {
1716                 info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1);
1717                 info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2);
1718         }
1719
1720         if (rt2x00_rf(rt2x00dev, RF2020) ||
1721             rt2x00_rf(rt2x00dev, RF3020) ||
1722             rt2x00_rf(rt2x00dev, RF3021) ||
1723             rt2x00_rf(rt2x00dev, RF3022) ||
1724             rt2x00_rf(rt2x00dev, RF3052) ||
1725             rt2x00_rf(rt2x00dev, RF3320))
1726                 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
1727         else if (rt2x00_rf(rt2x00dev, RF5390))
1728                 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
1729         else
1730                 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
1731
1732         /*
1733          * Change BBP settings
1734          */
1735         rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
1736         rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
1737         rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
1738         rt2800_bbp_write(rt2x00dev, 86, 0);
1739
1740         if (rf->channel <= 14) {
1741                 if (!rt2x00_rt(rt2x00dev, RT5390)) {
1742                         if (test_bit(CONFIG_EXTERNAL_LNA_BG,
1743                                      &rt2x00dev->flags)) {
1744                                 rt2800_bbp_write(rt2x00dev, 82, 0x62);
1745                                 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1746                         } else {
1747                                 rt2800_bbp_write(rt2x00dev, 82, 0x84);
1748                                 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1749                         }
1750                 }
1751         } else {
1752                 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
1753
1754                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1755                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
1756                 else
1757                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
1758         }
1759
1760         rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
1761         rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
1762         rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
1763         rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
1764         rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
1765
1766         tx_pin = 0;
1767
1768         /* Turn on unused PA or LNA when not using 1T or 1R */
1769         if (rt2x00dev->default_ant.tx_chain_num == 2) {
1770                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
1771                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
1772         }
1773
1774         /* Turn on unused PA or LNA when not using 1T or 1R */
1775         if (rt2x00dev->default_ant.rx_chain_num == 2) {
1776                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
1777                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
1778         }
1779
1780         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
1781         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
1782         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
1783         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
1784         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
1785         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
1786
1787         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
1788
1789         rt2800_bbp_read(rt2x00dev, 4, &bbp);
1790         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
1791         rt2800_bbp_write(rt2x00dev, 4, bbp);
1792
1793         rt2800_bbp_read(rt2x00dev, 3, &bbp);
1794         rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
1795         rt2800_bbp_write(rt2x00dev, 3, bbp);
1796
1797         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
1798                 if (conf_is_ht40(conf)) {
1799                         rt2800_bbp_write(rt2x00dev, 69, 0x1a);
1800                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1801                         rt2800_bbp_write(rt2x00dev, 73, 0x16);
1802                 } else {
1803                         rt2800_bbp_write(rt2x00dev, 69, 0x16);
1804                         rt2800_bbp_write(rt2x00dev, 70, 0x08);
1805                         rt2800_bbp_write(rt2x00dev, 73, 0x11);
1806                 }
1807         }
1808
1809         msleep(1);
1810
1811         /*
1812          * Clear channel statistic counters
1813          */
1814         rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
1815         rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
1816         rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
1817 }
1818
1819 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
1820 {
1821         u8 tssi_bounds[9];
1822         u8 current_tssi;
1823         u16 eeprom;
1824         u8 step;
1825         int i;
1826
1827         /*
1828          * Read TSSI boundaries for temperature compensation from
1829          * the EEPROM.
1830          *
1831          * Array idx               0    1    2    3    4    5    6    7    8
1832          * Matching Delta value   -4   -3   -2   -1    0   +1   +2   +3   +4
1833          * Example TSSI bounds  0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
1834          */
1835         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1836                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
1837                 tssi_bounds[0] = rt2x00_get_field16(eeprom,
1838                                         EEPROM_TSSI_BOUND_BG1_MINUS4);
1839                 tssi_bounds[1] = rt2x00_get_field16(eeprom,
1840                                         EEPROM_TSSI_BOUND_BG1_MINUS3);
1841
1842                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
1843                 tssi_bounds[2] = rt2x00_get_field16(eeprom,
1844                                         EEPROM_TSSI_BOUND_BG2_MINUS2);
1845                 tssi_bounds[3] = rt2x00_get_field16(eeprom,
1846                                         EEPROM_TSSI_BOUND_BG2_MINUS1);
1847
1848                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
1849                 tssi_bounds[4] = rt2x00_get_field16(eeprom,
1850                                         EEPROM_TSSI_BOUND_BG3_REF);
1851                 tssi_bounds[5] = rt2x00_get_field16(eeprom,
1852                                         EEPROM_TSSI_BOUND_BG3_PLUS1);
1853
1854                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
1855                 tssi_bounds[6] = rt2x00_get_field16(eeprom,
1856                                         EEPROM_TSSI_BOUND_BG4_PLUS2);
1857                 tssi_bounds[7] = rt2x00_get_field16(eeprom,
1858                                         EEPROM_TSSI_BOUND_BG4_PLUS3);
1859
1860                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
1861                 tssi_bounds[8] = rt2x00_get_field16(eeprom,
1862                                         EEPROM_TSSI_BOUND_BG5_PLUS4);
1863
1864                 step = rt2x00_get_field16(eeprom,
1865                                           EEPROM_TSSI_BOUND_BG5_AGC_STEP);
1866         } else {
1867                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
1868                 tssi_bounds[0] = rt2x00_get_field16(eeprom,
1869                                         EEPROM_TSSI_BOUND_A1_MINUS4);
1870                 tssi_bounds[1] = rt2x00_get_field16(eeprom,
1871                                         EEPROM_TSSI_BOUND_A1_MINUS3);
1872
1873                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
1874                 tssi_bounds[2] = rt2x00_get_field16(eeprom,
1875                                         EEPROM_TSSI_BOUND_A2_MINUS2);
1876                 tssi_bounds[3] = rt2x00_get_field16(eeprom,
1877                                         EEPROM_TSSI_BOUND_A2_MINUS1);
1878
1879                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
1880                 tssi_bounds[4] = rt2x00_get_field16(eeprom,
1881                                         EEPROM_TSSI_BOUND_A3_REF);
1882                 tssi_bounds[5] = rt2x00_get_field16(eeprom,
1883                                         EEPROM_TSSI_BOUND_A3_PLUS1);
1884
1885                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
1886                 tssi_bounds[6] = rt2x00_get_field16(eeprom,
1887                                         EEPROM_TSSI_BOUND_A4_PLUS2);
1888                 tssi_bounds[7] = rt2x00_get_field16(eeprom,
1889                                         EEPROM_TSSI_BOUND_A4_PLUS3);
1890
1891                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
1892                 tssi_bounds[8] = rt2x00_get_field16(eeprom,
1893                                         EEPROM_TSSI_BOUND_A5_PLUS4);
1894
1895                 step = rt2x00_get_field16(eeprom,
1896                                           EEPROM_TSSI_BOUND_A5_AGC_STEP);
1897         }
1898
1899         /*
1900          * Check if temperature compensation is supported.
1901          */
1902         if (tssi_bounds[4] == 0xff)
1903                 return 0;
1904
1905         /*
1906          * Read current TSSI (BBP 49).
1907          */
1908         rt2800_bbp_read(rt2x00dev, 49, &current_tssi);
1909
1910         /*
1911          * Compare TSSI value (BBP49) with the compensation boundaries
1912          * from the EEPROM and increase or decrease tx power.
1913          */
1914         for (i = 0; i <= 3; i++) {
1915                 if (current_tssi > tssi_bounds[i])
1916                         break;
1917         }
1918
1919         if (i == 4) {
1920                 for (i = 8; i >= 5; i--) {
1921                         if (current_tssi < tssi_bounds[i])
1922                                 break;
1923                 }
1924         }
1925
1926         return (i - 4) * step;
1927 }
1928
1929 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
1930                                       enum ieee80211_band band)
1931 {
1932         u16 eeprom;
1933         u8 comp_en;
1934         u8 comp_type;
1935         int comp_value = 0;
1936
1937         rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
1938
1939         /*
1940          * HT40 compensation not required.
1941          */
1942         if (eeprom == 0xffff ||
1943             !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1944                 return 0;
1945
1946         if (band == IEEE80211_BAND_2GHZ) {
1947                 comp_en = rt2x00_get_field16(eeprom,
1948                                  EEPROM_TXPOWER_DELTA_ENABLE_2G);
1949                 if (comp_en) {
1950                         comp_type = rt2x00_get_field16(eeprom,
1951                                            EEPROM_TXPOWER_DELTA_TYPE_2G);
1952                         comp_value = rt2x00_get_field16(eeprom,
1953                                             EEPROM_TXPOWER_DELTA_VALUE_2G);
1954                         if (!comp_type)
1955                                 comp_value = -comp_value;
1956                 }
1957         } else {
1958                 comp_en = rt2x00_get_field16(eeprom,
1959                                  EEPROM_TXPOWER_DELTA_ENABLE_5G);
1960                 if (comp_en) {
1961                         comp_type = rt2x00_get_field16(eeprom,
1962                                            EEPROM_TXPOWER_DELTA_TYPE_5G);
1963                         comp_value = rt2x00_get_field16(eeprom,
1964                                             EEPROM_TXPOWER_DELTA_VALUE_5G);
1965                         if (!comp_type)
1966                                 comp_value = -comp_value;
1967                 }
1968         }
1969
1970         return comp_value;
1971 }
1972
1973 static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
1974                                    enum ieee80211_band band, int power_level,
1975                                    u8 txpower, int delta)
1976 {
1977         u32 reg;
1978         u16 eeprom;
1979         u8 criterion;
1980         u8 eirp_txpower;
1981         u8 eirp_txpower_criterion;
1982         u8 reg_limit;
1983
1984         if (!((band == IEEE80211_BAND_5GHZ) && is_rate_b))
1985                 return txpower;
1986
1987         if (test_bit(CONFIG_SUPPORT_POWER_LIMIT, &rt2x00dev->flags)) {
1988                 /*
1989                  * Check if eirp txpower exceed txpower_limit.
1990                  * We use OFDM 6M as criterion and its eirp txpower
1991                  * is stored at EEPROM_EIRP_MAX_TX_POWER.
1992                  * .11b data rate need add additional 4dbm
1993                  * when calculating eirp txpower.
1994                  */
1995                 rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
1996                 criterion = rt2x00_get_field32(reg, TX_PWR_CFG_0_6MBS);
1997
1998                 rt2x00_eeprom_read(rt2x00dev,
1999                                    EEPROM_EIRP_MAX_TX_POWER, &eeprom);
2000
2001                 if (band == IEEE80211_BAND_2GHZ)
2002                         eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2003                                                  EEPROM_EIRP_MAX_TX_POWER_2GHZ);
2004                 else
2005                         eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2006                                                  EEPROM_EIRP_MAX_TX_POWER_5GHZ);
2007
2008                 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
2009                                (is_rate_b ? 4 : 0) + delta;
2010
2011                 reg_limit = (eirp_txpower > power_level) ?
2012                                         (eirp_txpower - power_level) : 0;
2013         } else
2014                 reg_limit = 0;
2015
2016         return txpower + delta - reg_limit;
2017 }
2018
2019 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
2020                                   enum ieee80211_band band,
2021                                   int power_level)
2022 {
2023         u8 txpower;
2024         u16 eeprom;
2025         int i, is_rate_b;
2026         u32 reg;
2027         u8 r1;
2028         u32 offset;
2029         int delta;
2030
2031         /*
2032          * Calculate HT40 compensation delta
2033          */
2034         delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
2035
2036         /*
2037          * calculate temperature compensation delta
2038          */
2039         delta += rt2800_get_gain_calibration_delta(rt2x00dev);
2040
2041         /*
2042          * set to normal bbp tx power control mode: +/- 0dBm
2043          */
2044         rt2800_bbp_read(rt2x00dev, 1, &r1);
2045         rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, 0);
2046         rt2800_bbp_write(rt2x00dev, 1, r1);
2047         offset = TX_PWR_CFG_0;
2048
2049         for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
2050                 /* just to be safe */
2051                 if (offset > TX_PWR_CFG_4)
2052                         break;
2053
2054                 rt2800_register_read(rt2x00dev, offset, &reg);
2055
2056                 /* read the next four txpower values */
2057                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
2058                                    &eeprom);
2059
2060                 is_rate_b = i ? 0 : 1;
2061                 /*
2062                  * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
2063                  * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
2064                  * TX_PWR_CFG_4: unknown
2065                  */
2066                 txpower = rt2x00_get_field16(eeprom,
2067                                              EEPROM_TXPOWER_BYRATE_RATE0);
2068                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2069                                              power_level, txpower, delta);
2070                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
2071
2072                 /*
2073                  * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
2074                  * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
2075                  * TX_PWR_CFG_4: unknown
2076                  */
2077                 txpower = rt2x00_get_field16(eeprom,
2078                                              EEPROM_TXPOWER_BYRATE_RATE1);
2079                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2080                                              power_level, txpower, delta);
2081                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
2082
2083                 /*
2084                  * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
2085                  * TX_PWR_CFG_2: MCS6,  TX_PWR_CFG_3: MCS14,
2086                  * TX_PWR_CFG_4: unknown
2087                  */
2088                 txpower = rt2x00_get_field16(eeprom,
2089                                              EEPROM_TXPOWER_BYRATE_RATE2);
2090                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2091                                              power_level, txpower, delta);
2092                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
2093
2094                 /*
2095                  * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
2096                  * TX_PWR_CFG_2: MCS7,  TX_PWR_CFG_3: MCS15,
2097                  * TX_PWR_CFG_4: unknown
2098                  */
2099                 txpower = rt2x00_get_field16(eeprom,
2100                                              EEPROM_TXPOWER_BYRATE_RATE3);
2101                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2102                                              power_level, txpower, delta);
2103                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
2104
2105                 /* read the next four txpower values */
2106                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
2107                                    &eeprom);
2108
2109                 is_rate_b = 0;
2110                 /*
2111                  * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
2112                  * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
2113                  * TX_PWR_CFG_4: unknown
2114                  */
2115                 txpower = rt2x00_get_field16(eeprom,
2116                                              EEPROM_TXPOWER_BYRATE_RATE0);
2117                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2118                                              power_level, txpower, delta);
2119                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
2120
2121                 /*
2122                  * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
2123                  * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
2124                  * TX_PWR_CFG_4: unknown
2125                  */
2126                 txpower = rt2x00_get_field16(eeprom,
2127                                              EEPROM_TXPOWER_BYRATE_RATE1);
2128                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2129                                              power_level, txpower, delta);
2130                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
2131
2132                 /*
2133                  * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
2134                  * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
2135                  * TX_PWR_CFG_4: unknown
2136                  */
2137                 txpower = rt2x00_get_field16(eeprom,
2138                                              EEPROM_TXPOWER_BYRATE_RATE2);
2139                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2140                                              power_level, txpower, delta);
2141                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
2142
2143                 /*
2144                  * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
2145                  * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
2146                  * TX_PWR_CFG_4: unknown
2147                  */
2148                 txpower = rt2x00_get_field16(eeprom,
2149                                              EEPROM_TXPOWER_BYRATE_RATE3);
2150                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2151                                              power_level, txpower, delta);
2152                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
2153
2154                 rt2800_register_write(rt2x00dev, offset, reg);
2155
2156                 /* next TX_PWR_CFG register */
2157                 offset += 4;
2158         }
2159 }
2160
2161 void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
2162 {
2163         rt2800_config_txpower(rt2x00dev, rt2x00dev->curr_band,
2164                               rt2x00dev->tx_power);
2165 }
2166 EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
2167
2168 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
2169                                       struct rt2x00lib_conf *libconf)
2170 {
2171         u32 reg;
2172
2173         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
2174         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
2175                            libconf->conf->short_frame_max_tx_count);
2176         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
2177                            libconf->conf->long_frame_max_tx_count);
2178         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
2179 }
2180
2181 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
2182                              struct rt2x00lib_conf *libconf)
2183 {
2184         enum dev_state state =
2185             (libconf->conf->flags & IEEE80211_CONF_PS) ?
2186                 STATE_SLEEP : STATE_AWAKE;
2187         u32 reg;
2188
2189         if (state == STATE_SLEEP) {
2190                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
2191
2192                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
2193                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
2194                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
2195                                    libconf->conf->listen_interval - 1);
2196                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
2197                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
2198
2199                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
2200         } else {
2201                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
2202                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
2203                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
2204                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
2205                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
2206
2207                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
2208         }
2209 }
2210
2211 void rt2800_config(struct rt2x00_dev *rt2x00dev,
2212                    struct rt2x00lib_conf *libconf,
2213                    const unsigned int flags)
2214 {
2215         /* Always recalculate LNA gain before changing configuration */
2216         rt2800_config_lna_gain(rt2x00dev, libconf);
2217
2218         if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
2219                 rt2800_config_channel(rt2x00dev, libconf->conf,
2220                                       &libconf->rf, &libconf->channel);
2221                 rt2800_config_txpower(rt2x00dev, libconf->conf->channel->band,
2222                                       libconf->conf->power_level);
2223         }
2224         if (flags & IEEE80211_CONF_CHANGE_POWER)
2225                 rt2800_config_txpower(rt2x00dev, libconf->conf->channel->band,
2226                                       libconf->conf->power_level);
2227         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
2228                 rt2800_config_retry_limit(rt2x00dev, libconf);
2229         if (flags & IEEE80211_CONF_CHANGE_PS)
2230                 rt2800_config_ps(rt2x00dev, libconf);
2231 }
2232 EXPORT_SYMBOL_GPL(rt2800_config);
2233
2234 /*
2235  * Link tuning
2236  */
2237 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
2238 {
2239         u32 reg;
2240
2241         /*
2242          * Update FCS error count from register.
2243          */
2244         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
2245         qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
2246 }
2247 EXPORT_SYMBOL_GPL(rt2800_link_stats);
2248
2249 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
2250 {
2251         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
2252                 if (rt2x00_rt(rt2x00dev, RT3070) ||
2253                     rt2x00_rt(rt2x00dev, RT3071) ||
2254                     rt2x00_rt(rt2x00dev, RT3090) ||
2255                     rt2x00_rt(rt2x00dev, RT3390) ||
2256                     rt2x00_rt(rt2x00dev, RT5390))
2257                         return 0x1c + (2 * rt2x00dev->lna_gain);
2258                 else
2259                         return 0x2e + rt2x00dev->lna_gain;
2260         }
2261
2262         if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
2263                 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
2264         else
2265                 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
2266 }
2267
2268 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
2269                                   struct link_qual *qual, u8 vgc_level)
2270 {
2271         if (qual->vgc_level != vgc_level) {
2272                 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
2273                 qual->vgc_level = vgc_level;
2274                 qual->vgc_level_reg = vgc_level;
2275         }
2276 }
2277
2278 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
2279 {
2280         rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
2281 }
2282 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
2283
2284 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
2285                        const u32 count)
2286 {
2287         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
2288                 return;
2289
2290         /*
2291          * When RSSI is better then -80 increase VGC level with 0x10
2292          */
2293         rt2800_set_vgc(rt2x00dev, qual,
2294                        rt2800_get_default_vgc(rt2x00dev) +
2295                        ((qual->rssi > -80) * 0x10));
2296 }
2297 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
2298
2299 /*
2300  * Initialization functions.
2301  */
2302 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
2303 {
2304         u32 reg;
2305         u16 eeprom;
2306         unsigned int i;
2307         int ret;
2308
2309         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2310         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2311         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2312         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2313         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2314         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2315         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2316
2317         ret = rt2800_drv_init_registers(rt2x00dev);
2318         if (ret)
2319                 return ret;
2320
2321         rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
2322         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
2323         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
2324         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
2325         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
2326         rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
2327
2328         rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
2329         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
2330         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
2331         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
2332         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
2333         rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
2334
2335         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
2336         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
2337
2338         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
2339
2340         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2341         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
2342         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
2343         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
2344         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
2345         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
2346         rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
2347         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2348
2349         rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
2350
2351         rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
2352         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
2353         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
2354         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
2355
2356         if (rt2x00_rt(rt2x00dev, RT3071) ||
2357             rt2x00_rt(rt2x00dev, RT3090) ||
2358             rt2x00_rt(rt2x00dev, RT3390)) {
2359                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2360                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2361                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2362                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2363                     rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
2364                         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2365                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
2366                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
2367                                                       0x0000002c);
2368                         else
2369                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
2370                                                       0x0000000f);
2371                 } else {
2372                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2373                 }
2374         } else if (rt2x00_rt(rt2x00dev, RT3070)) {
2375                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2376
2377                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
2378                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2379                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
2380                 } else {
2381                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2382                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2383                 }
2384         } else if (rt2800_is_305x_soc(rt2x00dev)) {
2385                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2386                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2387                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000001f);
2388         } else if (rt2x00_rt(rt2x00dev, RT5390)) {
2389                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
2390                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2391                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2392         } else {
2393                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
2394                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2395         }
2396
2397         rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
2398         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
2399         rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
2400         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
2401         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
2402         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
2403         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
2404         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
2405         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
2406         rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
2407
2408         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
2409         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
2410         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
2411         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
2412         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
2413
2414         rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
2415         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
2416         if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
2417             rt2x00_rt(rt2x00dev, RT2883) ||
2418             rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
2419                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
2420         else
2421                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
2422         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
2423         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
2424         rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
2425
2426         rt2800_register_read(rt2x00dev, LED_CFG, &reg);
2427         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
2428         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
2429         rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
2430         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
2431         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
2432         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
2433         rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
2434         rt2800_register_write(rt2x00dev, LED_CFG, reg);
2435
2436         rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
2437
2438         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
2439         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
2440         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
2441         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
2442         rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
2443         rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
2444         rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
2445         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
2446
2447         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
2448         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
2449         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
2450         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
2451         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
2452         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
2453         rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
2454         rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
2455         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
2456
2457         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2458         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
2459         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
2460         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
2461         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2462         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2463         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2464         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2465         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2466         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2467         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
2468         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2469
2470         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2471         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
2472         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
2473         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
2474         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2475         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2476         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2477         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2478         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2479         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2480         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
2481         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2482
2483         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2484         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
2485         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
2486         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
2487         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2488         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2489         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2490         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2491         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2492         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2493         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
2494         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2495
2496         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2497         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
2498         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
2499         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
2500         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2501         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2502         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2503         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2504         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2505         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
2506         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
2507         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2508
2509         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2510         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
2511         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
2512         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
2513         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2514         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2515         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2516         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2517         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2518         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2519         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
2520         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2521
2522         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2523         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
2524         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
2525         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
2526         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2527         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2528         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2529         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2530         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2531         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
2532         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
2533         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2534
2535         if (rt2x00_is_usb(rt2x00dev)) {
2536                 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
2537
2538                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2539                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2540                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2541                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2542                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2543                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
2544                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
2545                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
2546                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
2547                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
2548                 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2549         }
2550
2551         /*
2552          * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
2553          * although it is reserved.
2554          */
2555         rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
2556         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
2557         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
2558         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
2559         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
2560         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
2561         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
2562         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
2563         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
2564         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
2565         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
2566         rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
2567
2568         rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
2569
2570         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2571         rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
2572         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
2573                            IEEE80211_MAX_RTS_THRESHOLD);
2574         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
2575         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
2576
2577         rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
2578
2579         /*
2580          * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
2581          * time should be set to 16. However, the original Ralink driver uses
2582          * 16 for both and indeed using a value of 10 for CCK SIFS results in
2583          * connection problems with 11g + CTS protection. Hence, use the same
2584          * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
2585          */
2586         rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
2587         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
2588         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
2589         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
2590         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
2591         rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
2592         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
2593
2594         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
2595
2596         /*
2597          * ASIC will keep garbage value after boot, clear encryption keys.
2598          */
2599         for (i = 0; i < 4; i++)
2600                 rt2800_register_write(rt2x00dev,
2601                                          SHARED_KEY_MODE_ENTRY(i), 0);
2602
2603         for (i = 0; i < 256; i++) {
2604                 static const u32 wcid[2] = { 0xffffffff, 0x00ffffff };
2605                 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
2606                                               wcid, sizeof(wcid));
2607
2608                 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 0);
2609                 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
2610         }
2611
2612         /*
2613          * Clear all beacons
2614          */
2615         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE0);
2616         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE1);
2617         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE2);
2618         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE3);
2619         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE4);
2620         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE5);
2621         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE6);
2622         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE7);
2623
2624         if (rt2x00_is_usb(rt2x00dev)) {
2625                 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
2626                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
2627                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
2628         } else if (rt2x00_is_pcie(rt2x00dev)) {
2629                 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
2630                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
2631                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
2632         }
2633
2634         rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
2635         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
2636         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
2637         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
2638         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
2639         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
2640         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
2641         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
2642         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
2643         rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
2644
2645         rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
2646         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
2647         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
2648         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
2649         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
2650         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
2651         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
2652         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
2653         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
2654         rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
2655
2656         rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
2657         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
2658         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
2659         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
2660         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
2661         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
2662         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
2663         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
2664         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
2665         rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
2666
2667         rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
2668         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
2669         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
2670         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
2671         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
2672         rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
2673
2674         /*
2675          * Do not force the BA window size, we use the TXWI to set it
2676          */
2677         rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
2678         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
2679         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
2680         rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
2681
2682         /*
2683          * We must clear the error counters.
2684          * These registers are cleared on read,
2685          * so we may pass a useless variable to store the value.
2686          */
2687         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
2688         rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
2689         rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
2690         rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
2691         rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
2692         rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
2693
2694         /*
2695          * Setup leadtime for pre tbtt interrupt to 6ms
2696          */
2697         rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
2698         rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
2699         rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
2700
2701         /*
2702          * Set up channel statistics timer
2703          */
2704         rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
2705         rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
2706         rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
2707         rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
2708         rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
2709         rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
2710         rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
2711
2712         return 0;
2713 }
2714
2715 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
2716 {
2717         unsigned int i;
2718         u32 reg;
2719
2720         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2721                 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
2722                 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
2723                         return 0;
2724
2725                 udelay(REGISTER_BUSY_DELAY);
2726         }
2727
2728         ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
2729         return -EACCES;
2730 }
2731
2732 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
2733 {
2734         unsigned int i;
2735         u8 value;
2736
2737         /*
2738          * BBP was enabled after firmware was loaded,
2739          * but we need to reactivate it now.
2740          */
2741         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
2742         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
2743         msleep(1);
2744
2745         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2746                 rt2800_bbp_read(rt2x00dev, 0, &value);
2747                 if ((value != 0xff) && (value != 0x00))
2748                         return 0;
2749                 udelay(REGISTER_BUSY_DELAY);
2750         }
2751
2752         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
2753         return -EACCES;
2754 }
2755
2756 static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
2757 {
2758         unsigned int i;
2759         u16 eeprom;
2760         u8 reg_id;
2761         u8 value;
2762
2763         if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
2764                      rt2800_wait_bbp_ready(rt2x00dev)))
2765                 return -EACCES;
2766
2767         if (rt2x00_rt(rt2x00dev, RT5390)) {
2768                 rt2800_bbp_read(rt2x00dev, 4, &value);
2769                 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
2770                 rt2800_bbp_write(rt2x00dev, 4, value);
2771         }
2772
2773         if (rt2800_is_305x_soc(rt2x00dev) ||
2774             rt2x00_rt(rt2x00dev, RT5390))
2775                 rt2800_bbp_write(rt2x00dev, 31, 0x08);
2776
2777         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
2778         rt2800_bbp_write(rt2x00dev, 66, 0x38);
2779
2780         if (rt2x00_rt(rt2x00dev, RT5390))
2781                 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
2782
2783         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
2784                 rt2800_bbp_write(rt2x00dev, 69, 0x16);
2785                 rt2800_bbp_write(rt2x00dev, 73, 0x12);
2786         } else if (rt2x00_rt(rt2x00dev, RT5390)) {
2787                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
2788                 rt2800_bbp_write(rt2x00dev, 73, 0x13);
2789                 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2790                 rt2800_bbp_write(rt2x00dev, 76, 0x28);
2791                 rt2800_bbp_write(rt2x00dev, 77, 0x59);
2792         } else {
2793                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
2794                 rt2800_bbp_write(rt2x00dev, 73, 0x10);
2795         }
2796
2797         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
2798
2799         if (rt2x00_rt(rt2x00dev, RT3070) ||
2800             rt2x00_rt(rt2x00dev, RT3071) ||
2801             rt2x00_rt(rt2x00dev, RT3090) ||
2802             rt2x00_rt(rt2x00dev, RT3390) ||
2803             rt2x00_rt(rt2x00dev, RT5390)) {
2804                 rt2800_bbp_write(rt2x00dev, 79, 0x13);
2805                 rt2800_bbp_write(rt2x00dev, 80, 0x05);
2806                 rt2800_bbp_write(rt2x00dev, 81, 0x33);
2807         } else if (rt2800_is_305x_soc(rt2x00dev)) {
2808                 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
2809                 rt2800_bbp_write(rt2x00dev, 80, 0x08);
2810         } else {
2811                 rt2800_bbp_write(rt2x00dev, 81, 0x37);
2812         }
2813
2814         rt2800_bbp_write(rt2x00dev, 82, 0x62);
2815         if (rt2x00_rt(rt2x00dev, RT5390))
2816                 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
2817         else
2818                 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
2819
2820         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
2821                 rt2800_bbp_write(rt2x00dev, 84, 0x19);
2822         else if (rt2x00_rt(rt2x00dev, RT5390))
2823                 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
2824         else
2825                 rt2800_bbp_write(rt2x00dev, 84, 0x99);
2826
2827         if (rt2x00_rt(rt2x00dev, RT5390))
2828                 rt2800_bbp_write(rt2x00dev, 86, 0x38);
2829         else
2830                 rt2800_bbp_write(rt2x00dev, 86, 0x00);
2831
2832         rt2800_bbp_write(rt2x00dev, 91, 0x04);
2833
2834         if (rt2x00_rt(rt2x00dev, RT5390))
2835                 rt2800_bbp_write(rt2x00dev, 92, 0x02);
2836         else
2837                 rt2800_bbp_write(rt2x00dev, 92, 0x00);
2838
2839         if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
2840             rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
2841             rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
2842             rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
2843             rt2x00_rt(rt2x00dev, RT5390) ||
2844             rt2800_is_305x_soc(rt2x00dev))
2845                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
2846         else
2847                 rt2800_bbp_write(rt2x00dev, 103, 0x00);
2848
2849         if (rt2x00_rt(rt2x00dev, RT5390))
2850                 rt2800_bbp_write(rt2x00dev, 104, 0x92);
2851
2852         if (rt2800_is_305x_soc(rt2x00dev))
2853                 rt2800_bbp_write(rt2x00dev, 105, 0x01);
2854         else if (rt2x00_rt(rt2x00dev, RT5390))
2855                 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
2856         else
2857                 rt2800_bbp_write(rt2x00dev, 105, 0x05);
2858
2859         if (rt2x00_rt(rt2x00dev, RT5390))
2860                 rt2800_bbp_write(rt2x00dev, 106, 0x03);
2861         else
2862                 rt2800_bbp_write(rt2x00dev, 106, 0x35);
2863
2864         if (rt2x00_rt(rt2x00dev, RT5390))
2865                 rt2800_bbp_write(rt2x00dev, 128, 0x12);
2866
2867         if (rt2x00_rt(rt2x00dev, RT3071) ||
2868             rt2x00_rt(rt2x00dev, RT3090) ||
2869             rt2x00_rt(rt2x00dev, RT3390) ||
2870             rt2x00_rt(rt2x00dev, RT5390)) {
2871                 rt2800_bbp_read(rt2x00dev, 138, &value);
2872
2873                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
2874                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
2875                         value |= 0x20;
2876                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
2877                         value &= ~0x02;
2878
2879                 rt2800_bbp_write(rt2x00dev, 138, value);
2880         }
2881
2882         if (rt2x00_rt(rt2x00dev, RT5390)) {
2883                 int ant, div_mode;
2884
2885                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2886                 div_mode = rt2x00_get_field16(eeprom,
2887                                               EEPROM_NIC_CONF1_ANT_DIVERSITY);
2888                 ant = (div_mode == 3) ? 1 : 0;
2889
2890                 /* check if this is a Bluetooth combo card */
2891                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2892                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST)) {
2893                         u32 reg;
2894
2895                         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
2896                         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
2897                         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT6, 0);
2898                         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 0);
2899                         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 0);
2900                         if (ant == 0)
2901                                 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 1);
2902                         else if (ant == 1)
2903                                 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 1);
2904                         rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
2905                 }
2906
2907                 rt2800_bbp_read(rt2x00dev, 152, &value);
2908                 if (ant == 0)
2909                         rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
2910                 else
2911                         rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
2912                 rt2800_bbp_write(rt2x00dev, 152, value);
2913
2914                 /* Init frequency calibration */
2915                 rt2800_bbp_write(rt2x00dev, 142, 1);
2916                 rt2800_bbp_write(rt2x00dev, 143, 57);
2917         }
2918
2919         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
2920                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
2921
2922                 if (eeprom != 0xffff && eeprom != 0x0000) {
2923                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
2924                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
2925                         rt2800_bbp_write(rt2x00dev, reg_id, value);
2926                 }
2927         }
2928
2929         return 0;
2930 }
2931
2932 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
2933                                 bool bw40, u8 rfcsr24, u8 filter_target)
2934 {
2935         unsigned int i;
2936         u8 bbp;
2937         u8 rfcsr;
2938         u8 passband;
2939         u8 stopband;
2940         u8 overtuned = 0;
2941
2942         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2943
2944         rt2800_bbp_read(rt2x00dev, 4, &bbp);
2945         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
2946         rt2800_bbp_write(rt2x00dev, 4, bbp);
2947
2948         rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
2949         rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
2950         rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2951
2952         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
2953         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
2954         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
2955
2956         /*
2957          * Set power & frequency of passband test tone
2958          */
2959         rt2800_bbp_write(rt2x00dev, 24, 0);
2960
2961         for (i = 0; i < 100; i++) {
2962                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
2963                 msleep(1);
2964
2965                 rt2800_bbp_read(rt2x00dev, 55, &passband);
2966                 if (passband)
2967                         break;
2968         }
2969
2970         /*
2971          * Set power & frequency of stopband test tone
2972          */
2973         rt2800_bbp_write(rt2x00dev, 24, 0x06);
2974
2975         for (i = 0; i < 100; i++) {
2976                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
2977                 msleep(1);
2978
2979                 rt2800_bbp_read(rt2x00dev, 55, &stopband);
2980
2981                 if ((passband - stopband) <= filter_target) {
2982                         rfcsr24++;
2983                         overtuned += ((passband - stopband) == filter_target);
2984                 } else
2985                         break;
2986
2987                 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2988         }
2989
2990         rfcsr24 -= !!overtuned;
2991
2992         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2993         return rfcsr24;
2994 }
2995
2996 static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
2997 {
2998         u8 rfcsr;
2999         u8 bbp;
3000         u32 reg;
3001         u16 eeprom;
3002
3003         if (!rt2x00_rt(rt2x00dev, RT3070) &&
3004             !rt2x00_rt(rt2x00dev, RT3071) &&
3005             !rt2x00_rt(rt2x00dev, RT3090) &&
3006             !rt2x00_rt(rt2x00dev, RT3390) &&
3007             !rt2x00_rt(rt2x00dev, RT5390) &&
3008             !rt2800_is_305x_soc(rt2x00dev))
3009                 return 0;
3010
3011         /*
3012          * Init RF calibration.
3013          */
3014         if (rt2x00_rt(rt2x00dev, RT5390)) {
3015                 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
3016                 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
3017                 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3018                 msleep(1);
3019                 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0);
3020                 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3021         } else {
3022                 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3023                 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
3024                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3025                 msleep(1);
3026                 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
3027                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3028         }
3029
3030         if (rt2x00_rt(rt2x00dev, RT3070) ||
3031             rt2x00_rt(rt2x00dev, RT3071) ||
3032             rt2x00_rt(rt2x00dev, RT3090)) {
3033                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3034                 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
3035                 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
3036                 rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
3037                 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
3038                 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
3039                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3040                 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
3041                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3042                 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
3043                 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
3044                 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
3045                 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
3046                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
3047                 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
3048                 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
3049                 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
3050                 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
3051                 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
3052         } else if (rt2x00_rt(rt2x00dev, RT3390)) {
3053                 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
3054                 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
3055                 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
3056                 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
3057                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3058                 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
3059                 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
3060                 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
3061                 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
3062                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
3063                 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
3064                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3065                 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
3066                 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
3067                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3068                 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
3069                 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
3070                 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
3071                 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
3072                 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
3073                 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
3074                 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
3075                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
3076                 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
3077                 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
3078                 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
3079                 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
3080                 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
3081                 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
3082                 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
3083                 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
3084                 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
3085         } else if (rt2800_is_305x_soc(rt2x00dev)) {
3086                 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
3087                 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
3088                 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
3089                 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
3090                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3091                 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
3092                 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
3093                 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
3094                 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
3095                 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
3096                 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
3097                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3098                 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
3099                 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
3100                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3101                 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
3102                 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
3103                 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
3104                 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
3105                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
3106                 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
3107                 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
3108                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
3109                 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
3110                 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
3111                 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
3112                 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
3113                 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
3114                 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
3115                 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
3116                 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
3117                 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
3118                 return 0;
3119         } else if (rt2x00_rt(rt2x00dev, RT5390)) {
3120                 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
3121                 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
3122                 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
3123                 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
3124                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3125                         rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
3126                 else
3127                         rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
3128                 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
3129                 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
3130                 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
3131                 rt2800_rfcsr_write(rt2x00dev, 12, 0xc6);
3132                 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
3133                 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
3134                 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
3135                 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
3136                 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
3137                 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
3138
3139                 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
3140                 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
3141                 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
3142                 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
3143                 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
3144                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3145                         rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
3146                 else
3147                         rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
3148                 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
3149                 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
3150                 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
3151                 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
3152
3153                 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
3154                 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3155                 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3156                 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
3157                 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
3158                 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
3159                 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
3160                 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
3161                 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
3162                 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
3163
3164                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3165                         rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
3166                 else
3167                         rt2800_rfcsr_write(rt2x00dev, 40, 0x4b);
3168                 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
3169                 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
3170                 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
3171                 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
3172                 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
3173                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3174                         rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
3175                 else
3176                         rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
3177                 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
3178                 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
3179                 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
3180
3181                 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
3182                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3183                         rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
3184                 else
3185                         rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
3186                 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
3187                 rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
3188                 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
3189                 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
3190                 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
3191                 rt2800_rfcsr_write(rt2x00dev, 59, 0x63);
3192
3193                 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
3194                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3195                         rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
3196                 else
3197                         rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
3198                 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
3199                 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
3200         }
3201
3202         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
3203                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3204                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3205                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3206                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3207         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
3208                    rt2x00_rt(rt2x00dev, RT3090)) {
3209                 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
3210
3211                 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
3212                 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
3213                 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
3214
3215                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3216                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3217                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3218                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
3219                         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3220                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
3221                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3222                         else
3223                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
3224                 }
3225                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3226
3227                 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
3228                 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
3229                 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
3230         } else if (rt2x00_rt(rt2x00dev, RT3390)) {
3231                 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
3232                 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
3233                 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
3234         }
3235
3236         /*
3237          * Set RX Filter calibration for 20MHz and 40MHz
3238          */
3239         if (rt2x00_rt(rt2x00dev, RT3070)) {
3240                 rt2x00dev->calibration[0] =
3241                         rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
3242                 rt2x00dev->calibration[1] =
3243                         rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
3244         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
3245                    rt2x00_rt(rt2x00dev, RT3090) ||
3246                    rt2x00_rt(rt2x00dev, RT3390)) {
3247                 rt2x00dev->calibration[0] =
3248                         rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
3249                 rt2x00dev->calibration[1] =
3250                         rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
3251         }
3252
3253         if (!rt2x00_rt(rt2x00dev, RT5390)) {
3254                 /*
3255                  * Set back to initial state
3256                  */
3257                 rt2800_bbp_write(rt2x00dev, 24, 0);
3258
3259                 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
3260                 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
3261                 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
3262
3263                 /*
3264                  * Set BBP back to BW20
3265                  */
3266                 rt2800_bbp_read(rt2x00dev, 4, &bbp);
3267                 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
3268                 rt2800_bbp_write(rt2x00dev, 4, bbp);
3269         }
3270
3271         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
3272             rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3273             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
3274             rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
3275                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
3276
3277         rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
3278         rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
3279         rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
3280
3281         if (!rt2x00_rt(rt2x00dev, RT5390)) {
3282                 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
3283                 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
3284                 if (rt2x00_rt(rt2x00dev, RT3070) ||
3285                     rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3286                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
3287                     rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
3288                         if (!test_bit(CONFIG_EXTERNAL_LNA_BG,
3289                                       &rt2x00dev->flags))
3290                                 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
3291                 }
3292                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
3293                 if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
3294                         rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
3295                                         rt2x00_get_field16(eeprom,
3296                                                 EEPROM_TXMIXER_GAIN_BG_VAL));
3297                 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
3298         }
3299
3300         if (rt2x00_rt(rt2x00dev, RT3090)) {
3301                 rt2800_bbp_read(rt2x00dev, 138, &bbp);
3302
3303                 /*  Turn off unused DAC1 and ADC1 to reduce power consumption */
3304                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3305                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
3306                         rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
3307                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
3308                         rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
3309
3310                 rt2800_bbp_write(rt2x00dev, 138, bbp);
3311         }
3312
3313         if (rt2x00_rt(rt2x00dev, RT3071) ||
3314             rt2x00_rt(rt2x00dev, RT3090) ||
3315             rt2x00_rt(rt2x00dev, RT3390)) {
3316                 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
3317                 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
3318                 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
3319                 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
3320                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
3321                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
3322                 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3323
3324                 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
3325                 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
3326                 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
3327
3328                 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
3329                 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
3330                 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
3331
3332                 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
3333                 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
3334                 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
3335         }
3336
3337         if (rt2x00_rt(rt2x00dev, RT3070)) {
3338                 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
3339                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
3340                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
3341                 else
3342                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
3343                 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
3344                 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
3345                 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
3346                 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
3347         }
3348
3349         if (rt2x00_rt(rt2x00dev, RT5390)) {
3350                 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
3351                 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
3352                 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
3353
3354                 rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
3355                 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
3356                 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
3357
3358                 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3359                 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
3360                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3361         }
3362
3363         return 0;
3364 }
3365
3366 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
3367 {
3368         u32 reg;
3369         u16 word;
3370
3371         /*
3372          * Initialize all registers.
3373          */
3374         if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
3375                      rt2800_init_registers(rt2x00dev) ||
3376                      rt2800_init_bbp(rt2x00dev) ||
3377                      rt2800_init_rfcsr(rt2x00dev)))
3378                 return -EIO;
3379
3380         /*
3381          * Send signal to firmware during boot time.
3382          */
3383         rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
3384
3385         if (rt2x00_is_usb(rt2x00dev) &&
3386             (rt2x00_rt(rt2x00dev, RT3070) ||
3387              rt2x00_rt(rt2x00dev, RT3071) ||
3388              rt2x00_rt(rt2x00dev, RT3572))) {
3389                 udelay(200);
3390                 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
3391                 udelay(10);
3392         }
3393
3394         /*
3395          * Enable RX.
3396          */
3397         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3398         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
3399         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
3400         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
3401
3402         udelay(50);
3403
3404         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
3405         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
3406         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
3407         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
3408         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
3409         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
3410
3411         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3412         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
3413         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
3414         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
3415
3416         /*
3417          * Initialize LED control
3418          */
3419         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
3420         rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
3421                            word & 0xff, (word >> 8) & 0xff);
3422
3423         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
3424         rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
3425                            word & 0xff, (word >> 8) & 0xff);
3426
3427         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
3428         rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
3429                            word & 0xff, (word >> 8) & 0xff);
3430
3431         return 0;
3432 }
3433 EXPORT_SYMBOL_GPL(rt2800_enable_radio);
3434
3435 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
3436 {
3437         u32 reg;
3438
3439         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
3440         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
3441         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
3442         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
3443
3444         /* Wait for DMA, ignore error */
3445         rt2800_wait_wpdma_ready(rt2x00dev);
3446
3447         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3448         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
3449         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
3450         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
3451 }
3452 EXPORT_SYMBOL_GPL(rt2800_disable_radio);
3453
3454 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
3455 {
3456         u32 reg;
3457
3458         rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
3459
3460         return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
3461 }
3462 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
3463
3464 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
3465 {
3466         u32 reg;
3467
3468         mutex_lock(&rt2x00dev->csr_mutex);
3469
3470         rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
3471         rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
3472         rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
3473         rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
3474         rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
3475
3476         /* Wait until the EEPROM has been loaded */
3477         rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
3478
3479         /* Apparently the data is read from end to start */
3480         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3,
3481                                         (u32 *)&rt2x00dev->eeprom[i]);
3482         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2,
3483                                         (u32 *)&rt2x00dev->eeprom[i + 2]);
3484         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1,
3485                                         (u32 *)&rt2x00dev->eeprom[i + 4]);
3486         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0,
3487                                         (u32 *)&rt2x00dev->eeprom[i + 6]);
3488
3489         mutex_unlock(&rt2x00dev->csr_mutex);
3490 }
3491
3492 void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
3493 {
3494         unsigned int i;
3495
3496         for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
3497                 rt2800_efuse_read(rt2x00dev, i);
3498 }
3499 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
3500
3501 int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
3502 {
3503         u16 word;
3504         u8 *mac;
3505         u8 default_lna_gain;
3506
3507         /*
3508          * Start validation of the data that has been read.
3509          */
3510         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
3511         if (!is_valid_ether_addr(mac)) {
3512                 random_ether_addr(mac);
3513                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
3514         }
3515
3516         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
3517         if (word == 0xffff) {
3518                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
3519                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
3520                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
3521                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
3522                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
3523         } else if (rt2x00_rt(rt2x00dev, RT2860) ||
3524                    rt2x00_rt(rt2x00dev, RT2872)) {
3525                 /*
3526                  * There is a max of 2 RX streams for RT28x0 series
3527                  */
3528                 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
3529                         rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
3530                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
3531         }
3532
3533         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
3534         if (word == 0xffff) {
3535                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
3536                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
3537                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
3538                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
3539                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
3540                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
3541                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
3542                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
3543                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
3544                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
3545                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
3546                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
3547                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
3548                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
3549                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
3550                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
3551                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
3552         }
3553
3554         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
3555         if ((word & 0x00ff) == 0x00ff) {
3556                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
3557                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
3558                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
3559         }
3560         if ((word & 0xff00) == 0xff00) {
3561                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
3562                                    LED_MODE_TXRX_ACTIVITY);
3563                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
3564                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
3565                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
3566                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
3567                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
3568                 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word);
3569         }
3570
3571         /*
3572          * During the LNA validation we are going to use
3573          * lna0 as correct value. Note that EEPROM_LNA
3574          * is never validated.
3575          */
3576         rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
3577         default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
3578
3579         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
3580         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
3581                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
3582         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
3583                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
3584         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
3585
3586         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
3587         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
3588                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
3589         if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
3590             rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
3591                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
3592                                    default_lna_gain);
3593         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
3594
3595         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
3596         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
3597                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
3598         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
3599                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
3600         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
3601
3602         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
3603         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
3604                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
3605         if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
3606             rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
3607                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
3608                                    default_lna_gain);
3609         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
3610
3611         return 0;
3612 }
3613 EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
3614
3615 int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
3616 {
3617         u32 reg;
3618         u16 value;
3619         u16 eeprom;
3620
3621         /*
3622          * Read EEPROM word for configuration.
3623          */
3624         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3625
3626         /*
3627          * Identify RF chipset by EEPROM value
3628          * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
3629          * RT53xx: defined in "EEPROM_CHIP_ID" field
3630          */
3631         rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
3632         if (rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5390)
3633                 rt2x00_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &value);
3634         else
3635                 value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
3636
3637         rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
3638                         value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
3639
3640         if (!rt2x00_rt(rt2x00dev, RT2860) &&
3641             !rt2x00_rt(rt2x00dev, RT2872) &&
3642             !rt2x00_rt(rt2x00dev, RT2883) &&
3643             !rt2x00_rt(rt2x00dev, RT3070) &&
3644             !rt2x00_rt(rt2x00dev, RT3071) &&
3645             !rt2x00_rt(rt2x00dev, RT3090) &&
3646             !rt2x00_rt(rt2x00dev, RT3390) &&
3647             !rt2x00_rt(rt2x00dev, RT3572) &&
3648             !rt2x00_rt(rt2x00dev, RT5390)) {
3649                 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
3650                 return -ENODEV;
3651         }
3652
3653         if (!rt2x00_rf(rt2x00dev, RF2820) &&
3654             !rt2x00_rf(rt2x00dev, RF2850) &&
3655             !rt2x00_rf(rt2x00dev, RF2720) &&
3656             !rt2x00_rf(rt2x00dev, RF2750) &&
3657             !rt2x00_rf(rt2x00dev, RF3020) &&
3658             !rt2x00_rf(rt2x00dev, RF2020) &&
3659             !rt2x00_rf(rt2x00dev, RF3021) &&
3660             !rt2x00_rf(rt2x00dev, RF3022) &&
3661             !rt2x00_rf(rt2x00dev, RF3052) &&
3662             !rt2x00_rf(rt2x00dev, RF3320) &&
3663             !rt2x00_rf(rt2x00dev, RF5390)) {
3664                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
3665                 return -ENODEV;
3666         }
3667
3668         /*
3669          * Identify default antenna configuration.
3670          */
3671         rt2x00dev->default_ant.tx_chain_num =
3672             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
3673         rt2x00dev->default_ant.rx_chain_num =
3674             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
3675
3676         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3677
3678         if (rt2x00_rt(rt2x00dev, RT3070) ||
3679             rt2x00_rt(rt2x00dev, RT3090) ||
3680             rt2x00_rt(rt2x00dev, RT3390)) {
3681                 value = rt2x00_get_field16(eeprom,
3682                                 EEPROM_NIC_CONF1_ANT_DIVERSITY);
3683                 switch (value) {
3684                 case 0:
3685                 case 1:
3686                 case 2:
3687                         rt2x00dev->default_ant.tx = ANTENNA_A;
3688                         rt2x00dev->default_ant.rx = ANTENNA_A;
3689                         break;
3690                 case 3:
3691                         rt2x00dev->default_ant.tx = ANTENNA_A;
3692                         rt2x00dev->default_ant.rx = ANTENNA_B;
3693                         break;
3694                 }
3695         } else {
3696                 rt2x00dev->default_ant.tx = ANTENNA_A;
3697                 rt2x00dev->default_ant.rx = ANTENNA_A;
3698         }
3699
3700         /*
3701          * Read frequency offset and RF programming sequence.
3702          */
3703         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
3704         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
3705
3706         /*
3707          * Read external LNA informations.
3708          */
3709         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3710
3711         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
3712                 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
3713         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
3714                 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
3715
3716         /*
3717          * Detect if this device has an hardware controlled radio.
3718          */
3719         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
3720                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
3721
3722         /*
3723          * Store led settings, for correct led behaviour.
3724          */
3725 #ifdef CONFIG_RT2X00_LIB_LEDS
3726         rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
3727         rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
3728         rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
3729
3730         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
3731 #endif /* CONFIG_RT2X00_LIB_LEDS */
3732
3733         /*
3734          * Check if support EIRP tx power limit feature.
3735          */
3736         rt2x00_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
3737
3738         if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
3739                                         EIRP_MAX_TX_POWER_LIMIT)
3740                 __set_bit(CONFIG_SUPPORT_POWER_LIMIT, &rt2x00dev->flags);
3741
3742         return 0;
3743 }
3744 EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
3745
3746 /*
3747  * RF value list for rt28xx
3748  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
3749  */
3750 static const struct rf_channel rf_vals[] = {
3751         { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
3752         { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
3753         { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
3754         { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
3755         { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
3756         { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
3757         { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
3758         { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
3759         { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
3760         { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
3761         { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
3762         { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
3763         { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
3764         { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
3765
3766         /* 802.11 UNI / HyperLan 2 */
3767         { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
3768         { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
3769         { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
3770         { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
3771         { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
3772         { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
3773         { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
3774         { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
3775         { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
3776         { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
3777         { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
3778         { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
3779
3780         /* 802.11 HyperLan 2 */
3781         { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
3782         { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
3783         { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
3784         { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
3785         { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
3786         { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
3787         { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
3788         { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
3789         { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
3790         { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
3791         { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
3792         { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
3793         { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
3794         { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
3795         { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
3796         { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
3797
3798         /* 802.11 UNII */
3799         { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
3800         { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
3801         { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
3802         { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
3803         { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
3804         { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
3805         { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
3806         { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
3807         { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
3808         { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
3809         { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
3810
3811         /* 802.11 Japan */
3812         { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
3813         { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
3814         { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
3815         { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
3816         { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
3817         { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
3818         { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
3819 };
3820
3821 /*
3822  * RF value list for rt3xxx
3823  * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
3824  */
3825 static const struct rf_channel rf_vals_3x[] = {
3826         {1,  241, 2, 2 },
3827         {2,  241, 2, 7 },
3828         {3,  242, 2, 2 },
3829         {4,  242, 2, 7 },
3830         {5,  243, 2, 2 },
3831         {6,  243, 2, 7 },
3832         {7,  244, 2, 2 },
3833         {8,  244, 2, 7 },
3834         {9,  245, 2, 2 },
3835         {10, 245, 2, 7 },
3836         {11, 246, 2, 2 },
3837         {12, 246, 2, 7 },
3838         {13, 247, 2, 2 },
3839         {14, 248, 2, 4 },
3840
3841         /* 802.11 UNI / HyperLan 2 */
3842         {36, 0x56, 0, 4},
3843         {38, 0x56, 0, 6},
3844         {40, 0x56, 0, 8},
3845         {44, 0x57, 0, 0},
3846         {46, 0x57, 0, 2},
3847         {48, 0x57, 0, 4},
3848         {52, 0x57, 0, 8},
3849         {54, 0x57, 0, 10},
3850         {56, 0x58, 0, 0},
3851         {60, 0x58, 0, 4},
3852         {62, 0x58, 0, 6},
3853         {64, 0x58, 0, 8},
3854
3855         /* 802.11 HyperLan 2 */
3856         {100, 0x5b, 0, 8},
3857         {102, 0x5b, 0, 10},
3858         {104, 0x5c, 0, 0},
3859         {108, 0x5c, 0, 4},
3860         {110, 0x5c, 0, 6},
3861         {112, 0x5c, 0, 8},
3862         {116, 0x5d, 0, 0},
3863         {118, 0x5d, 0, 2},
3864         {120, 0x5d, 0, 4},
3865         {124, 0x5d, 0, 8},
3866         {126, 0x5d, 0, 10},
3867         {128, 0x5e, 0, 0},
3868         {132, 0x5e, 0, 4},
3869         {134, 0x5e, 0, 6},
3870         {136, 0x5e, 0, 8},
3871         {140, 0x5f, 0, 0},
3872
3873         /* 802.11 UNII */
3874         {149, 0x5f, 0, 9},
3875         {151, 0x5f, 0, 11},
3876         {153, 0x60, 0, 1},
3877         {157, 0x60, 0, 5},
3878         {159, 0x60, 0, 7},
3879         {161, 0x60, 0, 9},
3880         {165, 0x61, 0, 1},
3881         {167, 0x61, 0, 3},
3882         {169, 0x61, 0, 5},
3883         {171, 0x61, 0, 7},
3884         {173, 0x61, 0, 9},
3885 };
3886
3887 int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
3888 {
3889         struct hw_mode_spec *spec = &rt2x00dev->spec;
3890         struct channel_info *info;
3891         char *default_power1;
3892         char *default_power2;
3893         unsigned int i;
3894         u16 eeprom;
3895
3896         /*
3897          * Disable powersaving as default on PCI devices.
3898          */
3899         if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
3900                 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
3901
3902         /*
3903          * Initialize all hw fields.
3904          */
3905         rt2x00dev->hw->flags =
3906             IEEE80211_HW_SIGNAL_DBM |
3907             IEEE80211_HW_SUPPORTS_PS |
3908             IEEE80211_HW_PS_NULLFUNC_STACK |
3909             IEEE80211_HW_AMPDU_AGGREGATION;
3910         /*
3911          * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
3912          * unless we are capable of sending the buffered frames out after the
3913          * DTIM transmission using rt2x00lib_beacondone. This will send out
3914          * multicast and broadcast traffic immediately instead of buffering it
3915          * infinitly and thus dropping it after some time.
3916          */
3917         if (!rt2x00_is_usb(rt2x00dev))
3918                 rt2x00dev->hw->flags |=
3919                         IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
3920
3921         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
3922         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
3923                                 rt2x00_eeprom_addr(rt2x00dev,
3924                                                    EEPROM_MAC_ADDR_0));
3925
3926         /*
3927          * As rt2800 has a global fallback table we cannot specify
3928          * more then one tx rate per frame but since the hw will
3929          * try several rates (based on the fallback table) we should
3930          * initialize max_report_rates to the maximum number of rates
3931          * we are going to try. Otherwise mac80211 will truncate our
3932          * reported tx rates and the rc algortihm will end up with
3933          * incorrect data.
3934          */
3935         rt2x00dev->hw->max_rates = 1;
3936         rt2x00dev->hw->max_report_rates = 7;
3937         rt2x00dev->hw->max_rate_tries = 1;
3938
3939         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3940
3941         /*
3942          * Initialize hw_mode information.
3943          */
3944         spec->supported_bands = SUPPORT_BAND_2GHZ;
3945         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
3946
3947         if (rt2x00_rf(rt2x00dev, RF2820) ||
3948             rt2x00_rf(rt2x00dev, RF2720)) {
3949                 spec->num_channels = 14;
3950                 spec->channels = rf_vals;
3951         } else if (rt2x00_rf(rt2x00dev, RF2850) ||
3952                    rt2x00_rf(rt2x00dev, RF2750)) {
3953                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
3954                 spec->num_channels = ARRAY_SIZE(rf_vals);
3955                 spec->channels = rf_vals;
3956         } else if (rt2x00_rf(rt2x00dev, RF3020) ||
3957                    rt2x00_rf(rt2x00dev, RF2020) ||
3958                    rt2x00_rf(rt2x00dev, RF3021) ||
3959                    rt2x00_rf(rt2x00dev, RF3022) ||
3960                    rt2x00_rf(rt2x00dev, RF3320) ||
3961                    rt2x00_rf(rt2x00dev, RF5390)) {
3962                 spec->num_channels = 14;
3963                 spec->channels = rf_vals_3x;
3964         } else if (rt2x00_rf(rt2x00dev, RF3052)) {
3965                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
3966                 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
3967                 spec->channels = rf_vals_3x;
3968         }
3969
3970         /*
3971          * Initialize HT information.
3972          */
3973         if (!rt2x00_rf(rt2x00dev, RF2020))
3974                 spec->ht.ht_supported = true;
3975         else
3976                 spec->ht.ht_supported = false;
3977
3978         spec->ht.cap =
3979             IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
3980             IEEE80211_HT_CAP_GRN_FLD |
3981             IEEE80211_HT_CAP_SGI_20 |
3982             IEEE80211_HT_CAP_SGI_40;
3983
3984         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2)
3985                 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
3986
3987         spec->ht.cap |=
3988             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) <<
3989                 IEEE80211_HT_CAP_RX_STBC_SHIFT;
3990
3991         spec->ht.ampdu_factor = 3;
3992         spec->ht.ampdu_density = 4;
3993         spec->ht.mcs.tx_params =
3994             IEEE80211_HT_MCS_TX_DEFINED |
3995             IEEE80211_HT_MCS_TX_RX_DIFF |
3996             ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) <<
3997                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
3998
3999         switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) {
4000         case 3:
4001                 spec->ht.mcs.rx_mask[2] = 0xff;
4002         case 2:
4003                 spec->ht.mcs.rx_mask[1] = 0xff;
4004         case 1:
4005                 spec->ht.mcs.rx_mask[0] = 0xff;
4006                 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
4007                 break;
4008         }
4009
4010         /*
4011          * Create channel information array
4012          */
4013         info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
4014         if (!info)
4015                 return -ENOMEM;
4016
4017         spec->channels_info = info;
4018
4019         default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
4020         default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
4021
4022         for (i = 0; i < 14; i++) {
4023                 info[i].default_power1 = default_power1[i];
4024                 info[i].default_power2 = default_power2[i];
4025         }
4026
4027         if (spec->num_channels > 14) {
4028                 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
4029                 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
4030
4031                 for (i = 14; i < spec->num_channels; i++) {
4032                         info[i].default_power1 = default_power1[i];
4033                         info[i].default_power2 = default_power2[i];
4034                 }
4035         }
4036
4037         return 0;
4038 }
4039 EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
4040
4041 /*
4042  * IEEE80211 stack callback functions.
4043  */
4044 void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
4045                          u16 *iv16)
4046 {
4047         struct rt2x00_dev *rt2x00dev = hw->priv;
4048         struct mac_iveiv_entry iveiv_entry;
4049         u32 offset;
4050
4051         offset = MAC_IVEIV_ENTRY(hw_key_idx);
4052         rt2800_register_multiread(rt2x00dev, offset,
4053                                       &iveiv_entry, sizeof(iveiv_entry));
4054
4055         memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
4056         memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
4057 }
4058 EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
4059
4060 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
4061 {
4062         struct rt2x00_dev *rt2x00dev = hw->priv;
4063         u32 reg;
4064         bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
4065
4066         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
4067         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
4068         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
4069
4070         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
4071         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
4072         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
4073
4074         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
4075         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
4076         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
4077
4078         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
4079         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
4080         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
4081
4082         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
4083         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
4084         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
4085
4086         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
4087         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
4088         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
4089
4090         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
4091         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
4092         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
4093
4094         return 0;
4095 }
4096 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
4097
4098 int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
4099                    const struct ieee80211_tx_queue_params *params)
4100 {
4101         struct rt2x00_dev *rt2x00dev = hw->priv;
4102         struct data_queue *queue;
4103         struct rt2x00_field32 field;
4104         int retval;
4105         u32 reg;
4106         u32 offset;
4107
4108         /*
4109          * First pass the configuration through rt2x00lib, that will
4110          * update the queue settings and validate the input. After that
4111          * we are free to update the registers based on the value
4112          * in the queue parameter.
4113          */
4114         retval = rt2x00mac_conf_tx(hw, queue_idx, params);
4115         if (retval)
4116                 return retval;
4117
4118         /*
4119          * We only need to perform additional register initialization
4120          * for WMM queues/
4121          */
4122         if (queue_idx >= 4)
4123                 return 0;
4124
4125         queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
4126
4127         /* Update WMM TXOP register */
4128         offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
4129         field.bit_offset = (queue_idx & 1) * 16;
4130         field.bit_mask = 0xffff << field.bit_offset;
4131
4132         rt2800_register_read(rt2x00dev, offset, &reg);
4133         rt2x00_set_field32(&reg, field, queue->txop);
4134         rt2800_register_write(rt2x00dev, offset, reg);
4135
4136         /* Update WMM registers */
4137         field.bit_offset = queue_idx * 4;
4138         field.bit_mask = 0xf << field.bit_offset;
4139
4140         rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
4141         rt2x00_set_field32(&reg, field, queue->aifs);
4142         rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
4143
4144         rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
4145         rt2x00_set_field32(&reg, field, queue->cw_min);
4146         rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
4147
4148         rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
4149         rt2x00_set_field32(&reg, field, queue->cw_max);
4150         rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
4151
4152         /* Update EDCA registers */
4153         offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
4154
4155         rt2800_register_read(rt2x00dev, offset, &reg);
4156         rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
4157         rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
4158         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
4159         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
4160         rt2800_register_write(rt2x00dev, offset, reg);
4161
4162         return 0;
4163 }
4164 EXPORT_SYMBOL_GPL(rt2800_conf_tx);
4165
4166 u64 rt2800_get_tsf(struct ieee80211_hw *hw)
4167 {
4168         struct rt2x00_dev *rt2x00dev = hw->priv;
4169         u64 tsf;
4170         u32 reg;
4171
4172         rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
4173         tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
4174         rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
4175         tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
4176
4177         return tsf;
4178 }
4179 EXPORT_SYMBOL_GPL(rt2800_get_tsf);
4180
4181 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4182                         enum ieee80211_ampdu_mlme_action action,
4183                         struct ieee80211_sta *sta, u16 tid, u16 *ssn,
4184                         u8 buf_size)
4185 {
4186         int ret = 0;
4187
4188         switch (action) {
4189         case IEEE80211_AMPDU_RX_START:
4190         case IEEE80211_AMPDU_RX_STOP:
4191                 /*
4192                  * The hw itself takes care of setting up BlockAck mechanisms.
4193                  * So, we only have to allow mac80211 to nagotiate a BlockAck
4194                  * agreement. Once that is done, the hw will BlockAck incoming
4195                  * AMPDUs without further setup.
4196                  */
4197                 break;
4198         case IEEE80211_AMPDU_TX_START:
4199                 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
4200                 break;
4201         case IEEE80211_AMPDU_TX_STOP:
4202                 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
4203                 break;
4204         case IEEE80211_AMPDU_TX_OPERATIONAL:
4205                 break;
4206         default:
4207                 WARNING((struct rt2x00_dev *)hw->priv, "Unknown AMPDU action\n");
4208         }
4209
4210         return ret;
4211 }
4212 EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
4213
4214 int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
4215                       struct survey_info *survey)
4216 {
4217         struct rt2x00_dev *rt2x00dev = hw->priv;
4218         struct ieee80211_conf *conf = &hw->conf;
4219         u32 idle, busy, busy_ext;
4220
4221         if (idx != 0)
4222                 return -ENOENT;
4223
4224         survey->channel = conf->channel;
4225
4226         rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
4227         rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
4228         rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
4229
4230         if (idle || busy) {
4231                 survey->filled = SURVEY_INFO_CHANNEL_TIME |
4232                                  SURVEY_INFO_CHANNEL_TIME_BUSY |
4233                                  SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
4234
4235                 survey->channel_time = (idle + busy) / 1000;
4236                 survey->channel_time_busy = busy / 1000;
4237                 survey->channel_time_ext_busy = busy_ext / 1000;
4238         }
4239
4240         return 0;
4241
4242 }
4243 EXPORT_SYMBOL_GPL(rt2800_get_survey);
4244
4245 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
4246 MODULE_VERSION(DRV_VERSION);
4247 MODULE_DESCRIPTION("Ralink RT2800 library");
4248 MODULE_LICENSE("GPL");