drivers/net/wireless/rt2x00/rt2800lib.c

   1 /*
   2         Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
   3         Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
   4         Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
   5         Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
   6
   7         Based on the original rt2800pci.c and rt2800usb.c.
   8           Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
   9           Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
  10           Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
  11           Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
  12           Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
  13           Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
  14           <http://rt2x00.serialmonkey.com>
  15
  16         This program is free software; you can redistribute it and/or modify
  17         it under the terms of the GNU General Public License as published by
  18         the Free Software Foundation; either version 2 of the License, or
  19         (at your option) any later version.
  20
  21         This program is distributed in the hope that it will be useful,
  22         but WITHOUT ANY WARRANTY; without even the implied warranty of
  23         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24         GNU General Public License for more details.
  25
  26         You should have received a copy of the GNU General Public License
  27         along with this program; if not, write to the
  28         Free Software Foundation, Inc.,
  29         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  30  */
  31
  32 /*
  33         Module: rt2800lib
  34         Abstract: rt2800 generic device routines.
  35  */
  36
  37 #include <linux/crc-ccitt.h>
  38 #include <linux/kernel.h>
  39 #include <linux/module.h>
  40 #include <linux/slab.h>
  41
  42 #include "rt2x00.h"
  43 #include "rt2800lib.h"
  44 #include "rt2800.h"
  45
  46 /*
  47  * Register access.
  48  * All access to the CSR registers will go through the methods
  49  * rt2800_register_read and rt2800_register_write.
  50  * BBP and RF register require indirect register access,
  51  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  52  * These indirect registers work with busy bits,
  53  * and we will try maximal REGISTER_BUSY_COUNT times to access
  54  * the register while taking a REGISTER_BUSY_DELAY us delay
  55  * between each attampt. When the busy bit is still set at that time,
  56  * the access attempt is considered to have failed,
  57  * and we will print an error.
  58  * The _lock versions must be used if you already hold the csr_mutex
  59  */
  60 #define WAIT_FOR_BBP(__dev, __reg) \
  61         rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
  62 #define WAIT_FOR_RFCSR(__dev, __reg) \
  63         rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
  64 #define WAIT_FOR_RF(__dev, __reg) \
  65         rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
  66 #define WAIT_FOR_MCU(__dev, __reg) \
  67         rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  68                             H2M_MAILBOX_CSR_OWNER, (__reg))
  69
  70 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
  71 {
  72         /* check for rt2872 on SoC */
  73         if (!rt2x00_is_soc(rt2x00dev) ||
  74             !rt2x00_rt(rt2x00dev, RT2872))
  75                 return false;
  76
  77         /* we know for sure that these rf chipsets are used on rt305x boards */
  78         if (rt2x00_rf(rt2x00dev, RF3020) ||
  79             rt2x00_rf(rt2x00dev, RF3021) ||
  80             rt2x00_rf(rt2x00dev, RF3022))
  81                 return true;
  82
  83         rt2x00_warn(rt2x00dev, "Unknown RF chipset on rt305x\n");
  84         return false;
  85 }
  86
  87 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
  88                              const unsigned int word, const u8 value)
  89 {
  90         u32 reg;
  91
  92         mutex_lock(&rt2x00dev->csr_mutex);
  93
  94         /*
  95          * Wait until the BBP becomes available, afterwards we
  96          * can safely write the new data into the register.
  97          */
  98         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  99                 reg = 0;
 100                 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
 101                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 102                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 103                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
 104                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 105
 106                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 107         }
 108
 109         mutex_unlock(&rt2x00dev->csr_mutex);
 110 }
 111
 112 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
 113                             const unsigned int word, u8 *value)
 114 {
 115         u32 reg;
 116
 117         mutex_lock(&rt2x00dev->csr_mutex);
 118
 119         /*
 120          * Wait until the BBP becomes available, afterwards we
 121          * can safely write the read request into the register.
 122          * After the data has been written, we wait until hardware
 123          * returns the correct value, if at any time the register
 124          * doesn't become available in time, reg will be 0xffffffff
 125          * which means we return 0xff to the caller.
 126          */
 127         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 128                 reg = 0;
 129                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 130                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 131                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
 132                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 133
 134                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 135
 136                 WAIT_FOR_BBP(rt2x00dev, &reg);
 137         }
 138
 139         *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
 140
 141         mutex_unlock(&rt2x00dev->csr_mutex);
 142 }
 143
 144 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
 145                                const unsigned int word, const u8 value)
 146 {
 147         u32 reg;
 148
 149         mutex_lock(&rt2x00dev->csr_mutex);
 150
 151         /*
 152          * Wait until the RFCSR becomes available, afterwards we
 153          * can safely write the new data into the register.
 154          */
 155         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 156                 reg = 0;
 157                 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
 158                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 159                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
 160                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 161
 162                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 163         }
 164
 165         mutex_unlock(&rt2x00dev->csr_mutex);
 166 }
 167
 168 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
 169                               const unsigned int word, u8 *value)
 170 {
 171         u32 reg;
 172
 173         mutex_lock(&rt2x00dev->csr_mutex);
 174
 175         /*
 176          * Wait until the RFCSR becomes available, afterwards we
 177          * can safely write the read request into the register.
 178          * After the data has been written, we wait until hardware
 179          * returns the correct value, if at any time the register
 180          * doesn't become available in time, reg will be 0xffffffff
 181          * which means we return 0xff to the caller.
 182          */
 183         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 184                 reg = 0;
 185                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 186                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
 187                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 188
 189                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 190
 191                 WAIT_FOR_RFCSR(rt2x00dev, &reg);
 192         }
 193
 194         *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
 195
 196         mutex_unlock(&rt2x00dev->csr_mutex);
 197 }
 198
 199 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
 200                             const unsigned int word, const u32 value)
 201 {
 202         u32 reg;
 203
 204         mutex_lock(&rt2x00dev->csr_mutex);
 205
 206         /*
 207          * Wait until the RF becomes available, afterwards we
 208          * can safely write the new data into the register.
 209          */
 210         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 211                 reg = 0;
 212                 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
 213                 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
 214                 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
 215                 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
 216
 217                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
 218                 rt2x00_rf_write(rt2x00dev, word, value);
 219         }
 220
 221         mutex_unlock(&rt2x00dev->csr_mutex);
 222 }
 223
 224 static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev)
 225 {
 226         u32 reg;
 227         int i, count;
 228
 229         rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
 230         if (rt2x00_get_field32(reg, WLAN_EN))
 231                 return 0;
 232
 233         rt2x00_set_field32(&reg, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff);
 234         rt2x00_set_field32(&reg, FRC_WL_ANT_SET, 1);
 235         rt2x00_set_field32(&reg, WLAN_CLK_EN, 0);
 236         rt2x00_set_field32(&reg, WLAN_EN, 1);
 237         rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
 238
 239         udelay(REGISTER_BUSY_DELAY);
 240
 241         count = 0;
 242         do {
 243                 /*
 244                  * Check PLL_LD & XTAL_RDY.
 245                  */
 246                 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 247                         rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
 248                         if (rt2x00_get_field32(reg, PLL_LD) &&
 249                             rt2x00_get_field32(reg, XTAL_RDY))
 250                                 break;
 251                         udelay(REGISTER_BUSY_DELAY);
 252                 }
 253
 254                 if (i >= REGISTER_BUSY_COUNT) {
 255
 256                         if (count >= 10)
 257                                 return -EIO;
 258
 259                         rt2800_register_write(rt2x00dev, 0x58, 0x018);
 260                         udelay(REGISTER_BUSY_DELAY);
 261                         rt2800_register_write(rt2x00dev, 0x58, 0x418);
 262                         udelay(REGISTER_BUSY_DELAY);
 263                         rt2800_register_write(rt2x00dev, 0x58, 0x618);
 264                         udelay(REGISTER_BUSY_DELAY);
 265                         count++;
 266                 } else {
 267                         count = 0;
 268                 }
 269
 270                 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
 271                 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 0);
 272                 rt2x00_set_field32(&reg, WLAN_CLK_EN, 1);
 273                 rt2x00_set_field32(&reg, WLAN_RESET, 1);
 274                 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
 275                 udelay(10);
 276                 rt2x00_set_field32(&reg, WLAN_RESET, 0);
 277                 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
 278                 udelay(10);
 279                 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff);
 280         } while (count != 0);
 281
 282         return 0;
 283 }
 284
 285 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
 286                         const u8 command, const u8 token,
 287                         const u8 arg0, const u8 arg1)
 288 {
 289         u32 reg;
 290
 291         /*
 292          * SOC devices don't support MCU requests.
 293          */
 294         if (rt2x00_is_soc(rt2x00dev))
 295                 return;
 296
 297         mutex_lock(&rt2x00dev->csr_mutex);
 298
 299         /*
 300          * Wait until the MCU becomes available, afterwards we
 301          * can safely write the new data into the register.
 302          */
 303         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 304                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 305                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 306                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 307                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 308                 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
 309
 310                 reg = 0;
 311                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 312                 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
 313         }
 314
 315         mutex_unlock(&rt2x00dev->csr_mutex);
 316 }
 317 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
 318
 319 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
 320 {
 321         unsigned int i = 0;
 322         u32 reg;
 323
 324         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 325                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
 326                 if (reg && reg != ~0)
 327                         return 0;
 328                 msleep(1);
 329         }
 330
 331         rt2x00_err(rt2x00dev, "Unstable hardware\n");
 332         return -EBUSY;
 333 }
 334 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
 335
 336 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
 337 {
 338         unsigned int i;
 339         u32 reg;
 340
 341         /*
 342          * Some devices are really slow to respond here. Wait a whole second
 343          * before timing out.
 344          */
 345         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 346                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 347                 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
 348                     !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
 349                         return 0;
 350
 351                 msleep(10);
 352         }
 353
 354         rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg);
 355         return -EACCES;
 356 }
 357 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
 358
 359 void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev)
 360 {
 361         u32 reg;
 362
 363         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 364         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
 365         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
 366         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
 367         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
 368         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
 369         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 370 }
 371 EXPORT_SYMBOL_GPL(rt2800_disable_wpdma);
 372
 373 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
 374 {
 375         u16 fw_crc;
 376         u16 crc;
 377
 378         /*
 379          * The last 2 bytes in the firmware array are the crc checksum itself,
 380          * this means that we should never pass those 2 bytes to the crc
 381          * algorithm.
 382          */
 383         fw_crc = (data[len - 2] << 8 | data[len - 1]);
 384
 385         /*
 386          * Use the crc ccitt algorithm.
 387          * This will return the same value as the legacy driver which
 388          * used bit ordering reversion on the both the firmware bytes
 389          * before input input as well as on the final output.
 390          * Obviously using crc ccitt directly is much more efficient.
 391          */
 392         crc = crc_ccitt(~0, data, len - 2);
 393
 394         /*
 395          * There is a small difference between the crc-itu-t + bitrev and
 396          * the crc-ccitt crc calculation. In the latter method the 2 bytes
 397          * will be swapped, use swab16 to convert the crc to the correct
 398          * value.
 399          */
 400         crc = swab16(crc);
 401
 402         return fw_crc == crc;
 403 }
 404
 405 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
 406                           const u8 *data, const size_t len)
 407 {
 408         size_t offset = 0;
 409         size_t fw_len;
 410         bool multiple;
 411
 412         /*
 413          * PCI(e) & SOC devices require firmware with a length
 414          * of 8kb. USB devices require firmware files with a length
 415          * of 4kb. Certain USB chipsets however require different firmware,
 416          * which Ralink only provides attached to the original firmware
 417          * file. Thus for USB devices, firmware files have a length
 418          * which is a multiple of 4kb. The firmware for rt3290 chip also
 419          * have a length which is a multiple of 4kb.
 420          */
 421         if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290))
 422                 fw_len = 4096;
 423         else
 424                 fw_len = 8192;
 425
 426         multiple = true;
 427         /*
 428          * Validate the firmware length
 429          */
 430         if (len != fw_len && (!multiple || (len % fw_len) != 0))
 431                 return FW_BAD_LENGTH;
 432
 433         /*
 434          * Check if the chipset requires one of the upper parts
 435          * of the firmware.
 436          */
 437         if (rt2x00_is_usb(rt2x00dev) &&
 438             !rt2x00_rt(rt2x00dev, RT2860) &&
 439             !rt2x00_rt(rt2x00dev, RT2872) &&
 440             !rt2x00_rt(rt2x00dev, RT3070) &&
 441             ((len / fw_len) == 1))
 442                 return FW_BAD_VERSION;
 443
 444         /*
 445          * 8kb firmware files must be checked as if it were
 446          * 2 separate firmware files.
 447          */
 448         while (offset < len) {
 449                 if (!rt2800_check_firmware_crc(data + offset, fw_len))
 450                         return FW_BAD_CRC;
 451
 452                 offset += fw_len;
 453         }
 454
 455         return FW_OK;
 456 }
 457 EXPORT_SYMBOL_GPL(rt2800_check_firmware);
 458
 459 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
 460                          const u8 *data, const size_t len)
 461 {
 462         unsigned int i;
 463         u32 reg;
 464         int retval;
 465
 466         if (rt2x00_rt(rt2x00dev, RT3290)) {
 467                 retval = rt2800_enable_wlan_rt3290(rt2x00dev);
 468                 if (retval)
 469                         return -EBUSY;
 470         }
 471
 472         /*
 473          * If driver doesn't wake up firmware here,
 474          * rt2800_load_firmware will hang forever when interface is up again.
 475          */
 476         rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
 477
 478         /*
 479          * Wait for stable hardware.
 480          */
 481         if (rt2800_wait_csr_ready(rt2x00dev))
 482                 return -EBUSY;
 483
 484         if (rt2x00_is_pci(rt2x00dev)) {
 485                 if (rt2x00_rt(rt2x00dev, RT3290) ||
 486                     rt2x00_rt(rt2x00dev, RT3572) ||
 487                     rt2x00_rt(rt2x00dev, RT5390) ||
 488                     rt2x00_rt(rt2x00dev, RT5392)) {
 489                         rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
 490                         rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
 491                         rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
 492                         rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
 493                 }
 494                 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
 495         }
 496
 497         rt2800_disable_wpdma(rt2x00dev);
 498
 499         /*
 500          * Write firmware to the device.
 501          */
 502         rt2800_drv_write_firmware(rt2x00dev, data, len);
 503
 504         /*
 505          * Wait for device to stabilize.
 506          */
 507         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 508                 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
 509                 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
 510                         break;
 511                 msleep(1);
 512         }
 513
 514         if (i == REGISTER_BUSY_COUNT) {
 515                 rt2x00_err(rt2x00dev, "PBF system register not ready\n");
 516                 return -EBUSY;
 517         }
 518
 519         /*
 520          * Disable DMA, will be reenabled later when enabling
 521          * the radio.
 522          */
 523         rt2800_disable_wpdma(rt2x00dev);
 524
 525         /*
 526          * Initialize firmware.
 527          */
 528         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
 529         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
 530         if (rt2x00_is_usb(rt2x00dev)) {
 531                 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
 532                 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
 533         }
 534         msleep(1);
 535
 536         return 0;
 537 }
 538 EXPORT_SYMBOL_GPL(rt2800_load_firmware);
 539
 540 void rt2800_write_tx_data(struct queue_entry *entry,
 541                           struct txentry_desc *txdesc)
 542 {
 543         __le32 *txwi = rt2800_drv_get_txwi(entry);
 544         u32 word;
 545         int i;
 546
 547         /*
 548          * Initialize TX Info descriptor
 549          */
 550         rt2x00_desc_read(txwi, 0, &word);
 551         rt2x00_set_field32(&word, TXWI_W0_FRAG,
 552                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
 553         rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
 554                            test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
 555         rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
 556         rt2x00_set_field32(&word, TXWI_W0_TS,
 557                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
 558         rt2x00_set_field32(&word, TXWI_W0_AMPDU,
 559                            test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
 560         rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
 561                            txdesc->u.ht.mpdu_density);
 562         rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
 563         rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
 564         rt2x00_set_field32(&word, TXWI_W0_BW,
 565                            test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
 566         rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
 567                            test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
 568         rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
 569         rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
 570         rt2x00_desc_write(txwi, 0, word);
 571
 572         rt2x00_desc_read(txwi, 1, &word);
 573         rt2x00_set_field32(&word, TXWI_W1_ACK,
 574                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
 575         rt2x00_set_field32(&word, TXWI_W1_NSEQ,
 576                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
 577         rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
 578         rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
 579                            test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
 580                            txdesc->key_idx : txdesc->u.ht.wcid);
 581         rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
 582                            txdesc->length);
 583         rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
 584         rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
 585         rt2x00_desc_write(txwi, 1, word);
 586
 587         /*
 588          * Always write 0 to IV/EIV fields (word 2 and 3), hardware will insert
 589          * the IV from the IVEIV register when TXD_W3_WIV is set to 0.
 590          * When TXD_W3_WIV is set to 1 it will use the IV data
 591          * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
 592          * crypto entry in the registers should be used to encrypt the frame.
 593          *
 594          * Nulify all remaining words as well, we don't know how to program them.
 595          */
 596         for (i = 2; i < entry->queue->winfo_size / sizeof(__le32); i++)
 597                 _rt2x00_desc_write(txwi, i, 0);
 598 }
 599 EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
 600
 601 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
 602 {
 603         s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
 604         s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
 605         s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
 606         u16 eeprom;
 607         u8 offset0;
 608         u8 offset1;
 609         u8 offset2;
 610
 611         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
 612                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
 613                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
 614                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
 615                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
 616                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
 617         } else {
 618                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
 619                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
 620                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
 621                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
 622                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
 623         }
 624
 625         /*
 626          * Convert the value from the descriptor into the RSSI value
 627          * If the value in the descriptor is 0, it is considered invalid
 628          * and the default (extremely low) rssi value is assumed
 629          */
 630         rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
 631         rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
 632         rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
 633
 634         /*
 635          * mac80211 only accepts a single RSSI value. Calculating the
 636          * average doesn't deliver a fair answer either since -60:-60 would
 637          * be considered equally good as -50:-70 while the second is the one
 638          * which gives less energy...
 639          */
 640         rssi0 = max(rssi0, rssi1);
 641         return (int)max(rssi0, rssi2);
 642 }
 643
 644 void rt2800_process_rxwi(struct queue_entry *entry,
 645                          struct rxdone_entry_desc *rxdesc)
 646 {
 647         __le32 *rxwi = (__le32 *) entry->skb->data;
 648         u32 word;
 649
 650         rt2x00_desc_read(rxwi, 0, &word);
 651
 652         rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
 653         rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
 654
 655         rt2x00_desc_read(rxwi, 1, &word);
 656
 657         if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
 658                 rxdesc->flags |= RX_FLAG_SHORT_GI;
 659
 660         if (rt2x00_get_field32(word, RXWI_W1_BW))
 661                 rxdesc->flags |= RX_FLAG_40MHZ;
 662
 663         /*
 664          * Detect RX rate, always use MCS as signal type.
 665          */
 666         rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
 667         rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
 668         rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
 669
 670         /*
 671          * Mask of 0x8 bit to remove the short preamble flag.
 672          */
 673         if (rxdesc->rate_mode == RATE_MODE_CCK)
 674                 rxdesc->signal &= ~0x8;
 675
 676         rt2x00_desc_read(rxwi, 2, &word);
 677
 678         /*
 679          * Convert descriptor AGC value to RSSI value.
 680          */
 681         rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
 682         /*
 683          * Remove RXWI descriptor from start of the buffer.
 684          */
 685         skb_pull(entry->skb, entry->queue->winfo_size);
 686 }
 687 EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
 688
 689 void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi)
 690 {
 691         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 692         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 693         struct txdone_entry_desc txdesc;
 694         u32 word;
 695         u16 mcs, real_mcs;
 696         int aggr, ampdu;
 697
 698         /*
 699          * Obtain the status about this packet.
 700          */
 701         txdesc.flags = 0;
 702         rt2x00_desc_read(txwi, 0, &word);
 703
 704         mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
 705         ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
 706
 707         real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
 708         aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
 709
 710         /*
 711          * If a frame was meant to be sent as a single non-aggregated MPDU
 712          * but ended up in an aggregate the used tx rate doesn't correlate
 713          * with the one specified in the TXWI as the whole aggregate is sent
 714          * with the same rate.
 715          *
 716          * For example: two frames are sent to rt2x00, the first one sets
 717          * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
 718          * and requests MCS15. If the hw aggregates both frames into one
 719          * AMDPU the tx status for both frames will contain MCS7 although
 720          * the frame was sent successfully.
 721          *
 722          * Hence, replace the requested rate with the real tx rate to not
 723          * confuse the rate control algortihm by providing clearly wrong
 724          * data.
 725          */
 726         if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
 727                 skbdesc->tx_rate_idx = real_mcs;
 728                 mcs = real_mcs;
 729         }
 730
 731         if (aggr == 1 || ampdu == 1)
 732                 __set_bit(TXDONE_AMPDU, &txdesc.flags);
 733
 734         /*
 735          * Ralink has a retry mechanism using a global fallback
 736          * table. We setup this fallback table to try the immediate
 737          * lower rate for all rates. In the TX_STA_FIFO, the MCS field
 738          * always contains the MCS used for the last transmission, be
 739          * it successful or not.
 740          */
 741         if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
 742                 /*
 743                  * Transmission succeeded. The number of retries is
 744                  * mcs - real_mcs
 745                  */
 746                 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
 747                 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
 748         } else {
 749                 /*
 750                  * Transmission failed. The number of retries is
 751                  * always 7 in this case (for a total number of 8
 752                  * frames sent).
 753                  */
 754                 __set_bit(TXDONE_FAILURE, &txdesc.flags);
 755                 txdesc.retry = rt2x00dev->long_retry;
 756         }
 757
 758         /*
 759          * the frame was retried at least once
 760          * -> hw used fallback rates
 761          */
 762         if (txdesc.retry)
 763                 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
 764
 765         rt2x00lib_txdone(entry, &txdesc);
 766 }
 767 EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
 768
 769 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
 770 {
 771         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 772         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 773         unsigned int beacon_base;
 774         unsigned int padding_len;
 775         u32 orig_reg, reg;
 776         const int txwi_desc_size = entry->queue->winfo_size;
 777
 778         /*
 779          * Disable beaconing while we are reloading the beacon data,
 780          * otherwise we might be sending out invalid data.
 781          */
 782         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 783         orig_reg = reg;
 784         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
 785         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 786
 787         /*
 788          * Add space for the TXWI in front of the skb.
 789          */
 790         memset(skb_push(entry->skb, txwi_desc_size), 0, txwi_desc_size);
 791
 792         /*
 793          * Register descriptor details in skb frame descriptor.
 794          */
 795         skbdesc->flags |= SKBDESC_DESC_IN_SKB;
 796         skbdesc->desc = entry->skb->data;
 797         skbdesc->desc_len = txwi_desc_size;
 798
 799         /*
 800          * Add the TXWI for the beacon to the skb.
 801          */
 802         rt2800_write_tx_data(entry, txdesc);
 803
 804         /*
 805          * Dump beacon to userspace through debugfs.
 806          */
 807         rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
 808
 809         /*
 810          * Write entire beacon with TXWI and padding to register.
 811          */
 812         padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
 813         if (padding_len && skb_pad(entry->skb, padding_len)) {
 814                 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n");
 815                 /* skb freed by skb_pad() on failure */
 816                 entry->skb = NULL;
 817                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
 818                 return;
 819         }
 820
 821         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
 822         rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
 823                                    entry->skb->len + padding_len);
 824
 825         /*
 826          * Enable beaconing again.
 827          */
 828         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
 829         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 830
 831         /*
 832          * Clean up beacon skb.
 833          */
 834         dev_kfree_skb_any(entry->skb);
 835         entry->skb = NULL;
 836 }
 837 EXPORT_SYMBOL_GPL(rt2800_write_beacon);
 838
 839 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
 840                                                 unsigned int beacon_base)
 841 {
 842         int i;
 843         const int txwi_desc_size = rt2x00dev->ops->bcn->winfo_size;
 844
 845         /*
 846          * For the Beacon base registers we only need to clear
 847          * the whole TXWI which (when set to 0) will invalidate
 848          * the entire beacon.
 849          */
 850         for (i = 0; i < txwi_desc_size; i += sizeof(__le32))
 851                 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
 852 }
 853
 854 void rt2800_clear_beacon(struct queue_entry *entry)
 855 {
 856         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 857         u32 reg;
 858
 859         /*
 860          * Disable beaconing while we are reloading the beacon data,
 861          * otherwise we might be sending out invalid data.
 862          */
 863         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 864         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
 865         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 866
 867         /*
 868          * Clear beacon.
 869          */
 870         rt2800_clear_beacon_register(rt2x00dev,
 871                                      HW_BEACON_OFFSET(entry->entry_idx));
 872
 873         /*
 874          * Enabled beaconing again.
 875          */
 876         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
 877         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 878 }
 879 EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
 880
 881 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 882 const struct rt2x00debug rt2800_rt2x00debug = {
 883         .owner  = THIS_MODULE,
 884         .csr    = {
 885                 .read           = rt2800_register_read,
 886                 .write          = rt2800_register_write,
 887                 .flags          = RT2X00DEBUGFS_OFFSET,
 888                 .word_base      = CSR_REG_BASE,
 889                 .word_size      = sizeof(u32),
 890                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 891         },
 892         .eeprom = {
 893                 .read           = rt2x00_eeprom_read,
 894                 .write          = rt2x00_eeprom_write,
 895                 .word_base      = EEPROM_BASE,
 896                 .word_size      = sizeof(u16),
 897                 .word_count     = EEPROM_SIZE / sizeof(u16),
 898         },
 899         .bbp    = {
 900                 .read           = rt2800_bbp_read,
 901                 .write          = rt2800_bbp_write,
 902                 .word_base      = BBP_BASE,
 903                 .word_size      = sizeof(u8),
 904                 .word_count     = BBP_SIZE / sizeof(u8),
 905         },
 906         .rf     = {
 907                 .read           = rt2x00_rf_read,
 908                 .write          = rt2800_rf_write,
 909                 .word_base      = RF_BASE,
 910                 .word_size      = sizeof(u32),
 911                 .word_count     = RF_SIZE / sizeof(u32),
 912         },
 913         .rfcsr  = {
 914                 .read           = rt2800_rfcsr_read,
 915                 .write          = rt2800_rfcsr_write,
 916                 .word_base      = RFCSR_BASE,
 917                 .word_size      = sizeof(u8),
 918                 .word_count     = RFCSR_SIZE / sizeof(u8),
 919         },
 920 };
 921 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
 922 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 923
 924 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 925 {
 926         u32 reg;
 927
 928         if (rt2x00_rt(rt2x00dev, RT3290)) {
 929                 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
 930                 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0);
 931         } else {
 932                 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
 933                 return rt2x00_get_field32(reg, GPIO_CTRL_VAL2);
 934         }
 935 }
 936 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
 937
 938 #ifdef CONFIG_RT2X00_LIB_LEDS
 939 static void rt2800_brightness_set(struct led_classdev *led_cdev,
 940                                   enum led_brightness brightness)
 941 {
 942         struct rt2x00_led *led =
 943             container_of(led_cdev, struct rt2x00_led, led_dev);
 944         unsigned int enabled = brightness != LED_OFF;
 945         unsigned int bg_mode =
 946             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 947         unsigned int polarity =
 948                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 949                                    EEPROM_FREQ_LED_POLARITY);
 950         unsigned int ledmode =
 951                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 952                                    EEPROM_FREQ_LED_MODE);
 953         u32 reg;
 954
 955         /* Check for SoC (SOC devices don't support MCU requests) */
 956         if (rt2x00_is_soc(led->rt2x00dev)) {
 957                 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
 958
 959                 /* Set LED Polarity */
 960                 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
 961
 962                 /* Set LED Mode */
 963                 if (led->type == LED_TYPE_RADIO) {
 964                         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
 965                                            enabled ? 3 : 0);
 966                 } else if (led->type == LED_TYPE_ASSOC) {
 967                         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
 968                                            enabled ? 3 : 0);
 969                 } else if (led->type == LED_TYPE_QUALITY) {
 970                         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
 971                                            enabled ? 3 : 0);
 972                 }
 973
 974                 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
 975
 976         } else {
 977                 if (led->type == LED_TYPE_RADIO) {
 978                         rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 979                                               enabled ? 0x20 : 0);
 980                 } else if (led->type == LED_TYPE_ASSOC) {
 981                         rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 982                                               enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
 983                 } else if (led->type == LED_TYPE_QUALITY) {
 984                         /*
 985                          * The brightness is divided into 6 levels (0 - 5),
 986                          * The specs tell us the following levels:
 987                          *      0, 1 ,3, 7, 15, 31
 988                          * to determine the level in a simple way we can simply
 989                          * work with bitshifting:
 990                          *      (1 << level) - 1
 991                          */
 992                         rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
 993                                               (1 << brightness / (LED_FULL / 6)) - 1,
 994                                               polarity);
 995                 }
 996         }
 997 }
 998
 999 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
1000                      struct rt2x00_led *led, enum led_type type)
1001 {
1002         led->rt2x00dev = rt2x00dev;
1003         led->type = type;
1004         led->led_dev.brightness_set = rt2800_brightness_set;
1005         led->flags = LED_INITIALIZED;
1006 }
1007 #endif /* CONFIG_RT2X00_LIB_LEDS */
1008
1009 /*
1010  * Configuration handlers.
1011  */
1012 static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
1013                                const u8 *address,
1014                                int wcid)
1015 {
1016         struct mac_wcid_entry wcid_entry;
1017         u32 offset;
1018
1019         offset = MAC_WCID_ENTRY(wcid);
1020
1021         memset(&wcid_entry, 0xff, sizeof(wcid_entry));
1022         if (address)
1023                 memcpy(wcid_entry.mac, address, ETH_ALEN);
1024
1025         rt2800_register_multiwrite(rt2x00dev, offset,
1026                                       &wcid_entry, sizeof(wcid_entry));
1027 }
1028
1029 static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
1030 {
1031         u32 offset;
1032         offset = MAC_WCID_ATTR_ENTRY(wcid);
1033         rt2800_register_write(rt2x00dev, offset, 0);
1034 }
1035
1036 static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
1037                                            int wcid, u32 bssidx)
1038 {
1039         u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
1040         u32 reg;
1041
1042         /*
1043          * The BSS Idx numbers is split in a main value of 3 bits,
1044          * and a extended field for adding one additional bit to the value.
1045          */
1046         rt2800_register_read(rt2x00dev, offset, &reg);
1047         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
1048         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
1049                            (bssidx & 0x8) >> 3);
1050         rt2800_register_write(rt2x00dev, offset, reg);
1051 }
1052
1053 static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
1054                                            struct rt2x00lib_crypto *crypto,
1055                                            struct ieee80211_key_conf *key)
1056 {
1057         struct mac_iveiv_entry iveiv_entry;
1058         u32 offset;
1059         u32 reg;
1060
1061         offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
1062
1063         if (crypto->cmd == SET_KEY) {
1064                 rt2800_register_read(rt2x00dev, offset, &reg);
1065                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
1066                                    !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
1067                 /*
1068                  * Both the cipher as the BSS Idx numbers are split in a main
1069                  * value of 3 bits, and a extended field for adding one additional
1070                  * bit to the value.
1071                  */
1072                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
1073                                    (crypto->cipher & 0x7));
1074                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
1075                                    (crypto->cipher & 0x8) >> 3);
1076                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
1077                 rt2800_register_write(rt2x00dev, offset, reg);
1078         } else {
1079                 /* Delete the cipher without touching the bssidx */
1080                 rt2800_register_read(rt2x00dev, offset, &reg);
1081                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
1082                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 0);
1083                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
1084                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
1085                 rt2800_register_write(rt2x00dev, offset, reg);
1086         }
1087
1088         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1089
1090         memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1091         if ((crypto->cipher == CIPHER_TKIP) ||
1092             (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1093             (crypto->cipher == CIPHER_AES))
1094                 iveiv_entry.iv[3] |= 0x20;
1095         iveiv_entry.iv[3] |= key->keyidx << 6;
1096         rt2800_register_multiwrite(rt2x00dev, offset,
1097                                       &iveiv_entry, sizeof(iveiv_entry));
1098 }
1099
1100 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1101                              struct rt2x00lib_crypto *crypto,
1102                              struct ieee80211_key_conf *key)
1103 {
1104         struct hw_key_entry key_entry;
1105         struct rt2x00_field32 field;
1106         u32 offset;
1107         u32 reg;
1108
1109         if (crypto->cmd == SET_KEY) {
1110                 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1111
1112                 memcpy(key_entry.key, crypto->key,
1113                        sizeof(key_entry.key));
1114                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1115                        sizeof(key_entry.tx_mic));
1116                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1117                        sizeof(key_entry.rx_mic));
1118
1119                 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1120                 rt2800_register_multiwrite(rt2x00dev, offset,
1121                                               &key_entry, sizeof(key_entry));
1122         }
1123
1124         /*
1125          * The cipher types are stored over multiple registers
1126          * starting with SHARED_KEY_MODE_BASE each word will have
1127          * 32 bits and contains the cipher types for 2 bssidx each.
1128          * Using the correct defines correctly will cause overhead,
1129          * so just calculate the correct offset.
1130          */
1131         field.bit_offset = 4 * (key->hw_key_idx % 8);
1132         field.bit_mask = 0x7 << field.bit_offset;
1133
1134         offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1135
1136         rt2800_register_read(rt2x00dev, offset, &reg);
1137         rt2x00_set_field32(&reg, field,
1138                            (crypto->cmd == SET_KEY) * crypto->cipher);
1139         rt2800_register_write(rt2x00dev, offset, reg);
1140
1141         /*
1142          * Update WCID information
1143          */
1144         rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1145         rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1146                                        crypto->bssidx);
1147         rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1148
1149         return 0;
1150 }
1151 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1152
1153 static inline int rt2800_find_wcid(struct rt2x00_dev *rt2x00dev)
1154 {
1155         struct mac_wcid_entry wcid_entry;
1156         int idx;
1157         u32 offset;
1158
1159         /*
1160          * Search for the first free WCID entry and return the corresponding
1161          * index.
1162          *
1163          * Make sure the WCID starts _after_ the last possible shared key
1164          * entry (>32).
1165          *
1166          * Since parts of the pairwise key table might be shared with
1167          * the beacon frame buffers 6 & 7 we should only write into the
1168          * first 222 entries.
1169          */
1170         for (idx = 33; idx <= 222; idx++) {
1171                 offset = MAC_WCID_ENTRY(idx);
1172                 rt2800_register_multiread(rt2x00dev, offset, &wcid_entry,
1173                                           sizeof(wcid_entry));
1174                 if (is_broadcast_ether_addr(wcid_entry.mac))
1175                         return idx;
1176         }
1177
1178         /*
1179          * Use -1 to indicate that we don't have any more space in the WCID
1180          * table.
1181          */
1182         return -1;
1183 }
1184
1185 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1186                                struct rt2x00lib_crypto *crypto,
1187                                struct ieee80211_key_conf *key)
1188 {
1189         struct hw_key_entry key_entry;
1190         u32 offset;
1191
1192         if (crypto->cmd == SET_KEY) {
1193                 /*
1194                  * Allow key configuration only for STAs that are
1195                  * known by the hw.
1196                  */
1197                 if (crypto->wcid < 0)
1198                         return -ENOSPC;
1199                 key->hw_key_idx = crypto->wcid;
1200
1201                 memcpy(key_entry.key, crypto->key,
1202                        sizeof(key_entry.key));
1203                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1204                        sizeof(key_entry.tx_mic));
1205                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1206                        sizeof(key_entry.rx_mic));
1207
1208                 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1209                 rt2800_register_multiwrite(rt2x00dev, offset,
1210                                               &key_entry, sizeof(key_entry));
1211         }
1212
1213         /*
1214          * Update WCID information
1215          */
1216         rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1217
1218         return 0;
1219 }
1220 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1221
1222 int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif,
1223                    struct ieee80211_sta *sta)
1224 {
1225         int wcid;
1226         struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1227
1228         /*
1229          * Find next free WCID.
1230          */
1231         wcid = rt2800_find_wcid(rt2x00dev);
1232
1233         /*
1234          * Store selected wcid even if it is invalid so that we can
1235          * later decide if the STA is uploaded into the hw.
1236          */
1237         sta_priv->wcid = wcid;
1238
1239         /*
1240          * No space left in the device, however, we can still communicate
1241          * with the STA -> No error.
1242          */
1243         if (wcid < 0)
1244                 return 0;
1245
1246         /*
1247          * Clean up WCID attributes and write STA address to the device.
1248          */
1249         rt2800_delete_wcid_attr(rt2x00dev, wcid);
1250         rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1251         rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1252                                        rt2x00lib_get_bssidx(rt2x00dev, vif));
1253         return 0;
1254 }
1255 EXPORT_SYMBOL_GPL(rt2800_sta_add);
1256
1257 int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, int wcid)
1258 {
1259         /*
1260          * Remove WCID entry, no need to clean the attributes as they will
1261          * get renewed when the WCID is reused.
1262          */
1263         rt2800_config_wcid(rt2x00dev, NULL, wcid);
1264
1265         return 0;
1266 }
1267 EXPORT_SYMBOL_GPL(rt2800_sta_remove);
1268
1269 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1270                           const unsigned int filter_flags)
1271 {
1272         u32 reg;
1273
1274         /*
1275          * Start configuration steps.
1276          * Note that the version error will always be dropped
1277          * and broadcast frames will always be accepted since
1278          * there is no filter for it at this time.
1279          */
1280         rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1281         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1282                            !(filter_flags & FIF_FCSFAIL));
1283         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1284                            !(filter_flags & FIF_PLCPFAIL));
1285         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1286                            !(filter_flags & FIF_PROMISC_IN_BSS));
1287         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1288         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1289         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1290                            !(filter_flags & FIF_ALLMULTI));
1291         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1292         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1293         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1294                            !(filter_flags & FIF_CONTROL));
1295         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1296                            !(filter_flags & FIF_CONTROL));
1297         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1298                            !(filter_flags & FIF_CONTROL));
1299         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1300                            !(filter_flags & FIF_CONTROL));
1301         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1302                            !(filter_flags & FIF_CONTROL));
1303         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1304                            !(filter_flags & FIF_PSPOLL));
1305         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 0);
1306         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR,
1307                            !(filter_flags & FIF_CONTROL));
1308         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1309                            !(filter_flags & FIF_CONTROL));
1310         rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1311 }
1312 EXPORT_SYMBOL_GPL(rt2800_config_filter);
1313
1314 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1315                         struct rt2x00intf_conf *conf, const unsigned int flags)
1316 {
1317         u32 reg;
1318         bool update_bssid = false;
1319
1320         if (flags & CONFIG_UPDATE_TYPE) {
1321                 /*
1322                  * Enable synchronisation.
1323                  */
1324                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1325                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
1326                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1327
1328                 if (conf->sync == TSF_SYNC_AP_NONE) {
1329                         /*
1330                          * Tune beacon queue transmit parameters for AP mode
1331                          */
1332                         rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1333                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1334                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1335                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1336                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1337                         rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1338                 } else {
1339                         rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1340                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1341                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1342                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1343                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1344                         rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1345                 }
1346         }
1347
1348         if (flags & CONFIG_UPDATE_MAC) {
1349                 if (flags & CONFIG_UPDATE_TYPE &&
1350                     conf->sync == TSF_SYNC_AP_NONE) {
1351                         /*
1352                          * The BSSID register has to be set to our own mac
1353                          * address in AP mode.
1354                          */
1355                         memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1356                         update_bssid = true;
1357                 }
1358
1359                 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1360                         reg = le32_to_cpu(conf->mac[1]);
1361                         rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1362                         conf->mac[1] = cpu_to_le32(reg);
1363                 }
1364
1365                 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1366                                               conf->mac, sizeof(conf->mac));
1367         }
1368
1369         if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
1370                 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1371                         reg = le32_to_cpu(conf->bssid[1]);
1372                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1373                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1374                         conf->bssid[1] = cpu_to_le32(reg);
1375                 }
1376
1377                 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1378                                               conf->bssid, sizeof(conf->bssid));
1379         }
1380 }
1381 EXPORT_SYMBOL_GPL(rt2800_config_intf);
1382
1383 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1384                                     struct rt2x00lib_erp *erp)
1385 {
1386         bool any_sta_nongf = !!(erp->ht_opmode &
1387                                 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1388         u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1389         u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1390         u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1391         u32 reg;
1392
1393         /* default protection rate for HT20: OFDM 24M */
1394         mm20_rate = gf20_rate = 0x4004;
1395
1396         /* default protection rate for HT40: duplicate OFDM 24M */
1397         mm40_rate = gf40_rate = 0x4084;
1398
1399         switch (protection) {
1400         case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1401                 /*
1402                  * All STAs in this BSS are HT20/40 but there might be
1403                  * STAs not supporting greenfield mode.
1404                  * => Disable protection for HT transmissions.
1405                  */
1406                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1407
1408                 break;
1409         case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1410                 /*
1411                  * All STAs in this BSS are HT20 or HT20/40 but there
1412                  * might be STAs not supporting greenfield mode.
1413                  * => Protect all HT40 transmissions.
1414                  */
1415                 mm20_mode = gf20_mode = 0;
1416                 mm40_mode = gf40_mode = 2;
1417
1418                 break;
1419         case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1420                 /*
1421                  * Nonmember protection:
1422                  * According to 802.11n we _should_ protect all
1423                  * HT transmissions (but we don't have to).
1424                  *
1425                  * But if cts_protection is enabled we _shall_ protect
1426                  * all HT transmissions using a CCK rate.
1427                  *
1428                  * And if any station is non GF we _shall_ protect
1429                  * GF transmissions.
1430                  *
1431                  * We decide to protect everything
1432                  * -> fall through to mixed mode.
1433                  */
1434         case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1435                 /*
1436                  * Legacy STAs are present
1437                  * => Protect all HT transmissions.
1438                  */
1439                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1440
1441                 /*
1442                  * If erp protection is needed we have to protect HT
1443                  * transmissions with CCK 11M long preamble.
1444                  */
1445                 if (erp->cts_protection) {
1446                         /* don't duplicate RTS/CTS in CCK mode */
1447                         mm20_rate = mm40_rate = 0x0003;
1448                         gf20_rate = gf40_rate = 0x0003;
1449                 }
1450                 break;
1451         }
1452
1453         /* check for STAs not supporting greenfield mode */
1454         if (any_sta_nongf)
1455                 gf20_mode = gf40_mode = 2;
1456
1457         /* Update HT protection config */
1458         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1459         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1460         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1461         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1462
1463         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1464         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1465         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1466         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1467
1468         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1469         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1470         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1471         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1472
1473         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1474         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1475         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1476         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1477 }
1478
1479 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1480                        u32 changed)
1481 {
1482         u32 reg;
1483
1484         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1485                 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1486                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1487                                    !!erp->short_preamble);
1488                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1489                                    !!erp->short_preamble);
1490                 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1491         }
1492
1493         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1494                 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1495                 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1496                                    erp->cts_protection ? 2 : 0);
1497                 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1498         }
1499
1500         if (changed & BSS_CHANGED_BASIC_RATES) {
1501                 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1502                                          erp->basic_rates);
1503                 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1504         }
1505
1506         if (changed & BSS_CHANGED_ERP_SLOT) {
1507                 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1508                 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1509                                    erp->slot_time);
1510                 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1511
1512                 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1513                 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1514                 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1515         }
1516
1517         if (changed & BSS_CHANGED_BEACON_INT) {
1518                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1519                 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1520                                    erp->beacon_int * 16);
1521                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1522         }
1523
1524         if (changed & BSS_CHANGED_HT)
1525                 rt2800_config_ht_opmode(rt2x00dev, erp);
1526 }
1527 EXPORT_SYMBOL_GPL(rt2800_config_erp);
1528
1529 static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
1530 {
1531         u32 reg;
1532         u16 eeprom;
1533         u8 led_ctrl, led_g_mode, led_r_mode;
1534
1535         rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
1536         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1537                 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
1538                 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
1539         } else {
1540                 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
1541                 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
1542         }
1543         rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1544
1545         rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1546         led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
1547         led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
1548         if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
1549             led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
1550                 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1551                 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
1552                 if (led_ctrl == 0 || led_ctrl > 0x40) {
1553                         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
1554                         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
1555                         rt2800_register_write(rt2x00dev, LED_CFG, reg);
1556                 } else {
1557                         rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
1558                                            (led_g_mode << 2) | led_r_mode, 1);
1559                 }
1560         }
1561 }
1562
1563 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1564                                      enum antenna ant)
1565 {
1566         u32 reg;
1567         u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1568         u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1569
1570         if (rt2x00_is_pci(rt2x00dev)) {
1571                 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1572                 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1573                 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1574         } else if (rt2x00_is_usb(rt2x00dev))
1575                 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1576                                    eesk_pin, 0);
1577
1578         rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1579         rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
1580         rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, gpio_bit3);
1581         rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
1582 }
1583
1584 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1585 {
1586         u8 r1;
1587         u8 r3;
1588         u16 eeprom;
1589
1590         rt2800_bbp_read(rt2x00dev, 1, &r1);
1591         rt2800_bbp_read(rt2x00dev, 3, &r3);
1592
1593         if (rt2x00_rt(rt2x00dev, RT3572) &&
1594             test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1595                 rt2800_config_3572bt_ant(rt2x00dev);
1596
1597         /*
1598          * Configure the TX antenna.
1599          */
1600         switch (ant->tx_chain_num) {
1601         case 1:
1602                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1603                 break;
1604         case 2:
1605                 if (rt2x00_rt(rt2x00dev, RT3572) &&
1606                     test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1607                         rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
1608                 else
1609                         rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1610                 break;
1611         case 3:
1612                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1613                 break;
1614         }
1615
1616         /*
1617          * Configure the RX antenna.
1618          */
1619         switch (ant->rx_chain_num) {
1620         case 1:
1621                 if (rt2x00_rt(rt2x00dev, RT3070) ||
1622                     rt2x00_rt(rt2x00dev, RT3090) ||
1623                     rt2x00_rt(rt2x00dev, RT3352) ||
1624                     rt2x00_rt(rt2x00dev, RT3390)) {
1625                         rt2x00_eeprom_read(rt2x00dev,
1626                                            EEPROM_NIC_CONF1, &eeprom);
1627                         if (rt2x00_get_field16(eeprom,
1628                                                 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1629                                 rt2800_set_ant_diversity(rt2x00dev,
1630                                                 rt2x00dev->default_ant.rx);
1631                 }
1632                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1633                 break;
1634         case 2:
1635                 if (rt2x00_rt(rt2x00dev, RT3572) &&
1636                     test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1637                         rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
1638                         rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
1639                                 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
1640                         rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
1641                 } else {
1642                         rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1643                 }
1644                 break;
1645         case 3:
1646                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1647                 break;
1648         }
1649
1650         rt2800_bbp_write(rt2x00dev, 3, r3);
1651         rt2800_bbp_write(rt2x00dev, 1, r1);
1652 }
1653 EXPORT_SYMBOL_GPL(rt2800_config_ant);
1654
1655 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1656                                    struct rt2x00lib_conf *libconf)
1657 {
1658         u16 eeprom;
1659         short lna_gain;
1660
1661         if (libconf->rf.channel <= 14) {
1662                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1663                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1664         } else if (libconf->rf.channel <= 64) {
1665                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1666                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1667         } else if (libconf->rf.channel <= 128) {
1668                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1669                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
1670         } else {
1671                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1672                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
1673         }
1674
1675         rt2x00dev->lna_gain = lna_gain;
1676 }
1677
1678 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1679                                          struct ieee80211_conf *conf,
1680                                          struct rf_channel *rf,
1681                                          struct channel_info *info)
1682 {
1683         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1684
1685         if (rt2x00dev->default_ant.tx_chain_num == 1)
1686                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1687
1688         if (rt2x00dev->default_ant.rx_chain_num == 1) {
1689                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1690                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1691         } else if (rt2x00dev->default_ant.rx_chain_num == 2)
1692                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1693
1694         if (rf->channel > 14) {
1695                 /*
1696                  * When TX power is below 0, we should increase it by 7 to
1697                  * make it a positive value (Minimum value is -7).
1698                  * However this means that values between 0 and 7 have
1699                  * double meaning, and we should set a 7DBm boost flag.
1700                  */
1701                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
1702                                    (info->default_power1 >= 0));
1703
1704                 if (info->default_power1 < 0)
1705                         info->default_power1 += 7;
1706
1707                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
1708
1709                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
1710                                    (info->default_power2 >= 0));
1711
1712                 if (info->default_power2 < 0)
1713                         info->default_power2 += 7;
1714
1715                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
1716         } else {
1717                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1718                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
1719         }
1720
1721         rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1722
1723         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1724         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1725         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1726         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1727
1728         udelay(200);
1729
1730         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1731         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1732         rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1733         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1734
1735         udelay(200);
1736
1737         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1738         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1739         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1740         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1741 }
1742
1743 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1744                                          struct ieee80211_conf *conf,
1745                                          struct rf_channel *rf,
1746                                          struct channel_info *info)
1747 {
1748         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1749         u8 rfcsr, calib_tx, calib_rx;
1750
1751         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1752
1753         rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
1754         rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
1755         rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
1756
1757         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1758         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1759         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1760
1761         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1762         rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
1763         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1764
1765         rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1766         rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
1767         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1768
1769         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1770         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1771         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
1772                           rt2x00dev->default_ant.rx_chain_num <= 1);
1773         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD,
1774                           rt2x00dev->default_ant.rx_chain_num <= 2);
1775         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1776         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
1777                           rt2x00dev->default_ant.tx_chain_num <= 1);
1778         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD,
1779                           rt2x00dev->default_ant.tx_chain_num <= 2);
1780         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1781
1782         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1783         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1784         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1785         msleep(1);
1786         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1787         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1788
1789         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1790         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1791         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1792
1793         if (rt2x00_rt(rt2x00dev, RT3390)) {
1794                 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f;
1795                 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f;
1796         } else {
1797                 if (conf_is_ht40(conf)) {
1798                         calib_tx = drv_data->calibration_bw40;
1799                         calib_rx = drv_data->calibration_bw40;
1800                 } else {
1801                         calib_tx = drv_data->calibration_bw20;
1802                         calib_rx = drv_data->calibration_bw20;
1803                 }
1804         }
1805
1806         rt2800_rfcsr_read(rt2x00dev, 24, &rfcsr);
1807         rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx);
1808         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
1809
1810         rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
1811         rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx);
1812         rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
1813
1814         rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1815         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1816         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1817
1818         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1819         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1820         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1821         msleep(1);
1822         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1823         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1824 }
1825
1826 static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
1827                                          struct ieee80211_conf *conf,
1828                                          struct rf_channel *rf,
1829                                          struct channel_info *info)
1830 {
1831         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1832         u8 rfcsr;
1833         u32 reg;
1834
1835         if (rf->channel <= 14) {
1836                 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
1837                 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
1838         } else {
1839                 rt2800_bbp_write(rt2x00dev, 25, 0x09);
1840                 rt2800_bbp_write(rt2x00dev, 26, 0xff);
1841         }
1842
1843         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1844         rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
1845
1846         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1847         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1848         if (rf->channel <= 14)
1849                 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
1850         else
1851                 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
1852         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1853
1854         rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr);
1855         if (rf->channel <= 14)
1856                 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
1857         else
1858                 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
1859         rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
1860
1861         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1862         if (rf->channel <= 14) {
1863                 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
1864                 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1865                                   info->default_power1);
1866         } else {
1867                 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
1868                 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1869                                 (info->default_power1 & 0x3) |
1870                                 ((info->default_power1 & 0xC) << 1));
1871         }
1872         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1873
1874         rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1875         if (rf->channel <= 14) {
1876                 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
1877                 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1878                                   info->default_power2);
1879         } else {
1880                 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
1881                 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1882                                 (info->default_power2 & 0x3) |
1883                                 ((info->default_power2 & 0xC) << 1));
1884         }
1885         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1886
1887         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1888         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1889         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1890         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
1891         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
1892         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
1893         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
1894         if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1895                 if (rf->channel <= 14) {
1896                         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
1897                         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
1898                 }
1899                 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1900                 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1901         } else {
1902                 switch (rt2x00dev->default_ant.tx_chain_num) {
1903                 case 1:
1904                         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
1905                 case 2:
1906                         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1907                         break;
1908                 }
1909
1910                 switch (rt2x00dev->default_ant.rx_chain_num) {
1911                 case 1:
1912                         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
1913                 case 2:
1914                         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1915                         break;
1916                 }
1917         }
1918         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1919
1920         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1921         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1922         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1923
1924         if (conf_is_ht40(conf)) {
1925                 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
1926                 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
1927         } else {
1928                 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
1929                 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
1930         }
1931
1932         if (rf->channel <= 14) {
1933                 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
1934                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
1935                 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1936                 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
1937                 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
1938                 rfcsr = 0x4c;
1939                 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
1940                                   drv_data->txmixer_gain_24g);
1941                 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
1942                 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1943                 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
1944                 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
1945                 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
1946                 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
1947                 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
1948                 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
1949         } else {
1950                 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1951                 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1);
1952                 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0);
1953                 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1);
1954                 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0);
1955                 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1956                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
1957                 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1958                 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
1959                 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
1960                 rfcsr = 0x7a;
1961                 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
1962                                   drv_data->txmixer_gain_5g);
1963                 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
1964                 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1965                 if (rf->channel <= 64) {
1966                         rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
1967                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
1968                         rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
1969                 } else if (rf->channel <= 128) {
1970                         rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
1971                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
1972                         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1973                 } else {
1974                         rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
1975                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
1976                         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1977                 }
1978                 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
1979                 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
1980                 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
1981         }
1982
1983         rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1984         rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
1985         if (rf->channel <= 14)
1986                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
1987         else
1988                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 0);
1989         rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
1990
1991         rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1992         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1993         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1994 }
1995
1996 #define POWER_BOUND             0x27
1997 #define POWER_BOUND_5G          0x2b
1998 #define FREQ_OFFSET_BOUND       0x5f
1999
2000 static void rt2800_adjust_freq_offset(struct rt2x00_dev *rt2x00dev)
2001 {
2002         u8 rfcsr;
2003
2004         rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
2005         if (rt2x00dev->freq_offset > FREQ_OFFSET_BOUND)
2006                 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, FREQ_OFFSET_BOUND);
2007         else
2008                 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
2009         rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2010 }
2011
2012 static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
2013                                          struct ieee80211_conf *conf,
2014                                          struct rf_channel *rf,
2015                                          struct channel_info *info)
2016 {
2017         u8 rfcsr;
2018
2019         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2020         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2021         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2022         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2023         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2024
2025         rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2026         if (info->default_power1 > POWER_BOUND)
2027                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
2028         else
2029                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2030         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2031
2032         rt2800_adjust_freq_offset(rt2x00dev);
2033
2034         if (rf->channel <= 14) {
2035                 if (rf->channel == 6)
2036                         rt2800_bbp_write(rt2x00dev, 68, 0x0c);
2037                 else
2038                         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
2039
2040                 if (rf->channel >= 1 && rf->channel <= 6)
2041                         rt2800_bbp_write(rt2x00dev, 59, 0x0f);
2042                 else if (rf->channel >= 7 && rf->channel <= 11)
2043                         rt2800_bbp_write(rt2x00dev, 59, 0x0e);
2044                 else if (rf->channel >= 12 && rf->channel <= 14)
2045                         rt2800_bbp_write(rt2x00dev, 59, 0x0d);
2046         }
2047 }
2048
2049 static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev,
2050                                          struct ieee80211_conf *conf,
2051                                          struct rf_channel *rf,
2052                                          struct channel_info *info)
2053 {
2054         u8 rfcsr;
2055
2056         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2057         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2058
2059         rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
2060         rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
2061         rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
2062
2063         if (info->default_power1 > POWER_BOUND)
2064                 rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND);
2065         else
2066                 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1);
2067
2068         if (info->default_power2 > POWER_BOUND)
2069                 rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND);
2070         else
2071                 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2);
2072
2073         rt2800_adjust_freq_offset(rt2x00dev);
2074
2075         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2076         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2077         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2078
2079         if ( rt2x00dev->default_ant.tx_chain_num == 2 )
2080                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2081         else
2082                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2083
2084         if ( rt2x00dev->default_ant.rx_chain_num == 2 )
2085                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2086         else
2087                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2088
2089         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2090         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2091
2092         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2093
2094         rt2800_rfcsr_write(rt2x00dev, 31, 80);
2095 }
2096
2097 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
2098                                          struct ieee80211_conf *conf,
2099                                          struct rf_channel *rf,
2100                                          struct channel_info *info)
2101 {
2102         u8 rfcsr;
2103
2104         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2105         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2106         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2107         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2108         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2109
2110         rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2111         if (info->default_power1 > POWER_BOUND)
2112                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
2113         else
2114                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2115         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2116
2117         if (rt2x00_rt(rt2x00dev, RT5392)) {
2118                 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2119                 if (info->default_power1 > POWER_BOUND)
2120                         rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND);
2121                 else
2122                         rt2x00_set_field8(&rfcsr, RFCSR50_TX,
2123                                           info->default_power2);
2124                 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2125         }
2126
2127         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2128         if (rt2x00_rt(rt2x00dev, RT5392)) {
2129                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2130                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2131         }
2132         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2133         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2134         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2135         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2136         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2137
2138         rt2800_adjust_freq_offset(rt2x00dev);
2139
2140         if (rf->channel <= 14) {
2141                 int idx = rf->channel-1;
2142
2143                 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
2144                         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2145                                 /* r55/r59 value array of channel 1~14 */
2146                                 static const char r55_bt_rev[] = {0x83, 0x83,
2147                                         0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
2148                                         0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
2149                                 static const char r59_bt_rev[] = {0x0e, 0x0e,
2150                                         0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
2151                                         0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
2152
2153                                 rt2800_rfcsr_write(rt2x00dev, 55,
2154                                                    r55_bt_rev[idx]);
2155                                 rt2800_rfcsr_write(rt2x00dev, 59,
2156                                                    r59_bt_rev[idx]);
2157                         } else {
2158                                 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
2159                                         0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
2160                                         0x88, 0x88, 0x86, 0x85, 0x84};
2161
2162                                 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
2163                         }
2164                 } else {
2165                         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2166                                 static const char r55_nonbt_rev[] = {0x23, 0x23,
2167                                         0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
2168                                         0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
2169                                 static const char r59_nonbt_rev[] = {0x07, 0x07,
2170                                         0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
2171                                         0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
2172
2173                                 rt2800_rfcsr_write(rt2x00dev, 55,
2174                                                    r55_nonbt_rev[idx]);
2175                                 rt2800_rfcsr_write(rt2x00dev, 59,
2176                                                    r59_nonbt_rev[idx]);
2177                         } else if (rt2x00_rt(rt2x00dev, RT5390) ||
2178                                    rt2x00_rt(rt2x00dev, RT5392)) {
2179                                 static const char r59_non_bt[] = {0x8f, 0x8f,
2180                                         0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
2181                                         0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
2182
2183                                 rt2800_rfcsr_write(rt2x00dev, 59,
2184                                                    r59_non_bt[idx]);
2185                         }
2186                 }
2187         }
2188 }
2189
2190 static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev,
2191                                          struct ieee80211_conf *conf,
2192                                          struct rf_channel *rf,
2193                                          struct channel_info *info)
2194 {
2195         u8 rfcsr, ep_reg;
2196         u32 reg;
2197         int power_bound;
2198
2199         /* TODO */
2200         const bool is_11b = false;
2201         const bool is_type_ep = false;
2202
2203         rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2204         rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL,
2205                            (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0);
2206         rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
2207
2208         /* Order of values on rf_channel entry: N, K, mod, R */
2209         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff);
2210
2211         rt2800_rfcsr_read(rt2x00dev,  9, &rfcsr);
2212         rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf);
2213         rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8);
2214         rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2);
2215         rt2800_rfcsr_write(rt2x00dev, 9, rfcsr);
2216
2217         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2218         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1);
2219         rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3);
2220         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2221
2222         if (rf->channel <= 14) {
2223                 rt2800_rfcsr_write(rt2x00dev, 10, 0x90);
2224                 /* FIXME: RF11 owerwrite ? */
2225                 rt2800_rfcsr_write(rt2x00dev, 11, 0x4A);
2226                 rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
2227                 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2228                 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2229                 rt2800_rfcsr_write(rt2x00dev, 24, 0x4A);
2230                 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
2231                 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2232                 rt2800_rfcsr_write(rt2x00dev, 36, 0x80);
2233                 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
2234                 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
2235                 rt2800_rfcsr_write(rt2x00dev, 39, 0x1B);
2236                 rt2800_rfcsr_write(rt2x00dev, 40, 0x0D);
2237                 rt2800_rfcsr_write(rt2x00dev, 41, 0x9B);
2238                 rt2800_rfcsr_write(rt2x00dev, 42, 0xD5);
2239                 rt2800_rfcsr_write(rt2x00dev, 43, 0x72);
2240                 rt2800_rfcsr_write(rt2x00dev, 44, 0x0E);
2241                 rt2800_rfcsr_write(rt2x00dev, 45, 0xA2);
2242                 rt2800_rfcsr_write(rt2x00dev, 46, 0x6B);
2243                 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
2244                 rt2800_rfcsr_write(rt2x00dev, 51, 0x3E);
2245                 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
2246                 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
2247                 rt2800_rfcsr_write(rt2x00dev, 56, 0xA1);
2248                 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
2249                 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
2250                 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
2251                 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
2252                 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
2253
2254                 /* TODO RF27 <- tssi */
2255
2256                 rfcsr = rf->channel <= 10 ? 0x07 : 0x06;
2257                 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2258                 rt2800_rfcsr_write(rt2x00dev, 59, rfcsr);
2259
2260                 if (is_11b) {
2261                         /* CCK */
2262                         rt2800_rfcsr_write(rt2x00dev, 31, 0xF8);
2263                         rt2800_rfcsr_write(rt2x00dev, 32, 0xC0);
2264                         if (is_type_ep)
2265                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x06);
2266                         else
2267                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x47);
2268                 } else {
2269                         /* OFDM */
2270                         if (is_type_ep)
2271                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x03);
2272                         else
2273                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
2274                 }
2275
2276                 power_bound = POWER_BOUND;
2277                 ep_reg = 0x2;
2278         } else {
2279                 rt2800_rfcsr_write(rt2x00dev, 10, 0x97);
2280                 /* FIMXE: RF11 overwrite */
2281                 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
2282                 rt2800_rfcsr_write(rt2x00dev, 25, 0xBF);
2283                 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2284                 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
2285                 rt2800_rfcsr_write(rt2x00dev, 37, 0x04);
2286                 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
2287                 rt2800_rfcsr_write(rt2x00dev, 40, 0x42);
2288                 rt2800_rfcsr_write(rt2x00dev, 41, 0xBB);
2289                 rt2800_rfcsr_write(rt2x00dev, 42, 0xD7);
2290                 rt2800_rfcsr_write(rt2x00dev, 45, 0x41);
2291                 rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
2292                 rt2800_rfcsr_write(rt2x00dev, 57, 0x77);
2293                 rt2800_rfcsr_write(rt2x00dev, 60, 0x05);
2294                 rt2800_rfcsr_write(rt2x00dev, 61, 0x01);
2295
2296                 /* TODO RF27 <- tssi */
2297
2298                 if (rf->channel >= 36 && rf->channel <= 64) {
2299
2300                         rt2800_rfcsr_write(rt2x00dev, 12, 0x2E);
2301                         rt2800_rfcsr_write(rt2x00dev, 13, 0x22);
2302                         rt2800_rfcsr_write(rt2x00dev, 22, 0x60);
2303                         rt2800_rfcsr_write(rt2x00dev, 23, 0x7F);
2304                         if (rf->channel <= 50)
2305                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x09);
2306                         else if (rf->channel >= 52)
2307                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x07);
2308                         rt2800_rfcsr_write(rt2x00dev, 39, 0x1C);
2309                         rt2800_rfcsr_write(rt2x00dev, 43, 0x5B);
2310                         rt2800_rfcsr_write(rt2x00dev, 44, 0X40);
2311                         rt2800_rfcsr_write(rt2x00dev, 46, 0X00);
2312                         rt2800_rfcsr_write(rt2x00dev, 51, 0xFE);
2313                         rt2800_rfcsr_write(rt2x00dev, 52, 0x0C);
2314                         rt2800_rfcsr_write(rt2x00dev, 54, 0xF8);
2315                         if (rf->channel <= 50) {
2316                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x06),
2317                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xD3);
2318                         } else if (rf->channel >= 52) {
2319                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x04);
2320                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2321                         }
2322
2323                         rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2324                         rt2800_rfcsr_write(rt2x00dev, 59, 0x7F);
2325                         rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2326
2327                 } else if (rf->channel >= 100 && rf->channel <= 165) {
2328
2329                         rt2800_rfcsr_write(rt2x00dev, 12, 0x0E);
2330                         rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2331                         rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2332                         if (rf->channel <= 153) {
2333                                 rt2800_rfcsr_write(rt2x00dev, 23, 0x3C);
2334                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x06);
2335                         } else if (rf->channel >= 155) {
2336                                 rt2800_rfcsr_write(rt2x00dev, 23, 0x38);
2337                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x05);
2338                         }
2339                         if (rf->channel <= 138) {
2340                                 rt2800_rfcsr_write(rt2x00dev, 39, 0x1A);
2341                                 rt2800_rfcsr_write(rt2x00dev, 43, 0x3B);
2342                                 rt2800_rfcsr_write(rt2x00dev, 44, 0x20);
2343                                 rt2800_rfcsr_write(rt2x00dev, 46, 0x18);
2344                         } else if (rf->channel >= 140) {
2345                                 rt2800_rfcsr_write(rt2x00dev, 39, 0x18);
2346                                 rt2800_rfcsr_write(rt2x00dev, 43, 0x1B);
2347                                 rt2800_rfcsr_write(rt2x00dev, 44, 0x10);
2348                                 rt2800_rfcsr_write(rt2x00dev, 46, 0X08);
2349                         }
2350                         if (rf->channel <= 124)
2351                                 rt2800_rfcsr_write(rt2x00dev, 51, 0xFC);
2352                         else if (rf->channel >= 126)
2353                                 rt2800_rfcsr_write(rt2x00dev, 51, 0xEC);
2354                         if (rf->channel <= 138)
2355                                 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2356                         else if (rf->channel >= 140)
2357                                 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2358                         rt2800_rfcsr_write(rt2x00dev, 54, 0xEB);
2359                         if (rf->channel <= 138)
2360                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x01);
2361                         else if (rf->channel >= 140)
2362                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x00);
2363                         if (rf->channel <= 128)
2364                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2365                         else if (rf->channel >= 130)
2366                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xAB);
2367                         if (rf->channel <= 116)
2368                                 rt2800_rfcsr_write(rt2x00dev, 58, 0x1D);
2369                         else if (rf->channel >= 118)
2370                                 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2371                         if (rf->channel <= 138)
2372                                 rt2800_rfcsr_write(rt2x00dev, 59, 0x3F);
2373                         else if (rf->channel >= 140)
2374                                 rt2800_rfcsr_write(rt2x00dev, 59, 0x7C);
2375                         if (rf->channel <= 116)
2376                                 rt2800_rfcsr_write(rt2x00dev, 62, 0x1D);
2377                         else if (rf->channel >= 118)
2378                                 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2379                 }
2380
2381                 power_bound = POWER_BOUND_5G;
2382                 ep_reg = 0x3;
2383         }
2384
2385         rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2386         if (info->default_power1 > power_bound)
2387                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound);
2388         else
2389                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2390         if (is_type_ep)
2391                 rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg);
2392         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2393
2394         rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2395         if (info->default_power1 > power_bound)
2396                 rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound);
2397         else
2398                 rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2);
2399         if (is_type_ep)
2400                 rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg);
2401         rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2402
2403         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2404         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2405         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2406
2407         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD,
2408                           rt2x00dev->default_ant.tx_chain_num >= 1);
2409         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
2410                           rt2x00dev->default_ant.tx_chain_num == 2);
2411         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2412
2413         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD,
2414                           rt2x00dev->default_ant.rx_chain_num >= 1);
2415         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
2416                           rt2x00dev->default_ant.rx_chain_num == 2);
2417         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2418
2419         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2420         rt2800_rfcsr_write(rt2x00dev, 6, 0xe4);
2421
2422         if (conf_is_ht40(conf))
2423                 rt2800_rfcsr_write(rt2x00dev, 30, 0x16);
2424         else
2425                 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
2426
2427         if (!is_11b) {
2428                 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
2429                 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
2430         }
2431
2432         /* TODO proper frequency adjustment */
2433         rt2800_adjust_freq_offset(rt2x00dev);
2434
2435         /* TODO merge with others */
2436         rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2437         rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2438         rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2439
2440         /* BBP settings */
2441         rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
2442         rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
2443         rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
2444
2445         rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18);
2446         rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08);
2447         rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38);
2448         rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92);
2449
2450         /* GLRT band configuration */
2451         rt2800_bbp_write(rt2x00dev, 195, 128);
2452         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0);
2453         rt2800_bbp_write(rt2x00dev, 195, 129);
2454         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E);
2455         rt2800_bbp_write(rt2x00dev, 195, 130);
2456         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28);
2457         rt2800_bbp_write(rt2x00dev, 195, 131);
2458         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20);
2459         rt2800_bbp_write(rt2x00dev, 195, 133);
2460         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F);
2461         rt2800_bbp_write(rt2x00dev, 195, 124);
2462         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F);
2463 }
2464
2465 static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev,
2466                                            const unsigned int word,
2467                                            const u8 value)
2468 {
2469         u8 chain, reg;
2470
2471         for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) {
2472                 rt2800_bbp_read(rt2x00dev, 27, &reg);
2473                 rt2x00_set_field8(&reg,  BBP27_RX_CHAIN_SEL, chain);
2474                 rt2800_bbp_write(rt2x00dev, 27, reg);
2475
2476                 rt2800_bbp_write(rt2x00dev, word, value);
2477         }
2478 }
2479
2480 static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel)
2481 {
2482         u8 cal;
2483
2484         /* TX0 IQ Gain */
2485         rt2800_bbp_write(rt2x00dev, 158, 0x2c);
2486         if (channel <= 14)
2487                 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX0_2G);
2488         else if (channel >= 36 && channel <= 64)
2489                 cal = rt2x00_eeprom_byte(rt2x00dev,
2490                                          EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G);
2491         else if (channel >= 100 && channel <= 138)
2492                 cal = rt2x00_eeprom_byte(rt2x00dev,
2493                                          EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G);
2494         else if (channel >= 140 && channel <= 165)
2495                 cal = rt2x00_eeprom_byte(rt2x00dev,
2496                                          EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G);
2497         else
2498                 cal = 0;
2499         rt2800_bbp_write(rt2x00dev, 159, cal);
2500
2501         /* TX0 IQ Phase */
2502         rt2800_bbp_write(rt2x00dev, 158, 0x2d);
2503         if (channel <= 14)
2504                 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX0_2G);
2505         else if (channel >= 36 && channel <= 64)
2506                 cal = rt2x00_eeprom_byte(rt2x00dev,
2507                                          EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G);
2508         else if (channel >= 100 && channel <= 138)
2509                 cal = rt2x00_eeprom_byte(rt2x00dev,
2510                                          EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G);
2511         else if (channel >= 140 && channel <= 165)
2512                 cal = rt2x00_eeprom_byte(rt2x00dev,
2513                                          EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G);
2514         else
2515                 cal = 0;
2516         rt2800_bbp_write(rt2x00dev, 159, cal);
2517
2518         /* TX1 IQ Gain */
2519         rt2800_bbp_write(rt2x00dev, 158, 0x4a);
2520         if (channel <= 14)
2521                 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX1_2G);
2522         else if (channel >= 36 && channel <= 64)
2523                 cal = rt2x00_eeprom_byte(rt2x00dev,
2524                                          EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G);
2525         else if (channel >= 100 && channel <= 138)
2526                 cal = rt2x00_eeprom_byte(rt2x00dev,
2527                                          EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G);
2528         else if (channel >= 140 && channel <= 165)
2529                 cal = rt2x00_eeprom_byte(rt2x00dev,
2530                                          EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G);
2531         else
2532                 cal = 0;
2533         rt2800_bbp_write(rt2x00dev, 159, cal);
2534
2535         /* TX1 IQ Phase */
2536         rt2800_bbp_write(rt2x00dev, 158, 0x4b);
2537         if (channel <= 14)
2538                 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX1_2G);
2539         else if (channel >= 36 && channel <= 64)
2540                 cal = rt2x00_eeprom_byte(rt2x00dev,
2541                                          EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G);
2542         else if (channel >= 100 && channel <= 138)
2543                 cal = rt2x00_eeprom_byte(rt2x00dev,
2544                                          EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G);
2545         else if (channel >= 140 && channel <= 165)
2546                 cal = rt2x00_eeprom_byte(rt2x00dev,
2547                                          EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G);
2548         else
2549                 cal = 0;
2550         rt2800_bbp_write(rt2x00dev, 159, cal);
2551
2552         /* FIXME: possible RX0, RX1 callibration ? */
2553
2554         /* RF IQ compensation control */
2555         rt2800_bbp_write(rt2x00dev, 158, 0x04);
2556         cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_COMPENSATION_CONTROL);
2557         rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
2558
2559         /* RF IQ imbalance compensation control */
2560         rt2800_bbp_write(rt2x00dev, 158, 0x03);
2561         cal = rt2x00_eeprom_byte(rt2x00dev,
2562                                  EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL);
2563         rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
2564 }
2565
2566 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
2567                                   struct ieee80211_conf *conf,
2568                                   struct rf_channel *rf,
2569                                   struct channel_info *info)
2570 {
2571         u32 reg;
2572         unsigned int tx_pin;
2573         u8 bbp, rfcsr;
2574
2575         if (rf->channel <= 14) {
2576                 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
2577                 info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2);
2578         } else {
2579                 info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1);
2580                 info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2);
2581         }
2582
2583         switch (rt2x00dev->chip.rf) {
2584         case RF2020:
2585         case RF3020:
2586         case RF3021:
2587         case RF3022:
2588         case RF3320:
2589                 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
2590                 break;
2591         case RF3052:
2592                 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
2593                 break;
2594         case RF3290:
2595                 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
2596                 break;
2597         case RF3322:
2598                 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
2599                 break;
2600         case RF5360:
2601         case RF5370:
2602         case RF5372:
2603         case RF5390:
2604         case RF5392:
2605                 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
2606                 break;
2607         case RF5592:
2608                 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info);
2609                 break;
2610         default:
2611                 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
2612         }
2613
2614         if (rt2x00_rf(rt2x00dev, RF3290) ||
2615             rt2x00_rf(rt2x00dev, RF3322) ||
2616             rt2x00_rf(rt2x00dev, RF5360) ||
2617             rt2x00_rf(rt2x00dev, RF5370) ||
2618             rt2x00_rf(rt2x00dev, RF5372) ||
2619             rt2x00_rf(rt2x00dev, RF5390) ||
2620             rt2x00_rf(rt2x00dev, RF5392)) {
2621                 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2622                 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
2623                 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
2624                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2625
2626                 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2627                 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2628                 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2629         }
2630
2631         /*
2632          * Change BBP settings
2633          */
2634         if (rt2x00_rt(rt2x00dev, RT3352)) {
2635                 rt2800_bbp_write(rt2x00dev, 27, 0x0);
2636                 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
2637                 rt2800_bbp_write(rt2x00dev, 27, 0x20);
2638                 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
2639         } else {
2640                 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
2641                 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
2642                 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
2643                 rt2800_bbp_write(rt2x00dev, 86, 0);
2644         }
2645
2646         if (rf->channel <= 14) {
2647                 if (!rt2x00_rt(rt2x00dev, RT5390) &&
2648                     !rt2x00_rt(rt2x00dev, RT5392)) {
2649                         if (test_bit(CAPABILITY_EXTERNAL_LNA_BG,
2650                                      &rt2x00dev->cap_flags)) {
2651                                 rt2800_bbp_write(rt2x00dev, 82, 0x62);
2652                                 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2653                         } else {
2654                                 rt2800_bbp_write(rt2x00dev, 82, 0x84);
2655                                 rt2800_bbp_write(rt2x00dev, 75, 0x50);
2656                         }
2657                 }
2658         } else {
2659                 if (rt2x00_rt(rt2x00dev, RT3572))
2660                         rt2800_bbp_write(rt2x00dev, 82, 0x94);
2661                 else
2662                         rt2800_bbp_write(rt2x00dev, 82, 0xf2);
2663
2664                 if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags))
2665                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
2666                 else
2667                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
2668         }
2669
2670         rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
2671         rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
2672         rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
2673         rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
2674         rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
2675
2676         if (rt2x00_rt(rt2x00dev, RT3572))
2677                 rt2800_rfcsr_write(rt2x00dev, 8, 0);
2678
2679         tx_pin = 0;
2680
2681         /* Turn on unused PA or LNA when not using 1T or 1R */
2682         if (rt2x00dev->default_ant.tx_chain_num == 2) {
2683                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
2684                                    rf->channel > 14);
2685                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
2686                                    rf->channel <= 14);
2687         }
2688
2689         /* Turn on unused PA or LNA when not using 1T or 1R */
2690         if (rt2x00dev->default_ant.rx_chain_num == 2) {
2691                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
2692                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
2693         }
2694
2695         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
2696         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
2697         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
2698         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
2699         if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
2700                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
2701         else
2702                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
2703                                    rf->channel <= 14);
2704         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
2705
2706         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
2707
2708         if (rt2x00_rt(rt2x00dev, RT3572))
2709                 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
2710
2711         if (rt2x00_rt(rt2x00dev, RT5592)) {
2712                 rt2800_bbp_write(rt2x00dev, 195, 141);
2713                 rt2800_bbp_write(rt2x00dev, 196, conf_is_ht40(conf) ? 0x10 : 0x1a);
2714
2715                 /* AGC init */
2716                 reg = (rf->channel <= 14 ? 0x1c : 0x24) + 2 * rt2x00dev->lna_gain;
2717                 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
2718
2719                 rt2800_iq_calibrate(rt2x00dev, rf->channel);
2720         }
2721
2722         rt2800_bbp_read(rt2x00dev, 4, &bbp);
2723         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
2724         rt2800_bbp_write(rt2x00dev, 4, bbp);
2725
2726         rt2800_bbp_read(rt2x00dev, 3, &bbp);
2727         rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
2728         rt2800_bbp_write(rt2x00dev, 3, bbp);
2729
2730         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
2731                 if (conf_is_ht40(conf)) {
2732                         rt2800_bbp_write(rt2x00dev, 69, 0x1a);
2733                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
2734                         rt2800_bbp_write(rt2x00dev, 73, 0x16);
2735                 } else {
2736                         rt2800_bbp_write(rt2x00dev, 69, 0x16);
2737                         rt2800_bbp_write(rt2x00dev, 70, 0x08);
2738                         rt2800_bbp_write(rt2x00dev, 73, 0x11);
2739                 }
2740         }
2741
2742         msleep(1);
2743
2744         /*
2745          * Clear channel statistic counters
2746          */
2747         rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
2748         rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
2749         rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
2750
2751         /*
2752          * Clear update flag
2753          */
2754         if (rt2x00_rt(rt2x00dev, RT3352)) {
2755                 rt2800_bbp_read(rt2x00dev, 49, &bbp);
2756                 rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0);
2757                 rt2800_bbp_write(rt2x00dev, 49, bbp);
2758         }
2759 }
2760
2761 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
2762 {
2763         u8 tssi_bounds[9];
2764         u8 current_tssi;
2765         u16 eeprom;
2766         u8 step;
2767         int i;
2768
2769         /*
2770          * Read TSSI boundaries for temperature compensation from
2771          * the EEPROM.
2772          *
2773          * Array idx               0    1    2    3    4    5    6    7    8
2774          * Matching Delta value   -4   -3   -2   -1    0   +1   +2   +3   +4
2775          * Example TSSI bounds  0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
2776          */
2777         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
2778                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
2779                 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2780                                         EEPROM_TSSI_BOUND_BG1_MINUS4);
2781                 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2782                                         EEPROM_TSSI_BOUND_BG1_MINUS3);
2783
2784                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
2785                 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2786                                         EEPROM_TSSI_BOUND_BG2_MINUS2);
2787                 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2788                                         EEPROM_TSSI_BOUND_BG2_MINUS1);
2789
2790                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
2791                 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2792                                         EEPROM_TSSI_BOUND_BG3_REF);
2793                 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2794                                         EEPROM_TSSI_BOUND_BG3_PLUS1);
2795
2796                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
2797                 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2798                                         EEPROM_TSSI_BOUND_BG4_PLUS2);
2799                 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2800                                         EEPROM_TSSI_BOUND_BG4_PLUS3);
2801
2802                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
2803                 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2804                                         EEPROM_TSSI_BOUND_BG5_PLUS4);
2805
2806                 step = rt2x00_get_field16(eeprom,
2807                                           EEPROM_TSSI_BOUND_BG5_AGC_STEP);
2808         } else {
2809                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
2810                 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2811                                         EEPROM_TSSI_BOUND_A1_MINUS4);
2812                 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2813                                         EEPROM_TSSI_BOUND_A1_MINUS3);
2814
2815                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
2816                 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2817                                         EEPROM_TSSI_BOUND_A2_MINUS2);
2818                 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2819                                         EEPROM_TSSI_BOUND_A2_MINUS1);
2820
2821                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
2822                 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2823                                         EEPROM_TSSI_BOUND_A3_REF);
2824                 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2825                                         EEPROM_TSSI_BOUND_A3_PLUS1);
2826
2827                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
2828                 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2829                                         EEPROM_TSSI_BOUND_A4_PLUS2);
2830                 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2831                                         EEPROM_TSSI_BOUND_A4_PLUS3);
2832
2833                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
2834                 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2835                                         EEPROM_TSSI_BOUND_A5_PLUS4);
2836
2837                 step = rt2x00_get_field16(eeprom,
2838                                           EEPROM_TSSI_BOUND_A5_AGC_STEP);
2839         }
2840
2841         /*
2842          * Check if temperature compensation is supported.
2843          */
2844         if (tssi_bounds[4] == 0xff || step == 0xff)
2845                 return 0;
2846
2847         /*
2848          * Read current TSSI (BBP 49).
2849          */
2850         rt2800_bbp_read(rt2x00dev, 49, &current_tssi);
2851
2852         /*
2853          * Compare TSSI value (BBP49) with the compensation boundaries
2854          * from the EEPROM and increase or decrease tx power.
2855          */
2856         for (i = 0; i <= 3; i++) {
2857                 if (current_tssi > tssi_bounds[i])
2858                         break;
2859         }
2860
2861         if (i == 4) {
2862                 for (i = 8; i >= 5; i--) {
2863                         if (current_tssi < tssi_bounds[i])
2864                                 break;
2865                 }
2866         }
2867
2868         return (i - 4) * step;
2869 }
2870
2871 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
2872                                       enum ieee80211_band band)
2873 {
2874         u16 eeprom;
2875         u8 comp_en;
2876         u8 comp_type;
2877         int comp_value = 0;
2878
2879         rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
2880
2881         /*
2882          * HT40 compensation not required.
2883          */
2884         if (eeprom == 0xffff ||
2885             !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
2886                 return 0;
2887
2888         if (band == IEEE80211_BAND_2GHZ) {
2889                 comp_en = rt2x00_get_field16(eeprom,
2890                                  EEPROM_TXPOWER_DELTA_ENABLE_2G);
2891                 if (comp_en) {
2892                         comp_type = rt2x00_get_field16(eeprom,
2893                                            EEPROM_TXPOWER_DELTA_TYPE_2G);
2894                         comp_value = rt2x00_get_field16(eeprom,
2895                                             EEPROM_TXPOWER_DELTA_VALUE_2G);
2896                         if (!comp_type)
2897                                 comp_value = -comp_value;
2898                 }
2899         } else {
2900                 comp_en = rt2x00_get_field16(eeprom,
2901                                  EEPROM_TXPOWER_DELTA_ENABLE_5G);
2902                 if (comp_en) {
2903                         comp_type = rt2x00_get_field16(eeprom,
2904                                            EEPROM_TXPOWER_DELTA_TYPE_5G);
2905                         comp_value = rt2x00_get_field16(eeprom,
2906                                             EEPROM_TXPOWER_DELTA_VALUE_5G);
2907                         if (!comp_type)
2908                                 comp_value = -comp_value;
2909                 }
2910         }
2911
2912         return comp_value;
2913 }
2914
2915 static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev,
2916                                         int power_level, int max_power)
2917 {
2918         int delta;
2919
2920         if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags))
2921                 return 0;
2922
2923         /*
2924          * XXX: We don't know the maximum transmit power of our hardware since
2925          * the EEPROM doesn't expose it. We only know that we are calibrated
2926          * to 100% tx power.
2927          *
2928          * Hence, we assume the regulatory limit that cfg80211 calulated for
2929          * the current channel is our maximum and if we are requested to lower
2930          * the value we just reduce our tx power accordingly.
2931          */
2932         delta = power_level - max_power;
2933         return min(delta, 0);
2934 }
2935
2936 static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
2937                                    enum ieee80211_band band, int power_level,
2938                                    u8 txpower, int delta)
2939 {
2940         u16 eeprom;
2941         u8 criterion;
2942         u8 eirp_txpower;
2943         u8 eirp_txpower_criterion;
2944         u8 reg_limit;
2945
2946         if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags)) {
2947                 /*
2948                  * Check if eirp txpower exceed txpower_limit.
2949                  * We use OFDM 6M as criterion and its eirp txpower
2950                  * is stored at EEPROM_EIRP_MAX_TX_POWER.
2951                  * .11b data rate need add additional 4dbm
2952                  * when calculating eirp txpower.
2953                  */
2954                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + 1,
2955                                    &eeprom);
2956                 criterion = rt2x00_get_field16(eeprom,
2957                                                EEPROM_TXPOWER_BYRATE_RATE0);
2958
2959                 rt2x00_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER,
2960                                    &eeprom);
2961
2962                 if (band == IEEE80211_BAND_2GHZ)
2963                         eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2964                                                  EEPROM_EIRP_MAX_TX_POWER_2GHZ);
2965                 else
2966                         eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2967                                                  EEPROM_EIRP_MAX_TX_POWER_5GHZ);
2968
2969                 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
2970                                (is_rate_b ? 4 : 0) + delta;
2971
2972                 reg_limit = (eirp_txpower > power_level) ?
2973                                         (eirp_txpower - power_level) : 0;
2974         } else
2975                 reg_limit = 0;
2976
2977         txpower = max(0, txpower + delta - reg_limit);
2978         return min_t(u8, txpower, 0xc);
2979 }
2980
2981 /*
2982  * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and
2983  * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values,
2984  * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power
2985  * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm.
2986  * Reference per rate transmit power values are located in the EEPROM at
2987  * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to
2988  * current conditions (i.e. band, bandwidth, temperature, user settings).
2989  */
2990 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
2991                                   struct ieee80211_channel *chan,
2992                                   int power_level)
2993 {
2994         u8 txpower, r1;
2995         u16 eeprom;
2996         u32 reg, offset;
2997         int i, is_rate_b, delta, power_ctrl;
2998         enum ieee80211_band band = chan->band;
2999
3000         /*
3001          * Calculate HT40 compensation. For 40MHz we need to add or subtract
3002          * value read from EEPROM (different for 2GHz and for 5GHz).
3003          */
3004         delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
3005
3006         /*
3007          * Calculate temperature compensation. Depends on measurement of current
3008          * TSSI (Transmitter Signal Strength Indication) we know TX power (due
3009          * to temperature or maybe other factors) is smaller or bigger than
3010          * expected. We adjust it, based on TSSI reference and boundaries values
3011          * provided in EEPROM.
3012          */
3013         delta += rt2800_get_gain_calibration_delta(rt2x00dev);
3014
3015         /*
3016          * Decrease power according to user settings, on devices with unknown
3017          * maximum tx power. For other devices we take user power_level into
3018          * consideration on rt2800_compensate_txpower().
3019          */
3020         delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level,
3021                                               chan->max_power);
3022
3023         /*
3024          * BBP_R1 controls TX power for all rates, it allow to set the following
3025          * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively.
3026          *
3027          * TODO: we do not use +6 dBm option to do not increase power beyond
3028          * regulatory limit, however this could be utilized for devices with
3029          * CAPABILITY_POWER_LIMIT.
3030          */
3031         rt2800_bbp_read(rt2x00dev, 1, &r1);
3032         if (delta <= -12) {
3033                 power_ctrl = 2;
3034                 delta += 12;
3035         } else if (delta <= -6) {
3036                 power_ctrl = 1;
3037                 delta += 6;
3038         } else {
3039                 power_ctrl = 0;
3040         }
3041         rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl);
3042         rt2800_bbp_write(rt2x00dev, 1, r1);
3043         offset = TX_PWR_CFG_0;
3044
3045         for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
3046                 /* just to be safe */
3047                 if (offset > TX_PWR_CFG_4)
3048                         break;
3049
3050                 rt2800_register_read(rt2x00dev, offset, &reg);
3051
3052                 /* read the next four txpower values */
3053                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
3054                                    &eeprom);
3055
3056                 is_rate_b = i ? 0 : 1;
3057                 /*
3058                  * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
3059                  * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
3060                  * TX_PWR_CFG_4: unknown
3061                  */
3062                 txpower = rt2x00_get_field16(eeprom,
3063                                              EEPROM_TXPOWER_BYRATE_RATE0);
3064                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
3065                                              power_level, txpower, delta);
3066                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
3067
3068                 /*
3069                  * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
3070                  * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
3071                  * TX_PWR_CFG_4: unknown
3072                  */
3073                 txpower = rt2x00_get_field16(eeprom,
3074                                              EEPROM_TXPOWER_BYRATE_RATE1);
3075                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
3076                                              power_level, txpower, delta);
3077                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
3078
3079                 /*
3080                  * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
3081                  * TX_PWR_CFG_2: MCS6,  TX_PWR_CFG_3: MCS14,
3082                  * TX_PWR_CFG_4: unknown
3083                  */
3084                 txpower = rt2x00_get_field16(eeprom,
3085                                              EEPROM_TXPOWER_BYRATE_RATE2);
3086                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
3087                                              power_level, txpower, delta);
3088                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
3089
3090                 /*
3091                  * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
3092                  * TX_PWR_CFG_2: MCS7,  TX_PWR_CFG_3: MCS15,
3093                  * TX_PWR_CFG_4: unknown
3094                  */
3095                 txpower = rt2x00_get_field16(eeprom,
3096                                              EEPROM_TXPOWER_BYRATE_RATE3);
3097                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
3098                                              power_level, txpower, delta);
3099                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
3100
3101                 /* read the next four txpower values */
3102                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
3103                                    &eeprom);
3104
3105                 is_rate_b = 0;
3106                 /*
3107                  * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
3108                  * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
3109                  * TX_PWR_CFG_4: unknown
3110                  */
3111                 txpower = rt2x00_get_field16(eeprom,
3112                                              EEPROM_TXPOWER_BYRATE_RATE0);
3113                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
3114                                              power_level, txpower, delta);
3115                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
3116
3117                 /*
3118                  * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
3119                  * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
3120                  * TX_PWR_CFG_4: unknown
3121                  */
3122                 txpower = rt2x00_get_field16(eeprom,
3123                                              EEPROM_TXPOWER_BYRATE_RATE1);
3124                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
3125                                              power_level, txpower, delta);
3126                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
3127
3128                 /*
3129                  * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
3130                  * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
3131                  * TX_PWR_CFG_4: unknown
3132                  */
3133                 txpower = rt2x00_get_field16(eeprom,
3134                                              EEPROM_TXPOWER_BYRATE_RATE2);
3135                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
3136                                              power_level, txpower, delta);
3137                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
3138
3139                 /*
3140                  * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
3141                  * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
3142                  * TX_PWR_CFG_4: unknown
3143                  */
3144                 txpower = rt2x00_get_field16(eeprom,
3145                                              EEPROM_TXPOWER_BYRATE_RATE3);
3146                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
3147                                              power_level, txpower, delta);
3148                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
3149
3150                 rt2800_register_write(rt2x00dev, offset, reg);
3151
3152                 /* next TX_PWR_CFG register */
3153                 offset += 4;
3154         }
3155 }
3156
3157 void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
3158 {
3159         rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.chandef.chan,
3160                               rt2x00dev->tx_power);
3161 }
3162 EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
3163
3164 void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
3165 {
3166         u32     tx_pin;
3167         u8      rfcsr;
3168
3169         /*
3170          * A voltage-controlled oscillator(VCO) is an electronic oscillator
3171          * designed to be controlled in oscillation frequency by a voltage
3172          * input. Maybe the temperature will affect the frequency of
3173          * oscillation to be shifted. The VCO calibration will be called
3174          * periodically to adjust the frequency to be precision.
3175         */
3176
3177         rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
3178         tx_pin &= TX_PIN_CFG_PA_PE_DISABLE;
3179         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
3180
3181         switch (rt2x00dev->chip.rf) {
3182         case RF2020:
3183         case RF3020:
3184         case RF3021:
3185         case RF3022:
3186         case RF3320:
3187         case RF3052:
3188                 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
3189                 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
3190                 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
3191                 break;
3192         case RF3290:
3193         case RF5360:
3194         case RF5370:
3195         case RF5372:
3196         case RF5390:
3197         case RF5392:
3198                 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
3199                 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
3200                 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3201                 break;
3202         default:
3203                 return;
3204         }
3205
3206         mdelay(1);
3207
3208         rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
3209         if (rt2x00dev->rf_channel <= 14) {
3210                 switch (rt2x00dev->default_ant.tx_chain_num) {
3211                 case 3:
3212                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1);
3213                         /* fall through */
3214                 case 2:
3215                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
3216                         /* fall through */
3217                 case 1:
3218                 default:
3219                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
3220                         break;
3221                 }
3222         } else {
3223                 switch (rt2x00dev->default_ant.tx_chain_num) {
3224                 case 3:
3225                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1);
3226                         /* fall through */
3227                 case 2:
3228                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
3229                         /* fall through */
3230                 case 1:
3231                 default:
3232                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
3233                         break;
3234                 }
3235         }
3236         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
3237
3238 }
3239 EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
3240
3241 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
3242                                       struct rt2x00lib_conf *libconf)
3243 {
3244         u32 reg;
3245
3246         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
3247         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
3248                            libconf->conf->short_frame_max_tx_count);
3249         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
3250                            libconf->conf->long_frame_max_tx_count);
3251         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
3252 }
3253
3254 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
3255                              struct rt2x00lib_conf *libconf)
3256 {
3257         enum dev_state state =
3258             (libconf->conf->flags & IEEE80211_CONF_PS) ?
3259                 STATE_SLEEP : STATE_AWAKE;
3260         u32 reg;
3261
3262         if (state == STATE_SLEEP) {
3263                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
3264
3265                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
3266                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
3267                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
3268                                    libconf->conf->listen_interval - 1);
3269                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
3270                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
3271
3272                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
3273         } else {
3274                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
3275                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
3276                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
3277                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
3278                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
3279
3280                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
3281         }
3282 }
3283
3284 void rt2800_config(struct rt2x00_dev *rt2x00dev,
3285                    struct rt2x00lib_conf *libconf,
3286                    const unsigned int flags)
3287 {
3288         /* Always recalculate LNA gain before changing configuration */
3289         rt2800_config_lna_gain(rt2x00dev, libconf);
3290
3291         if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
3292                 rt2800_config_channel(rt2x00dev, libconf->conf,
3293                                       &libconf->rf, &libconf->channel);
3294                 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
3295                                       libconf->conf->power_level);
3296         }
3297         if (flags & IEEE80211_CONF_CHANGE_POWER)
3298                 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
3299                                       libconf->conf->power_level);
3300         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
3301                 rt2800_config_retry_limit(rt2x00dev, libconf);
3302         if (flags & IEEE80211_CONF_CHANGE_PS)
3303                 rt2800_config_ps(rt2x00dev, libconf);
3304 }
3305 EXPORT_SYMBOL_GPL(rt2800_config);
3306
3307 /*
3308  * Link tuning
3309  */
3310 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
3311 {
3312         u32 reg;
3313
3314         /*
3315          * Update FCS error count from register.
3316          */
3317         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
3318         qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
3319 }
3320 EXPORT_SYMBOL_GPL(rt2800_link_stats);
3321
3322 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
3323 {
3324         u8 vgc;
3325
3326         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
3327                 if (rt2x00_rt(rt2x00dev, RT3070) ||
3328                     rt2x00_rt(rt2x00dev, RT3071) ||
3329                     rt2x00_rt(rt2x00dev, RT3090) ||
3330                     rt2x00_rt(rt2x00dev, RT3290) ||
3331                     rt2x00_rt(rt2x00dev, RT3390) ||
3332                     rt2x00_rt(rt2x00dev, RT3572) ||
3333                     rt2x00_rt(rt2x00dev, RT5390) ||
3334                     rt2x00_rt(rt2x00dev, RT5392) ||
3335                     rt2x00_rt(rt2x00dev, RT5592))
3336                         vgc = 0x1c + (2 * rt2x00dev->lna_gain);
3337                 else
3338                         vgc = 0x2e + rt2x00dev->lna_gain;
3339         } else { /* 5GHZ band */
3340                 if (rt2x00_rt(rt2x00dev, RT3572))
3341                         vgc = 0x22 + (rt2x00dev->lna_gain * 5) / 3;
3342                 else if (rt2x00_rt(rt2x00dev, RT5592))
3343                         vgc = 0x24 + (2 * rt2x00dev->lna_gain);
3344                 else {
3345                         if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
3346                                 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
3347                         else
3348                                 vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
3349                 }
3350         }
3351
3352         return vgc;
3353 }
3354
3355 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
3356                                   struct link_qual *qual, u8 vgc_level)
3357 {
3358         if (qual->vgc_level != vgc_level) {
3359                 if (rt2x00_rt(rt2x00dev, RT5592)) {
3360                         rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a);
3361                         rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, vgc_level);
3362                 } else
3363                         rt2800_bbp_write(rt2x00dev, 66, vgc_level);
3364                 qual->vgc_level = vgc_level;
3365                 qual->vgc_level_reg = vgc_level;
3366         }
3367 }
3368
3369 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
3370 {
3371         rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
3372 }
3373 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
3374
3375 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
3376                        const u32 count)
3377 {
3378         u8 vgc;
3379
3380         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
3381                 return;
3382         /*
3383          * When RSSI is better then -80 increase VGC level with 0x10, except
3384          * for rt5592 chip.
3385          */
3386
3387         vgc = rt2800_get_default_vgc(rt2x00dev);
3388
3389         if (rt2x00_rt(rt2x00dev, RT5592) && qual->rssi > -65)
3390                 vgc += 0x20;
3391         else if (qual->rssi > -80)
3392                 vgc += 0x10;
3393
3394         rt2800_set_vgc(rt2x00dev, qual, vgc);
3395 }
3396 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
3397
3398 /*
3399  * Initialization functions.
3400  */
3401 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
3402 {
3403         u32 reg;
3404         u16 eeprom;
3405         unsigned int i;
3406         int ret;
3407
3408         rt2800_disable_wpdma(rt2x00dev);
3409
3410         ret = rt2800_drv_init_registers(rt2x00dev);
3411         if (ret)
3412                 return ret;
3413
3414         rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
3415         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
3416         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
3417         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
3418         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
3419         rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
3420
3421         rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
3422         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
3423         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
3424         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
3425         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
3426         rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
3427
3428         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
3429         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
3430
3431         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
3432
3433         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
3434         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
3435         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
3436         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
3437         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
3438         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
3439         rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
3440         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
3441
3442         rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
3443
3444         rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
3445         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
3446         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
3447         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
3448
3449         if (rt2x00_rt(rt2x00dev, RT3290)) {
3450                 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
3451                 if (rt2x00_get_field32(reg, WLAN_EN) == 1) {
3452                         rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 1);
3453                         rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
3454                 }
3455
3456                 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
3457                 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) {
3458                         rt2x00_set_field32(&reg, LDO0_EN, 1);
3459                         rt2x00_set_field32(&reg, LDO_BGSEL, 3);
3460                         rt2800_register_write(rt2x00dev, CMB_CTRL, reg);
3461                 }
3462
3463                 rt2800_register_read(rt2x00dev, OSC_CTRL, &reg);
3464                 rt2x00_set_field32(&reg, OSC_ROSC_EN, 1);
3465                 rt2x00_set_field32(&reg, OSC_CAL_REQ, 1);
3466                 rt2x00_set_field32(&reg, OSC_REF_CYCLE, 0x27);
3467                 rt2800_register_write(rt2x00dev, OSC_CTRL, reg);
3468
3469                 rt2800_register_read(rt2x00dev, COEX_CFG0, &reg);
3470                 rt2x00_set_field32(&reg, COEX_CFG_ANT, 0x5e);
3471                 rt2800_register_write(rt2x00dev, COEX_CFG0, reg);
3472
3473                 rt2800_register_read(rt2x00dev, COEX_CFG2, &reg);
3474                 rt2x00_set_field32(&reg, BT_COEX_CFG1, 0x00);
3475                 rt2x00_set_field32(&reg, BT_COEX_CFG0, 0x17);
3476                 rt2x00_set_field32(&reg, WL_COEX_CFG1, 0x93);
3477                 rt2x00_set_field32(&reg, WL_COEX_CFG0, 0x7f);
3478                 rt2800_register_write(rt2x00dev, COEX_CFG2, reg);
3479
3480                 rt2800_register_read(rt2x00dev, PLL_CTRL, &reg);
3481                 rt2x00_set_field32(&reg, PLL_CONTROL, 1);
3482                 rt2800_register_write(rt2x00dev, PLL_CTRL, reg);
3483         }
3484
3485         if (rt2x00_rt(rt2x00dev, RT3071) ||
3486             rt2x00_rt(rt2x00dev, RT3090) ||
3487             rt2x00_rt(rt2x00dev, RT3290) ||
3488             rt2x00_rt(rt2x00dev, RT3390)) {
3489
3490                 if (rt2x00_rt(rt2x00dev, RT3290))
3491                         rt2800_register_write(rt2x00dev, TX_SW_CFG0,
3492                                               0x00000404);
3493                 else
3494                         rt2800_register_write(rt2x00dev, TX_SW_CFG0,
3495                                               0x00000400);
3496
3497                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
3498                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3499                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
3500                     rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
3501                         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3502                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
3503                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
3504                                                       0x0000002c);
3505                         else
3506                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
3507                                                       0x0000000f);
3508                 } else {
3509                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
3510                 }
3511         } else if (rt2x00_rt(rt2x00dev, RT3070)) {
3512                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
3513
3514                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
3515                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
3516                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
3517                 } else {
3518                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3519                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
3520                 }
3521         } else if (rt2800_is_305x_soc(rt2x00dev)) {
3522                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
3523                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
3524                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
3525         } else if (rt2x00_rt(rt2x00dev, RT3352)) {
3526                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
3527                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3528                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
3529         } else if (rt2x00_rt(rt2x00dev, RT3572)) {
3530                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
3531                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3532         } else if (rt2x00_rt(rt2x00dev, RT5390) ||
3533                    rt2x00_rt(rt2x00dev, RT5392) ||
3534                    rt2x00_rt(rt2x00dev, RT5592)) {
3535                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
3536                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3537                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
3538         } else {
3539                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
3540                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3541         }
3542
3543         rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
3544         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
3545         rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
3546         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
3547         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
3548         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
3549         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
3550         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
3551         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
3552         rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
3553
3554         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
3555         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
3556         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
3557         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
3558         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
3559
3560         rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
3561         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
3562         if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
3563             rt2x00_rt(rt2x00dev, RT2883) ||
3564             rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
3565                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
3566         else
3567                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
3568         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
3569         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
3570         rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
3571
3572         rt2800_register_read(rt2x00dev, LED_CFG, &reg);
3573         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
3574         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
3575         rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
3576         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
3577         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
3578         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
3579         rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
3580         rt2800_register_write(rt2x00dev, LED_CFG, reg);
3581
3582         rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
3583
3584         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
3585         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
3586         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
3587         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
3588         rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
3589         rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
3590         rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
3591         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
3592
3593         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
3594         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
3595         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
3596         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
3597         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
3598         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
3599         rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
3600         rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
3601         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
3602
3603         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
3604         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
3605         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
3606         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
3607         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3608         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3609         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3610         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
3611         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3612         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
3613         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
3614         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
3615
3616         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
3617         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
3618         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
3619         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
3620         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3621         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3622         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3623         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
3624         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3625         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
3626         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
3627         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
3628
3629         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
3630         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
3631         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
3632         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
3633         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3634         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3635         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3636         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
3637         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3638         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
3639         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
3640         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
3641
3642         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
3643         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
3644         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
3645         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
3646         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3647         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3648         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3649         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
3650         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3651         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
3652         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
3653         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
3654
3655         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
3656         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
3657         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
3658         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
3659         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3660         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3661         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3662         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
3663         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3664         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
3665         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
3666         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
3667
3668         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
3669         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
3670         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
3671         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
3672         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3673         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3674         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3675         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
3676         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3677         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
3678         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
3679         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
3680
3681         if (rt2x00_is_usb(rt2x00dev)) {
3682                 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
3683
3684                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
3685                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
3686                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
3687                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
3688                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
3689                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
3690                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
3691                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
3692                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
3693                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
3694                 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
3695         }
3696
3697         /*
3698          * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
3699          * although it is reserved.
3700          */
3701         rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
3702         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
3703         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
3704         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
3705         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
3706         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
3707         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
3708         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
3709         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
3710         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
3711         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
3712         rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
3713
3714         reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002;
3715         rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg);
3716
3717         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
3718         rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
3719         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
3720                            IEEE80211_MAX_RTS_THRESHOLD);
3721         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
3722         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
3723
3724         rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
3725
3726         /*
3727          * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
3728          * time should be set to 16. However, the original Ralink driver uses
3729          * 16 for both and indeed using a value of 10 for CCK SIFS results in
3730          * connection problems with 11g + CTS protection. Hence, use the same
3731          * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
3732          */
3733         rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
3734         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
3735         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
3736         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
3737         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
3738         rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
3739         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
3740
3741         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
3742
3743         /*
3744          * ASIC will keep garbage value after boot, clear encryption keys.
3745          */
3746         for (i = 0; i < 4; i++)
3747                 rt2800_register_write(rt2x00dev,
3748                                          SHARED_KEY_MODE_ENTRY(i), 0);
3749
3750         for (i = 0; i < 256; i++) {
3751                 rt2800_config_wcid(rt2x00dev, NULL, i);
3752                 rt2800_delete_wcid_attr(rt2x00dev, i);
3753                 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
3754         }
3755
3756         /*
3757          * Clear all beacons
3758          */
3759         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE0);
3760         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE1);
3761         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE2);
3762         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE3);
3763         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE4);
3764         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE5);
3765         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE6);
3766         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE7);
3767
3768         if (rt2x00_is_usb(rt2x00dev)) {
3769                 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
3770                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
3771                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
3772         } else if (rt2x00_is_pcie(rt2x00dev)) {
3773                 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
3774                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
3775                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
3776         }
3777
3778         rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
3779         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
3780         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
3781         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
3782         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
3783         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
3784         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
3785         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
3786         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
3787         rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
3788
3789         rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
3790         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
3791         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
3792         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
3793         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
3794         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
3795         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
3796         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
3797         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
3798         rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
3799
3800         rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
3801         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
3802         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
3803         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
3804         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
3805         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
3806         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
3807         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
3808         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
3809         rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
3810
3811         rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
3812         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
3813         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
3814         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
3815         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
3816         rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
3817
3818         /*
3819          * Do not force the BA window size, we use the TXWI to set it
3820          */
3821         rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
3822         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
3823         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
3824         rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
3825
3826         /*
3827          * We must clear the error counters.
3828          * These registers are cleared on read,
3829          * so we may pass a useless variable to store the value.
3830          */
3831         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
3832         rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
3833         rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
3834         rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
3835         rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
3836         rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
3837
3838         /*
3839          * Setup leadtime for pre tbtt interrupt to 6ms
3840          */
3841         rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
3842         rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
3843         rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
3844
3845         /*
3846          * Set up channel statistics timer
3847          */
3848         rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
3849         rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
3850         rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
3851         rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
3852         rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
3853         rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
3854         rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
3855
3856         return 0;
3857 }
3858
3859 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
3860 {
3861         unsigned int i;
3862         u32 reg;
3863
3864         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3865                 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
3866                 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
3867                         return 0;
3868
3869                 udelay(REGISTER_BUSY_DELAY);
3870         }
3871
3872         rt2x00_err(rt2x00dev, "BBP/RF register access failed, aborting\n");
3873         return -EACCES;
3874 }
3875
3876 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
3877 {
3878         unsigned int i;
3879         u8 value;
3880
3881         /*
3882          * BBP was enabled after firmware was loaded,
3883          * but we need to reactivate it now.
3884          */
3885         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
3886         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
3887         msleep(1);
3888
3889         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3890                 rt2800_bbp_read(rt2x00dev, 0, &value);
3891                 if ((value != 0xff) && (value != 0x00))
3892                         return 0;
3893                 udelay(REGISTER_BUSY_DELAY);
3894         }
3895
3896         rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
3897         return -EACCES;
3898 }
3899
3900 static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev)
3901 {
3902         u8 value;
3903
3904         rt2800_bbp_read(rt2x00dev, 4, &value);
3905         rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
3906         rt2800_bbp_write(rt2x00dev, 4, value);
3907 }
3908
3909 static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev)
3910 {
3911         rt2800_bbp_write(rt2x00dev, 142, 1);
3912         rt2800_bbp_write(rt2x00dev, 143, 57);
3913 }
3914
3915 static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev)
3916 {
3917         const u8 glrt_table[] = {
3918                 0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */
3919                 0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */
3920                 0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */
3921                 0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */
3922                 0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */
3923                 0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */
3924                 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */
3925                 0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */
3926                 0x2E, 0x36, 0x30, 0x6E,                                     /* 208 ~ 211 */
3927         };
3928         int i;
3929
3930         for (i = 0; i < ARRAY_SIZE(glrt_table); i++) {
3931                 rt2800_bbp_write(rt2x00dev, 195, 128 + i);
3932                 rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]);
3933         }
3934 };
3935
3936 static void rt2800_init_bbp_early(struct rt2x00_dev *rt2x00dev)
3937 {
3938         rt2800_bbp_write(rt2x00dev, 65, 0x2C);
3939         rt2800_bbp_write(rt2x00dev, 66, 0x38);
3940         rt2800_bbp_write(rt2x00dev, 68, 0x0B);
3941         rt2800_bbp_write(rt2x00dev, 69, 0x12);
3942         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3943         rt2800_bbp_write(rt2x00dev, 73, 0x10);
3944         rt2800_bbp_write(rt2x00dev, 81, 0x37);
3945         rt2800_bbp_write(rt2x00dev, 82, 0x62);
3946         rt2800_bbp_write(rt2x00dev, 83, 0x6A);
3947         rt2800_bbp_write(rt2x00dev, 84, 0x99);
3948         rt2800_bbp_write(rt2x00dev, 86, 0x00);
3949         rt2800_bbp_write(rt2x00dev, 91, 0x04);
3950         rt2800_bbp_write(rt2x00dev, 92, 0x00);
3951         rt2800_bbp_write(rt2x00dev, 103, 0x00);
3952         rt2800_bbp_write(rt2x00dev, 105, 0x05);
3953         rt2800_bbp_write(rt2x00dev, 106, 0x35);
3954 }
3955
3956 static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev)
3957 {
3958         int ant, div_mode;
3959         u16 eeprom;
3960         u8 value;
3961
3962         rt2800_init_bbp_early(rt2x00dev);
3963
3964         rt2800_bbp_read(rt2x00dev, 105, &value);
3965         rt2x00_set_field8(&value, BBP105_MLD,
3966                           rt2x00dev->default_ant.rx_chain_num == 2);
3967         rt2800_bbp_write(rt2x00dev, 105, value);
3968
3969         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
3970
3971         rt2800_bbp_write(rt2x00dev, 20, 0x06);
3972         rt2800_bbp_write(rt2x00dev, 31, 0x08);
3973         rt2800_bbp_write(rt2x00dev, 65, 0x2C);
3974         rt2800_bbp_write(rt2x00dev, 68, 0xDD);
3975         rt2800_bbp_write(rt2x00dev, 69, 0x1A);
3976         rt2800_bbp_write(rt2x00dev, 70, 0x05);
3977         rt2800_bbp_write(rt2x00dev, 73, 0x13);
3978         rt2800_bbp_write(rt2x00dev, 74, 0x0F);
3979         rt2800_bbp_write(rt2x00dev, 75, 0x4F);
3980         rt2800_bbp_write(rt2x00dev, 76, 0x28);
3981         rt2800_bbp_write(rt2x00dev, 77, 0x59);
3982         rt2800_bbp_write(rt2x00dev, 84, 0x9A);
3983         rt2800_bbp_write(rt2x00dev, 86, 0x38);
3984         rt2800_bbp_write(rt2x00dev, 88, 0x90);
3985         rt2800_bbp_write(rt2x00dev, 91, 0x04);
3986         rt2800_bbp_write(rt2x00dev, 92, 0x02);
3987         rt2800_bbp_write(rt2x00dev, 95, 0x9a);
3988         rt2800_bbp_write(rt2x00dev, 98, 0x12);
3989         rt2800_bbp_write(rt2x00dev, 103, 0xC0);
3990         rt2800_bbp_write(rt2x00dev, 104, 0x92);
3991         /* FIXME BBP105 owerwrite */
3992         rt2800_bbp_write(rt2x00dev, 105, 0x3C);
3993         rt2800_bbp_write(rt2x00dev, 106, 0x35);
3994         rt2800_bbp_write(rt2x00dev, 128, 0x12);
3995         rt2800_bbp_write(rt2x00dev, 134, 0xD0);
3996         rt2800_bbp_write(rt2x00dev, 135, 0xF6);
3997         rt2800_bbp_write(rt2x00dev, 137, 0x0F);
3998
3999         /* Initialize GLRT (Generalized Likehood Radio Test) */
4000         rt2800_init_bbp_5592_glrt(rt2x00dev);
4001
4002         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
4003
4004         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
4005         div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY);
4006         ant = (div_mode == 3) ? 1 : 0;
4007         rt2800_bbp_read(rt2x00dev, 152, &value);
4008         if (ant == 0) {
4009                 /* Main antenna */
4010                 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
4011         } else {
4012                 /* Auxiliary antenna */
4013                 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
4014         }
4015         rt2800_bbp_write(rt2x00dev, 152, value);
4016
4017         if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) {
4018                 rt2800_bbp_read(rt2x00dev, 254, &value);
4019                 rt2x00_set_field8(&value, BBP254_BIT7, 1);
4020                 rt2800_bbp_write(rt2x00dev, 254, value);
4021         }
4022
4023         rt2800_init_freq_calibration(rt2x00dev);
4024
4025         rt2800_bbp_write(rt2x00dev, 84, 0x19);
4026         if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
4027                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
4028 }
4029
4030 static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
4031 {
4032         unsigned int i;
4033         u16 eeprom;
4034         u8 reg_id;
4035         u8 value;
4036
4037         if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
4038                      rt2800_wait_bbp_ready(rt2x00dev)))
4039                 return -EACCES;
4040
4041         if (rt2x00_rt(rt2x00dev, RT5592)) {
4042                 rt2800_init_bbp_5592(rt2x00dev);
4043                 return 0;
4044         }
4045
4046         if (rt2x00_rt(rt2x00dev, RT3352)) {
4047                 rt2800_bbp_write(rt2x00dev, 3, 0x00);
4048                 rt2800_bbp_write(rt2x00dev, 4, 0x50);
4049         }
4050
4051         if (rt2x00_rt(rt2x00dev, RT3290) ||
4052             rt2x00_rt(rt2x00dev, RT5390) ||
4053             rt2x00_rt(rt2x00dev, RT5392))
4054                 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
4055
4056         if (rt2800_is_305x_soc(rt2x00dev) ||
4057             rt2x00_rt(rt2x00dev, RT3290) ||
4058             rt2x00_rt(rt2x00dev, RT3352) ||
4059             rt2x00_rt(rt2x00dev, RT3572) ||
4060             rt2x00_rt(rt2x00dev, RT5390) ||
4061             rt2x00_rt(rt2x00dev, RT5392))
4062                 rt2800_bbp_write(rt2x00dev, 31, 0x08);
4063
4064         if (rt2x00_rt(rt2x00dev, RT3352))
4065                 rt2800_bbp_write(rt2x00dev, 47, 0x48);
4066
4067         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
4068         rt2800_bbp_write(rt2x00dev, 66, 0x38);
4069
4070         if (rt2x00_rt(rt2x00dev, RT3290) ||
4071             rt2x00_rt(rt2x00dev, RT3352) ||
4072             rt2x00_rt(rt2x00dev, RT5390) ||
4073             rt2x00_rt(rt2x00dev, RT5392))
4074                 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
4075
4076         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
4077                 rt2800_bbp_write(rt2x00dev, 69, 0x16);
4078                 rt2800_bbp_write(rt2x00dev, 73, 0x12);
4079         } else if (rt2x00_rt(rt2x00dev, RT3290) ||
4080                    rt2x00_rt(rt2x00dev, RT3352) ||
4081                    rt2x00_rt(rt2x00dev, RT5390) ||
4082                    rt2x00_rt(rt2x00dev, RT5392)) {
4083                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
4084                 rt2800_bbp_write(rt2x00dev, 73, 0x13);
4085                 rt2800_bbp_write(rt2x00dev, 75, 0x46);
4086                 rt2800_bbp_write(rt2x00dev, 76, 0x28);
4087
4088                 if (rt2x00_rt(rt2x00dev, RT3290))
4089                         rt2800_bbp_write(rt2x00dev, 77, 0x58);
4090                 else
4091                         rt2800_bbp_write(rt2x00dev, 77, 0x59);
4092         } else {
4093                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
4094                 rt2800_bbp_write(rt2x00dev, 73, 0x10);
4095         }
4096
4097         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
4098
4099         if (rt2x00_rt(rt2x00dev, RT3070) ||
4100             rt2x00_rt(rt2x00dev, RT3071) ||
4101             rt2x00_rt(rt2x00dev, RT3090) ||
4102             rt2x00_rt(rt2x00dev, RT3390) ||
4103             rt2x00_rt(rt2x00dev, RT3572) ||
4104             rt2x00_rt(rt2x00dev, RT5390) ||
4105             rt2x00_rt(rt2x00dev, RT5392)) {
4106                 rt2800_bbp_write(rt2x00dev, 79, 0x13);
4107                 rt2800_bbp_write(rt2x00dev, 80, 0x05);
4108                 rt2800_bbp_write(rt2x00dev, 81, 0x33);
4109         } else if (rt2800_is_305x_soc(rt2x00dev)) {
4110                 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
4111                 rt2800_bbp_write(rt2x00dev, 80, 0x08);
4112         } else if (rt2x00_rt(rt2x00dev, RT3290)) {
4113                 rt2800_bbp_write(rt2x00dev, 74, 0x0b);
4114                 rt2800_bbp_write(rt2x00dev, 79, 0x18);
4115                 rt2800_bbp_write(rt2x00dev, 80, 0x09);
4116                 rt2800_bbp_write(rt2x00dev, 81, 0x33);
4117         } else if (rt2x00_rt(rt2x00dev, RT3352)) {
4118                 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
4119                 rt2800_bbp_write(rt2x00dev, 80, 0x08);
4120                 rt2800_bbp_write(rt2x00dev, 81, 0x37);
4121         } else {
4122                 rt2800_bbp_write(rt2x00dev, 81, 0x37);
4123         }
4124
4125         rt2800_bbp_write(rt2x00dev, 82, 0x62);
4126         if (rt2x00_rt(rt2x00dev, RT3290) ||
4127             rt2x00_rt(rt2x00dev, RT5390) ||
4128             rt2x00_rt(rt2x00dev, RT5392))
4129                 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
4130         else
4131                 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
4132
4133         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
4134                 rt2800_bbp_write(rt2x00dev, 84, 0x19);
4135         else if (rt2x00_rt(rt2x00dev, RT3290) ||
4136                  rt2x00_rt(rt2x00dev, RT5390) ||
4137                  rt2x00_rt(rt2x00dev, RT5392))
4138                 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
4139         else
4140                 rt2800_bbp_write(rt2x00dev, 84, 0x99);
4141
4142         if (rt2x00_rt(rt2x00dev, RT3290) ||
4143             rt2x00_rt(rt2x00dev, RT3352) ||
4144             rt2x00_rt(rt2x00dev, RT5390) ||
4145             rt2x00_rt(rt2x00dev, RT5392))
4146                 rt2800_bbp_write(rt2x00dev, 86, 0x38);
4147         else
4148                 rt2800_bbp_write(rt2x00dev, 86, 0x00);
4149
4150         if (rt2x00_rt(rt2x00dev, RT3352) ||
4151             rt2x00_rt(rt2x00dev, RT5392))
4152                 rt2800_bbp_write(rt2x00dev, 88, 0x90);
4153
4154         rt2800_bbp_write(rt2x00dev, 91, 0x04);
4155
4156         if (rt2x00_rt(rt2x00dev, RT3290) ||
4157             rt2x00_rt(rt2x00dev, RT3352) ||
4158             rt2x00_rt(rt2x00dev, RT5390) ||
4159             rt2x00_rt(rt2x00dev, RT5392))
4160                 rt2800_bbp_write(rt2x00dev, 92, 0x02);
4161         else
4162                 rt2800_bbp_write(rt2x00dev, 92, 0x00);
4163
4164         if (rt2x00_rt(rt2x00dev, RT5392)) {
4165                 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
4166                 rt2800_bbp_write(rt2x00dev, 98, 0x12);
4167         }
4168
4169         if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
4170             rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
4171             rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
4172             rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
4173             rt2x00_rt(rt2x00dev, RT3290) ||
4174             rt2x00_rt(rt2x00dev, RT3352) ||
4175             rt2x00_rt(rt2x00dev, RT3572) ||
4176             rt2x00_rt(rt2x00dev, RT5390) ||
4177             rt2x00_rt(rt2x00dev, RT5392) ||
4178             rt2800_is_305x_soc(rt2x00dev))
4179                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
4180         else
4181                 rt2800_bbp_write(rt2x00dev, 103, 0x00);
4182
4183         if (rt2x00_rt(rt2x00dev, RT3290) ||
4184             rt2x00_rt(rt2x00dev, RT3352) ||
4185             rt2x00_rt(rt2x00dev, RT5390) ||
4186             rt2x00_rt(rt2x00dev, RT5392))
4187                 rt2800_bbp_write(rt2x00dev, 104, 0x92);
4188
4189         if (rt2800_is_305x_soc(rt2x00dev))
4190                 rt2800_bbp_write(rt2x00dev, 105, 0x01);
4191         else if (rt2x00_rt(rt2x00dev, RT3290))
4192                 rt2800_bbp_write(rt2x00dev, 105, 0x1c);
4193         else if (rt2x00_rt(rt2x00dev, RT3352))
4194                 rt2800_bbp_write(rt2x00dev, 105, 0x34);
4195         else if (rt2x00_rt(rt2x00dev, RT5390) ||
4196                  rt2x00_rt(rt2x00dev, RT5392))
4197                 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
4198         else
4199                 rt2800_bbp_write(rt2x00dev, 105, 0x05);
4200
4201         if (rt2x00_rt(rt2x00dev, RT3290) ||
4202             rt2x00_rt(rt2x00dev, RT5390))
4203                 rt2800_bbp_write(rt2x00dev, 106, 0x03);
4204         else if (rt2x00_rt(rt2x00dev, RT3352))
4205                 rt2800_bbp_write(rt2x00dev, 106, 0x05);
4206         else if (rt2x00_rt(rt2x00dev, RT5392))
4207                 rt2800_bbp_write(rt2x00dev, 106, 0x12);
4208         else
4209                 rt2800_bbp_write(rt2x00dev, 106, 0x35);
4210
4211         if (rt2x00_rt(rt2x00dev, RT3352))
4212                 rt2800_bbp_write(rt2x00dev, 120, 0x50);
4213
4214         if (rt2x00_rt(rt2x00dev, RT3290) ||
4215             rt2x00_rt(rt2x00dev, RT5390) ||
4216             rt2x00_rt(rt2x00dev, RT5392))
4217                 rt2800_bbp_write(rt2x00dev, 128, 0x12);
4218
4219         if (rt2x00_rt(rt2x00dev, RT5392)) {
4220                 rt2800_bbp_write(rt2x00dev, 134, 0xd0);
4221                 rt2800_bbp_write(rt2x00dev, 135, 0xf6);
4222         }
4223
4224         if (rt2x00_rt(rt2x00dev, RT3352))
4225                 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
4226
4227         if (rt2x00_rt(rt2x00dev, RT3071) ||
4228             rt2x00_rt(rt2x00dev, RT3090) ||
4229             rt2x00_rt(rt2x00dev, RT3390) ||
4230             rt2x00_rt(rt2x00dev, RT3572) ||
4231             rt2x00_rt(rt2x00dev, RT5390) ||
4232             rt2x00_rt(rt2x00dev, RT5392)) {
4233                 rt2800_bbp_read(rt2x00dev, 138, &value);
4234
4235                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4236                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
4237                         value |= 0x20;
4238                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
4239                         value &= ~0x02;
4240
4241                 rt2800_bbp_write(rt2x00dev, 138, value);
4242         }
4243
4244         if (rt2x00_rt(rt2x00dev, RT3290)) {
4245                 rt2800_bbp_write(rt2x00dev, 67, 0x24);
4246                 rt2800_bbp_write(rt2x00dev, 143, 0x04);
4247                 rt2800_bbp_write(rt2x00dev, 142, 0x99);
4248                 rt2800_bbp_write(rt2x00dev, 150, 0x30);
4249                 rt2800_bbp_write(rt2x00dev, 151, 0x2e);
4250                 rt2800_bbp_write(rt2x00dev, 152, 0x20);
4251                 rt2800_bbp_write(rt2x00dev, 153, 0x34);
4252                 rt2800_bbp_write(rt2x00dev, 154, 0x40);
4253                 rt2800_bbp_write(rt2x00dev, 155, 0x3b);
4254                 rt2800_bbp_write(rt2x00dev, 253, 0x04);
4255
4256                 rt2800_bbp_read(rt2x00dev, 47, &value);
4257                 rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1);
4258                 rt2800_bbp_write(rt2x00dev, 47, value);
4259
4260                 /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */
4261                 rt2800_bbp_read(rt2x00dev, 3, &value);
4262                 rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1);
4263                 rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1);
4264                 rt2800_bbp_write(rt2x00dev, 3, value);
4265         }
4266
4267         if (rt2x00_rt(rt2x00dev, RT3352)) {
4268                 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
4269                 /* Set ITxBF timeout to 0x9c40=1000msec */
4270                 rt2800_bbp_write(rt2x00dev, 179, 0x02);
4271                 rt2800_bbp_write(rt2x00dev, 180, 0x00);
4272                 rt2800_bbp_write(rt2x00dev, 182, 0x40);
4273                 rt2800_bbp_write(rt2x00dev, 180, 0x01);
4274                 rt2800_bbp_write(rt2x00dev, 182, 0x9c);
4275                 rt2800_bbp_write(rt2x00dev, 179, 0x00);
4276                 /* Reprogram the inband interface to put right values in RXWI */
4277                 rt2800_bbp_write(rt2x00dev, 142, 0x04);
4278                 rt2800_bbp_write(rt2x00dev, 143, 0x3b);
4279                 rt2800_bbp_write(rt2x00dev, 142, 0x06);
4280                 rt2800_bbp_write(rt2x00dev, 143, 0xa0);
4281                 rt2800_bbp_write(rt2x00dev, 142, 0x07);
4282                 rt2800_bbp_write(rt2x00dev, 143, 0xa1);
4283                 rt2800_bbp_write(rt2x00dev, 142, 0x08);
4284                 rt2800_bbp_write(rt2x00dev, 143, 0xa2);
4285
4286                 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
4287         }
4288
4289         if (rt2x00_rt(rt2x00dev, RT5390) ||
4290             rt2x00_rt(rt2x00dev, RT5392)) {
4291                 int ant, div_mode;
4292
4293                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
4294                 div_mode = rt2x00_get_field16(eeprom,
4295                                               EEPROM_NIC_CONF1_ANT_DIVERSITY);
4296                 ant = (div_mode == 3) ? 1 : 0;
4297
4298                 /* check if this is a Bluetooth combo card */
4299                 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
4300                         u32 reg;
4301
4302                         rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
4303                         rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
4304                         rt2x00_set_field32(&reg, GPIO_CTRL_DIR6, 0);
4305                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 0);
4306                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 0);
4307                         if (ant == 0)
4308                                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 1);
4309                         else if (ant == 1)
4310                                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 1);
4311                         rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
4312                 }
4313
4314                 /* This chip has hardware antenna diversity*/
4315                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
4316                         rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */
4317                         rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */
4318                         rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */
4319                 }
4320
4321                 rt2800_bbp_read(rt2x00dev, 152, &value);
4322                 if (ant == 0)
4323                         rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
4324                 else
4325                         rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
4326                 rt2800_bbp_write(rt2x00dev, 152, value);
4327
4328                 rt2800_init_freq_calibration(rt2x00dev);
4329         }
4330
4331         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
4332                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
4333
4334                 if (eeprom != 0xffff && eeprom != 0x0000) {
4335                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
4336                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
4337                         rt2800_bbp_write(rt2x00dev, reg_id, value);
4338                 }
4339         }
4340
4341         return 0;
4342 }
4343
4344 static void rt2800_led_open_drain_enable(struct rt2x00_dev *rt2x00dev)
4345 {
4346         u32 reg;
4347
4348         rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
4349         rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
4350         rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
4351 }
4352
4353 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, bool bw40,
4354                                 u8 filter_target)
4355 {
4356         unsigned int i;
4357         u8 bbp;
4358         u8 rfcsr;
4359         u8 passband;
4360         u8 stopband;
4361         u8 overtuned = 0;
4362         u8 rfcsr24 = (bw40) ? 0x27 : 0x07;
4363
4364         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
4365
4366         rt2800_bbp_read(rt2x00dev, 4, &bbp);
4367         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
4368         rt2800_bbp_write(rt2x00dev, 4, bbp);
4369
4370         rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
4371         rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
4372         rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
4373
4374         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
4375         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
4376         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
4377
4378         /*
4379          * Set power & frequency of passband test tone
4380          */
4381         rt2800_bbp_write(rt2x00dev, 24, 0);
4382
4383         for (i = 0; i < 100; i++) {
4384                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
4385                 msleep(1);
4386
4387                 rt2800_bbp_read(rt2x00dev, 55, &passband);
4388                 if (passband)
4389                         break;
4390         }
4391
4392         /*
4393          * Set power & frequency of stopband test tone
4394          */
4395         rt2800_bbp_write(rt2x00dev, 24, 0x06);
4396
4397         for (i = 0; i < 100; i++) {
4398                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
4399                 msleep(1);
4400
4401                 rt2800_bbp_read(rt2x00dev, 55, &stopband);
4402
4403                 if ((passband - stopband) <= filter_target) {
4404                         rfcsr24++;
4405                         overtuned += ((passband - stopband) == filter_target);
4406                 } else
4407                         break;
4408
4409                 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
4410         }
4411
4412         rfcsr24 -= !!overtuned;
4413
4414         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
4415         return rfcsr24;
4416 }
4417
4418 static void rt2800_rf_init_calibration(struct rt2x00_dev *rt2x00dev,
4419                                        const unsigned int rf_reg)
4420 {
4421         u8 rfcsr;
4422
4423         rt2800_rfcsr_read(rt2x00dev, rf_reg, &rfcsr);
4424         rt2x00_set_field8(&rfcsr, FIELD8(0x80), 1);
4425         rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
4426         msleep(1);
4427         rt2x00_set_field8(&rfcsr, FIELD8(0x80), 0);
4428         rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
4429 }
4430
4431 static void rt2800_rx_filter_calibration(struct rt2x00_dev *rt2x00dev)
4432 {
4433         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
4434         u8 filter_tgt_bw20;
4435         u8 filter_tgt_bw40;
4436         u8 rfcsr, bbp;
4437
4438         /*
4439          * TODO: sync filter_tgt values with vendor driver
4440          */
4441         if (rt2x00_rt(rt2x00dev, RT3070)) {
4442                 filter_tgt_bw20 = 0x16;
4443                 filter_tgt_bw40 = 0x19;
4444         } else {
4445                 filter_tgt_bw20 = 0x13;
4446                 filter_tgt_bw40 = 0x15;
4447         }
4448
4449         drv_data->calibration_bw20 =
4450                 rt2800_init_rx_filter(rt2x00dev, false, filter_tgt_bw20);
4451         drv_data->calibration_bw40 =
4452                 rt2800_init_rx_filter(rt2x00dev, true, filter_tgt_bw40);
4453
4454         /*
4455          * Save BBP 25 & 26 values for later use in channel switching (for 3052)
4456          */
4457         rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
4458         rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
4459
4460         /*
4461          * Set back to initial state
4462          */
4463         rt2800_bbp_write(rt2x00dev, 24, 0);
4464
4465         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
4466         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
4467         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
4468
4469         /*
4470          * Set BBP back to BW20
4471          */
4472         rt2800_bbp_read(rt2x00dev, 4, &bbp);
4473         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
4474         rt2800_bbp_write(rt2x00dev, 4, bbp);
4475 }
4476
4477 static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev)
4478 {
4479         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
4480         u8 min_gain, rfcsr, bbp;
4481         u16 eeprom;
4482
4483         rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
4484
4485         rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
4486         if (rt2x00_rt(rt2x00dev, RT3070) ||
4487             rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4488             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
4489             rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
4490                 if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags))
4491                         rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
4492         }
4493
4494         min_gain = rt2x00_rt(rt2x00dev, RT3070) ? 1 : 2;
4495         if (drv_data->txmixer_gain_24g >= min_gain) {
4496                 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
4497                                   drv_data->txmixer_gain_24g);
4498         }
4499
4500         rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
4501
4502         if (rt2x00_rt(rt2x00dev, RT3090)) {
4503                 /*  Turn off unused DAC1 and ADC1 to reduce power consumption */
4504                 rt2800_bbp_read(rt2x00dev, 138, &bbp);
4505                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4506                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
4507                         rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
4508                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
4509                         rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
4510                 rt2800_bbp_write(rt2x00dev, 138, bbp);
4511         }
4512
4513         if (rt2x00_rt(rt2x00dev, RT3070)) {
4514                 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
4515                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
4516                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
4517                 else
4518                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
4519                 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
4520                 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
4521                 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
4522                 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
4523         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
4524                    rt2x00_rt(rt2x00dev, RT3090) ||
4525                    rt2x00_rt(rt2x00dev, RT3390)) {
4526                 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
4527                 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
4528                 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
4529                 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
4530                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
4531                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
4532                 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
4533
4534                 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
4535                 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
4536                 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
4537
4538                 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
4539                 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
4540                 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
4541
4542                 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
4543                 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
4544                 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
4545         }
4546 }
4547
4548 static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev *rt2x00dev)
4549 {
4550         u8 reg;
4551         u16 eeprom;
4552
4553         /*  Turn off unused DAC1 and ADC1 to reduce power consumption */
4554         rt2800_bbp_read(rt2x00dev, 138, &reg);
4555         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4556         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
4557                 rt2x00_set_field8(&reg, BBP138_RX_ADC1, 0);
4558         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
4559                 rt2x00_set_field8(&reg, BBP138_TX_DAC1, 1);
4560         rt2800_bbp_write(rt2x00dev, 138, reg);
4561
4562         rt2800_rfcsr_read(rt2x00dev, 38, &reg);
4563         rt2x00_set_field8(&reg, RFCSR38_RX_LO1_EN, 0);
4564         rt2800_rfcsr_write(rt2x00dev, 38, reg);
4565
4566         rt2800_rfcsr_read(rt2x00dev, 39, &reg);
4567         rt2x00_set_field8(&reg, RFCSR39_RX_LO2_EN, 0);
4568         rt2800_rfcsr_write(rt2x00dev, 39, reg);
4569
4570         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
4571
4572         rt2800_rfcsr_read(rt2x00dev, 30, &reg);
4573         rt2x00_set_field8(&reg, RFCSR30_RX_VCM, 2);
4574         rt2800_rfcsr_write(rt2x00dev, 30, reg);
4575 }
4576
4577 static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev)
4578 {
4579         rt2800_rf_init_calibration(rt2x00dev, 30);
4580
4581         rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
4582         rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
4583         rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
4584         rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
4585         rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
4586         rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
4587         rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
4588         rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
4589         rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
4590         rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
4591         rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
4592         rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
4593         rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
4594         rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
4595         rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
4596         rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
4597         rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
4598         rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
4599         rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
4600         rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
4601         rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
4602         rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
4603         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
4604         rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
4605         rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
4606         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
4607         rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
4608         rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
4609         rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
4610         rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
4611         rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
4612         rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
4613 }
4614
4615 static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev)
4616 {
4617         u8 rfcsr;
4618         u16 eeprom;
4619         u32 reg;
4620
4621         /* XXX vendor driver do this only for 3070 */
4622         rt2800_rf_init_calibration(rt2x00dev, 30);
4623
4624         rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
4625         rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
4626         rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
4627         rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
4628         rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
4629         rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
4630         rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
4631         rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
4632         rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
4633         rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
4634         rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
4635         rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
4636         rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
4637         rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
4638         rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
4639         rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
4640         rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
4641         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
4642         rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
4643
4644         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
4645                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4646                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4647                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
4648                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4649         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
4650                    rt2x00_rt(rt2x00dev, RT3090)) {
4651                 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
4652
4653                 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
4654                 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
4655                 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
4656
4657                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4658                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4659                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4660                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
4661                         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
4662                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
4663                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
4664                         else
4665                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
4666                 }
4667                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4668
4669                 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
4670                 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
4671                 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
4672         }
4673
4674         rt2800_rx_filter_calibration(rt2x00dev);
4675
4676         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
4677             rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4678             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E))
4679                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
4680
4681         rt2800_led_open_drain_enable(rt2x00dev);
4682         rt2800_normal_mode_setup_3xxx(rt2x00dev);
4683 }
4684
4685 static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev)
4686 {
4687         u8 rfcsr;
4688
4689         rt2800_rf_init_calibration(rt2x00dev, 2);
4690
4691         rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
4692         rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
4693         rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
4694         rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
4695         rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
4696         rt2800_rfcsr_write(rt2x00dev, 8, 0xf3);
4697         rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
4698         rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
4699         rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
4700         rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
4701         rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
4702         rt2800_rfcsr_write(rt2x00dev, 18, 0x02);
4703         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
4704         rt2800_rfcsr_write(rt2x00dev, 25, 0x83);
4705         rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
4706         rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
4707         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
4708         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
4709         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
4710         rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
4711         rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
4712         rt2800_rfcsr_write(rt2x00dev, 34, 0x05);
4713         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
4714         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
4715         rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
4716         rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
4717         rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
4718         rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
4719         rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
4720         rt2800_rfcsr_write(rt2x00dev, 43, 0x7b);
4721         rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
4722         rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
4723         rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
4724         rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
4725         rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
4726         rt2800_rfcsr_write(rt2x00dev, 49, 0x98);
4727         rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
4728         rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
4729         rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
4730         rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
4731         rt2800_rfcsr_write(rt2x00dev, 56, 0x02);
4732         rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
4733         rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
4734         rt2800_rfcsr_write(rt2x00dev, 59, 0x09);
4735         rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
4736         rt2800_rfcsr_write(rt2x00dev, 61, 0xc1);
4737
4738         rt2800_rfcsr_read(rt2x00dev, 29, &rfcsr);
4739         rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3);
4740         rt2800_rfcsr_write(rt2x00dev, 29, rfcsr);
4741
4742         rt2800_led_open_drain_enable(rt2x00dev);
4743         rt2800_normal_mode_setup_3xxx(rt2x00dev);
4744 }
4745
4746 static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev)
4747 {
4748         rt2800_rf_init_calibration(rt2x00dev, 30);
4749
4750         rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
4751         rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
4752         rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
4753         rt2800_rfcsr_write(rt2x00dev, 3, 0x18);
4754         rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
4755         rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
4756         rt2800_rfcsr_write(rt2x00dev, 6, 0x33);
4757         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
4758         rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
4759         rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
4760         rt2800_rfcsr_write(rt2x00dev, 10, 0xd2);
4761         rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
4762         rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
4763         rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
4764         rt2800_rfcsr_write(rt2x00dev, 14, 0x5a);
4765         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
4766         rt2800_rfcsr_write(rt2x00dev, 16, 0x01);
4767         rt2800_rfcsr_write(rt2x00dev, 18, 0x45);
4768         rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
4769         rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
4770         rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
4771         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
4772         rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
4773         rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
4774         rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
4775         rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
4776         rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
4777         rt2800_rfcsr_write(rt2x00dev, 28, 0x03);
4778         rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
4779         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
4780         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
4781         rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
4782         rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
4783         rt2800_rfcsr_write(rt2x00dev, 34, 0x01);
4784         rt2800_rfcsr_write(rt2x00dev, 35, 0x03);
4785         rt2800_rfcsr_write(rt2x00dev, 36, 0xbd);
4786         rt2800_rfcsr_write(rt2x00dev, 37, 0x3c);
4787         rt2800_rfcsr_write(rt2x00dev, 38, 0x5f);
4788         rt2800_rfcsr_write(rt2x00dev, 39, 0xc5);
4789         rt2800_rfcsr_write(rt2x00dev, 40, 0x33);
4790         rt2800_rfcsr_write(rt2x00dev, 41, 0x5b);
4791         rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
4792         rt2800_rfcsr_write(rt2x00dev, 43, 0xdb);
4793         rt2800_rfcsr_write(rt2x00dev, 44, 0xdb);
4794         rt2800_rfcsr_write(rt2x00dev, 45, 0xdb);
4795         rt2800_rfcsr_write(rt2x00dev, 46, 0xdd);
4796         rt2800_rfcsr_write(rt2x00dev, 47, 0x0d);
4797         rt2800_rfcsr_write(rt2x00dev, 48, 0x14);
4798         rt2800_rfcsr_write(rt2x00dev, 49, 0x00);
4799         rt2800_rfcsr_write(rt2x00dev, 50, 0x2d);
4800         rt2800_rfcsr_write(rt2x00dev, 51, 0x7f);
4801         rt2800_rfcsr_write(rt2x00dev, 52, 0x00);
4802         rt2800_rfcsr_write(rt2x00dev, 53, 0x52);
4803         rt2800_rfcsr_write(rt2x00dev, 54, 0x1b);
4804         rt2800_rfcsr_write(rt2x00dev, 55, 0x7f);
4805         rt2800_rfcsr_write(rt2x00dev, 56, 0x00);
4806         rt2800_rfcsr_write(rt2x00dev, 57, 0x52);
4807         rt2800_rfcsr_write(rt2x00dev, 58, 0x1b);
4808         rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
4809         rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
4810         rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
4811         rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
4812         rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
4813
4814         rt2800_rx_filter_calibration(rt2x00dev);
4815         rt2800_led_open_drain_enable(rt2x00dev);
4816         rt2800_normal_mode_setup_3xxx(rt2x00dev);
4817 }
4818
4819 static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev)
4820 {
4821         u32 reg;
4822
4823         rt2800_rf_init_calibration(rt2x00dev, 30);
4824
4825         rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
4826         rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
4827         rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
4828         rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
4829         rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
4830         rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
4831         rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
4832         rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
4833         rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
4834         rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
4835         rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
4836         rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
4837         rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
4838         rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
4839         rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
4840         rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
4841         rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
4842         rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
4843         rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
4844         rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
4845         rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
4846         rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
4847         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
4848         rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
4849         rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
4850         rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
4851         rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
4852         rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
4853         rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
4854         rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
4855         rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
4856         rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
4857
4858         rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
4859         rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
4860         rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
4861
4862         rt2800_rx_filter_calibration(rt2x00dev);
4863
4864         if (rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
4865                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
4866
4867         rt2800_led_open_drain_enable(rt2x00dev);
4868         rt2800_normal_mode_setup_3xxx(rt2x00dev);
4869 }
4870
4871 static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev)
4872 {
4873         u8 rfcsr;
4874         u32 reg;
4875
4876         rt2800_rf_init_calibration(rt2x00dev, 30);
4877
4878         rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
4879         rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
4880         rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
4881         rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
4882         rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
4883         rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
4884         rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
4885         rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
4886         rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
4887         rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
4888         rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
4889         rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
4890         rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
4891         rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
4892         rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
4893         rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
4894         rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
4895         rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
4896         rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
4897         rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
4898         rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
4899         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
4900         rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
4901         rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
4902         rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
4903         rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
4904         rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
4905         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
4906         rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
4907         rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
4908         rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
4909
4910         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
4911         rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
4912         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
4913
4914         rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4915         rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
4916         rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4917         rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4918         msleep(1);
4919         rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4920         rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
4921         rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4922         rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4923
4924         rt2800_rx_filter_calibration(rt2x00dev);
4925         rt2800_led_open_drain_enable(rt2x00dev);
4926         rt2800_normal_mode_setup_3xxx(rt2x00dev);
4927 }
4928
4929 static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
4930 {
4931         rt2800_rf_init_calibration(rt2x00dev, 2);
4932
4933         rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
4934         rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
4935         rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
4936         rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
4937         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4938                 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
4939         else
4940                 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
4941         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
4942         rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
4943         rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
4944         rt2800_rfcsr_write(rt2x00dev, 12, 0xc6);
4945         rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
4946         rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
4947         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
4948         rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
4949         rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
4950         rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
4951
4952         rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
4953         rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
4954         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
4955         rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
4956         rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
4957         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4958                 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
4959         else
4960                 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
4961         rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
4962         rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
4963         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
4964         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
4965
4966         rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
4967         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
4968         rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
4969         rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
4970         rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
4971         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
4972         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
4973         rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
4974         rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
4975         rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
4976
4977         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4978                 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
4979         else
4980                 rt2800_rfcsr_write(rt2x00dev, 40, 0x4b);
4981         rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
4982         rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
4983         rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
4984         rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
4985         rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
4986         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4987                 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
4988         else
4989                 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
4990         rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
4991         rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
4992         rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
4993
4994         rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
4995         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4996                 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
4997         else
4998                 rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
4999         rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
5000         rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
5001         rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
5002         rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
5003         rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
5004         rt2800_rfcsr_write(rt2x00dev, 59, 0x63);
5005
5006         rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
5007         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
5008                 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
5009         else
5010                 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
5011         rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
5012         rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
5013
5014         rt2800_normal_mode_setup_5xxx(rt2x00dev);
5015
5016         rt2800_led_open_drain_enable(rt2x00dev);
5017 }
5018
5019 static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev)
5020 {
5021         rt2800_rf_init_calibration(rt2x00dev, 2);
5022
5023         rt2800_rfcsr_write(rt2x00dev, 1, 0x17);
5024         rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
5025         rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
5026         rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
5027         rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
5028         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
5029         rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
5030         rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
5031         rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
5032         rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
5033         rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
5034         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
5035         rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
5036         rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
5037         rt2800_rfcsr_write(rt2x00dev, 19, 0x4d);
5038         rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
5039         rt2800_rfcsr_write(rt2x00dev, 21, 0x8d);
5040         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
5041         rt2800_rfcsr_write(rt2x00dev, 23, 0x0b);
5042         rt2800_rfcsr_write(rt2x00dev, 24, 0x44);
5043         rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
5044         rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
5045         rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
5046         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
5047         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
5048         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
5049         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
5050         rt2800_rfcsr_write(rt2x00dev, 32, 0x20);
5051         rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
5052         rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
5053         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
5054         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
5055         rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
5056         rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
5057         rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
5058         rt2800_rfcsr_write(rt2x00dev, 40, 0x0f);
5059         rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
5060         rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
5061         rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
5062         rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
5063         rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
5064         rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
5065         rt2800_rfcsr_write(rt2x00dev, 47, 0x0c);
5066         rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
5067         rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
5068         rt2800_rfcsr_write(rt2x00dev, 50, 0x94);
5069         rt2800_rfcsr_write(rt2x00dev, 51, 0x3a);
5070         rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
5071         rt2800_rfcsr_write(rt2x00dev, 53, 0x44);
5072         rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
5073         rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
5074         rt2800_rfcsr_write(rt2x00dev, 56, 0xa1);
5075         rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
5076         rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
5077         rt2800_rfcsr_write(rt2x00dev, 59, 0x07);
5078         rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
5079         rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
5080         rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
5081         rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
5082
5083         rt2800_normal_mode_setup_5xxx(rt2x00dev);
5084
5085         rt2800_led_open_drain_enable(rt2x00dev);
5086 }
5087
5088 static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev)
5089 {
5090         rt2800_rf_init_calibration(rt2x00dev, 30);
5091
5092         rt2800_rfcsr_write(rt2x00dev, 1, 0x3F);
5093         rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
5094         rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
5095         rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
5096         rt2800_rfcsr_write(rt2x00dev, 6, 0xE4);
5097         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
5098         rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
5099         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
5100         rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
5101         rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
5102         rt2800_rfcsr_write(rt2x00dev, 19, 0x4D);
5103         rt2800_rfcsr_write(rt2x00dev, 20, 0x10);
5104         rt2800_rfcsr_write(rt2x00dev, 21, 0x8D);
5105         rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
5106         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
5107         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
5108         rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
5109         rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
5110         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
5111         rt2800_rfcsr_write(rt2x00dev, 47, 0x0C);
5112         rt2800_rfcsr_write(rt2x00dev, 53, 0x22);
5113         rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
5114
5115         rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
5116         msleep(1);
5117
5118         rt2800_adjust_freq_offset(rt2x00dev);
5119
5120         /* Enable DC filter */
5121         if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
5122                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5123
5124         rt2800_normal_mode_setup_5xxx(rt2x00dev);
5125
5126         if (rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C))
5127                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
5128
5129         rt2800_led_open_drain_enable(rt2x00dev);
5130 }
5131
5132 static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
5133 {
5134         if (rt2800_is_305x_soc(rt2x00dev)) {
5135                 rt2800_init_rfcsr_305x_soc(rt2x00dev);
5136                 return;
5137         }
5138
5139         switch (rt2x00dev->chip.rt) {
5140         case RT3070:
5141         case RT3071:
5142         case RT3090:
5143                 rt2800_init_rfcsr_30xx(rt2x00dev);
5144                 break;
5145         case RT3290:
5146                 rt2800_init_rfcsr_3290(rt2x00dev);
5147                 break;
5148         case RT3352:
5149                 rt2800_init_rfcsr_3352(rt2x00dev);
5150                 break;
5151         case RT3390:
5152                 rt2800_init_rfcsr_3390(rt2x00dev);
5153                 break;
5154         case RT3572:
5155                 rt2800_init_rfcsr_3572(rt2x00dev);
5156                 break;
5157         case RT5390:
5158                 rt2800_init_rfcsr_5390(rt2x00dev);
5159                 break;
5160         case RT5392:
5161                 rt2800_init_rfcsr_5392(rt2x00dev);
5162                 break;
5163         case RT5592:
5164                 rt2800_init_rfcsr_5592(rt2x00dev);
5165                 break;
5166         }
5167 }
5168
5169 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
5170 {
5171         u32 reg;
5172         u16 word;
5173
5174         /*
5175          * Initialize all registers.
5176          */
5177         if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
5178                      rt2800_init_registers(rt2x00dev)))
5179                 return -EIO;
5180
5181         /*
5182          * Send signal to firmware during boot time.
5183          */
5184         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
5185         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
5186         if (rt2x00_is_usb(rt2x00dev)) {
5187                 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
5188                 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
5189         }
5190         msleep(1);
5191
5192         if (unlikely(rt2800_init_bbp(rt2x00dev)))
5193                 return -EIO;
5194
5195         rt2800_init_rfcsr(rt2x00dev);
5196
5197         if (rt2x00_is_usb(rt2x00dev) &&
5198             (rt2x00_rt(rt2x00dev, RT3070) ||
5199              rt2x00_rt(rt2x00dev, RT3071) ||
5200              rt2x00_rt(rt2x00dev, RT3572))) {
5201                 udelay(200);
5202                 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
5203                 udelay(10);
5204         }
5205
5206         /*
5207          * Enable RX.
5208          */
5209         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
5210         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
5211         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
5212         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
5213
5214         udelay(50);
5215
5216         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
5217         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
5218         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
5219         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
5220         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
5221         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
5222
5223         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
5224         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
5225         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
5226         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
5227
5228         /*
5229          * Initialize LED control
5230          */
5231         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
5232         rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
5233                            word & 0xff, (word >> 8) & 0xff);
5234
5235         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
5236         rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
5237                            word & 0xff, (word >> 8) & 0xff);
5238
5239         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
5240         rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
5241                            word & 0xff, (word >> 8) & 0xff);
5242
5243         return 0;
5244 }
5245 EXPORT_SYMBOL_GPL(rt2800_enable_radio);
5246
5247 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
5248 {
5249         u32 reg;
5250
5251         rt2800_disable_wpdma(rt2x00dev);
5252
5253         /* Wait for DMA, ignore error */
5254         rt2800_wait_wpdma_ready(rt2x00dev);
5255
5256         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
5257         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
5258         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
5259         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
5260 }
5261 EXPORT_SYMBOL_GPL(rt2800_disable_radio);
5262
5263 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
5264 {
5265         u32 reg;
5266         u16 efuse_ctrl_reg;
5267
5268         if (rt2x00_rt(rt2x00dev, RT3290))
5269                 efuse_ctrl_reg = EFUSE_CTRL_3290;
5270         else
5271                 efuse_ctrl_reg = EFUSE_CTRL;
5272
5273         rt2800_register_read(rt2x00dev, efuse_ctrl_reg, &reg);
5274         return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
5275 }
5276 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
5277
5278 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
5279 {
5280         u32 reg;
5281         u16 efuse_ctrl_reg;
5282         u16 efuse_data0_reg;
5283         u16 efuse_data1_reg;
5284         u16 efuse_data2_reg;
5285         u16 efuse_data3_reg;
5286
5287         if (rt2x00_rt(rt2x00dev, RT3290)) {
5288                 efuse_ctrl_reg = EFUSE_CTRL_3290;
5289                 efuse_data0_reg = EFUSE_DATA0_3290;
5290                 efuse_data1_reg = EFUSE_DATA1_3290;
5291                 efuse_data2_reg = EFUSE_DATA2_3290;
5292                 efuse_data3_reg = EFUSE_DATA3_3290;
5293         } else {
5294                 efuse_ctrl_reg = EFUSE_CTRL;
5295                 efuse_data0_reg = EFUSE_DATA0;
5296                 efuse_data1_reg = EFUSE_DATA1;
5297                 efuse_data2_reg = EFUSE_DATA2;
5298                 efuse_data3_reg = EFUSE_DATA3;
5299         }
5300         mutex_lock(&rt2x00dev->csr_mutex);
5301
5302         rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg, &reg);
5303         rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
5304         rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
5305         rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
5306         rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg);
5307
5308         /* Wait until the EEPROM has been loaded */
5309         rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, &reg);
5310         /* Apparently the data is read from end to start */
5311         rt2800_register_read_lock(rt2x00dev, efuse_data3_reg, &reg);
5312         /* The returned value is in CPU order, but eeprom is le */
5313         *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
5314         rt2800_register_read_lock(rt2x00dev, efuse_data2_reg, &reg);
5315         *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
5316         rt2800_register_read_lock(rt2x00dev, efuse_data1_reg, &reg);
5317         *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
5318         rt2800_register_read_lock(rt2x00dev, efuse_data0_reg, &reg);
5319         *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
5320
5321         mutex_unlock(&rt2x00dev->csr_mutex);
5322 }
5323
5324 int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
5325 {
5326         unsigned int i;
5327
5328         for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
5329                 rt2800_efuse_read(rt2x00dev, i);
5330
5331         return 0;
5332 }
5333 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
5334
5335 static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
5336 {
5337         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5338         u16 word;
5339         u8 *mac;
5340         u8 default_lna_gain;
5341         int retval;
5342
5343         /*
5344          * Read the EEPROM.
5345          */
5346         retval = rt2800_read_eeprom(rt2x00dev);
5347         if (retval)
5348                 return retval;
5349
5350         /*
5351          * Start validation of the data that has been read.
5352          */
5353         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
5354         if (!is_valid_ether_addr(mac)) {
5355                 eth_random_addr(mac);
5356                 rt2x00_eeprom_dbg(rt2x00dev, "MAC: %pM\n", mac);
5357         }
5358
5359         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
5360         if (word == 0xffff) {
5361                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
5362                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
5363                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
5364                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
5365                 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word);
5366         } else if (rt2x00_rt(rt2x00dev, RT2860) ||
5367                    rt2x00_rt(rt2x00dev, RT2872)) {
5368                 /*
5369                  * There is a max of 2 RX streams for RT28x0 series
5370                  */
5371                 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
5372                         rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
5373                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
5374         }
5375
5376         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
5377         if (word == 0xffff) {
5378                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
5379                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
5380                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
5381                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
5382                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
5383                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
5384                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
5385                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
5386                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
5387                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
5388                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
5389                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
5390                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
5391                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
5392                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
5393                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
5394                 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word);
5395         }
5396
5397         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
5398         if ((word & 0x00ff) == 0x00ff) {
5399                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
5400                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
5401                 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word);
5402         }
5403         if ((word & 0xff00) == 0xff00) {
5404                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
5405                                    LED_MODE_TXRX_ACTIVITY);
5406                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
5407                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
5408                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
5409                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
5410                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
5411                 rt2x00_eeprom_dbg(rt2x00dev, "Led Mode: 0x%04x\n", word);
5412         }
5413
5414         /*
5415          * During the LNA validation we are going to use
5416          * lna0 as correct value. Note that EEPROM_LNA
5417          * is never validated.
5418          */
5419         rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
5420         default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
5421
5422         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
5423         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
5424                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
5425         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
5426                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
5427         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
5428
5429         rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &word);
5430         if ((word & 0x00ff) != 0x00ff) {
5431                 drv_data->txmixer_gain_24g =
5432                         rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL);
5433         } else {
5434                 drv_data->txmixer_gain_24g = 0;
5435         }
5436
5437         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
5438         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
5439                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
5440         if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
5441             rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
5442                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
5443                                    default_lna_gain);
5444         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
5445
5446         rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A, &word);
5447         if ((word & 0x00ff) != 0x00ff) {
5448                 drv_data->txmixer_gain_5g =
5449                         rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL);
5450         } else {
5451                 drv_data->txmixer_gain_5g = 0;
5452         }
5453
5454         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
5455         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
5456                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
5457         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
5458                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
5459         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
5460
5461         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
5462         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
5463                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
5464         if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
5465             rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
5466                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
5467                                    default_lna_gain);
5468         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
5469
5470         return 0;
5471 }
5472
5473 static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
5474 {
5475         u16 value;
5476         u16 eeprom;
5477         u16 rf;
5478
5479         /*
5480          * Read EEPROM word for configuration.
5481          */
5482         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5483
5484         /*
5485          * Identify RF chipset by EEPROM value
5486          * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
5487          * RT53xx: defined in "EEPROM_CHIP_ID" field
5488          */
5489         if (rt2x00_rt(rt2x00dev, RT3290) ||
5490             rt2x00_rt(rt2x00dev, RT5390) ||
5491             rt2x00_rt(rt2x00dev, RT5392))
5492                 rt2x00_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &rf);
5493         else
5494                 rf = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
5495
5496         switch (rf) {
5497         case RF2820:
5498         case RF2850:
5499         case RF2720:
5500         case RF2750:
5501         case RF3020:
5502         case RF2020:
5503         case RF3021:
5504         case RF3022:
5505         case RF3052:
5506         case RF3290:
5507         case RF3320:
5508         case RF3322:
5509         case RF5360:
5510         case RF5370:
5511         case RF5372:
5512         case RF5390:
5513         case RF5392:
5514         case RF5592:
5515                 break;
5516         default:
5517                 rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n",
5518                            rf);
5519                 return -ENODEV;
5520         }
5521
5522         rt2x00_set_rf(rt2x00dev, rf);
5523
5524         /*
5525          * Identify default antenna configuration.
5526          */
5527         rt2x00dev->default_ant.tx_chain_num =
5528             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
5529         rt2x00dev->default_ant.rx_chain_num =
5530             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
5531
5532         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
5533
5534         if (rt2x00_rt(rt2x00dev, RT3070) ||
5535             rt2x00_rt(rt2x00dev, RT3090) ||
5536             rt2x00_rt(rt2x00dev, RT3352) ||
5537             rt2x00_rt(rt2x00dev, RT3390)) {
5538                 value = rt2x00_get_field16(eeprom,
5539                                 EEPROM_NIC_CONF1_ANT_DIVERSITY);
5540                 switch (value) {
5541                 case 0:
5542                 case 1:
5543                 case 2:
5544                         rt2x00dev->default_ant.tx = ANTENNA_A;
5545                         rt2x00dev->default_ant.rx = ANTENNA_A;
5546                         break;
5547                 case 3:
5548                         rt2x00dev->default_ant.tx = ANTENNA_A;
5549                         rt2x00dev->default_ant.rx = ANTENNA_B;
5550                         break;
5551                 }
5552         } else {
5553                 rt2x00dev->default_ant.tx = ANTENNA_A;
5554                 rt2x00dev->default_ant.rx = ANTENNA_A;
5555         }
5556
5557         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
5558                 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */
5559                 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */
5560         }
5561
5562         /*
5563          * Determine external LNA informations.
5564          */
5565         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
5566                 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
5567         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
5568                 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
5569
5570         /*
5571          * Detect if this device has an hardware controlled radio.
5572          */
5573         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
5574                 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
5575
5576         /*
5577          * Detect if this device has Bluetooth co-existence.
5578          */
5579         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
5580                 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
5581
5582         /*
5583          * Read frequency offset and RF programming sequence.
5584          */
5585         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
5586         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
5587
5588         /*
5589          * Store led settings, for correct led behaviour.
5590          */
5591 #ifdef CONFIG_RT2X00_LIB_LEDS
5592         rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
5593         rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
5594         rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
5595
5596         rt2x00dev->led_mcu_reg = eeprom;
5597 #endif /* CONFIG_RT2X00_LIB_LEDS */
5598
5599         /*
5600          * Check if support EIRP tx power limit feature.
5601          */
5602         rt2x00_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
5603
5604         if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
5605                                         EIRP_MAX_TX_POWER_LIMIT)
5606                 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
5607
5608         return 0;
5609 }
5610
5611 /*
5612  * RF value list for rt28xx
5613  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
5614  */
5615 static const struct rf_channel rf_vals[] = {
5616         { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
5617         { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
5618         { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
5619         { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
5620         { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
5621         { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
5622         { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
5623         { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
5624         { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
5625         { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
5626         { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
5627         { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
5628         { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
5629         { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
5630
5631         /* 802.11 UNI / HyperLan 2 */
5632         { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
5633         { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
5634         { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
5635         { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
5636         { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
5637         { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
5638         { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
5639         { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
5640         { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
5641         { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
5642         { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
5643         { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
5644
5645         /* 802.11 HyperLan 2 */
5646         { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
5647         { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
5648         { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
5649         { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
5650         { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
5651         { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
5652         { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
5653         { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
5654         { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
5655         { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
5656         { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
5657         { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
5658         { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
5659         { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
5660         { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
5661         { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
5662
5663         /* 802.11 UNII */
5664         { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
5665         { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
5666         { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
5667         { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
5668         { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
5669         { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
5670         { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
5671         { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
5672         { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
5673         { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
5674         { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
5675
5676         /* 802.11 Japan */
5677         { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
5678         { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
5679         { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
5680         { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
5681         { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
5682         { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
5683         { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
5684 };
5685
5686 /*
5687  * RF value list for rt3xxx
5688  * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
5689  */
5690 static const struct rf_channel rf_vals_3x[] = {
5691         {1,  241, 2, 2 },
5692         {2,  241, 2, 7 },
5693         {3,  242, 2, 2 },
5694         {4,  242, 2, 7 },
5695         {5,  243, 2, 2 },
5696         {6,  243, 2, 7 },
5697         {7,  244, 2, 2 },
5698         {8,  244, 2, 7 },
5699         {9,  245, 2, 2 },
5700         {10, 245, 2, 7 },
5701         {11, 246, 2, 2 },
5702         {12, 246, 2, 7 },
5703         {13, 247, 2, 2 },
5704         {14, 248, 2, 4 },
5705
5706         /* 802.11 UNI / HyperLan 2 */
5707         {36, 0x56, 0, 4},
5708         {38, 0x56, 0, 6},
5709         {40, 0x56, 0, 8},
5710         {44, 0x57, 0, 0},
5711         {46, 0x57, 0, 2},
5712         {48, 0x57, 0, 4},
5713         {52, 0x57, 0, 8},
5714         {54, 0x57, 0, 10},
5715         {56, 0x58, 0, 0},
5716         {60, 0x58, 0, 4},
5717         {62, 0x58, 0, 6},
5718         {64, 0x58, 0, 8},
5719
5720         /* 802.11 HyperLan 2 */
5721         {100, 0x5b, 0, 8},
5722         {102, 0x5b, 0, 10},
5723         {104, 0x5c, 0, 0},
5724         {108, 0x5c, 0, 4},
5725         {110, 0x5c, 0, 6},
5726         {112, 0x5c, 0, 8},
5727         {116, 0x5d, 0, 0},
5728         {118, 0x5d, 0, 2},
5729         {120, 0x5d, 0, 4},
5730         {124, 0x5d, 0, 8},
5731         {126, 0x5d, 0, 10},
5732         {128, 0x5e, 0, 0},
5733         {132, 0x5e, 0, 4},
5734         {134, 0x5e, 0, 6},
5735         {136, 0x5e, 0, 8},
5736         {140, 0x5f, 0, 0},
5737
5738         /* 802.11 UNII */
5739         {149, 0x5f, 0, 9},
5740         {151, 0x5f, 0, 11},
5741         {153, 0x60, 0, 1},
5742         {157, 0x60, 0, 5},
5743         {159, 0x60, 0, 7},
5744         {161, 0x60, 0, 9},
5745         {165, 0x61, 0, 1},
5746         {167, 0x61, 0, 3},
5747         {169, 0x61, 0, 5},
5748         {171, 0x61, 0, 7},
5749         {173, 0x61, 0, 9},
5750 };
5751
5752 static const struct rf_channel rf_vals_5592_xtal20[] = {
5753         /* Channel, N, K, mod, R */
5754         {1, 482, 4, 10, 3},
5755         {2, 483, 4, 10, 3},
5756         {3, 484, 4, 10, 3},
5757         {4, 485, 4, 10, 3},
5758         {5, 486, 4, 10, 3},
5759         {6, 487, 4, 10, 3},
5760         {7, 488, 4, 10, 3},
5761         {8, 489, 4, 10, 3},
5762         {9, 490, 4, 10, 3},
5763         {10, 491, 4, 10, 3},
5764         {11, 492, 4, 10, 3},
5765         {12, 493, 4, 10, 3},
5766         {13, 494, 4, 10, 3},
5767         {14, 496, 8, 10, 3},
5768         {36, 172, 8, 12, 1},
5769         {38, 173, 0, 12, 1},
5770         {40, 173, 4, 12, 1},
5771         {42, 173, 8, 12, 1},
5772         {44, 174, 0, 12, 1},
5773         {46, 174, 4, 12, 1},
5774         {48, 174, 8, 12, 1},
5775         {50, 175, 0, 12, 1},
5776         {52, 175, 4, 12, 1},
5777         {54, 175, 8, 12, 1},
5778         {56, 176, 0, 12, 1},
5779         {58, 176, 4, 12, 1},
5780         {60, 176, 8, 12, 1},
5781         {62, 177, 0, 12, 1},
5782         {64, 177, 4, 12, 1},
5783         {100, 183, 4, 12, 1},
5784         {102, 183, 8, 12, 1},
5785         {104, 184, 0, 12, 1},
5786         {106, 184, 4, 12, 1},
5787         {108, 184, 8, 12, 1},
5788         {110, 185, 0, 12, 1},
5789         {112, 185, 4, 12, 1},
5790         {114, 185, 8, 12, 1},
5791         {116, 186, 0, 12, 1},
5792         {118, 186, 4, 12, 1},
5793         {120, 186, 8, 12, 1},
5794         {122, 187, 0, 12, 1},
5795         {124, 187, 4, 12, 1},
5796         {126, 187, 8, 12, 1},
5797         {128, 188, 0, 12, 1},
5798         {130, 188, 4, 12, 1},
5799         {132, 188, 8, 12, 1},
5800         {134, 189, 0, 12, 1},
5801         {136, 189, 4, 12, 1},
5802         {138, 189, 8, 12, 1},
5803         {140, 190, 0, 12, 1},
5804         {149, 191, 6, 12, 1},
5805         {151, 191, 10, 12, 1},
5806         {153, 192, 2, 12, 1},
5807         {155, 192, 6, 12, 1},
5808         {157, 192, 10, 12, 1},
5809         {159, 193, 2, 12, 1},
5810         {161, 193, 6, 12, 1},
5811         {165, 194, 2, 12, 1},
5812         {184, 164, 0, 12, 1},
5813         {188, 164, 4, 12, 1},
5814         {192, 165, 8, 12, 1},
5815         {196, 166, 0, 12, 1},
5816 };
5817
5818 static const struct rf_channel rf_vals_5592_xtal40[] = {
5819         /* Channel, N, K, mod, R */
5820         {1, 241, 2, 10, 3},
5821         {2, 241, 7, 10, 3},
5822         {3, 242, 2, 10, 3},
5823         {4, 242, 7, 10, 3},
5824         {5, 243, 2, 10, 3},
5825         {6, 243, 7, 10, 3},
5826         {7, 244, 2, 10, 3},
5827         {8, 244, 7, 10, 3},
5828         {9, 245, 2, 10, 3},
5829         {10, 245, 7, 10, 3},
5830         {11, 246, 2, 10, 3},
5831         {12, 246, 7, 10, 3},
5832         {13, 247, 2, 10, 3},
5833         {14, 248, 4, 10, 3},
5834         {36, 86, 4, 12, 1},
5835         {38, 86, 6, 12, 1},
5836         {40, 86, 8, 12, 1},
5837         {42, 86, 10, 12, 1},
5838         {44, 87, 0, 12, 1},
5839         {46, 87, 2, 12, 1},
5840         {48, 87, 4, 12, 1},
5841         {50, 87, 6, 12, 1},
5842         {52, 87, 8, 12, 1},
5843         {54, 87, 10, 12, 1},
5844         {56, 88, 0, 12, 1},
5845         {58, 88, 2, 12, 1},
5846         {60, 88, 4, 12, 1},
5847         {62, 88, 6, 12, 1},
5848         {64, 88, 8, 12, 1},
5849         {100, 91, 8, 12, 1},
5850         {102, 91, 10, 12, 1},
5851         {104, 92, 0, 12, 1},
5852         {106, 92, 2, 12, 1},
5853         {108, 92, 4, 12, 1},
5854         {110, 92, 6, 12, 1},
5855         {112, 92, 8, 12, 1},
5856         {114, 92, 10, 12, 1},
5857         {116, 93, 0, 12, 1},
5858         {118, 93, 2, 12, 1},
5859         {120, 93, 4, 12, 1},
5860         {122, 93, 6, 12, 1},
5861         {124, 93, 8, 12, 1},
5862         {126, 93, 10, 12, 1},
5863         {128, 94, 0, 12, 1},
5864         {130, 94, 2, 12, 1},
5865         {132, 94, 4, 12, 1},
5866         {134, 94, 6, 12, 1},
5867         {136, 94, 8, 12, 1},
5868         {138, 94, 10, 12, 1},
5869         {140, 95, 0, 12, 1},
5870         {149, 95, 9, 12, 1},
5871         {151, 95, 11, 12, 1},
5872         {153, 96, 1, 12, 1},
5873         {155, 96, 3, 12, 1},
5874         {157, 96, 5, 12, 1},
5875         {159, 96, 7, 12, 1},
5876         {161, 96, 9, 12, 1},
5877         {165, 97, 1, 12, 1},
5878         {184, 82, 0, 12, 1},
5879         {188, 82, 4, 12, 1},
5880         {192, 82, 8, 12, 1},
5881         {196, 83, 0, 12, 1},
5882 };
5883
5884 static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
5885 {
5886         struct hw_mode_spec *spec = &rt2x00dev->spec;
5887         struct channel_info *info;
5888         char *default_power1;
5889         char *default_power2;
5890         unsigned int i;
5891         u16 eeprom;
5892         u32 reg;
5893
5894         /*
5895          * Disable powersaving as default on PCI devices.
5896          */
5897         if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
5898                 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
5899
5900         /*
5901          * Initialize all hw fields.
5902          */
5903         rt2x00dev->hw->flags =
5904             IEEE80211_HW_SIGNAL_DBM |
5905             IEEE80211_HW_SUPPORTS_PS |
5906             IEEE80211_HW_PS_NULLFUNC_STACK |
5907             IEEE80211_HW_AMPDU_AGGREGATION |
5908             IEEE80211_HW_REPORTS_TX_ACK_STATUS;
5909
5910         /*
5911          * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
5912          * unless we are capable of sending the buffered frames out after the
5913          * DTIM transmission using rt2x00lib_beacondone. This will send out
5914          * multicast and broadcast traffic immediately instead of buffering it
5915          * infinitly and thus dropping it after some time.
5916          */
5917         if (!rt2x00_is_usb(rt2x00dev))
5918                 rt2x00dev->hw->flags |=
5919                         IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
5920
5921         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
5922         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
5923                                 rt2x00_eeprom_addr(rt2x00dev,
5924                                                    EEPROM_MAC_ADDR_0));
5925
5926         /*
5927          * As rt2800 has a global fallback table we cannot specify
5928          * more then one tx rate per frame but since the hw will
5929          * try several rates (based on the fallback table) we should
5930          * initialize max_report_rates to the maximum number of rates
5931          * we are going to try. Otherwise mac80211 will truncate our
5932          * reported tx rates and the rc algortihm will end up with
5933          * incorrect data.
5934          */
5935         rt2x00dev->hw->max_rates = 1;
5936         rt2x00dev->hw->max_report_rates = 7;
5937         rt2x00dev->hw->max_rate_tries = 1;
5938
5939         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5940
5941         /*
5942          * Initialize hw_mode information.
5943          */
5944         spec->supported_bands = SUPPORT_BAND_2GHZ;
5945         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
5946
5947         if (rt2x00_rf(rt2x00dev, RF2820) ||
5948             rt2x00_rf(rt2x00dev, RF2720)) {
5949                 spec->num_channels = 14;
5950                 spec->channels = rf_vals;
5951         } else if (rt2x00_rf(rt2x00dev, RF2850) ||
5952                    rt2x00_rf(rt2x00dev, RF2750)) {
5953                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
5954                 spec->num_channels = ARRAY_SIZE(rf_vals);
5955                 spec->channels = rf_vals;
5956         } else if (rt2x00_rf(rt2x00dev, RF3020) ||
5957                    rt2x00_rf(rt2x00dev, RF2020) ||
5958                    rt2x00_rf(rt2x00dev, RF3021) ||
5959                    rt2x00_rf(rt2x00dev, RF3022) ||
5960                    rt2x00_rf(rt2x00dev, RF3290) ||
5961                    rt2x00_rf(rt2x00dev, RF3320) ||
5962                    rt2x00_rf(rt2x00dev, RF3322) ||
5963                    rt2x00_rf(rt2x00dev, RF5360) ||
5964                    rt2x00_rf(rt2x00dev, RF5370) ||
5965                    rt2x00_rf(rt2x00dev, RF5372) ||
5966                    rt2x00_rf(rt2x00dev, RF5390) ||
5967                    rt2x00_rf(rt2x00dev, RF5392)) {
5968                 spec->num_channels = 14;
5969                 spec->channels = rf_vals_3x;
5970         } else if (rt2x00_rf(rt2x00dev, RF3052)) {
5971                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
5972                 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
5973                 spec->channels = rf_vals_3x;
5974         } else if (rt2x00_rf(rt2x00dev, RF5592)) {
5975                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
5976
5977                 rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX, &reg);
5978                 if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) {
5979                         spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40);
5980                         spec->channels = rf_vals_5592_xtal40;
5981                 } else {
5982                         spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20);
5983                         spec->channels = rf_vals_5592_xtal20;
5984                 }
5985         }
5986
5987         if (WARN_ON_ONCE(!spec->channels))
5988                 return -ENODEV;
5989
5990         /*
5991          * Initialize HT information.
5992          */
5993         if (!rt2x00_rf(rt2x00dev, RF2020))
5994                 spec->ht.ht_supported = true;
5995         else
5996                 spec->ht.ht_supported = false;
5997
5998         spec->ht.cap =
5999             IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
6000             IEEE80211_HT_CAP_GRN_FLD |
6001             IEEE80211_HT_CAP_SGI_20 |
6002             IEEE80211_HT_CAP_SGI_40;
6003
6004         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2)
6005                 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
6006
6007         spec->ht.cap |=
6008             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) <<
6009                 IEEE80211_HT_CAP_RX_STBC_SHIFT;
6010
6011         spec->ht.ampdu_factor = 3;
6012         spec->ht.ampdu_density = 4;
6013         spec->ht.mcs.tx_params =
6014             IEEE80211_HT_MCS_TX_DEFINED |
6015             IEEE80211_HT_MCS_TX_RX_DIFF |
6016             ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) <<
6017                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
6018
6019         switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) {
6020         case 3:
6021                 spec->ht.mcs.rx_mask[2] = 0xff;
6022         case 2:
6023                 spec->ht.mcs.rx_mask[1] = 0xff;
6024         case 1:
6025                 spec->ht.mcs.rx_mask[0] = 0xff;
6026                 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
6027                 break;
6028         }
6029
6030         /*
6031          * Create channel information array
6032          */
6033         info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
6034         if (!info)
6035                 return -ENOMEM;
6036
6037         spec->channels_info = info;
6038
6039         default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
6040         default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
6041
6042         for (i = 0; i < 14; i++) {
6043                 info[i].default_power1 = default_power1[i];
6044                 info[i].default_power2 = default_power2[i];
6045         }
6046
6047         if (spec->num_channels > 14) {
6048                 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
6049                 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
6050
6051                 for (i = 14; i < spec->num_channels; i++) {
6052                         info[i].default_power1 = default_power1[i];
6053                         info[i].default_power2 = default_power2[i];
6054                 }
6055         }
6056
6057         switch (rt2x00dev->chip.rf) {
6058         case RF2020:
6059         case RF3020:
6060         case RF3021:
6061         case RF3022:
6062         case RF3320:
6063         case RF3052:
6064         case RF3290:
6065         case RF5360:
6066         case RF5370:
6067         case RF5372:
6068         case RF5390:
6069         case RF5392:
6070                 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
6071                 break;
6072         }
6073
6074         return 0;
6075 }
6076
6077 static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev)
6078 {
6079         u32 reg;
6080         u32 rt;
6081         u32 rev;
6082
6083         if (rt2x00_rt(rt2x00dev, RT3290))
6084                 rt2800_register_read(rt2x00dev, MAC_CSR0_3290, &reg);
6085         else
6086                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
6087
6088         rt = rt2x00_get_field32(reg, MAC_CSR0_CHIPSET);
6089         rev = rt2x00_get_field32(reg, MAC_CSR0_REVISION);
6090
6091         switch (rt) {
6092         case RT2860:
6093         case RT2872:
6094         case RT2883:
6095         case RT3070:
6096         case RT3071:
6097         case RT3090:
6098         case RT3290:
6099         case RT3352:
6100         case RT3390:
6101         case RT3572:
6102         case RT5390:
6103         case RT5392:
6104         case RT5592:
6105                 break;
6106         default:
6107                 rt2x00_err(rt2x00dev, "Invalid RT chipset 0x%04x, rev %04x detected\n",
6108                            rt, rev);
6109                 return -ENODEV;
6110         }
6111
6112         rt2x00_set_rt(rt2x00dev, rt, rev);
6113
6114         return 0;
6115 }
6116
6117 int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev)
6118 {
6119         int retval;
6120         u32 reg;
6121
6122         retval = rt2800_probe_rt(rt2x00dev);
6123         if (retval)
6124                 return retval;
6125
6126         /*
6127          * Allocate eeprom data.
6128          */
6129         retval = rt2800_validate_eeprom(rt2x00dev);
6130         if (retval)
6131                 return retval;
6132
6133         retval = rt2800_init_eeprom(rt2x00dev);
6134         if (retval)
6135                 return retval;
6136
6137         /*
6138          * Enable rfkill polling by setting GPIO direction of the
6139          * rfkill switch GPIO pin correctly.
6140          */
6141         rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
6142         rt2x00_set_field32(&reg, GPIO_CTRL_DIR2, 1);
6143         rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
6144
6145         /*
6146          * Initialize hw specifications.
6147          */
6148         retval = rt2800_probe_hw_mode(rt2x00dev);
6149         if (retval)
6150                 return retval;
6151
6152         /*
6153          * Set device capabilities.
6154          */
6155         __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
6156         __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
6157         if (!rt2x00_is_usb(rt2x00dev))
6158                 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
6159
6160         /*
6161          * Set device requirements.
6162          */
6163         if (!rt2x00_is_soc(rt2x00dev))
6164                 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
6165         __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
6166         __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
6167         if (!rt2800_hwcrypt_disabled(rt2x00dev))
6168                 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
6169         __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
6170         __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
6171         if (rt2x00_is_usb(rt2x00dev))
6172                 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
6173         else {
6174                 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
6175                 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
6176         }
6177
6178         /*
6179          * Set the rssi offset.
6180          */
6181         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
6182
6183         return 0;
6184 }
6185 EXPORT_SYMBOL_GPL(rt2800_probe_hw);
6186
6187 /*
6188  * IEEE80211 stack callback functions.
6189  */
6190 void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
6191                          u16 *iv16)
6192 {
6193         struct rt2x00_dev *rt2x00dev = hw->priv;
6194         struct mac_iveiv_entry iveiv_entry;
6195         u32 offset;
6196
6197         offset = MAC_IVEIV_ENTRY(hw_key_idx);
6198         rt2800_register_multiread(rt2x00dev, offset,
6199                                       &iveiv_entry, sizeof(iveiv_entry));
6200
6201         memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
6202         memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
6203 }
6204 EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
6205
6206 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
6207 {
6208         struct rt2x00_dev *rt2x00dev = hw->priv;
6209         u32 reg;
6210         bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
6211
6212         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
6213         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
6214         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
6215
6216         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
6217         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
6218         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
6219
6220         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
6221         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
6222         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
6223
6224         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
6225         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
6226         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
6227
6228         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
6229         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
6230         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
6231
6232         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
6233         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
6234         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
6235
6236         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
6237         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
6238         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
6239
6240         return 0;
6241 }
6242 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
6243
6244 int rt2800_conf_tx(struct ieee80211_hw *hw,
6245                    struct ieee80211_vif *vif, u16 queue_idx,
6246                    const struct ieee80211_tx_queue_params *params)
6247 {
6248         struct rt2x00_dev *rt2x00dev = hw->priv;
6249         struct data_queue *queue;
6250         struct rt2x00_field32 field;
6251         int retval;
6252         u32 reg;
6253         u32 offset;
6254
6255         /*
6256          * First pass the configuration through rt2x00lib, that will
6257          * update the queue settings and validate the input. After that
6258          * we are free to update the registers based on the value
6259          * in the queue parameter.
6260          */
6261         retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
6262         if (retval)
6263                 return retval;
6264
6265         /*
6266          * We only need to perform additional register initialization
6267          * for WMM queues/
6268          */
6269         if (queue_idx >= 4)
6270                 return 0;
6271
6272         queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
6273
6274         /* Update WMM TXOP register */
6275         offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
6276         field.bit_offset = (queue_idx & 1) * 16;
6277         field.bit_mask = 0xffff << field.bit_offset;
6278
6279         rt2800_register_read(rt2x00dev, offset, &reg);
6280         rt2x00_set_field32(&reg, field, queue->txop);
6281         rt2800_register_write(rt2x00dev, offset, reg);
6282
6283         /* Update WMM registers */
6284         field.bit_offset = queue_idx * 4;
6285         field.bit_mask = 0xf << field.bit_offset;
6286
6287         rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
6288         rt2x00_set_field32(&reg, field, queue->aifs);
6289         rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
6290
6291         rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
6292         rt2x00_set_field32(&reg, field, queue->cw_min);
6293         rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
6294
6295         rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
6296         rt2x00_set_field32(&reg, field, queue->cw_max);
6297         rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
6298
6299         /* Update EDCA registers */
6300         offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
6301
6302         rt2800_register_read(rt2x00dev, offset, &reg);
6303         rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
6304         rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
6305         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
6306         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
6307         rt2800_register_write(rt2x00dev, offset, reg);
6308
6309         return 0;
6310 }
6311 EXPORT_SYMBOL_GPL(rt2800_conf_tx);
6312
6313 u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
6314 {
6315         struct rt2x00_dev *rt2x00dev = hw->priv;
6316         u64 tsf;
6317         u32 reg;
6318
6319         rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
6320         tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
6321         rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
6322         tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
6323
6324         return tsf;
6325 }
6326 EXPORT_SYMBOL_GPL(rt2800_get_tsf);
6327
6328 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
6329                         enum ieee80211_ampdu_mlme_action action,
6330                         struct ieee80211_sta *sta, u16 tid, u16 *ssn,
6331                         u8 buf_size)
6332 {
6333         struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
6334         int ret = 0;
6335
6336         /*
6337          * Don't allow aggregation for stations the hardware isn't aware
6338          * of because tx status reports for frames to an unknown station
6339          * always contain wcid=255 and thus we can't distinguish between
6340          * multiple stations which leads to unwanted situations when the
6341          * hw reorders frames due to aggregation.
6342          */
6343         if (sta_priv->wcid < 0)
6344                 return 1;
6345
6346         switch (action) {
6347         case IEEE80211_AMPDU_RX_START:
6348         case IEEE80211_AMPDU_RX_STOP:
6349                 /*
6350                  * The hw itself takes care of setting up BlockAck mechanisms.
6351                  * So, we only have to allow mac80211 to nagotiate a BlockAck
6352                  * agreement. Once that is done, the hw will BlockAck incoming
6353                  * AMPDUs without further setup.
6354                  */
6355                 break;
6356         case IEEE80211_AMPDU_TX_START:
6357                 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
6358                 break;
6359         case IEEE80211_AMPDU_TX_STOP_CONT:
6360         case IEEE80211_AMPDU_TX_STOP_FLUSH:
6361         case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
6362                 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
6363                 break;
6364         case IEEE80211_AMPDU_TX_OPERATIONAL:
6365                 break;
6366         default:
6367                 rt2x00_warn((struct rt2x00_dev *)hw->priv,
6368                             "Unknown AMPDU action\n");
6369         }
6370
6371         return ret;
6372 }
6373 EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
6374
6375 int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
6376                       struct survey_info *survey)
6377 {
6378         struct rt2x00_dev *rt2x00dev = hw->priv;
6379         struct ieee80211_conf *conf = &hw->conf;
6380         u32 idle, busy, busy_ext;
6381
6382         if (idx != 0)
6383                 return -ENOENT;
6384
6385         survey->channel = conf->chandef.chan;
6386
6387         rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
6388         rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
6389         rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
6390
6391         if (idle || busy) {
6392                 survey->filled = SURVEY_INFO_CHANNEL_TIME |
6393                                  SURVEY_INFO_CHANNEL_TIME_BUSY |
6394                                  SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
6395
6396                 survey->channel_time = (idle + busy) / 1000;
6397                 survey->channel_time_busy = busy / 1000;
6398                 survey->channel_time_ext_busy = busy_ext / 1000;
6399         }
6400
6401         if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
6402                 survey->filled |= SURVEY_INFO_IN_USE;
6403
6404         return 0;
6405
6406 }
6407 EXPORT_SYMBOL_GPL(rt2800_get_survey);
6408
6409 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
6410 MODULE_VERSION(DRV_VERSION);
6411 MODULE_DESCRIPTION("Ralink RT2800 library");
6412 MODULE_LICENSE("GPL");