drivers/net/wireless/rt2x00/rt2800lib.c

   1 /*
   2         Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
   3         Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
   4         Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
   5         Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
   6
   7         Based on the original rt2800pci.c and rt2800usb.c.
   8           Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
   9           Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
  10           Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
  11           Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
  12           Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
  13           Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
  14           <http://rt2x00.serialmonkey.com>
  15
  16         This program is free software; you can redistribute it and/or modify
  17         it under the terms of the GNU General Public License as published by
  18         the Free Software Foundation; either version 2 of the License, or
  19         (at your option) any later version.
  20
  21         This program is distributed in the hope that it will be useful,
  22         but WITHOUT ANY WARRANTY; without even the implied warranty of
  23         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24         GNU General Public License for more details.
  25
  26         You should have received a copy of the GNU General Public License
  27         along with this program; if not, write to the
  28         Free Software Foundation, Inc.,
  29         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  30  */
  31
  32 /*
  33         Module: rt2800lib
  34         Abstract: rt2800 generic device routines.
  35  */
  36
  37 #include <linux/crc-ccitt.h>
  38 #include <linux/kernel.h>
  39 #include <linux/module.h>
  40 #include <linux/slab.h>
  41
  42 #include "rt2x00.h"
  43 #include "rt2800lib.h"
  44 #include "rt2800.h"
  45
  46 /*
  47  * Register access.
  48  * All access to the CSR registers will go through the methods
  49  * rt2800_register_read and rt2800_register_write.
  50  * BBP and RF register require indirect register access,
  51  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  52  * These indirect registers work with busy bits,
  53  * and we will try maximal REGISTER_BUSY_COUNT times to access
  54  * the register while taking a REGISTER_BUSY_DELAY us delay
  55  * between each attampt. When the busy bit is still set at that time,
  56  * the access attempt is considered to have failed,
  57  * and we will print an error.
  58  * The _lock versions must be used if you already hold the csr_mutex
  59  */
  60 #define WAIT_FOR_BBP(__dev, __reg) \
  61         rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
  62 #define WAIT_FOR_RFCSR(__dev, __reg) \
  63         rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
  64 #define WAIT_FOR_RF(__dev, __reg) \
  65         rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
  66 #define WAIT_FOR_MCU(__dev, __reg) \
  67         rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  68                             H2M_MAILBOX_CSR_OWNER, (__reg))
  69
  70 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
  71 {
  72         /* check for rt2872 on SoC */
  73         if (!rt2x00_is_soc(rt2x00dev) ||
  74             !rt2x00_rt(rt2x00dev, RT2872))
  75                 return false;
  76
  77         /* we know for sure that these rf chipsets are used on rt305x boards */
  78         if (rt2x00_rf(rt2x00dev, RF3020) ||
  79             rt2x00_rf(rt2x00dev, RF3021) ||
  80             rt2x00_rf(rt2x00dev, RF3022))
  81                 return true;
  82
  83         NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n");
  84         return false;
  85 }
  86
  87 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
  88                              const unsigned int word, const u8 value)
  89 {
  90         u32 reg;
  91
  92         mutex_lock(&rt2x00dev->csr_mutex);
  93
  94         /*
  95          * Wait until the BBP becomes available, afterwards we
  96          * can safely write the new data into the register.
  97          */
  98         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  99                 reg = 0;
 100                 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
 101                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 102                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 103                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
 104                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 105
 106                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 107         }
 108
 109         mutex_unlock(&rt2x00dev->csr_mutex);
 110 }
 111
 112 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
 113                             const unsigned int word, u8 *value)
 114 {
 115         u32 reg;
 116
 117         mutex_lock(&rt2x00dev->csr_mutex);
 118
 119         /*
 120          * Wait until the BBP becomes available, afterwards we
 121          * can safely write the read request into the register.
 122          * After the data has been written, we wait until hardware
 123          * returns the correct value, if at any time the register
 124          * doesn't become available in time, reg will be 0xffffffff
 125          * which means we return 0xff to the caller.
 126          */
 127         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 128                 reg = 0;
 129                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 130                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 131                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
 132                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 133
 134                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 135
 136                 WAIT_FOR_BBP(rt2x00dev, &reg);
 137         }
 138
 139         *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
 140
 141         mutex_unlock(&rt2x00dev->csr_mutex);
 142 }
 143
 144 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
 145                                const unsigned int word, const u8 value)
 146 {
 147         u32 reg;
 148
 149         mutex_lock(&rt2x00dev->csr_mutex);
 150
 151         /*
 152          * Wait until the RFCSR becomes available, afterwards we
 153          * can safely write the new data into the register.
 154          */
 155         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 156                 reg = 0;
 157                 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
 158                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 159                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
 160                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 161
 162                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 163         }
 164
 165         mutex_unlock(&rt2x00dev->csr_mutex);
 166 }
 167
 168 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
 169                               const unsigned int word, u8 *value)
 170 {
 171         u32 reg;
 172
 173         mutex_lock(&rt2x00dev->csr_mutex);
 174
 175         /*
 176          * Wait until the RFCSR becomes available, afterwards we
 177          * can safely write the read request into the register.
 178          * After the data has been written, we wait until hardware
 179          * returns the correct value, if at any time the register
 180          * doesn't become available in time, reg will be 0xffffffff
 181          * which means we return 0xff to the caller.
 182          */
 183         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 184                 reg = 0;
 185                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 186                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
 187                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 188
 189                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 190
 191                 WAIT_FOR_RFCSR(rt2x00dev, &reg);
 192         }
 193
 194         *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
 195
 196         mutex_unlock(&rt2x00dev->csr_mutex);
 197 }
 198
 199 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
 200                             const unsigned int word, const u32 value)
 201 {
 202         u32 reg;
 203
 204         mutex_lock(&rt2x00dev->csr_mutex);
 205
 206         /*
 207          * Wait until the RF becomes available, afterwards we
 208          * can safely write the new data into the register.
 209          */
 210         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 211                 reg = 0;
 212                 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
 213                 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
 214                 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
 215                 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
 216
 217                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
 218                 rt2x00_rf_write(rt2x00dev, word, value);
 219         }
 220
 221         mutex_unlock(&rt2x00dev->csr_mutex);
 222 }
 223
 224 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
 225                         const u8 command, const u8 token,
 226                         const u8 arg0, const u8 arg1)
 227 {
 228         u32 reg;
 229
 230         /*
 231          * SOC devices don't support MCU requests.
 232          */
 233         if (rt2x00_is_soc(rt2x00dev))
 234                 return;
 235
 236         mutex_lock(&rt2x00dev->csr_mutex);
 237
 238         /*
 239          * Wait until the MCU becomes available, afterwards we
 240          * can safely write the new data into the register.
 241          */
 242         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 243                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 244                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 245                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 246                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 247                 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
 248
 249                 reg = 0;
 250                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 251                 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
 252         }
 253
 254         mutex_unlock(&rt2x00dev->csr_mutex);
 255 }
 256 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
 257
 258 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
 259 {
 260         unsigned int i = 0;
 261         u32 reg;
 262
 263         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 264                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
 265                 if (reg && reg != ~0)
 266                         return 0;
 267                 msleep(1);
 268         }
 269
 270         ERROR(rt2x00dev, "Unstable hardware.\n");
 271         return -EBUSY;
 272 }
 273 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
 274
 275 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
 276 {
 277         unsigned int i;
 278         u32 reg;
 279
 280         /*
 281          * Some devices are really slow to respond here. Wait a whole second
 282          * before timing out.
 283          */
 284         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 285                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 286                 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
 287                     !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
 288                         return 0;
 289
 290                 msleep(10);
 291         }
 292
 293         ERROR(rt2x00dev, "WPDMA TX/RX busy [0x%08x].\n", reg);
 294         return -EACCES;
 295 }
 296 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
 297
 298 void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev)
 299 {
 300         u32 reg;
 301
 302         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 303         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
 304         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
 305         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
 306         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
 307         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
 308         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 309 }
 310 EXPORT_SYMBOL_GPL(rt2800_disable_wpdma);
 311
 312 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
 313 {
 314         u16 fw_crc;
 315         u16 crc;
 316
 317         /*
 318          * The last 2 bytes in the firmware array are the crc checksum itself,
 319          * this means that we should never pass those 2 bytes to the crc
 320          * algorithm.
 321          */
 322         fw_crc = (data[len - 2] << 8 | data[len - 1]);
 323
 324         /*
 325          * Use the crc ccitt algorithm.
 326          * This will return the same value as the legacy driver which
 327          * used bit ordering reversion on the both the firmware bytes
 328          * before input input as well as on the final output.
 329          * Obviously using crc ccitt directly is much more efficient.
 330          */
 331         crc = crc_ccitt(~0, data, len - 2);
 332
 333         /*
 334          * There is a small difference between the crc-itu-t + bitrev and
 335          * the crc-ccitt crc calculation. In the latter method the 2 bytes
 336          * will be swapped, use swab16 to convert the crc to the correct
 337          * value.
 338          */
 339         crc = swab16(crc);
 340
 341         return fw_crc == crc;
 342 }
 343
 344 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
 345                           const u8 *data, const size_t len)
 346 {
 347         size_t offset = 0;
 348         size_t fw_len;
 349         bool multiple;
 350
 351         /*
 352          * PCI(e) & SOC devices require firmware with a length
 353          * of 8kb. USB devices require firmware files with a length
 354          * of 4kb. Certain USB chipsets however require different firmware,
 355          * which Ralink only provides attached to the original firmware
 356          * file. Thus for USB devices, firmware files have a length
 357          * which is a multiple of 4kb.
 358          */
 359         if (rt2x00_is_usb(rt2x00dev)) {
 360                 fw_len = 4096;
 361                 multiple = true;
 362         } else {
 363                 fw_len = 8192;
 364                 multiple = true;
 365         }
 366
 367         /*
 368          * Validate the firmware length
 369          */
 370         if (len != fw_len && (!multiple || (len % fw_len) != 0))
 371                 return FW_BAD_LENGTH;
 372
 373         /*
 374          * Check if the chipset requires one of the upper parts
 375          * of the firmware.
 376          */
 377         if (rt2x00_is_usb(rt2x00dev) &&
 378             !rt2x00_rt(rt2x00dev, RT2860) &&
 379             !rt2x00_rt(rt2x00dev, RT2872) &&
 380             !rt2x00_rt(rt2x00dev, RT3070) &&
 381             ((len / fw_len) == 1))
 382                 return FW_BAD_VERSION;
 383
 384         /*
 385          * 8kb firmware files must be checked as if it were
 386          * 2 separate firmware files.
 387          */
 388         while (offset < len) {
 389                 if (!rt2800_check_firmware_crc(data + offset, fw_len))
 390                         return FW_BAD_CRC;
 391
 392                 offset += fw_len;
 393         }
 394
 395         return FW_OK;
 396 }
 397 EXPORT_SYMBOL_GPL(rt2800_check_firmware);
 398
 399 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
 400                          const u8 *data, const size_t len)
 401 {
 402         unsigned int i;
 403         u32 reg;
 404
 405         /*
 406          * If driver doesn't wake up firmware here,
 407          * rt2800_load_firmware will hang forever when interface is up again.
 408          */
 409         rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
 410
 411         /*
 412          * Wait for stable hardware.
 413          */
 414         if (rt2800_wait_csr_ready(rt2x00dev))
 415                 return -EBUSY;
 416
 417         if (rt2x00_is_pci(rt2x00dev)) {
 418                 if (rt2x00_rt(rt2x00dev, RT3572) ||
 419                     rt2x00_rt(rt2x00dev, RT5390) ||
 420                     rt2x00_rt(rt2x00dev, RT5392)) {
 421                         rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
 422                         rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
 423                         rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
 424                         rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
 425                 }
 426                 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
 427         }
 428
 429         rt2800_disable_wpdma(rt2x00dev);
 430
 431         /*
 432          * Write firmware to the device.
 433          */
 434         rt2800_drv_write_firmware(rt2x00dev, data, len);
 435
 436         /*
 437          * Wait for device to stabilize.
 438          */
 439         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 440                 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
 441                 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
 442                         break;
 443                 msleep(1);
 444         }
 445
 446         if (i == REGISTER_BUSY_COUNT) {
 447                 ERROR(rt2x00dev, "PBF system register not ready.\n");
 448                 return -EBUSY;
 449         }
 450
 451         /*
 452          * Disable DMA, will be reenabled later when enabling
 453          * the radio.
 454          */
 455         rt2800_disable_wpdma(rt2x00dev);
 456
 457         /*
 458          * Initialize firmware.
 459          */
 460         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
 461         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
 462         if (rt2x00_is_usb(rt2x00dev))
 463                 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
 464         msleep(1);
 465
 466         return 0;
 467 }
 468 EXPORT_SYMBOL_GPL(rt2800_load_firmware);
 469
 470 void rt2800_write_tx_data(struct queue_entry *entry,
 471                           struct txentry_desc *txdesc)
 472 {
 473         __le32 *txwi = rt2800_drv_get_txwi(entry);
 474         u32 word;
 475
 476         /*
 477          * Initialize TX Info descriptor
 478          */
 479         rt2x00_desc_read(txwi, 0, &word);
 480         rt2x00_set_field32(&word, TXWI_W0_FRAG,
 481                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
 482         rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
 483                            test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
 484         rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
 485         rt2x00_set_field32(&word, TXWI_W0_TS,
 486                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
 487         rt2x00_set_field32(&word, TXWI_W0_AMPDU,
 488                            test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
 489         rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
 490                            txdesc->u.ht.mpdu_density);
 491         rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
 492         rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
 493         rt2x00_set_field32(&word, TXWI_W0_BW,
 494                            test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
 495         rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
 496                            test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
 497         rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
 498         rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
 499         rt2x00_desc_write(txwi, 0, word);
 500
 501         rt2x00_desc_read(txwi, 1, &word);
 502         rt2x00_set_field32(&word, TXWI_W1_ACK,
 503                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
 504         rt2x00_set_field32(&word, TXWI_W1_NSEQ,
 505                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
 506         rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
 507         rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
 508                            test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
 509                            txdesc->key_idx : txdesc->u.ht.wcid);
 510         rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
 511                            txdesc->length);
 512         rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
 513         rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
 514         rt2x00_desc_write(txwi, 1, word);
 515
 516         /*
 517          * Always write 0 to IV/EIV fields, hardware will insert the IV
 518          * from the IVEIV register when TXD_W3_WIV is set to 0.
 519          * When TXD_W3_WIV is set to 1 it will use the IV data
 520          * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
 521          * crypto entry in the registers should be used to encrypt the frame.
 522          */
 523         _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
 524         _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
 525 }
 526 EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
 527
 528 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
 529 {
 530         s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
 531         s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
 532         s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
 533         u16 eeprom;
 534         u8 offset0;
 535         u8 offset1;
 536         u8 offset2;
 537
 538         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
 539                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
 540                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
 541                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
 542                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
 543                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
 544         } else {
 545                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
 546                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
 547                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
 548                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
 549                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
 550         }
 551
 552         /*
 553          * Convert the value from the descriptor into the RSSI value
 554          * If the value in the descriptor is 0, it is considered invalid
 555          * and the default (extremely low) rssi value is assumed
 556          */
 557         rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
 558         rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
 559         rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
 560
 561         /*
 562          * mac80211 only accepts a single RSSI value. Calculating the
 563          * average doesn't deliver a fair answer either since -60:-60 would
 564          * be considered equally good as -50:-70 while the second is the one
 565          * which gives less energy...
 566          */
 567         rssi0 = max(rssi0, rssi1);
 568         return (int)max(rssi0, rssi2);
 569 }
 570
 571 void rt2800_process_rxwi(struct queue_entry *entry,
 572                          struct rxdone_entry_desc *rxdesc)
 573 {
 574         __le32 *rxwi = (__le32 *) entry->skb->data;
 575         u32 word;
 576
 577         rt2x00_desc_read(rxwi, 0, &word);
 578
 579         rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
 580         rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
 581
 582         rt2x00_desc_read(rxwi, 1, &word);
 583
 584         if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
 585                 rxdesc->flags |= RX_FLAG_SHORT_GI;
 586
 587         if (rt2x00_get_field32(word, RXWI_W1_BW))
 588                 rxdesc->flags |= RX_FLAG_40MHZ;
 589
 590         /*
 591          * Detect RX rate, always use MCS as signal type.
 592          */
 593         rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
 594         rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
 595         rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
 596
 597         /*
 598          * Mask of 0x8 bit to remove the short preamble flag.
 599          */
 600         if (rxdesc->rate_mode == RATE_MODE_CCK)
 601                 rxdesc->signal &= ~0x8;
 602
 603         rt2x00_desc_read(rxwi, 2, &word);
 604
 605         /*
 606          * Convert descriptor AGC value to RSSI value.
 607          */
 608         rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
 609
 610         /*
 611          * Remove RXWI descriptor from start of buffer.
 612          */
 613         skb_pull(entry->skb, RXWI_DESC_SIZE);
 614 }
 615 EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
 616
 617 void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi)
 618 {
 619         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 620         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 621         struct txdone_entry_desc txdesc;
 622         u32 word;
 623         u16 mcs, real_mcs;
 624         int aggr, ampdu;
 625
 626         /*
 627          * Obtain the status about this packet.
 628          */
 629         txdesc.flags = 0;
 630         rt2x00_desc_read(txwi, 0, &word);
 631
 632         mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
 633         ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
 634
 635         real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
 636         aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
 637
 638         /*
 639          * If a frame was meant to be sent as a single non-aggregated MPDU
 640          * but ended up in an aggregate the used tx rate doesn't correlate
 641          * with the one specified in the TXWI as the whole aggregate is sent
 642          * with the same rate.
 643          *
 644          * For example: two frames are sent to rt2x00, the first one sets
 645          * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
 646          * and requests MCS15. If the hw aggregates both frames into one
 647          * AMDPU the tx status for both frames will contain MCS7 although
 648          * the frame was sent successfully.
 649          *
 650          * Hence, replace the requested rate with the real tx rate to not
 651          * confuse the rate control algortihm by providing clearly wrong
 652          * data.
 653          */
 654         if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
 655                 skbdesc->tx_rate_idx = real_mcs;
 656                 mcs = real_mcs;
 657         }
 658
 659         if (aggr == 1 || ampdu == 1)
 660                 __set_bit(TXDONE_AMPDU, &txdesc.flags);
 661
 662         /*
 663          * Ralink has a retry mechanism using a global fallback
 664          * table. We setup this fallback table to try the immediate
 665          * lower rate for all rates. In the TX_STA_FIFO, the MCS field
 666          * always contains the MCS used for the last transmission, be
 667          * it successful or not.
 668          */
 669         if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
 670                 /*
 671                  * Transmission succeeded. The number of retries is
 672                  * mcs - real_mcs
 673                  */
 674                 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
 675                 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
 676         } else {
 677                 /*
 678                  * Transmission failed. The number of retries is
 679                  * always 7 in this case (for a total number of 8
 680                  * frames sent).
 681                  */
 682                 __set_bit(TXDONE_FAILURE, &txdesc.flags);
 683                 txdesc.retry = rt2x00dev->long_retry;
 684         }
 685
 686         /*
 687          * the frame was retried at least once
 688          * -> hw used fallback rates
 689          */
 690         if (txdesc.retry)
 691                 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
 692
 693         rt2x00lib_txdone(entry, &txdesc);
 694 }
 695 EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
 696
 697 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
 698 {
 699         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 700         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 701         unsigned int beacon_base;
 702         unsigned int padding_len;
 703         u32 orig_reg, reg;
 704
 705         /*
 706          * Disable beaconing while we are reloading the beacon data,
 707          * otherwise we might be sending out invalid data.
 708          */
 709         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 710         orig_reg = reg;
 711         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
 712         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 713
 714         /*
 715          * Add space for the TXWI in front of the skb.
 716          */
 717         memset(skb_push(entry->skb, TXWI_DESC_SIZE), 0, TXWI_DESC_SIZE);
 718
 719         /*
 720          * Register descriptor details in skb frame descriptor.
 721          */
 722         skbdesc->flags |= SKBDESC_DESC_IN_SKB;
 723         skbdesc->desc = entry->skb->data;
 724         skbdesc->desc_len = TXWI_DESC_SIZE;
 725
 726         /*
 727          * Add the TXWI for the beacon to the skb.
 728          */
 729         rt2800_write_tx_data(entry, txdesc);
 730
 731         /*
 732          * Dump beacon to userspace through debugfs.
 733          */
 734         rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
 735
 736         /*
 737          * Write entire beacon with TXWI and padding to register.
 738          */
 739         padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
 740         if (padding_len && skb_pad(entry->skb, padding_len)) {
 741                 ERROR(rt2x00dev, "Failure padding beacon, aborting\n");
 742                 /* skb freed by skb_pad() on failure */
 743                 entry->skb = NULL;
 744                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
 745                 return;
 746         }
 747
 748         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
 749         rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
 750                                    entry->skb->len + padding_len);
 751
 752         /*
 753          * Enable beaconing again.
 754          */
 755         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
 756         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 757
 758         /*
 759          * Clean up beacon skb.
 760          */
 761         dev_kfree_skb_any(entry->skb);
 762         entry->skb = NULL;
 763 }
 764 EXPORT_SYMBOL_GPL(rt2800_write_beacon);
 765
 766 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
 767                                                 unsigned int beacon_base)
 768 {
 769         int i;
 770
 771         /*
 772          * For the Beacon base registers we only need to clear
 773          * the whole TXWI which (when set to 0) will invalidate
 774          * the entire beacon.
 775          */
 776         for (i = 0; i < TXWI_DESC_SIZE; i += sizeof(__le32))
 777                 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
 778 }
 779
 780 void rt2800_clear_beacon(struct queue_entry *entry)
 781 {
 782         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 783         u32 reg;
 784
 785         /*
 786          * Disable beaconing while we are reloading the beacon data,
 787          * otherwise we might be sending out invalid data.
 788          */
 789         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 790         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
 791         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 792
 793         /*
 794          * Clear beacon.
 795          */
 796         rt2800_clear_beacon_register(rt2x00dev,
 797                                      HW_BEACON_OFFSET(entry->entry_idx));
 798
 799         /*
 800          * Enabled beaconing again.
 801          */
 802         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
 803         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 804 }
 805 EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
 806
 807 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 808 const struct rt2x00debug rt2800_rt2x00debug = {
 809         .owner  = THIS_MODULE,
 810         .csr    = {
 811                 .read           = rt2800_register_read,
 812                 .write          = rt2800_register_write,
 813                 .flags          = RT2X00DEBUGFS_OFFSET,
 814                 .word_base      = CSR_REG_BASE,
 815                 .word_size      = sizeof(u32),
 816                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 817         },
 818         .eeprom = {
 819                 .read           = rt2x00_eeprom_read,
 820                 .write          = rt2x00_eeprom_write,
 821                 .word_base      = EEPROM_BASE,
 822                 .word_size      = sizeof(u16),
 823                 .word_count     = EEPROM_SIZE / sizeof(u16),
 824         },
 825         .bbp    = {
 826                 .read           = rt2800_bbp_read,
 827                 .write          = rt2800_bbp_write,
 828                 .word_base      = BBP_BASE,
 829                 .word_size      = sizeof(u8),
 830                 .word_count     = BBP_SIZE / sizeof(u8),
 831         },
 832         .rf     = {
 833                 .read           = rt2x00_rf_read,
 834                 .write          = rt2800_rf_write,
 835                 .word_base      = RF_BASE,
 836                 .word_size      = sizeof(u32),
 837                 .word_count     = RF_SIZE / sizeof(u32),
 838         },
 839         .rfcsr  = {
 840                 .read           = rt2800_rfcsr_read,
 841                 .write          = rt2800_rfcsr_write,
 842                 .word_base      = RFCSR_BASE,
 843                 .word_size      = sizeof(u8),
 844                 .word_count     = RFCSR_SIZE / sizeof(u8),
 845         },
 846 };
 847 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
 848 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 849
 850 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 851 {
 852         u32 reg;
 853
 854         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
 855         return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
 856 }
 857 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
 858
 859 #ifdef CONFIG_RT2X00_LIB_LEDS
 860 static void rt2800_brightness_set(struct led_classdev *led_cdev,
 861                                   enum led_brightness brightness)
 862 {
 863         struct rt2x00_led *led =
 864             container_of(led_cdev, struct rt2x00_led, led_dev);
 865         unsigned int enabled = brightness != LED_OFF;
 866         unsigned int bg_mode =
 867             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 868         unsigned int polarity =
 869                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 870                                    EEPROM_FREQ_LED_POLARITY);
 871         unsigned int ledmode =
 872                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 873                                    EEPROM_FREQ_LED_MODE);
 874         u32 reg;
 875
 876         /* Check for SoC (SOC devices don't support MCU requests) */
 877         if (rt2x00_is_soc(led->rt2x00dev)) {
 878                 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
 879
 880                 /* Set LED Polarity */
 881                 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
 882
 883                 /* Set LED Mode */
 884                 if (led->type == LED_TYPE_RADIO) {
 885                         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
 886                                            enabled ? 3 : 0);
 887                 } else if (led->type == LED_TYPE_ASSOC) {
 888                         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
 889                                            enabled ? 3 : 0);
 890                 } else if (led->type == LED_TYPE_QUALITY) {
 891                         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
 892                                            enabled ? 3 : 0);
 893                 }
 894
 895                 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
 896
 897         } else {
 898                 if (led->type == LED_TYPE_RADIO) {
 899                         rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 900                                               enabled ? 0x20 : 0);
 901                 } else if (led->type == LED_TYPE_ASSOC) {
 902                         rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 903                                               enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
 904                 } else if (led->type == LED_TYPE_QUALITY) {
 905                         /*
 906                          * The brightness is divided into 6 levels (0 - 5),
 907                          * The specs tell us the following levels:
 908                          *      0, 1 ,3, 7, 15, 31
 909                          * to determine the level in a simple way we can simply
 910                          * work with bitshifting:
 911                          *      (1 << level) - 1
 912                          */
 913                         rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
 914                                               (1 << brightness / (LED_FULL / 6)) - 1,
 915                                               polarity);
 916                 }
 917         }
 918 }
 919
 920 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
 921                      struct rt2x00_led *led, enum led_type type)
 922 {
 923         led->rt2x00dev = rt2x00dev;
 924         led->type = type;
 925         led->led_dev.brightness_set = rt2800_brightness_set;
 926         led->flags = LED_INITIALIZED;
 927 }
 928 #endif /* CONFIG_RT2X00_LIB_LEDS */
 929
 930 /*
 931  * Configuration handlers.
 932  */
 933 static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
 934                                const u8 *address,
 935                                int wcid)
 936 {
 937         struct mac_wcid_entry wcid_entry;
 938         u32 offset;
 939
 940         offset = MAC_WCID_ENTRY(wcid);
 941
 942         memset(&wcid_entry, 0xff, sizeof(wcid_entry));
 943         if (address)
 944                 memcpy(wcid_entry.mac, address, ETH_ALEN);
 945
 946         rt2800_register_multiwrite(rt2x00dev, offset,
 947                                       &wcid_entry, sizeof(wcid_entry));
 948 }
 949
 950 static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
 951 {
 952         u32 offset;
 953         offset = MAC_WCID_ATTR_ENTRY(wcid);
 954         rt2800_register_write(rt2x00dev, offset, 0);
 955 }
 956
 957 static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
 958                                            int wcid, u32 bssidx)
 959 {
 960         u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
 961         u32 reg;
 962
 963         /*
 964          * The BSS Idx numbers is split in a main value of 3 bits,
 965          * and a extended field for adding one additional bit to the value.
 966          */
 967         rt2800_register_read(rt2x00dev, offset, &reg);
 968         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
 969         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
 970                            (bssidx & 0x8) >> 3);
 971         rt2800_register_write(rt2x00dev, offset, reg);
 972 }
 973
 974 static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
 975                                            struct rt2x00lib_crypto *crypto,
 976                                            struct ieee80211_key_conf *key)
 977 {
 978         struct mac_iveiv_entry iveiv_entry;
 979         u32 offset;
 980         u32 reg;
 981
 982         offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
 983
 984         if (crypto->cmd == SET_KEY) {
 985                 rt2800_register_read(rt2x00dev, offset, &reg);
 986                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
 987                                    !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
 988                 /*
 989                  * Both the cipher as the BSS Idx numbers are split in a main
 990                  * value of 3 bits, and a extended field for adding one additional
 991                  * bit to the value.
 992                  */
 993                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
 994                                    (crypto->cipher & 0x7));
 995                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
 996                                    (crypto->cipher & 0x8) >> 3);
 997                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
 998                 rt2800_register_write(rt2x00dev, offset, reg);
 999         } else {
1000                 /* Delete the cipher without touching the bssidx */
1001                 rt2800_register_read(rt2x00dev, offset, &reg);
1002                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
1003                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 0);
1004                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
1005                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
1006                 rt2800_register_write(rt2x00dev, offset, reg);
1007         }
1008
1009         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1010
1011         memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1012         if ((crypto->cipher == CIPHER_TKIP) ||
1013             (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1014             (crypto->cipher == CIPHER_AES))
1015                 iveiv_entry.iv[3] |= 0x20;
1016         iveiv_entry.iv[3] |= key->keyidx << 6;
1017         rt2800_register_multiwrite(rt2x00dev, offset,
1018                                       &iveiv_entry, sizeof(iveiv_entry));
1019 }
1020
1021 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1022                              struct rt2x00lib_crypto *crypto,
1023                              struct ieee80211_key_conf *key)
1024 {
1025         struct hw_key_entry key_entry;
1026         struct rt2x00_field32 field;
1027         u32 offset;
1028         u32 reg;
1029
1030         if (crypto->cmd == SET_KEY) {
1031                 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1032
1033                 memcpy(key_entry.key, crypto->key,
1034                        sizeof(key_entry.key));
1035                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1036                        sizeof(key_entry.tx_mic));
1037                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1038                        sizeof(key_entry.rx_mic));
1039
1040                 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1041                 rt2800_register_multiwrite(rt2x00dev, offset,
1042                                               &key_entry, sizeof(key_entry));
1043         }
1044
1045         /*
1046          * The cipher types are stored over multiple registers
1047          * starting with SHARED_KEY_MODE_BASE each word will have
1048          * 32 bits and contains the cipher types for 2 bssidx each.
1049          * Using the correct defines correctly will cause overhead,
1050          * so just calculate the correct offset.
1051          */
1052         field.bit_offset = 4 * (key->hw_key_idx % 8);
1053         field.bit_mask = 0x7 << field.bit_offset;
1054
1055         offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1056
1057         rt2800_register_read(rt2x00dev, offset, &reg);
1058         rt2x00_set_field32(&reg, field,
1059                            (crypto->cmd == SET_KEY) * crypto->cipher);
1060         rt2800_register_write(rt2x00dev, offset, reg);
1061
1062         /*
1063          * Update WCID information
1064          */
1065         rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1066         rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1067                                        crypto->bssidx);
1068         rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1069
1070         return 0;
1071 }
1072 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1073
1074 static inline int rt2800_find_wcid(struct rt2x00_dev *rt2x00dev)
1075 {
1076         struct mac_wcid_entry wcid_entry;
1077         int idx;
1078         u32 offset;
1079
1080         /*
1081          * Search for the first free WCID entry and return the corresponding
1082          * index.
1083          *
1084          * Make sure the WCID starts _after_ the last possible shared key
1085          * entry (>32).
1086          *
1087          * Since parts of the pairwise key table might be shared with
1088          * the beacon frame buffers 6 & 7 we should only write into the
1089          * first 222 entries.
1090          */
1091         for (idx = 33; idx <= 222; idx++) {
1092                 offset = MAC_WCID_ENTRY(idx);
1093                 rt2800_register_multiread(rt2x00dev, offset, &wcid_entry,
1094                                           sizeof(wcid_entry));
1095                 if (is_broadcast_ether_addr(wcid_entry.mac))
1096                         return idx;
1097         }
1098
1099         /*
1100          * Use -1 to indicate that we don't have any more space in the WCID
1101          * table.
1102          */
1103         return -1;
1104 }
1105
1106 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1107                                struct rt2x00lib_crypto *crypto,
1108                                struct ieee80211_key_conf *key)
1109 {
1110         struct hw_key_entry key_entry;
1111         u32 offset;
1112
1113         if (crypto->cmd == SET_KEY) {
1114                 /*
1115                  * Allow key configuration only for STAs that are
1116                  * known by the hw.
1117                  */
1118                 if (crypto->wcid < 0)
1119                         return -ENOSPC;
1120                 key->hw_key_idx = crypto->wcid;
1121
1122                 memcpy(key_entry.key, crypto->key,
1123                        sizeof(key_entry.key));
1124                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1125                        sizeof(key_entry.tx_mic));
1126                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1127                        sizeof(key_entry.rx_mic));
1128
1129                 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1130                 rt2800_register_multiwrite(rt2x00dev, offset,
1131                                               &key_entry, sizeof(key_entry));
1132         }
1133
1134         /*
1135          * Update WCID information
1136          */
1137         rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1138
1139         return 0;
1140 }
1141 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1142
1143 int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif,
1144                    struct ieee80211_sta *sta)
1145 {
1146         int wcid;
1147         struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1148
1149         /*
1150          * Find next free WCID.
1151          */
1152         wcid = rt2800_find_wcid(rt2x00dev);
1153
1154         /*
1155          * Store selected wcid even if it is invalid so that we can
1156          * later decide if the STA is uploaded into the hw.
1157          */
1158         sta_priv->wcid = wcid;
1159
1160         /*
1161          * No space left in the device, however, we can still communicate
1162          * with the STA -> No error.
1163          */
1164         if (wcid < 0)
1165                 return 0;
1166
1167         /*
1168          * Clean up WCID attributes and write STA address to the device.
1169          */
1170         rt2800_delete_wcid_attr(rt2x00dev, wcid);
1171         rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1172         rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1173                                        rt2x00lib_get_bssidx(rt2x00dev, vif));
1174         return 0;
1175 }
1176 EXPORT_SYMBOL_GPL(rt2800_sta_add);
1177
1178 int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, int wcid)
1179 {
1180         /*
1181          * Remove WCID entry, no need to clean the attributes as they will
1182          * get renewed when the WCID is reused.
1183          */
1184         rt2800_config_wcid(rt2x00dev, NULL, wcid);
1185
1186         return 0;
1187 }
1188 EXPORT_SYMBOL_GPL(rt2800_sta_remove);
1189
1190 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1191                           const unsigned int filter_flags)
1192 {
1193         u32 reg;
1194
1195         /*
1196          * Start configuration steps.
1197          * Note that the version error will always be dropped
1198          * and broadcast frames will always be accepted since
1199          * there is no filter for it at this time.
1200          */
1201         rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1202         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1203                            !(filter_flags & FIF_FCSFAIL));
1204         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1205                            !(filter_flags & FIF_PLCPFAIL));
1206         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1207                            !(filter_flags & FIF_PROMISC_IN_BSS));
1208         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1209         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1210         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1211                            !(filter_flags & FIF_ALLMULTI));
1212         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1213         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1214         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1215                            !(filter_flags & FIF_CONTROL));
1216         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1217                            !(filter_flags & FIF_CONTROL));
1218         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1219                            !(filter_flags & FIF_CONTROL));
1220         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1221                            !(filter_flags & FIF_CONTROL));
1222         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1223                            !(filter_flags & FIF_CONTROL));
1224         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1225                            !(filter_flags & FIF_PSPOLL));
1226         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA,
1227                            !(filter_flags & FIF_CONTROL));
1228         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR,
1229                            !(filter_flags & FIF_CONTROL));
1230         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1231                            !(filter_flags & FIF_CONTROL));
1232         rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1233 }
1234 EXPORT_SYMBOL_GPL(rt2800_config_filter);
1235
1236 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1237                         struct rt2x00intf_conf *conf, const unsigned int flags)
1238 {
1239         u32 reg;
1240         bool update_bssid = false;
1241
1242         if (flags & CONFIG_UPDATE_TYPE) {
1243                 /*
1244                  * Enable synchronisation.
1245                  */
1246                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1247                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
1248                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1249
1250                 if (conf->sync == TSF_SYNC_AP_NONE) {
1251                         /*
1252                          * Tune beacon queue transmit parameters for AP mode
1253                          */
1254                         rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1255                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1256                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1257                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1258                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1259                         rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1260                 } else {
1261                         rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1262                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1263                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1264                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1265                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1266                         rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1267                 }
1268         }
1269
1270         if (flags & CONFIG_UPDATE_MAC) {
1271                 if (flags & CONFIG_UPDATE_TYPE &&
1272                     conf->sync == TSF_SYNC_AP_NONE) {
1273                         /*
1274                          * The BSSID register has to be set to our own mac
1275                          * address in AP mode.
1276                          */
1277                         memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1278                         update_bssid = true;
1279                 }
1280
1281                 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1282                         reg = le32_to_cpu(conf->mac[1]);
1283                         rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1284                         conf->mac[1] = cpu_to_le32(reg);
1285                 }
1286
1287                 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1288                                               conf->mac, sizeof(conf->mac));
1289         }
1290
1291         if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
1292                 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1293                         reg = le32_to_cpu(conf->bssid[1]);
1294                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1295                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1296                         conf->bssid[1] = cpu_to_le32(reg);
1297                 }
1298
1299                 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1300                                               conf->bssid, sizeof(conf->bssid));
1301         }
1302 }
1303 EXPORT_SYMBOL_GPL(rt2800_config_intf);
1304
1305 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1306                                     struct rt2x00lib_erp *erp)
1307 {
1308         bool any_sta_nongf = !!(erp->ht_opmode &
1309                                 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1310         u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1311         u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1312         u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1313         u32 reg;
1314
1315         /* default protection rate for HT20: OFDM 24M */
1316         mm20_rate = gf20_rate = 0x4004;
1317
1318         /* default protection rate for HT40: duplicate OFDM 24M */
1319         mm40_rate = gf40_rate = 0x4084;
1320
1321         switch (protection) {
1322         case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1323                 /*
1324                  * All STAs in this BSS are HT20/40 but there might be
1325                  * STAs not supporting greenfield mode.
1326                  * => Disable protection for HT transmissions.
1327                  */
1328                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1329
1330                 break;
1331         case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1332                 /*
1333                  * All STAs in this BSS are HT20 or HT20/40 but there
1334                  * might be STAs not supporting greenfield mode.
1335                  * => Protect all HT40 transmissions.
1336                  */
1337                 mm20_mode = gf20_mode = 0;
1338                 mm40_mode = gf40_mode = 2;
1339
1340                 break;
1341         case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1342                 /*
1343                  * Nonmember protection:
1344                  * According to 802.11n we _should_ protect all
1345                  * HT transmissions (but we don't have to).
1346                  *
1347                  * But if cts_protection is enabled we _shall_ protect
1348                  * all HT transmissions using a CCK rate.
1349                  *
1350                  * And if any station is non GF we _shall_ protect
1351                  * GF transmissions.
1352                  *
1353                  * We decide to protect everything
1354                  * -> fall through to mixed mode.
1355                  */
1356         case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1357                 /*
1358                  * Legacy STAs are present
1359                  * => Protect all HT transmissions.
1360                  */
1361                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1362
1363                 /*
1364                  * If erp protection is needed we have to protect HT
1365                  * transmissions with CCK 11M long preamble.
1366                  */
1367                 if (erp->cts_protection) {
1368                         /* don't duplicate RTS/CTS in CCK mode */
1369                         mm20_rate = mm40_rate = 0x0003;
1370                         gf20_rate = gf40_rate = 0x0003;
1371                 }
1372                 break;
1373         }
1374
1375         /* check for STAs not supporting greenfield mode */
1376         if (any_sta_nongf)
1377                 gf20_mode = gf40_mode = 2;
1378
1379         /* Update HT protection config */
1380         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1381         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1382         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1383         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1384
1385         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1386         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1387         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1388         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1389
1390         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1391         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1392         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1393         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1394
1395         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1396         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1397         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1398         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1399 }
1400
1401 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1402                        u32 changed)
1403 {
1404         u32 reg;
1405
1406         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1407                 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1408                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1409                                    !!erp->short_preamble);
1410                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1411                                    !!erp->short_preamble);
1412                 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1413         }
1414
1415         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1416                 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1417                 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1418                                    erp->cts_protection ? 2 : 0);
1419                 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1420         }
1421
1422         if (changed & BSS_CHANGED_BASIC_RATES) {
1423                 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1424                                          erp->basic_rates);
1425                 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1426         }
1427
1428         if (changed & BSS_CHANGED_ERP_SLOT) {
1429                 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1430                 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1431                                    erp->slot_time);
1432                 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1433
1434                 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1435                 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1436                 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1437         }
1438
1439         if (changed & BSS_CHANGED_BEACON_INT) {
1440                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1441                 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1442                                    erp->beacon_int * 16);
1443                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1444         }
1445
1446         if (changed & BSS_CHANGED_HT)
1447                 rt2800_config_ht_opmode(rt2x00dev, erp);
1448 }
1449 EXPORT_SYMBOL_GPL(rt2800_config_erp);
1450
1451 static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
1452 {
1453         u32 reg;
1454         u16 eeprom;
1455         u8 led_ctrl, led_g_mode, led_r_mode;
1456
1457         rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
1458         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1459                 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
1460                 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
1461         } else {
1462                 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
1463                 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
1464         }
1465         rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1466
1467         rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1468         led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
1469         led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
1470         if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
1471             led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
1472                 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1473                 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
1474                 if (led_ctrl == 0 || led_ctrl > 0x40) {
1475                         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
1476                         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
1477                         rt2800_register_write(rt2x00dev, LED_CFG, reg);
1478                 } else {
1479                         rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
1480                                            (led_g_mode << 2) | led_r_mode, 1);
1481                 }
1482         }
1483 }
1484
1485 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1486                                      enum antenna ant)
1487 {
1488         u32 reg;
1489         u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1490         u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1491
1492         if (rt2x00_is_pci(rt2x00dev)) {
1493                 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1494                 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1495                 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1496         } else if (rt2x00_is_usb(rt2x00dev))
1497                 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1498                                    eesk_pin, 0);
1499
1500         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
1501         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
1502         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, gpio_bit3);
1503         rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
1504 }
1505
1506 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1507 {
1508         u8 r1;
1509         u8 r3;
1510         u16 eeprom;
1511
1512         rt2800_bbp_read(rt2x00dev, 1, &r1);
1513         rt2800_bbp_read(rt2x00dev, 3, &r3);
1514
1515         if (rt2x00_rt(rt2x00dev, RT3572) &&
1516             test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1517                 rt2800_config_3572bt_ant(rt2x00dev);
1518
1519         /*
1520          * Configure the TX antenna.
1521          */
1522         switch (ant->tx_chain_num) {
1523         case 1:
1524                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1525                 break;
1526         case 2:
1527                 if (rt2x00_rt(rt2x00dev, RT3572) &&
1528                     test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1529                         rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
1530                 else
1531                         rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1532                 break;
1533         case 3:
1534                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1535                 break;
1536         }
1537
1538         /*
1539          * Configure the RX antenna.
1540          */
1541         switch (ant->rx_chain_num) {
1542         case 1:
1543                 if (rt2x00_rt(rt2x00dev, RT3070) ||
1544                     rt2x00_rt(rt2x00dev, RT3090) ||
1545                     rt2x00_rt(rt2x00dev, RT3390)) {
1546                         rt2x00_eeprom_read(rt2x00dev,
1547                                            EEPROM_NIC_CONF1, &eeprom);
1548                         if (rt2x00_get_field16(eeprom,
1549                                                 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1550                                 rt2800_set_ant_diversity(rt2x00dev,
1551                                                 rt2x00dev->default_ant.rx);
1552                 }
1553                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1554                 break;
1555         case 2:
1556                 if (rt2x00_rt(rt2x00dev, RT3572) &&
1557                     test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1558                         rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
1559                         rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
1560                                 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
1561                         rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
1562                 } else {
1563                         rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1564                 }
1565                 break;
1566         case 3:
1567                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1568                 break;
1569         }
1570
1571         rt2800_bbp_write(rt2x00dev, 3, r3);
1572         rt2800_bbp_write(rt2x00dev, 1, r1);
1573 }
1574 EXPORT_SYMBOL_GPL(rt2800_config_ant);
1575
1576 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1577                                    struct rt2x00lib_conf *libconf)
1578 {
1579         u16 eeprom;
1580         short lna_gain;
1581
1582         if (libconf->rf.channel <= 14) {
1583                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1584                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1585         } else if (libconf->rf.channel <= 64) {
1586                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1587                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1588         } else if (libconf->rf.channel <= 128) {
1589                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1590                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
1591         } else {
1592                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1593                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
1594         }
1595
1596         rt2x00dev->lna_gain = lna_gain;
1597 }
1598
1599 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1600                                          struct ieee80211_conf *conf,
1601                                          struct rf_channel *rf,
1602                                          struct channel_info *info)
1603 {
1604         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1605
1606         if (rt2x00dev->default_ant.tx_chain_num == 1)
1607                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1608
1609         if (rt2x00dev->default_ant.rx_chain_num == 1) {
1610                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1611                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1612         } else if (rt2x00dev->default_ant.rx_chain_num == 2)
1613                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1614
1615         if (rf->channel > 14) {
1616                 /*
1617                  * When TX power is below 0, we should increase it by 7 to
1618                  * make it a positive value (Minimum value is -7).
1619                  * However this means that values between 0 and 7 have
1620                  * double meaning, and we should set a 7DBm boost flag.
1621                  */
1622                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
1623                                    (info->default_power1 >= 0));
1624
1625                 if (info->default_power1 < 0)
1626                         info->default_power1 += 7;
1627
1628                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
1629
1630                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
1631                                    (info->default_power2 >= 0));
1632
1633                 if (info->default_power2 < 0)
1634                         info->default_power2 += 7;
1635
1636                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
1637         } else {
1638                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1639                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
1640         }
1641
1642         rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1643
1644         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1645         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1646         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1647         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1648
1649         udelay(200);
1650
1651         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1652         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1653         rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1654         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1655
1656         udelay(200);
1657
1658         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1659         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1660         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1661         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1662 }
1663
1664 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1665                                          struct ieee80211_conf *conf,
1666                                          struct rf_channel *rf,
1667                                          struct channel_info *info)
1668 {
1669         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1670         u8 rfcsr, calib_tx, calib_rx;
1671
1672         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1673
1674         rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
1675         rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
1676         rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
1677
1678         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1679         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1680         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1681
1682         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1683         rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
1684         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1685
1686         rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1687         rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
1688         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1689
1690         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1691         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1692         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1693         if (rt2x00_rt(rt2x00dev, RT3390)) {
1694                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
1695                                   rt2x00dev->default_ant.rx_chain_num == 1);
1696                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
1697                                   rt2x00dev->default_ant.tx_chain_num == 1);
1698         } else {
1699                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
1700                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
1701                 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
1702                 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
1703
1704                 switch (rt2x00dev->default_ant.tx_chain_num) {
1705                 case 1:
1706                         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
1707                         /* fall through */
1708                 case 2:
1709                         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1710                         break;
1711                 }
1712
1713                 switch (rt2x00dev->default_ant.rx_chain_num) {
1714                 case 1:
1715                         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
1716                         /* fall through */
1717                 case 2:
1718                         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1719                         break;
1720                 }
1721         }
1722         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1723
1724         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1725         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1726         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1727         msleep(1);
1728         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1729         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1730
1731         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1732         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1733         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1734
1735         if (rt2x00_rt(rt2x00dev, RT3390)) {
1736                 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f;
1737                 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f;
1738         } else {
1739                 if (conf_is_ht40(conf)) {
1740                         calib_tx = drv_data->calibration_bw40;
1741                         calib_rx = drv_data->calibration_bw40;
1742                 } else {
1743                         calib_tx = drv_data->calibration_bw20;
1744                         calib_rx = drv_data->calibration_bw20;
1745                 }
1746         }
1747
1748         rt2800_rfcsr_read(rt2x00dev, 24, &rfcsr);
1749         rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx);
1750         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
1751
1752         rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
1753         rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx);
1754         rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
1755
1756         rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1757         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1758         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1759
1760         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1761         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1762         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1763         msleep(1);
1764         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1765         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1766 }
1767
1768 static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
1769                                          struct ieee80211_conf *conf,
1770                                          struct rf_channel *rf,
1771                                          struct channel_info *info)
1772 {
1773         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1774         u8 rfcsr;
1775         u32 reg;
1776
1777         if (rf->channel <= 14) {
1778                 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
1779                 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
1780         } else {
1781                 rt2800_bbp_write(rt2x00dev, 25, 0x09);
1782                 rt2800_bbp_write(rt2x00dev, 26, 0xff);
1783         }
1784
1785         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1786         rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
1787
1788         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1789         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1790         if (rf->channel <= 14)
1791                 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
1792         else
1793                 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
1794         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1795
1796         rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr);
1797         if (rf->channel <= 14)
1798                 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
1799         else
1800                 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
1801         rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
1802
1803         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1804         if (rf->channel <= 14) {
1805                 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
1806                 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1807                                   info->default_power1);
1808         } else {
1809                 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
1810                 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1811                                 (info->default_power1 & 0x3) |
1812                                 ((info->default_power1 & 0xC) << 1));
1813         }
1814         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1815
1816         rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1817         if (rf->channel <= 14) {
1818                 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
1819                 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1820                                   info->default_power2);
1821         } else {
1822                 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
1823                 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1824                                 (info->default_power2 & 0x3) |
1825                                 ((info->default_power2 & 0xC) << 1));
1826         }
1827         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1828
1829         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1830         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1831         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1832         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
1833         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
1834         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
1835         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
1836         if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1837                 if (rf->channel <= 14) {
1838                         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
1839                         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
1840                 }
1841                 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1842                 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1843         } else {
1844                 switch (rt2x00dev->default_ant.tx_chain_num) {
1845                 case 1:
1846                         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
1847                 case 2:
1848                         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1849                         break;
1850                 }
1851
1852                 switch (rt2x00dev->default_ant.rx_chain_num) {
1853                 case 1:
1854                         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
1855                 case 2:
1856                         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1857                         break;
1858                 }
1859         }
1860         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1861
1862         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1863         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1864         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1865
1866         if (conf_is_ht40(conf)) {
1867                 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
1868                 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
1869         } else {
1870                 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
1871                 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
1872         }
1873
1874         if (rf->channel <= 14) {
1875                 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
1876                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
1877                 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1878                 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
1879                 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
1880                 rfcsr = 0x4c;
1881                 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
1882                                   drv_data->txmixer_gain_24g);
1883                 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
1884                 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1885                 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
1886                 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
1887                 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
1888                 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
1889                 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
1890                 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
1891         } else {
1892                 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1893                 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1);
1894                 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0);
1895                 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1);
1896                 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0);
1897                 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1898                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
1899                 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1900                 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
1901                 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
1902                 rfcsr = 0x7a;
1903                 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
1904                                   drv_data->txmixer_gain_5g);
1905                 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
1906                 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1907                 if (rf->channel <= 64) {
1908                         rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
1909                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
1910                         rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
1911                 } else if (rf->channel <= 128) {
1912                         rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
1913                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
1914                         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1915                 } else {
1916                         rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
1917                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
1918                         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1919                 }
1920                 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
1921                 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
1922                 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
1923         }
1924
1925         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
1926         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT7, 0);
1927         if (rf->channel <= 14)
1928                 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT7, 1);
1929         else
1930                 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT7, 0);
1931         rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
1932
1933         rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1934         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1935         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1936 }
1937
1938 #define RT5390_POWER_BOUND     0x27
1939 #define RT5390_FREQ_OFFSET_BOUND       0x5f
1940
1941 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
1942                                          struct ieee80211_conf *conf,
1943                                          struct rf_channel *rf,
1944                                          struct channel_info *info)
1945 {
1946         u8 rfcsr;
1947
1948         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
1949         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
1950         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
1951         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
1952         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
1953
1954         rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
1955         if (info->default_power1 > RT5390_POWER_BOUND)
1956                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, RT5390_POWER_BOUND);
1957         else
1958                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
1959         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
1960
1961         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1962         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
1963         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
1964         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
1965         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
1966         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1967
1968         rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1969         if (rt2x00dev->freq_offset > RT5390_FREQ_OFFSET_BOUND)
1970                 rt2x00_set_field8(&rfcsr, RFCSR17_CODE,
1971                                   RT5390_FREQ_OFFSET_BOUND);
1972         else
1973                 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
1974         rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
1975
1976         if (rf->channel <= 14) {
1977                 int idx = rf->channel-1;
1978
1979                 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1980                         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
1981                                 /* r55/r59 value array of channel 1~14 */
1982                                 static const char r55_bt_rev[] = {0x83, 0x83,
1983                                         0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
1984                                         0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
1985                                 static const char r59_bt_rev[] = {0x0e, 0x0e,
1986                                         0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
1987                                         0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
1988
1989                                 rt2800_rfcsr_write(rt2x00dev, 55,
1990                                                    r55_bt_rev[idx]);
1991                                 rt2800_rfcsr_write(rt2x00dev, 59,
1992                                                    r59_bt_rev[idx]);
1993                         } else {
1994                                 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
1995                                         0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
1996                                         0x88, 0x88, 0x86, 0x85, 0x84};
1997
1998                                 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
1999                         }
2000                 } else {
2001                         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2002                                 static const char r55_nonbt_rev[] = {0x23, 0x23,
2003                                         0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
2004                                         0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
2005                                 static const char r59_nonbt_rev[] = {0x07, 0x07,
2006                                         0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
2007                                         0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
2008
2009                                 rt2800_rfcsr_write(rt2x00dev, 55,
2010                                                    r55_nonbt_rev[idx]);
2011                                 rt2800_rfcsr_write(rt2x00dev, 59,
2012                                                    r59_nonbt_rev[idx]);
2013                         } else if (rt2x00_rt(rt2x00dev, RT5390) ||
2014                                            rt2x00_rt(rt2x00dev, RT5392)) {
2015                                 static const char r59_non_bt[] = {0x8f, 0x8f,
2016                                         0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
2017                                         0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
2018
2019                                 rt2800_rfcsr_write(rt2x00dev, 59,
2020                                                    r59_non_bt[idx]);
2021                         }
2022                 }
2023         }
2024
2025         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2026         rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
2027         rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
2028         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2029
2030         rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2031         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2032         rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2033 }
2034
2035 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
2036                                   struct ieee80211_conf *conf,
2037                                   struct rf_channel *rf,
2038                                   struct channel_info *info)
2039 {
2040         u32 reg;
2041         unsigned int tx_pin;
2042         u8 bbp;
2043
2044         if (rf->channel <= 14) {
2045                 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
2046                 info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2);
2047         } else {
2048                 info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1);
2049                 info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2);
2050         }
2051
2052         switch (rt2x00dev->chip.rf) {
2053         case RF2020:
2054         case RF3020:
2055         case RF3021:
2056         case RF3022:
2057         case RF3320:
2058                 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
2059                 break;
2060         case RF3052:
2061                 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
2062                 break;
2063         case RF5370:
2064         case RF5372:
2065         case RF5390:
2066                 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
2067                 break;
2068         default:
2069                 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
2070         }
2071
2072         /*
2073          * Change BBP settings
2074          */
2075         rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
2076         rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
2077         rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
2078         rt2800_bbp_write(rt2x00dev, 86, 0);
2079
2080         if (rf->channel <= 14) {
2081                 if (!rt2x00_rt(rt2x00dev, RT5390) &&
2082                         !rt2x00_rt(rt2x00dev, RT5392)) {
2083                         if (test_bit(CAPABILITY_EXTERNAL_LNA_BG,
2084                                      &rt2x00dev->cap_flags)) {
2085                                 rt2800_bbp_write(rt2x00dev, 82, 0x62);
2086                                 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2087                         } else {
2088                                 rt2800_bbp_write(rt2x00dev, 82, 0x84);
2089                                 rt2800_bbp_write(rt2x00dev, 75, 0x50);
2090                         }
2091                 }
2092         } else {
2093                 if (rt2x00_rt(rt2x00dev, RT3572))
2094                         rt2800_bbp_write(rt2x00dev, 82, 0x94);
2095                 else
2096                         rt2800_bbp_write(rt2x00dev, 82, 0xf2);
2097
2098                 if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags))
2099                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
2100                 else
2101                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
2102         }
2103
2104         rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
2105         rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
2106         rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
2107         rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
2108         rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
2109
2110         if (rt2x00_rt(rt2x00dev, RT3572))
2111                 rt2800_rfcsr_write(rt2x00dev, 8, 0);
2112
2113         tx_pin = 0;
2114
2115         /* Turn on unused PA or LNA when not using 1T or 1R */
2116         if (rt2x00dev->default_ant.tx_chain_num == 2) {
2117                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
2118                                    rf->channel > 14);
2119                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
2120                                    rf->channel <= 14);
2121         }
2122
2123         /* Turn on unused PA or LNA when not using 1T or 1R */
2124         if (rt2x00dev->default_ant.rx_chain_num == 2) {
2125                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
2126                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
2127         }
2128
2129         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
2130         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
2131         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
2132         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
2133         if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
2134                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
2135         else
2136                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
2137                                    rf->channel <= 14);
2138         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
2139
2140         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
2141
2142         if (rt2x00_rt(rt2x00dev, RT3572))
2143                 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
2144
2145         rt2800_bbp_read(rt2x00dev, 4, &bbp);
2146         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
2147         rt2800_bbp_write(rt2x00dev, 4, bbp);
2148
2149         rt2800_bbp_read(rt2x00dev, 3, &bbp);
2150         rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
2151         rt2800_bbp_write(rt2x00dev, 3, bbp);
2152
2153         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
2154                 if (conf_is_ht40(conf)) {
2155                         rt2800_bbp_write(rt2x00dev, 69, 0x1a);
2156                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
2157                         rt2800_bbp_write(rt2x00dev, 73, 0x16);
2158                 } else {
2159                         rt2800_bbp_write(rt2x00dev, 69, 0x16);
2160                         rt2800_bbp_write(rt2x00dev, 70, 0x08);
2161                         rt2800_bbp_write(rt2x00dev, 73, 0x11);
2162                 }
2163         }
2164
2165         msleep(1);
2166
2167         /*
2168          * Clear channel statistic counters
2169          */
2170         rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
2171         rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
2172         rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
2173 }
2174
2175 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
2176 {
2177         u8 tssi_bounds[9];
2178         u8 current_tssi;
2179         u16 eeprom;
2180         u8 step;
2181         int i;
2182
2183         /*
2184          * Read TSSI boundaries for temperature compensation from
2185          * the EEPROM.
2186          *
2187          * Array idx               0    1    2    3    4    5    6    7    8
2188          * Matching Delta value   -4   -3   -2   -1    0   +1   +2   +3   +4
2189          * Example TSSI bounds  0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
2190          */
2191         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
2192                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
2193                 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2194                                         EEPROM_TSSI_BOUND_BG1_MINUS4);
2195                 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2196                                         EEPROM_TSSI_BOUND_BG1_MINUS3);
2197
2198                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
2199                 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2200                                         EEPROM_TSSI_BOUND_BG2_MINUS2);
2201                 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2202                                         EEPROM_TSSI_BOUND_BG2_MINUS1);
2203
2204                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
2205                 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2206                                         EEPROM_TSSI_BOUND_BG3_REF);
2207                 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2208                                         EEPROM_TSSI_BOUND_BG3_PLUS1);
2209
2210                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
2211                 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2212                                         EEPROM_TSSI_BOUND_BG4_PLUS2);
2213                 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2214                                         EEPROM_TSSI_BOUND_BG4_PLUS3);
2215
2216                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
2217                 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2218                                         EEPROM_TSSI_BOUND_BG5_PLUS4);
2219
2220                 step = rt2x00_get_field16(eeprom,
2221                                           EEPROM_TSSI_BOUND_BG5_AGC_STEP);
2222         } else {
2223                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
2224                 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2225                                         EEPROM_TSSI_BOUND_A1_MINUS4);
2226                 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2227                                         EEPROM_TSSI_BOUND_A1_MINUS3);
2228
2229                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
2230                 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2231                                         EEPROM_TSSI_BOUND_A2_MINUS2);
2232                 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2233                                         EEPROM_TSSI_BOUND_A2_MINUS1);
2234
2235                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
2236                 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2237                                         EEPROM_TSSI_BOUND_A3_REF);
2238                 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2239                                         EEPROM_TSSI_BOUND_A3_PLUS1);
2240
2241                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
2242                 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2243                                         EEPROM_TSSI_BOUND_A4_PLUS2);
2244                 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2245                                         EEPROM_TSSI_BOUND_A4_PLUS3);
2246
2247                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
2248                 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2249                                         EEPROM_TSSI_BOUND_A5_PLUS4);
2250
2251                 step = rt2x00_get_field16(eeprom,
2252                                           EEPROM_TSSI_BOUND_A5_AGC_STEP);
2253         }
2254
2255         /*
2256          * Check if temperature compensation is supported.
2257          */
2258         if (tssi_bounds[4] == 0xff)
2259                 return 0;
2260
2261         /*
2262          * Read current TSSI (BBP 49).
2263          */
2264         rt2800_bbp_read(rt2x00dev, 49, &current_tssi);
2265
2266         /*
2267          * Compare TSSI value (BBP49) with the compensation boundaries
2268          * from the EEPROM and increase or decrease tx power.
2269          */
2270         for (i = 0; i <= 3; i++) {
2271                 if (current_tssi > tssi_bounds[i])
2272                         break;
2273         }
2274
2275         if (i == 4) {
2276                 for (i = 8; i >= 5; i--) {
2277                         if (current_tssi < tssi_bounds[i])
2278                                 break;
2279                 }
2280         }
2281
2282         return (i - 4) * step;
2283 }
2284
2285 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
2286                                       enum ieee80211_band band)
2287 {
2288         u16 eeprom;
2289         u8 comp_en;
2290         u8 comp_type;
2291         int comp_value = 0;
2292
2293         rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
2294
2295         /*
2296          * HT40 compensation not required.
2297          */
2298         if (eeprom == 0xffff ||
2299             !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
2300                 return 0;
2301
2302         if (band == IEEE80211_BAND_2GHZ) {
2303                 comp_en = rt2x00_get_field16(eeprom,
2304                                  EEPROM_TXPOWER_DELTA_ENABLE_2G);
2305                 if (comp_en) {
2306                         comp_type = rt2x00_get_field16(eeprom,
2307                                            EEPROM_TXPOWER_DELTA_TYPE_2G);
2308                         comp_value = rt2x00_get_field16(eeprom,
2309                                             EEPROM_TXPOWER_DELTA_VALUE_2G);
2310                         if (!comp_type)
2311                                 comp_value = -comp_value;
2312                 }
2313         } else {
2314                 comp_en = rt2x00_get_field16(eeprom,
2315                                  EEPROM_TXPOWER_DELTA_ENABLE_5G);
2316                 if (comp_en) {
2317                         comp_type = rt2x00_get_field16(eeprom,
2318                                            EEPROM_TXPOWER_DELTA_TYPE_5G);
2319                         comp_value = rt2x00_get_field16(eeprom,
2320                                             EEPROM_TXPOWER_DELTA_VALUE_5G);
2321                         if (!comp_type)
2322                                 comp_value = -comp_value;
2323                 }
2324         }
2325
2326         return comp_value;
2327 }
2328
2329 static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
2330                                    enum ieee80211_band band, int power_level,
2331                                    u8 txpower, int delta)
2332 {
2333         u32 reg;
2334         u16 eeprom;
2335         u8 criterion;
2336         u8 eirp_txpower;
2337         u8 eirp_txpower_criterion;
2338         u8 reg_limit;
2339
2340         if (!((band == IEEE80211_BAND_5GHZ) && is_rate_b))
2341                 return txpower;
2342
2343         if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags)) {
2344                 /*
2345                  * Check if eirp txpower exceed txpower_limit.
2346                  * We use OFDM 6M as criterion and its eirp txpower
2347                  * is stored at EEPROM_EIRP_MAX_TX_POWER.
2348                  * .11b data rate need add additional 4dbm
2349                  * when calculating eirp txpower.
2350                  */
2351                 rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
2352                 criterion = rt2x00_get_field32(reg, TX_PWR_CFG_0_6MBS);
2353
2354                 rt2x00_eeprom_read(rt2x00dev,
2355                                    EEPROM_EIRP_MAX_TX_POWER, &eeprom);
2356
2357                 if (band == IEEE80211_BAND_2GHZ)
2358                         eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2359                                                  EEPROM_EIRP_MAX_TX_POWER_2GHZ);
2360                 else
2361                         eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2362                                                  EEPROM_EIRP_MAX_TX_POWER_5GHZ);
2363
2364                 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
2365                                (is_rate_b ? 4 : 0) + delta;
2366
2367                 reg_limit = (eirp_txpower > power_level) ?
2368                                         (eirp_txpower - power_level) : 0;
2369         } else
2370                 reg_limit = 0;
2371
2372         return txpower + delta - reg_limit;
2373 }
2374
2375 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
2376                                   enum ieee80211_band band,
2377                                   int power_level)
2378 {
2379         u8 txpower;
2380         u16 eeprom;
2381         int i, is_rate_b;
2382         u32 reg;
2383         u8 r1;
2384         u32 offset;
2385         int delta;
2386
2387         /*
2388          * Calculate HT40 compensation delta
2389          */
2390         delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
2391
2392         /*
2393          * calculate temperature compensation delta
2394          */
2395         delta += rt2800_get_gain_calibration_delta(rt2x00dev);
2396
2397         /*
2398          * set to normal bbp tx power control mode: +/- 0dBm
2399          */
2400         rt2800_bbp_read(rt2x00dev, 1, &r1);
2401         rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, 0);
2402         rt2800_bbp_write(rt2x00dev, 1, r1);
2403         offset = TX_PWR_CFG_0;
2404
2405         for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
2406                 /* just to be safe */
2407                 if (offset > TX_PWR_CFG_4)
2408                         break;
2409
2410                 rt2800_register_read(rt2x00dev, offset, &reg);
2411
2412                 /* read the next four txpower values */
2413                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
2414                                    &eeprom);
2415
2416                 is_rate_b = i ? 0 : 1;
2417                 /*
2418                  * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
2419                  * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
2420                  * TX_PWR_CFG_4: unknown
2421                  */
2422                 txpower = rt2x00_get_field16(eeprom,
2423                                              EEPROM_TXPOWER_BYRATE_RATE0);
2424                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2425                                              power_level, txpower, delta);
2426                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
2427
2428                 /*
2429                  * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
2430                  * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
2431                  * TX_PWR_CFG_4: unknown
2432                  */
2433                 txpower = rt2x00_get_field16(eeprom,
2434                                              EEPROM_TXPOWER_BYRATE_RATE1);
2435                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2436                                              power_level, txpower, delta);
2437                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
2438
2439                 /*
2440                  * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
2441                  * TX_PWR_CFG_2: MCS6,  TX_PWR_CFG_3: MCS14,
2442                  * TX_PWR_CFG_4: unknown
2443                  */
2444                 txpower = rt2x00_get_field16(eeprom,
2445                                              EEPROM_TXPOWER_BYRATE_RATE2);
2446                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2447                                              power_level, txpower, delta);
2448                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
2449
2450                 /*
2451                  * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
2452                  * TX_PWR_CFG_2: MCS7,  TX_PWR_CFG_3: MCS15,
2453                  * TX_PWR_CFG_4: unknown
2454                  */
2455                 txpower = rt2x00_get_field16(eeprom,
2456                                              EEPROM_TXPOWER_BYRATE_RATE3);
2457                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2458                                              power_level, txpower, delta);
2459                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
2460
2461                 /* read the next four txpower values */
2462                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
2463                                    &eeprom);
2464
2465                 is_rate_b = 0;
2466                 /*
2467                  * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
2468                  * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
2469                  * TX_PWR_CFG_4: unknown
2470                  */
2471                 txpower = rt2x00_get_field16(eeprom,
2472                                              EEPROM_TXPOWER_BYRATE_RATE0);
2473                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2474                                              power_level, txpower, delta);
2475                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
2476
2477                 /*
2478                  * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
2479                  * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
2480                  * TX_PWR_CFG_4: unknown
2481                  */
2482                 txpower = rt2x00_get_field16(eeprom,
2483                                              EEPROM_TXPOWER_BYRATE_RATE1);
2484                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2485                                              power_level, txpower, delta);
2486                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
2487
2488                 /*
2489                  * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
2490                  * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
2491                  * TX_PWR_CFG_4: unknown
2492                  */
2493                 txpower = rt2x00_get_field16(eeprom,
2494                                              EEPROM_TXPOWER_BYRATE_RATE2);
2495                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2496                                              power_level, txpower, delta);
2497                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
2498
2499                 /*
2500                  * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
2501                  * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
2502                  * TX_PWR_CFG_4: unknown
2503                  */
2504                 txpower = rt2x00_get_field16(eeprom,
2505                                              EEPROM_TXPOWER_BYRATE_RATE3);
2506                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2507                                              power_level, txpower, delta);
2508                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
2509
2510                 rt2800_register_write(rt2x00dev, offset, reg);
2511
2512                 /* next TX_PWR_CFG register */
2513                 offset += 4;
2514         }
2515 }
2516
2517 void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
2518 {
2519         rt2800_config_txpower(rt2x00dev, rt2x00dev->curr_band,
2520                               rt2x00dev->tx_power);
2521 }
2522 EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
2523
2524 void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
2525 {
2526         u32     tx_pin;
2527         u8      rfcsr;
2528
2529         /*
2530          * A voltage-controlled oscillator(VCO) is an electronic oscillator
2531          * designed to be controlled in oscillation frequency by a voltage
2532          * input. Maybe the temperature will affect the frequency of
2533          * oscillation to be shifted. The VCO calibration will be called
2534          * periodically to adjust the frequency to be precision.
2535         */
2536
2537         rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
2538         tx_pin &= TX_PIN_CFG_PA_PE_DISABLE;
2539         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
2540
2541         switch (rt2x00dev->chip.rf) {
2542         case RF2020:
2543         case RF3020:
2544         case RF3021:
2545         case RF3022:
2546         case RF3320:
2547         case RF3052:
2548                 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2549                 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2550                 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2551                 break;
2552         case RF5370:
2553         case RF5372:
2554         case RF5390:
2555                 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2556                 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2557                 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2558                 break;
2559         default:
2560                 return;
2561         }
2562
2563         mdelay(1);
2564
2565         rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
2566         if (rt2x00dev->rf_channel <= 14) {
2567                 switch (rt2x00dev->default_ant.tx_chain_num) {
2568                 case 3:
2569                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1);
2570                         /* fall through */
2571                 case 2:
2572                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
2573                         /* fall through */
2574                 case 1:
2575                 default:
2576                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
2577                         break;
2578                 }
2579         } else {
2580                 switch (rt2x00dev->default_ant.tx_chain_num) {
2581                 case 3:
2582                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1);
2583                         /* fall through */
2584                 case 2:
2585                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
2586                         /* fall through */
2587                 case 1:
2588                 default:
2589                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
2590                         break;
2591                 }
2592         }
2593         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
2594
2595 }
2596 EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
2597
2598 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
2599                                       struct rt2x00lib_conf *libconf)
2600 {
2601         u32 reg;
2602
2603         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
2604         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
2605                            libconf->conf->short_frame_max_tx_count);
2606         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
2607                            libconf->conf->long_frame_max_tx_count);
2608         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
2609 }
2610
2611 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
2612                              struct rt2x00lib_conf *libconf)
2613 {
2614         enum dev_state state =
2615             (libconf->conf->flags & IEEE80211_CONF_PS) ?
2616                 STATE_SLEEP : STATE_AWAKE;
2617         u32 reg;
2618
2619         if (state == STATE_SLEEP) {
2620                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
2621
2622                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
2623                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
2624                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
2625                                    libconf->conf->listen_interval - 1);
2626                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
2627                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
2628
2629                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
2630         } else {
2631                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
2632                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
2633                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
2634                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
2635                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
2636
2637                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
2638         }
2639 }
2640
2641 void rt2800_config(struct rt2x00_dev *rt2x00dev,
2642                    struct rt2x00lib_conf *libconf,
2643                    const unsigned int flags)
2644 {
2645         /* Always recalculate LNA gain before changing configuration */
2646         rt2800_config_lna_gain(rt2x00dev, libconf);
2647
2648         if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
2649                 rt2800_config_channel(rt2x00dev, libconf->conf,
2650                                       &libconf->rf, &libconf->channel);
2651                 rt2800_config_txpower(rt2x00dev, libconf->conf->channel->band,
2652                                       libconf->conf->power_level);
2653         }
2654         if (flags & IEEE80211_CONF_CHANGE_POWER)
2655                 rt2800_config_txpower(rt2x00dev, libconf->conf->channel->band,
2656                                       libconf->conf->power_level);
2657         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
2658                 rt2800_config_retry_limit(rt2x00dev, libconf);
2659         if (flags & IEEE80211_CONF_CHANGE_PS)
2660                 rt2800_config_ps(rt2x00dev, libconf);
2661 }
2662 EXPORT_SYMBOL_GPL(rt2800_config);
2663
2664 /*
2665  * Link tuning
2666  */
2667 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
2668 {
2669         u32 reg;
2670
2671         /*
2672          * Update FCS error count from register.
2673          */
2674         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
2675         qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
2676 }
2677 EXPORT_SYMBOL_GPL(rt2800_link_stats);
2678
2679 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
2680 {
2681         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
2682                 if (rt2x00_rt(rt2x00dev, RT3070) ||
2683                     rt2x00_rt(rt2x00dev, RT3071) ||
2684                     rt2x00_rt(rt2x00dev, RT3090) ||
2685                     rt2x00_rt(rt2x00dev, RT3390) ||
2686                     rt2x00_rt(rt2x00dev, RT5390) ||
2687                     rt2x00_rt(rt2x00dev, RT5392))
2688                         return 0x1c + (2 * rt2x00dev->lna_gain);
2689                 else
2690                         return 0x2e + rt2x00dev->lna_gain;
2691         }
2692
2693         if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
2694                 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
2695         else
2696                 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
2697 }
2698
2699 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
2700                                   struct link_qual *qual, u8 vgc_level)
2701 {
2702         if (qual->vgc_level != vgc_level) {
2703                 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
2704                 qual->vgc_level = vgc_level;
2705                 qual->vgc_level_reg = vgc_level;
2706         }
2707 }
2708
2709 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
2710 {
2711         rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
2712 }
2713 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
2714
2715 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
2716                        const u32 count)
2717 {
2718         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
2719                 return;
2720
2721         /*
2722          * When RSSI is better then -80 increase VGC level with 0x10
2723          */
2724         rt2800_set_vgc(rt2x00dev, qual,
2725                        rt2800_get_default_vgc(rt2x00dev) +
2726                        ((qual->rssi > -80) * 0x10));
2727 }
2728 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
2729
2730 /*
2731  * Initialization functions.
2732  */
2733 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
2734 {
2735         u32 reg;
2736         u16 eeprom;
2737         unsigned int i;
2738         int ret;
2739
2740         rt2800_disable_wpdma(rt2x00dev);
2741
2742         ret = rt2800_drv_init_registers(rt2x00dev);
2743         if (ret)
2744                 return ret;
2745
2746         rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
2747         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
2748         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
2749         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
2750         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
2751         rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
2752
2753         rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
2754         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
2755         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
2756         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
2757         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
2758         rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
2759
2760         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
2761         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
2762
2763         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
2764
2765         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2766         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
2767         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
2768         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
2769         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
2770         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
2771         rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
2772         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2773
2774         rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
2775
2776         rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
2777         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
2778         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
2779         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
2780
2781         if (rt2x00_rt(rt2x00dev, RT3071) ||
2782             rt2x00_rt(rt2x00dev, RT3090) ||
2783             rt2x00_rt(rt2x00dev, RT3390)) {
2784                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2785                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2786                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2787                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2788                     rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
2789                         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2790                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
2791                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
2792                                                       0x0000002c);
2793                         else
2794                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
2795                                                       0x0000000f);
2796                 } else {
2797                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2798                 }
2799         } else if (rt2x00_rt(rt2x00dev, RT3070)) {
2800                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2801
2802                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
2803                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2804                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
2805                 } else {
2806                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2807                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2808                 }
2809         } else if (rt2800_is_305x_soc(rt2x00dev)) {
2810                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2811                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2812                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
2813         } else if (rt2x00_rt(rt2x00dev, RT3572)) {
2814                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2815                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2816         } else if (rt2x00_rt(rt2x00dev, RT5390) ||
2817                            rt2x00_rt(rt2x00dev, RT5392)) {
2818                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
2819                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2820                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2821         } else {
2822                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
2823                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2824         }
2825
2826         rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
2827         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
2828         rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
2829         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
2830         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
2831         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
2832         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
2833         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
2834         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
2835         rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
2836
2837         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
2838         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
2839         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
2840         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
2841         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
2842
2843         rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
2844         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
2845         if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
2846             rt2x00_rt(rt2x00dev, RT2883) ||
2847             rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
2848                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
2849         else
2850                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
2851         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
2852         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
2853         rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
2854
2855         rt2800_register_read(rt2x00dev, LED_CFG, &reg);
2856         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
2857         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
2858         rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
2859         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
2860         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
2861         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
2862         rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
2863         rt2800_register_write(rt2x00dev, LED_CFG, reg);
2864
2865         rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
2866
2867         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
2868         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
2869         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
2870         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
2871         rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
2872         rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
2873         rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
2874         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
2875
2876         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
2877         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
2878         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
2879         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
2880         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
2881         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
2882         rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
2883         rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
2884         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
2885
2886         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2887         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
2888         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
2889         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
2890         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2891         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2892         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2893         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2894         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2895         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2896         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
2897         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2898
2899         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2900         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
2901         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
2902         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
2903         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2904         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2905         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2906         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2907         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2908         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2909         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
2910         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2911
2912         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2913         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
2914         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
2915         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
2916         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2917         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2918         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2919         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2920         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2921         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2922         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
2923         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2924
2925         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2926         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
2927         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
2928         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
2929         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2930         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2931         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2932         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2933         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2934         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
2935         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
2936         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2937
2938         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2939         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
2940         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
2941         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
2942         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2943         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2944         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2945         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2946         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2947         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2948         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
2949         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2950
2951         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2952         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
2953         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
2954         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
2955         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2956         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2957         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2958         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2959         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2960         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
2961         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
2962         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2963
2964         if (rt2x00_is_usb(rt2x00dev)) {
2965                 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
2966
2967                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2968                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2969                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2970                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2971                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2972                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
2973                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
2974                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
2975                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
2976                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
2977                 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2978         }
2979
2980         /*
2981          * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
2982          * although it is reserved.
2983          */
2984         rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
2985         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
2986         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
2987         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
2988         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
2989         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
2990         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
2991         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
2992         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
2993         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
2994         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
2995         rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
2996
2997         rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
2998
2999         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
3000         rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
3001         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
3002                            IEEE80211_MAX_RTS_THRESHOLD);
3003         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
3004         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
3005
3006         rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
3007
3008         /*
3009          * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
3010          * time should be set to 16. However, the original Ralink driver uses
3011          * 16 for both and indeed using a value of 10 for CCK SIFS results in
3012          * connection problems with 11g + CTS protection. Hence, use the same
3013          * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
3014          */
3015         rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
3016         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
3017         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
3018         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
3019         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
3020         rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
3021         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
3022
3023         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
3024
3025         /*
3026          * ASIC will keep garbage value after boot, clear encryption keys.
3027          */
3028         for (i = 0; i < 4; i++)
3029                 rt2800_register_write(rt2x00dev,
3030                                          SHARED_KEY_MODE_ENTRY(i), 0);
3031
3032         for (i = 0; i < 256; i++) {
3033                 rt2800_config_wcid(rt2x00dev, NULL, i);
3034                 rt2800_delete_wcid_attr(rt2x00dev, i);
3035                 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
3036         }
3037
3038         /*
3039          * Clear all beacons
3040          */
3041         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE0);
3042         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE1);
3043         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE2);
3044         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE3);
3045         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE4);
3046         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE5);
3047         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE6);
3048         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE7);
3049
3050         if (rt2x00_is_usb(rt2x00dev)) {
3051                 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
3052                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
3053                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
3054         } else if (rt2x00_is_pcie(rt2x00dev)) {
3055                 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
3056                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
3057                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
3058         }
3059
3060         rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
3061         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
3062         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
3063         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
3064         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
3065         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
3066         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
3067         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
3068         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
3069         rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
3070
3071         rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
3072         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
3073         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
3074         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
3075         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
3076         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
3077         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
3078         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
3079         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
3080         rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
3081
3082         rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
3083         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
3084         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
3085         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
3086         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
3087         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
3088         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
3089         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
3090         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
3091         rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
3092
3093         rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
3094         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
3095         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
3096         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
3097         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
3098         rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
3099
3100         /*
3101          * Do not force the BA window size, we use the TXWI to set it
3102          */
3103         rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
3104         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
3105         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
3106         rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
3107
3108         /*
3109          * We must clear the error counters.
3110          * These registers are cleared on read,
3111          * so we may pass a useless variable to store the value.
3112          */
3113         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
3114         rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
3115         rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
3116         rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
3117         rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
3118         rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
3119
3120         /*
3121          * Setup leadtime for pre tbtt interrupt to 6ms
3122          */
3123         rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
3124         rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
3125         rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
3126
3127         /*
3128          * Set up channel statistics timer
3129          */
3130         rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
3131         rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
3132         rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
3133         rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
3134         rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
3135         rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
3136         rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
3137
3138         return 0;
3139 }
3140
3141 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
3142 {
3143         unsigned int i;
3144         u32 reg;
3145
3146         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3147                 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
3148                 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
3149                         return 0;
3150
3151                 udelay(REGISTER_BUSY_DELAY);
3152         }
3153
3154         ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
3155         return -EACCES;
3156 }
3157
3158 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
3159 {
3160         unsigned int i;
3161         u8 value;
3162
3163         /*
3164          * BBP was enabled after firmware was loaded,
3165          * but we need to reactivate it now.
3166          */
3167         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
3168         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
3169         msleep(1);
3170
3171         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3172                 rt2800_bbp_read(rt2x00dev, 0, &value);
3173                 if ((value != 0xff) && (value != 0x00))
3174                         return 0;
3175                 udelay(REGISTER_BUSY_DELAY);
3176         }
3177
3178         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
3179         return -EACCES;
3180 }
3181
3182 static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
3183 {
3184         unsigned int i;
3185         u16 eeprom;
3186         u8 reg_id;
3187         u8 value;
3188
3189         if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
3190                      rt2800_wait_bbp_ready(rt2x00dev)))
3191                 return -EACCES;
3192
3193         if (rt2x00_rt(rt2x00dev, RT5390) ||
3194                 rt2x00_rt(rt2x00dev, RT5392)) {
3195                 rt2800_bbp_read(rt2x00dev, 4, &value);
3196                 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
3197                 rt2800_bbp_write(rt2x00dev, 4, value);
3198         }
3199
3200         if (rt2800_is_305x_soc(rt2x00dev) ||
3201             rt2x00_rt(rt2x00dev, RT3572) ||
3202             rt2x00_rt(rt2x00dev, RT5390) ||
3203             rt2x00_rt(rt2x00dev, RT5392))
3204                 rt2800_bbp_write(rt2x00dev, 31, 0x08);
3205
3206         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
3207         rt2800_bbp_write(rt2x00dev, 66, 0x38);
3208
3209         if (rt2x00_rt(rt2x00dev, RT5390) ||
3210                 rt2x00_rt(rt2x00dev, RT5392))
3211                 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
3212
3213         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
3214                 rt2800_bbp_write(rt2x00dev, 69, 0x16);
3215                 rt2800_bbp_write(rt2x00dev, 73, 0x12);
3216         } else if (rt2x00_rt(rt2x00dev, RT5390) ||
3217                            rt2x00_rt(rt2x00dev, RT5392)) {
3218                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
3219                 rt2800_bbp_write(rt2x00dev, 73, 0x13);
3220                 rt2800_bbp_write(rt2x00dev, 75, 0x46);
3221                 rt2800_bbp_write(rt2x00dev, 76, 0x28);
3222                 rt2800_bbp_write(rt2x00dev, 77, 0x59);
3223         } else {
3224                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
3225                 rt2800_bbp_write(rt2x00dev, 73, 0x10);
3226         }
3227
3228         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3229
3230         if (rt2x00_rt(rt2x00dev, RT3070) ||
3231             rt2x00_rt(rt2x00dev, RT3071) ||
3232             rt2x00_rt(rt2x00dev, RT3090) ||
3233             rt2x00_rt(rt2x00dev, RT3390) ||
3234             rt2x00_rt(rt2x00dev, RT3572) ||
3235             rt2x00_rt(rt2x00dev, RT5390) ||
3236             rt2x00_rt(rt2x00dev, RT5392)) {
3237                 rt2800_bbp_write(rt2x00dev, 79, 0x13);
3238                 rt2800_bbp_write(rt2x00dev, 80, 0x05);
3239                 rt2800_bbp_write(rt2x00dev, 81, 0x33);
3240         } else if (rt2800_is_305x_soc(rt2x00dev)) {
3241                 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
3242                 rt2800_bbp_write(rt2x00dev, 80, 0x08);
3243         } else {
3244                 rt2800_bbp_write(rt2x00dev, 81, 0x37);
3245         }
3246
3247         rt2800_bbp_write(rt2x00dev, 82, 0x62);
3248         if (rt2x00_rt(rt2x00dev, RT5390) ||
3249                 rt2x00_rt(rt2x00dev, RT5392))
3250                 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
3251         else
3252                 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3253
3254         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
3255                 rt2800_bbp_write(rt2x00dev, 84, 0x19);
3256         else if (rt2x00_rt(rt2x00dev, RT5390) ||
3257                          rt2x00_rt(rt2x00dev, RT5392))
3258                 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
3259         else
3260                 rt2800_bbp_write(rt2x00dev, 84, 0x99);
3261
3262         if (rt2x00_rt(rt2x00dev, RT5390) ||
3263                 rt2x00_rt(rt2x00dev, RT5392))
3264                 rt2800_bbp_write(rt2x00dev, 86, 0x38);
3265         else
3266                 rt2800_bbp_write(rt2x00dev, 86, 0x00);
3267
3268         if (rt2x00_rt(rt2x00dev, RT5392))
3269                 rt2800_bbp_write(rt2x00dev, 88, 0x90);
3270
3271         rt2800_bbp_write(rt2x00dev, 91, 0x04);
3272
3273         if (rt2x00_rt(rt2x00dev, RT5390) ||
3274                 rt2x00_rt(rt2x00dev, RT5392))
3275                 rt2800_bbp_write(rt2x00dev, 92, 0x02);
3276         else
3277                 rt2800_bbp_write(rt2x00dev, 92, 0x00);
3278
3279         if (rt2x00_rt(rt2x00dev, RT5392)) {
3280                 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
3281                 rt2800_bbp_write(rt2x00dev, 98, 0x12);
3282         }
3283
3284         if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
3285             rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
3286             rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
3287             rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
3288             rt2x00_rt(rt2x00dev, RT3572) ||
3289             rt2x00_rt(rt2x00dev, RT5390) ||
3290             rt2x00_rt(rt2x00dev, RT5392) ||
3291             rt2800_is_305x_soc(rt2x00dev))
3292                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
3293         else
3294                 rt2800_bbp_write(rt2x00dev, 103, 0x00);
3295
3296         if (rt2x00_rt(rt2x00dev, RT5390) ||
3297                 rt2x00_rt(rt2x00dev, RT5392))
3298                 rt2800_bbp_write(rt2x00dev, 104, 0x92);
3299
3300         if (rt2800_is_305x_soc(rt2x00dev))
3301                 rt2800_bbp_write(rt2x00dev, 105, 0x01);
3302         else if (rt2x00_rt(rt2x00dev, RT5390) ||
3303                          rt2x00_rt(rt2x00dev, RT5392))
3304                 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
3305         else
3306                 rt2800_bbp_write(rt2x00dev, 105, 0x05);
3307
3308         if (rt2x00_rt(rt2x00dev, RT5390))
3309                 rt2800_bbp_write(rt2x00dev, 106, 0x03);
3310         else if (rt2x00_rt(rt2x00dev, RT5392))
3311                 rt2800_bbp_write(rt2x00dev, 106, 0x12);
3312         else
3313                 rt2800_bbp_write(rt2x00dev, 106, 0x35);
3314
3315         if (rt2x00_rt(rt2x00dev, RT5390) ||
3316                 rt2x00_rt(rt2x00dev, RT5392))
3317                 rt2800_bbp_write(rt2x00dev, 128, 0x12);
3318
3319         if (rt2x00_rt(rt2x00dev, RT5392)) {
3320                 rt2800_bbp_write(rt2x00dev, 134, 0xd0);
3321                 rt2800_bbp_write(rt2x00dev, 135, 0xf6);
3322         }
3323
3324         if (rt2x00_rt(rt2x00dev, RT3071) ||
3325             rt2x00_rt(rt2x00dev, RT3090) ||
3326             rt2x00_rt(rt2x00dev, RT3390) ||
3327             rt2x00_rt(rt2x00dev, RT3572) ||
3328             rt2x00_rt(rt2x00dev, RT5390) ||
3329             rt2x00_rt(rt2x00dev, RT5392)) {
3330                 rt2800_bbp_read(rt2x00dev, 138, &value);
3331
3332                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3333                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
3334                         value |= 0x20;
3335                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
3336                         value &= ~0x02;
3337
3338                 rt2800_bbp_write(rt2x00dev, 138, value);
3339         }
3340
3341         if (rt2x00_rt(rt2x00dev, RT5390) ||
3342                 rt2x00_rt(rt2x00dev, RT5392)) {
3343                 int ant, div_mode;
3344
3345                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3346                 div_mode = rt2x00_get_field16(eeprom,
3347                                               EEPROM_NIC_CONF1_ANT_DIVERSITY);
3348                 ant = (div_mode == 3) ? 1 : 0;
3349
3350                 /* check if this is a Bluetooth combo card */
3351                 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
3352                         u32 reg;
3353
3354                         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
3355                         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
3356                         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_GPIOD_BIT6, 0);
3357                         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 0);
3358                         rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 0);
3359                         if (ant == 0)
3360                                 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT3, 1);
3361                         else if (ant == 1)
3362                                 rt2x00_set_field32(&reg, GPIO_CTRL_CFG_BIT6, 1);
3363                         rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
3364                 }
3365
3366                 /* This chip has hardware antenna diversity*/
3367                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
3368                         rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */
3369                         rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */
3370                         rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */
3371                 }
3372
3373                 rt2800_bbp_read(rt2x00dev, 152, &value);
3374                 if (ant == 0)
3375                         rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
3376                 else
3377                         rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
3378                 rt2800_bbp_write(rt2x00dev, 152, value);
3379
3380                 /* Init frequency calibration */
3381                 rt2800_bbp_write(rt2x00dev, 142, 1);
3382                 rt2800_bbp_write(rt2x00dev, 143, 57);
3383         }
3384
3385         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
3386                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
3387
3388                 if (eeprom != 0xffff && eeprom != 0x0000) {
3389                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
3390                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
3391                         rt2800_bbp_write(rt2x00dev, reg_id, value);
3392                 }
3393         }
3394
3395         return 0;
3396 }
3397
3398 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
3399                                 bool bw40, u8 rfcsr24, u8 filter_target)
3400 {
3401         unsigned int i;
3402         u8 bbp;
3403         u8 rfcsr;
3404         u8 passband;
3405         u8 stopband;
3406         u8 overtuned = 0;
3407
3408         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3409
3410         rt2800_bbp_read(rt2x00dev, 4, &bbp);
3411         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
3412         rt2800_bbp_write(rt2x00dev, 4, bbp);
3413
3414         rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
3415         rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
3416         rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
3417
3418         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
3419         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
3420         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
3421
3422         /*
3423          * Set power & frequency of passband test tone
3424          */
3425         rt2800_bbp_write(rt2x00dev, 24, 0);
3426
3427         for (i = 0; i < 100; i++) {
3428                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
3429                 msleep(1);
3430
3431                 rt2800_bbp_read(rt2x00dev, 55, &passband);
3432                 if (passband)
3433                         break;
3434         }
3435
3436         /*
3437          * Set power & frequency of stopband test tone
3438          */
3439         rt2800_bbp_write(rt2x00dev, 24, 0x06);
3440
3441         for (i = 0; i < 100; i++) {
3442                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
3443                 msleep(1);
3444
3445                 rt2800_bbp_read(rt2x00dev, 55, &stopband);
3446
3447                 if ((passband - stopband) <= filter_target) {
3448                         rfcsr24++;
3449                         overtuned += ((passband - stopband) == filter_target);
3450                 } else
3451                         break;
3452
3453                 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3454         }
3455
3456         rfcsr24 -= !!overtuned;
3457
3458         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3459         return rfcsr24;
3460 }
3461
3462 static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
3463 {
3464         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
3465         u8 rfcsr;
3466         u8 bbp;
3467         u32 reg;
3468         u16 eeprom;
3469
3470         if (!rt2x00_rt(rt2x00dev, RT3070) &&
3471             !rt2x00_rt(rt2x00dev, RT3071) &&
3472             !rt2x00_rt(rt2x00dev, RT3090) &&
3473             !rt2x00_rt(rt2x00dev, RT3390) &&
3474             !rt2x00_rt(rt2x00dev, RT3572) &&
3475             !rt2x00_rt(rt2x00dev, RT5390) &&
3476             !rt2x00_rt(rt2x00dev, RT5392) &&
3477             !rt2800_is_305x_soc(rt2x00dev))
3478                 return 0;
3479
3480         /*
3481          * Init RF calibration.
3482          */
3483         if (rt2x00_rt(rt2x00dev, RT5390) ||
3484                 rt2x00_rt(rt2x00dev, RT5392)) {
3485                 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
3486                 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
3487                 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3488                 msleep(1);
3489                 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0);
3490                 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3491         } else {
3492                 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3493                 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
3494                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3495                 msleep(1);
3496                 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
3497                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3498         }
3499
3500         if (rt2x00_rt(rt2x00dev, RT3070) ||
3501             rt2x00_rt(rt2x00dev, RT3071) ||
3502             rt2x00_rt(rt2x00dev, RT3090)) {
3503                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3504                 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
3505                 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
3506                 rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
3507                 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
3508                 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
3509                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3510                 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
3511                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3512                 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
3513                 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
3514                 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
3515                 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
3516                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
3517                 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
3518                 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
3519                 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
3520                 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
3521                 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
3522         } else if (rt2x00_rt(rt2x00dev, RT3390)) {
3523                 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
3524                 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
3525                 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
3526                 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
3527                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3528                 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
3529                 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
3530                 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
3531                 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
3532                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
3533                 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
3534                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3535                 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
3536                 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
3537                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3538                 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
3539                 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
3540                 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
3541                 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
3542                 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
3543                 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
3544                 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
3545                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
3546                 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
3547                 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
3548                 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
3549                 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
3550                 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
3551                 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
3552                 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
3553                 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
3554                 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
3555         } else if (rt2x00_rt(rt2x00dev, RT3572)) {
3556                 rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
3557                 rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
3558                 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
3559                 rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
3560                 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
3561                 rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
3562                 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
3563                 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
3564                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
3565                 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
3566                 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
3567                 rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
3568                 rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
3569                 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
3570                 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
3571                 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
3572                 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
3573                 rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
3574                 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
3575                 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
3576                 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
3577                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
3578                 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
3579                 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
3580                 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
3581                 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
3582                 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
3583                 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
3584                 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
3585                 rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
3586                 rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
3587         } else if (rt2800_is_305x_soc(rt2x00dev)) {
3588                 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
3589                 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
3590                 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
3591                 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
3592                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3593                 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
3594                 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
3595                 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
3596                 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
3597                 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
3598                 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
3599                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3600                 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
3601                 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
3602                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3603                 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
3604                 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
3605                 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
3606                 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
3607                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
3608                 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
3609                 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
3610                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
3611                 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
3612                 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
3613                 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
3614                 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
3615                 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
3616                 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
3617                 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
3618                 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
3619                 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
3620                 return 0;
3621         } else if (rt2x00_rt(rt2x00dev, RT5390)) {
3622                 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
3623                 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
3624                 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
3625                 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
3626                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3627                         rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
3628                 else
3629                         rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
3630                 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
3631                 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
3632                 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
3633                 rt2800_rfcsr_write(rt2x00dev, 12, 0xc6);
3634                 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
3635                 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
3636                 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
3637                 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
3638                 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
3639                 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
3640
3641                 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
3642                 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
3643                 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
3644                 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
3645                 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
3646                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3647                         rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
3648                 else
3649                         rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
3650                 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
3651                 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
3652                 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
3653                 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
3654
3655                 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
3656                 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3657                 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3658                 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
3659                 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
3660                 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
3661                 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
3662                 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
3663                 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
3664                 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
3665
3666                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3667                         rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
3668                 else
3669                         rt2800_rfcsr_write(rt2x00dev, 40, 0x4b);
3670                 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
3671                 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
3672                 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
3673                 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
3674                 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
3675                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3676                         rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
3677                 else
3678                         rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
3679                 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
3680                 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
3681                 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
3682
3683                 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
3684                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3685                         rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
3686                 else
3687                         rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
3688                 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
3689                 rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
3690                 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
3691                 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
3692                 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
3693                 rt2800_rfcsr_write(rt2x00dev, 59, 0x63);
3694
3695                 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
3696                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3697                         rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
3698                 else
3699                         rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
3700                 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
3701                 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
3702         }       else if (rt2x00_rt(rt2x00dev, RT5392)) {
3703                         rt2800_rfcsr_write(rt2x00dev, 1, 0x17);
3704                         rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
3705                         rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
3706                         rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
3707                         rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
3708                         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
3709                         rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
3710                         rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
3711                         rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
3712                         rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
3713                         rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
3714                         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
3715                         rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
3716                         rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
3717                         rt2800_rfcsr_write(rt2x00dev, 19, 0x4d);
3718                         rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
3719                         rt2800_rfcsr_write(rt2x00dev, 21, 0x8d);
3720                         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
3721                         rt2800_rfcsr_write(rt2x00dev, 23, 0x0b);
3722                         rt2800_rfcsr_write(rt2x00dev, 24, 0x44);
3723                         rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
3724                         rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
3725                         rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
3726                         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
3727                         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
3728                         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
3729                         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3730                         rt2800_rfcsr_write(rt2x00dev, 32, 0x20);
3731                         rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
3732                         rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
3733                         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
3734                         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
3735                         rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
3736                         rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
3737                         rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
3738                         rt2800_rfcsr_write(rt2x00dev, 40, 0x0f);
3739                         rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
3740                         rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
3741                         rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
3742                         rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
3743                         rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
3744                         rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
3745                         rt2800_rfcsr_write(rt2x00dev, 47, 0x0c);
3746                         rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
3747                         rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
3748                         rt2800_rfcsr_write(rt2x00dev, 50, 0x94);
3749                         rt2800_rfcsr_write(rt2x00dev, 51, 0x3a);
3750                         rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
3751                         rt2800_rfcsr_write(rt2x00dev, 53, 0x44);
3752                         rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
3753                         rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
3754                         rt2800_rfcsr_write(rt2x00dev, 56, 0xa1);
3755                         rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
3756                         rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
3757                         rt2800_rfcsr_write(rt2x00dev, 59, 0x07);
3758                         rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
3759                         rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
3760                         rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
3761                         rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
3762         }
3763
3764         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
3765                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3766                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3767                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3768                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3769         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
3770                    rt2x00_rt(rt2x00dev, RT3090)) {
3771                 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
3772
3773                 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
3774                 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
3775                 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
3776
3777                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3778                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3779                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3780                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
3781                         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3782                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
3783                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3784                         else
3785                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
3786                 }
3787                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3788
3789                 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
3790                 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
3791                 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
3792         } else if (rt2x00_rt(rt2x00dev, RT3390)) {
3793                 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
3794                 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
3795                 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
3796         } else if (rt2x00_rt(rt2x00dev, RT3572)) {
3797                 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
3798                 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
3799                 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
3800
3801                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3802                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3803                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3804                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3805                 msleep(1);
3806                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
3807                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
3808                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3809         }
3810
3811         /*
3812          * Set RX Filter calibration for 20MHz and 40MHz
3813          */
3814         if (rt2x00_rt(rt2x00dev, RT3070)) {
3815                 drv_data->calibration_bw20 =
3816                         rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
3817                 drv_data->calibration_bw40 =
3818                         rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
3819         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
3820                    rt2x00_rt(rt2x00dev, RT3090) ||
3821                    rt2x00_rt(rt2x00dev, RT3390) ||
3822                    rt2x00_rt(rt2x00dev, RT3572)) {
3823                 drv_data->calibration_bw20 =
3824                         rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
3825                 drv_data->calibration_bw40 =
3826                         rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
3827         }
3828
3829         /*
3830          * Save BBP 25 & 26 values for later use in channel switching
3831          */
3832         rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
3833         rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
3834
3835         if (!rt2x00_rt(rt2x00dev, RT5390) &&
3836                 !rt2x00_rt(rt2x00dev, RT5392)) {
3837                 /*
3838                  * Set back to initial state
3839                  */
3840                 rt2800_bbp_write(rt2x00dev, 24, 0);
3841
3842                 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
3843                 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
3844                 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
3845
3846                 /*
3847                  * Set BBP back to BW20
3848                  */
3849                 rt2800_bbp_read(rt2x00dev, 4, &bbp);
3850                 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
3851                 rt2800_bbp_write(rt2x00dev, 4, bbp);
3852         }
3853
3854         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
3855             rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3856             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
3857             rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
3858                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
3859
3860         rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
3861         rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
3862         rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
3863
3864         if (!rt2x00_rt(rt2x00dev, RT5390) &&
3865                 !rt2x00_rt(rt2x00dev, RT5392)) {
3866                 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
3867                 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
3868                 if (rt2x00_rt(rt2x00dev, RT3070) ||
3869                     rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3870                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
3871                     rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
3872                         if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG,
3873                                       &rt2x00dev->cap_flags))
3874                                 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
3875                 }
3876                 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
3877                                   drv_data->txmixer_gain_24g);
3878                 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
3879         }
3880
3881         if (rt2x00_rt(rt2x00dev, RT3090)) {
3882                 rt2800_bbp_read(rt2x00dev, 138, &bbp);
3883
3884                 /*  Turn off unused DAC1 and ADC1 to reduce power consumption */
3885                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3886                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
3887                         rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
3888                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
3889                         rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
3890
3891                 rt2800_bbp_write(rt2x00dev, 138, bbp);
3892         }
3893
3894         if (rt2x00_rt(rt2x00dev, RT3071) ||
3895             rt2x00_rt(rt2x00dev, RT3090) ||
3896             rt2x00_rt(rt2x00dev, RT3390)) {
3897                 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
3898                 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
3899                 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
3900                 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
3901                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
3902                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
3903                 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3904
3905                 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
3906                 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
3907                 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
3908
3909                 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
3910                 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
3911                 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
3912
3913                 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
3914                 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
3915                 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
3916         }
3917
3918         if (rt2x00_rt(rt2x00dev, RT3070)) {
3919                 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
3920                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
3921                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
3922                 else
3923                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
3924                 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
3925                 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
3926                 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
3927                 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
3928         }
3929
3930         if (rt2x00_rt(rt2x00dev, RT5390) ||
3931                 rt2x00_rt(rt2x00dev, RT5392)) {
3932                 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
3933                 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
3934                 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
3935
3936                 rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
3937                 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
3938                 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
3939
3940                 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3941                 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
3942                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3943         }
3944
3945         return 0;
3946 }
3947
3948 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
3949 {
3950         u32 reg;
3951         u16 word;
3952
3953         /*
3954          * Initialize all registers.
3955          */
3956         if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
3957                      rt2800_init_registers(rt2x00dev) ||
3958                      rt2800_init_bbp(rt2x00dev) ||
3959                      rt2800_init_rfcsr(rt2x00dev)))
3960                 return -EIO;
3961
3962         /*
3963          * Send signal to firmware during boot time.
3964          */
3965         rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
3966
3967         if (rt2x00_is_usb(rt2x00dev) &&
3968             (rt2x00_rt(rt2x00dev, RT3070) ||
3969              rt2x00_rt(rt2x00dev, RT3071) ||
3970              rt2x00_rt(rt2x00dev, RT3572))) {
3971                 udelay(200);
3972                 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
3973                 udelay(10);
3974         }
3975
3976         /*
3977          * Enable RX.
3978          */
3979         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3980         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
3981         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
3982         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
3983
3984         udelay(50);
3985
3986         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
3987         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
3988         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
3989         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
3990         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
3991         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
3992
3993         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
3994         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
3995         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
3996         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
3997
3998         /*
3999          * Initialize LED control
4000          */
4001         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
4002         rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
4003                            word & 0xff, (word >> 8) & 0xff);
4004
4005         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
4006         rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
4007                            word & 0xff, (word >> 8) & 0xff);
4008
4009         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
4010         rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
4011                            word & 0xff, (word >> 8) & 0xff);
4012
4013         return 0;
4014 }
4015 EXPORT_SYMBOL_GPL(rt2800_enable_radio);
4016
4017 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
4018 {
4019         u32 reg;
4020
4021         rt2800_disable_wpdma(rt2x00dev);
4022
4023         /* Wait for DMA, ignore error */
4024         rt2800_wait_wpdma_ready(rt2x00dev);
4025
4026         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
4027         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
4028         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
4029         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
4030 }
4031 EXPORT_SYMBOL_GPL(rt2800_disable_radio);
4032
4033 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
4034 {
4035         u32 reg;
4036
4037         rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
4038
4039         return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
4040 }
4041 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
4042
4043 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
4044 {
4045         u32 reg;
4046
4047         mutex_lock(&rt2x00dev->csr_mutex);
4048
4049         rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, &reg);
4050         rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
4051         rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
4052         rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
4053         rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
4054
4055         /* Wait until the EEPROM has been loaded */
4056         rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
4057
4058         /* Apparently the data is read from end to start */
4059         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3, &reg);
4060         /* The returned value is in CPU order, but eeprom is le */
4061         *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
4062         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2, &reg);
4063         *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
4064         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1, &reg);
4065         *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
4066         rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0, &reg);
4067         *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
4068
4069         mutex_unlock(&rt2x00dev->csr_mutex);
4070 }
4071
4072 void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
4073 {
4074         unsigned int i;
4075
4076         for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
4077                 rt2800_efuse_read(rt2x00dev, i);
4078 }
4079 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
4080
4081 int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
4082 {
4083         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
4084         u16 word;
4085         u8 *mac;
4086         u8 default_lna_gain;
4087
4088         /*
4089          * Start validation of the data that has been read.
4090          */
4091         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
4092         if (!is_valid_ether_addr(mac)) {
4093                 random_ether_addr(mac);
4094                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
4095         }
4096
4097         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
4098         if (word == 0xffff) {
4099                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
4100                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
4101                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
4102                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
4103                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
4104         } else if (rt2x00_rt(rt2x00dev, RT2860) ||
4105                    rt2x00_rt(rt2x00dev, RT2872)) {
4106                 /*
4107                  * There is a max of 2 RX streams for RT28x0 series
4108                  */
4109                 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
4110                         rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
4111                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
4112         }
4113
4114         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
4115         if (word == 0xffff) {
4116                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
4117                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
4118                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
4119                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
4120                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
4121                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
4122                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
4123                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
4124                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
4125                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
4126                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
4127                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
4128                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
4129                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
4130                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
4131                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
4132                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
4133         }
4134
4135         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
4136         if ((word & 0x00ff) == 0x00ff) {
4137                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
4138                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
4139                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
4140         }
4141         if ((word & 0xff00) == 0xff00) {
4142                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
4143                                    LED_MODE_TXRX_ACTIVITY);
4144                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
4145                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
4146                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
4147                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
4148                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
4149                 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word);
4150         }
4151
4152         /*
4153          * During the LNA validation we are going to use
4154          * lna0 as correct value. Note that EEPROM_LNA
4155          * is never validated.
4156          */
4157         rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
4158         default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
4159
4160         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
4161         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
4162                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
4163         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
4164                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
4165         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
4166
4167         rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &word);
4168         if ((word & 0x00ff) != 0x00ff) {
4169                 drv_data->txmixer_gain_24g =
4170                         rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL);
4171         } else {
4172                 drv_data->txmixer_gain_24g = 0;
4173         }
4174
4175         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
4176         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
4177                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
4178         if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
4179             rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
4180                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
4181                                    default_lna_gain);
4182         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
4183
4184         rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A, &word);
4185         if ((word & 0x00ff) != 0x00ff) {
4186                 drv_data->txmixer_gain_5g =
4187                         rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL);
4188         } else {
4189                 drv_data->txmixer_gain_5g = 0;
4190         }
4191
4192         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
4193         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
4194                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
4195         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
4196                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
4197         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
4198
4199         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
4200         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
4201                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
4202         if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
4203             rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
4204                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
4205                                    default_lna_gain);
4206         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
4207
4208         return 0;
4209 }
4210 EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
4211
4212 int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
4213 {
4214         u32 reg;
4215         u16 value;
4216         u16 eeprom;
4217
4218         /*
4219          * Read EEPROM word for configuration.
4220          */
4221         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4222
4223         /*
4224          * Identify RF chipset by EEPROM value
4225          * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
4226          * RT53xx: defined in "EEPROM_CHIP_ID" field
4227          */
4228         rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
4229         if (rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5390 ||
4230                 rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5392)
4231                 rt2x00_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &value);
4232         else
4233                 value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
4234
4235         rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
4236                         value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
4237
4238         switch (rt2x00dev->chip.rt) {
4239         case RT2860:
4240         case RT2872:
4241         case RT2883:
4242         case RT3070:
4243         case RT3071:
4244         case RT3090:
4245         case RT3390:
4246         case RT3572:
4247         case RT5390:
4248         case RT5392:
4249                 break;
4250         default:
4251                 ERROR(rt2x00dev, "Invalid RT chipset 0x%04x detected.\n", rt2x00dev->chip.rt);
4252                 return -ENODEV;
4253         }
4254
4255         switch (rt2x00dev->chip.rf) {
4256         case RF2820:
4257         case RF2850:
4258         case RF2720:
4259         case RF2750:
4260         case RF3020:
4261         case RF2020:
4262         case RF3021:
4263         case RF3022:
4264         case RF3052:
4265         case RF3320:
4266         case RF5370:
4267         case RF5372:
4268         case RF5390:
4269                 break;
4270         default:
4271                 ERROR(rt2x00dev, "Invalid RF chipset 0x%04x detected.\n",
4272                       rt2x00dev->chip.rf);
4273                 return -ENODEV;
4274         }
4275
4276         /*
4277          * Identify default antenna configuration.
4278          */
4279         rt2x00dev->default_ant.tx_chain_num =
4280             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
4281         rt2x00dev->default_ant.rx_chain_num =
4282             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
4283
4284         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
4285
4286         if (rt2x00_rt(rt2x00dev, RT3070) ||
4287             rt2x00_rt(rt2x00dev, RT3090) ||
4288             rt2x00_rt(rt2x00dev, RT3390)) {
4289                 value = rt2x00_get_field16(eeprom,
4290                                 EEPROM_NIC_CONF1_ANT_DIVERSITY);
4291                 switch (value) {
4292                 case 0:
4293                 case 1:
4294                 case 2:
4295                         rt2x00dev->default_ant.tx = ANTENNA_A;
4296                         rt2x00dev->default_ant.rx = ANTENNA_A;
4297                         break;
4298                 case 3:
4299                         rt2x00dev->default_ant.tx = ANTENNA_A;
4300                         rt2x00dev->default_ant.rx = ANTENNA_B;
4301                         break;
4302                 }
4303         } else {
4304                 rt2x00dev->default_ant.tx = ANTENNA_A;
4305                 rt2x00dev->default_ant.rx = ANTENNA_A;
4306         }
4307
4308         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
4309                 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */
4310                 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */
4311         }
4312
4313         /*
4314          * Determine external LNA informations.
4315          */
4316         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
4317                 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
4318         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
4319                 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
4320
4321         /*
4322          * Detect if this device has an hardware controlled radio.
4323          */
4324         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
4325                 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
4326
4327         /*
4328          * Detect if this device has Bluetooth co-existence.
4329          */
4330         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
4331                 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
4332
4333         /*
4334          * Read frequency offset and RF programming sequence.
4335          */
4336         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
4337         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
4338
4339         /*
4340          * Store led settings, for correct led behaviour.
4341          */
4342 #ifdef CONFIG_RT2X00_LIB_LEDS
4343         rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
4344         rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
4345         rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
4346
4347         rt2x00dev->led_mcu_reg = eeprom;
4348 #endif /* CONFIG_RT2X00_LIB_LEDS */
4349
4350         /*
4351          * Check if support EIRP tx power limit feature.
4352          */
4353         rt2x00_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
4354
4355         if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
4356                                         EIRP_MAX_TX_POWER_LIMIT)
4357                 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
4358
4359         return 0;
4360 }
4361 EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
4362
4363 /*
4364  * RF value list for rt28xx
4365  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
4366  */
4367 static const struct rf_channel rf_vals[] = {
4368         { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
4369         { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
4370         { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
4371         { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
4372         { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
4373         { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
4374         { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
4375         { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
4376         { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
4377         { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
4378         { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
4379         { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
4380         { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
4381         { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
4382
4383         /* 802.11 UNI / HyperLan 2 */
4384         { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
4385         { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
4386         { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
4387         { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
4388         { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
4389         { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
4390         { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
4391         { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
4392         { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
4393         { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
4394         { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
4395         { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
4396
4397         /* 802.11 HyperLan 2 */
4398         { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
4399         { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
4400         { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
4401         { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
4402         { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
4403         { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
4404         { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
4405         { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
4406         { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
4407         { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
4408         { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
4409         { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
4410         { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
4411         { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
4412         { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
4413         { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
4414
4415         /* 802.11 UNII */
4416         { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
4417         { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
4418         { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
4419         { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
4420         { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
4421         { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
4422         { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
4423         { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
4424         { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
4425         { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
4426         { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
4427
4428         /* 802.11 Japan */
4429         { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
4430         { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
4431         { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
4432         { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
4433         { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
4434         { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
4435         { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
4436 };
4437
4438 /*
4439  * RF value list for rt3xxx
4440  * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
4441  */
4442 static const struct rf_channel rf_vals_3x[] = {
4443         {1,  241, 2, 2 },
4444         {2,  241, 2, 7 },
4445         {3,  242, 2, 2 },
4446         {4,  242, 2, 7 },
4447         {5,  243, 2, 2 },
4448         {6,  243, 2, 7 },
4449         {7,  244, 2, 2 },
4450         {8,  244, 2, 7 },
4451         {9,  245, 2, 2 },
4452         {10, 245, 2, 7 },
4453         {11, 246, 2, 2 },
4454         {12, 246, 2, 7 },
4455         {13, 247, 2, 2 },
4456         {14, 248, 2, 4 },
4457
4458         /* 802.11 UNI / HyperLan 2 */
4459         {36, 0x56, 0, 4},
4460         {38, 0x56, 0, 6},
4461         {40, 0x56, 0, 8},
4462         {44, 0x57, 0, 0},
4463         {46, 0x57, 0, 2},
4464         {48, 0x57, 0, 4},
4465         {52, 0x57, 0, 8},
4466         {54, 0x57, 0, 10},
4467         {56, 0x58, 0, 0},
4468         {60, 0x58, 0, 4},
4469         {62, 0x58, 0, 6},
4470         {64, 0x58, 0, 8},
4471
4472         /* 802.11 HyperLan 2 */
4473         {100, 0x5b, 0, 8},
4474         {102, 0x5b, 0, 10},
4475         {104, 0x5c, 0, 0},
4476         {108, 0x5c, 0, 4},
4477         {110, 0x5c, 0, 6},
4478         {112, 0x5c, 0, 8},
4479         {116, 0x5d, 0, 0},
4480         {118, 0x5d, 0, 2},
4481         {120, 0x5d, 0, 4},
4482         {124, 0x5d, 0, 8},
4483         {126, 0x5d, 0, 10},
4484         {128, 0x5e, 0, 0},
4485         {132, 0x5e, 0, 4},
4486         {134, 0x5e, 0, 6},
4487         {136, 0x5e, 0, 8},
4488         {140, 0x5f, 0, 0},
4489
4490         /* 802.11 UNII */
4491         {149, 0x5f, 0, 9},
4492         {151, 0x5f, 0, 11},
4493         {153, 0x60, 0, 1},
4494         {157, 0x60, 0, 5},
4495         {159, 0x60, 0, 7},
4496         {161, 0x60, 0, 9},
4497         {165, 0x61, 0, 1},
4498         {167, 0x61, 0, 3},
4499         {169, 0x61, 0, 5},
4500         {171, 0x61, 0, 7},
4501         {173, 0x61, 0, 9},
4502 };
4503
4504 int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
4505 {
4506         struct hw_mode_spec *spec = &rt2x00dev->spec;
4507         struct channel_info *info;
4508         char *default_power1;
4509         char *default_power2;
4510         unsigned int i;
4511         u16 eeprom;
4512
4513         /*
4514          * Disable powersaving as default on PCI devices.
4515          */
4516         if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
4517                 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
4518
4519         /*
4520          * Initialize all hw fields.
4521          */
4522         rt2x00dev->hw->flags =
4523             IEEE80211_HW_SIGNAL_DBM |
4524             IEEE80211_HW_SUPPORTS_PS |
4525             IEEE80211_HW_PS_NULLFUNC_STACK |
4526             IEEE80211_HW_AMPDU_AGGREGATION |
4527             IEEE80211_HW_REPORTS_TX_ACK_STATUS;
4528
4529         /*
4530          * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
4531          * unless we are capable of sending the buffered frames out after the
4532          * DTIM transmission using rt2x00lib_beacondone. This will send out
4533          * multicast and broadcast traffic immediately instead of buffering it
4534          * infinitly and thus dropping it after some time.
4535          */
4536         if (!rt2x00_is_usb(rt2x00dev))
4537                 rt2x00dev->hw->flags |=
4538                         IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
4539
4540         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
4541         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
4542                                 rt2x00_eeprom_addr(rt2x00dev,
4543                                                    EEPROM_MAC_ADDR_0));
4544
4545         /*
4546          * As rt2800 has a global fallback table we cannot specify
4547          * more then one tx rate per frame but since the hw will
4548          * try several rates (based on the fallback table) we should
4549          * initialize max_report_rates to the maximum number of rates
4550          * we are going to try. Otherwise mac80211 will truncate our
4551          * reported tx rates and the rc algortihm will end up with
4552          * incorrect data.
4553          */
4554         rt2x00dev->hw->max_rates = 1;
4555         rt2x00dev->hw->max_report_rates = 7;
4556         rt2x00dev->hw->max_rate_tries = 1;
4557
4558         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4559
4560         /*
4561          * Initialize hw_mode information.
4562          */
4563         spec->supported_bands = SUPPORT_BAND_2GHZ;
4564         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
4565
4566         if (rt2x00_rf(rt2x00dev, RF2820) ||
4567             rt2x00_rf(rt2x00dev, RF2720)) {
4568                 spec->num_channels = 14;
4569                 spec->channels = rf_vals;
4570         } else if (rt2x00_rf(rt2x00dev, RF2850) ||
4571                    rt2x00_rf(rt2x00dev, RF2750)) {
4572                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
4573                 spec->num_channels = ARRAY_SIZE(rf_vals);
4574                 spec->channels = rf_vals;
4575         } else if (rt2x00_rf(rt2x00dev, RF3020) ||
4576                    rt2x00_rf(rt2x00dev, RF2020) ||
4577                    rt2x00_rf(rt2x00dev, RF3021) ||
4578                    rt2x00_rf(rt2x00dev, RF3022) ||
4579                    rt2x00_rf(rt2x00dev, RF3320) ||
4580                    rt2x00_rf(rt2x00dev, RF5370) ||
4581                    rt2x00_rf(rt2x00dev, RF5372) ||
4582                    rt2x00_rf(rt2x00dev, RF5390)) {
4583                 spec->num_channels = 14;
4584                 spec->channels = rf_vals_3x;
4585         } else if (rt2x00_rf(rt2x00dev, RF3052)) {
4586                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
4587                 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
4588                 spec->channels = rf_vals_3x;
4589         }
4590
4591         /*
4592          * Initialize HT information.
4593          */
4594         if (!rt2x00_rf(rt2x00dev, RF2020))
4595                 spec->ht.ht_supported = true;
4596         else
4597                 spec->ht.ht_supported = false;
4598
4599         spec->ht.cap =
4600             IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
4601             IEEE80211_HT_CAP_GRN_FLD |
4602             IEEE80211_HT_CAP_SGI_20 |
4603             IEEE80211_HT_CAP_SGI_40;
4604
4605         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2)
4606                 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
4607
4608         spec->ht.cap |=
4609             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) <<
4610                 IEEE80211_HT_CAP_RX_STBC_SHIFT;
4611
4612         spec->ht.ampdu_factor = 3;
4613         spec->ht.ampdu_density = 4;
4614         spec->ht.mcs.tx_params =
4615             IEEE80211_HT_MCS_TX_DEFINED |
4616             IEEE80211_HT_MCS_TX_RX_DIFF |
4617             ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) <<
4618                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
4619
4620         switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) {
4621         case 3:
4622                 spec->ht.mcs.rx_mask[2] = 0xff;
4623         case 2:
4624                 spec->ht.mcs.rx_mask[1] = 0xff;
4625         case 1:
4626                 spec->ht.mcs.rx_mask[0] = 0xff;
4627                 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
4628                 break;
4629         }
4630
4631         /*
4632          * Create channel information array
4633          */
4634         info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
4635         if (!info)
4636                 return -ENOMEM;
4637
4638         spec->channels_info = info;
4639
4640         default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
4641         default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
4642
4643         for (i = 0; i < 14; i++) {
4644                 info[i].default_power1 = default_power1[i];
4645                 info[i].default_power2 = default_power2[i];
4646         }
4647
4648         if (spec->num_channels > 14) {
4649                 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
4650                 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
4651
4652                 for (i = 14; i < spec->num_channels; i++) {
4653                         info[i].default_power1 = default_power1[i];
4654                         info[i].default_power2 = default_power2[i];
4655                 }
4656         }
4657
4658         switch (rt2x00dev->chip.rf) {
4659         case RF2020:
4660         case RF3020:
4661         case RF3021:
4662         case RF3022:
4663         case RF3320:
4664         case RF3052:
4665         case RF5370:
4666         case RF5372:
4667         case RF5390:
4668                 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
4669                 break;
4670         }
4671
4672         return 0;
4673 }
4674 EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
4675
4676 /*
4677  * IEEE80211 stack callback functions.
4678  */
4679 void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
4680                          u16 *iv16)
4681 {
4682         struct rt2x00_dev *rt2x00dev = hw->priv;
4683         struct mac_iveiv_entry iveiv_entry;
4684         u32 offset;
4685
4686         offset = MAC_IVEIV_ENTRY(hw_key_idx);
4687         rt2800_register_multiread(rt2x00dev, offset,
4688                                       &iveiv_entry, sizeof(iveiv_entry));
4689
4690         memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
4691         memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
4692 }
4693 EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
4694
4695 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
4696 {
4697         struct rt2x00_dev *rt2x00dev = hw->priv;
4698         u32 reg;
4699         bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
4700
4701         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
4702         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
4703         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
4704
4705         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
4706         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
4707         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
4708
4709         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
4710         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
4711         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
4712
4713         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
4714         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
4715         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
4716
4717         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
4718         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
4719         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
4720
4721         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
4722         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
4723         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
4724
4725         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
4726         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
4727         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
4728
4729         return 0;
4730 }
4731 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
4732
4733 int rt2800_conf_tx(struct ieee80211_hw *hw,
4734                    struct ieee80211_vif *vif, u16 queue_idx,
4735                    const struct ieee80211_tx_queue_params *params)
4736 {
4737         struct rt2x00_dev *rt2x00dev = hw->priv;
4738         struct data_queue *queue;
4739         struct rt2x00_field32 field;
4740         int retval;
4741         u32 reg;
4742         u32 offset;
4743
4744         /*
4745          * First pass the configuration through rt2x00lib, that will
4746          * update the queue settings and validate the input. After that
4747          * we are free to update the registers based on the value
4748          * in the queue parameter.
4749          */
4750         retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
4751         if (retval)
4752                 return retval;
4753
4754         /*
4755          * We only need to perform additional register initialization
4756          * for WMM queues/
4757          */
4758         if (queue_idx >= 4)
4759                 return 0;
4760
4761         queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
4762
4763         /* Update WMM TXOP register */
4764         offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
4765         field.bit_offset = (queue_idx & 1) * 16;
4766         field.bit_mask = 0xffff << field.bit_offset;
4767
4768         rt2800_register_read(rt2x00dev, offset, &reg);
4769         rt2x00_set_field32(&reg, field, queue->txop);
4770         rt2800_register_write(rt2x00dev, offset, reg);
4771
4772         /* Update WMM registers */
4773         field.bit_offset = queue_idx * 4;
4774         field.bit_mask = 0xf << field.bit_offset;
4775
4776         rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
4777         rt2x00_set_field32(&reg, field, queue->aifs);
4778         rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
4779
4780         rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
4781         rt2x00_set_field32(&reg, field, queue->cw_min);
4782         rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
4783
4784         rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
4785         rt2x00_set_field32(&reg, field, queue->cw_max);
4786         rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
4787
4788         /* Update EDCA registers */
4789         offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
4790
4791         rt2800_register_read(rt2x00dev, offset, &reg);
4792         rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
4793         rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
4794         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
4795         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
4796         rt2800_register_write(rt2x00dev, offset, reg);
4797
4798         return 0;
4799 }
4800 EXPORT_SYMBOL_GPL(rt2800_conf_tx);
4801
4802 u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
4803 {
4804         struct rt2x00_dev *rt2x00dev = hw->priv;
4805         u64 tsf;
4806         u32 reg;
4807
4808         rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
4809         tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
4810         rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
4811         tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
4812
4813         return tsf;
4814 }
4815 EXPORT_SYMBOL_GPL(rt2800_get_tsf);
4816
4817 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4818                         enum ieee80211_ampdu_mlme_action action,
4819                         struct ieee80211_sta *sta, u16 tid, u16 *ssn,
4820                         u8 buf_size)
4821 {
4822         struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
4823         int ret = 0;
4824
4825         /*
4826          * Don't allow aggregation for stations the hardware isn't aware
4827          * of because tx status reports for frames to an unknown station
4828          * always contain wcid=255 and thus we can't distinguish between
4829          * multiple stations which leads to unwanted situations when the
4830          * hw reorders frames due to aggregation.
4831          */
4832         if (sta_priv->wcid < 0)
4833                 return 1;
4834
4835         switch (action) {
4836         case IEEE80211_AMPDU_RX_START:
4837         case IEEE80211_AMPDU_RX_STOP:
4838                 /*
4839                  * The hw itself takes care of setting up BlockAck mechanisms.
4840                  * So, we only have to allow mac80211 to nagotiate a BlockAck
4841                  * agreement. Once that is done, the hw will BlockAck incoming
4842                  * AMPDUs without further setup.
4843                  */
4844                 break;
4845         case IEEE80211_AMPDU_TX_START:
4846                 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
4847                 break;
4848         case IEEE80211_AMPDU_TX_STOP:
4849                 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
4850                 break;
4851         case IEEE80211_AMPDU_TX_OPERATIONAL:
4852                 break;
4853         default:
4854                 WARNING((struct rt2x00_dev *)hw->priv, "Unknown AMPDU action\n");
4855         }
4856
4857         return ret;
4858 }
4859 EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
4860
4861 int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
4862                       struct survey_info *survey)
4863 {
4864         struct rt2x00_dev *rt2x00dev = hw->priv;
4865         struct ieee80211_conf *conf = &hw->conf;
4866         u32 idle, busy, busy_ext;
4867
4868         if (idx != 0)
4869                 return -ENOENT;
4870
4871         survey->channel = conf->channel;
4872
4873         rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
4874         rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
4875         rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
4876
4877         if (idle || busy) {
4878                 survey->filled = SURVEY_INFO_CHANNEL_TIME |
4879                                  SURVEY_INFO_CHANNEL_TIME_BUSY |
4880                                  SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
4881
4882                 survey->channel_time = (idle + busy) / 1000;
4883                 survey->channel_time_busy = busy / 1000;
4884                 survey->channel_time_ext_busy = busy_ext / 1000;
4885         }
4886
4887         if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
4888                 survey->filled |= SURVEY_INFO_IN_USE;
4889
4890         return 0;
4891
4892 }
4893 EXPORT_SYMBOL_GPL(rt2800_get_survey);
4894
4895 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
4896 MODULE_VERSION(DRV_VERSION);
4897 MODULE_DESCRIPTION("Ralink RT2800 library");
4898 MODULE_LICENSE("GPL");