2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
7 Based on the original rt2800pci.c and rt2800usb.c.
8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
14 <http://rt2x00.serialmonkey.com>
16 This program is free software; you can redistribute it and/or modify
17 it under the terms of the GNU General Public License as published by
18 the Free Software Foundation; either version 2 of the License, or
19 (at your option) any later version.
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
26 You should have received a copy of the GNU General Public License
27 along with this program; if not, write to the
28 Free Software Foundation, Inc.,
29 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
34 Abstract: rt2800 generic device routines.
37 #include <linux/crc-ccitt.h>
38 #include <linux/kernel.h>
39 #include <linux/module.h>
40 #include <linux/slab.h>
43 #include "rt2800lib.h"
48 * All access to the CSR registers will go through the methods
49 * rt2800_register_read and rt2800_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 * The _lock versions must be used if you already hold the csr_mutex
60 #define WAIT_FOR_BBP(__dev, __reg) \
61 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
62 #define WAIT_FOR_RFCSR(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
64 #define WAIT_FOR_RF(__dev, __reg) \
65 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
66 #define WAIT_FOR_MCU(__dev, __reg) \
67 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
68 H2M_MAILBOX_CSR_OWNER, (__reg))
70 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
72 /* check for rt2872 on SoC */
73 if (!rt2x00_is_soc(rt2x00dev) ||
74 !rt2x00_rt(rt2x00dev, RT2872))
77 /* we know for sure that these rf chipsets are used on rt305x boards */
78 if (rt2x00_rf(rt2x00dev, RF3020) ||
79 rt2x00_rf(rt2x00dev, RF3021) ||
80 rt2x00_rf(rt2x00dev, RF3022))
83 NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n");
87 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
88 const unsigned int word, const u8 value)
92 mutex_lock(&rt2x00dev->csr_mutex);
95 * Wait until the BBP becomes available, afterwards we
96 * can safely write the new data into the register.
98 if (WAIT_FOR_BBP(rt2x00dev, ®)) {
100 rt2x00_set_field32(®, BBP_CSR_CFG_VALUE, value);
101 rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word);
102 rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1);
103 rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 0);
104 rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1);
106 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
109 mutex_unlock(&rt2x00dev->csr_mutex);
112 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
113 const unsigned int word, u8 *value)
117 mutex_lock(&rt2x00dev->csr_mutex);
120 * Wait until the BBP becomes available, afterwards we
121 * can safely write the read request into the register.
122 * After the data has been written, we wait until hardware
123 * returns the correct value, if at any time the register
124 * doesn't become available in time, reg will be 0xffffffff
125 * which means we return 0xff to the caller.
127 if (WAIT_FOR_BBP(rt2x00dev, ®)) {
129 rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word);
130 rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1);
131 rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 1);
132 rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1);
134 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
136 WAIT_FOR_BBP(rt2x00dev, ®);
139 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
141 mutex_unlock(&rt2x00dev->csr_mutex);
144 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
145 const unsigned int word, const u8 value)
149 mutex_lock(&rt2x00dev->csr_mutex);
152 * Wait until the RFCSR becomes available, afterwards we
153 * can safely write the new data into the register.
155 if (WAIT_FOR_RFCSR(rt2x00dev, ®)) {
157 rt2x00_set_field32(®, RF_CSR_CFG_DATA, value);
158 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word);
159 rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 1);
160 rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1);
162 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
165 mutex_unlock(&rt2x00dev->csr_mutex);
168 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
169 const unsigned int word, u8 *value)
173 mutex_lock(&rt2x00dev->csr_mutex);
176 * Wait until the RFCSR becomes available, afterwards we
177 * can safely write the read request into the register.
178 * After the data has been written, we wait until hardware
179 * returns the correct value, if at any time the register
180 * doesn't become available in time, reg will be 0xffffffff
181 * which means we return 0xff to the caller.
183 if (WAIT_FOR_RFCSR(rt2x00dev, ®)) {
185 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word);
186 rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 0);
187 rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1);
189 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
191 WAIT_FOR_RFCSR(rt2x00dev, ®);
194 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
196 mutex_unlock(&rt2x00dev->csr_mutex);
199 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
200 const unsigned int word, const u32 value)
204 mutex_lock(&rt2x00dev->csr_mutex);
207 * Wait until the RF becomes available, afterwards we
208 * can safely write the new data into the register.
210 if (WAIT_FOR_RF(rt2x00dev, ®)) {
212 rt2x00_set_field32(®, RF_CSR_CFG0_REG_VALUE_BW, value);
213 rt2x00_set_field32(®, RF_CSR_CFG0_STANDBYMODE, 0);
214 rt2x00_set_field32(®, RF_CSR_CFG0_SEL, 0);
215 rt2x00_set_field32(®, RF_CSR_CFG0_BUSY, 1);
217 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
218 rt2x00_rf_write(rt2x00dev, word, value);
221 mutex_unlock(&rt2x00dev->csr_mutex);
224 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
225 const u8 command, const u8 token,
226 const u8 arg0, const u8 arg1)
231 * SOC devices don't support MCU requests.
233 if (rt2x00_is_soc(rt2x00dev))
236 mutex_lock(&rt2x00dev->csr_mutex);
239 * Wait until the MCU becomes available, afterwards we
240 * can safely write the new data into the register.
242 if (WAIT_FOR_MCU(rt2x00dev, ®)) {
243 rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1);
244 rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token);
245 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG0, arg0);
246 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG1, arg1);
247 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
250 rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command);
251 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
254 mutex_unlock(&rt2x00dev->csr_mutex);
256 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
258 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
263 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
264 rt2800_register_read(rt2x00dev, MAC_CSR0, ®);
265 if (reg && reg != ~0)
270 ERROR(rt2x00dev, "Unstable hardware.\n");
273 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
275 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
281 * Some devices are really slow to respond here. Wait a whole second
284 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
285 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®);
286 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
287 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
293 ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
296 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
298 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
304 * The last 2 bytes in the firmware array are the crc checksum itself,
305 * this means that we should never pass those 2 bytes to the crc
308 fw_crc = (data[len - 2] << 8 | data[len - 1]);
311 * Use the crc ccitt algorithm.
312 * This will return the same value as the legacy driver which
313 * used bit ordering reversion on the both the firmware bytes
314 * before input input as well as on the final output.
315 * Obviously using crc ccitt directly is much more efficient.
317 crc = crc_ccitt(~0, data, len - 2);
320 * There is a small difference between the crc-itu-t + bitrev and
321 * the crc-ccitt crc calculation. In the latter method the 2 bytes
322 * will be swapped, use swab16 to convert the crc to the correct
327 return fw_crc == crc;
330 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
331 const u8 *data, const size_t len)
338 * PCI(e) & SOC devices require firmware with a length
339 * of 8kb. USB devices require firmware files with a length
340 * of 4kb. Certain USB chipsets however require different firmware,
341 * which Ralink only provides attached to the original firmware
342 * file. Thus for USB devices, firmware files have a length
343 * which is a multiple of 4kb.
345 if (rt2x00_is_usb(rt2x00dev)) {
354 * Validate the firmware length
356 if (len != fw_len && (!multiple || (len % fw_len) != 0))
357 return FW_BAD_LENGTH;
360 * Check if the chipset requires one of the upper parts
363 if (rt2x00_is_usb(rt2x00dev) &&
364 !rt2x00_rt(rt2x00dev, RT2860) &&
365 !rt2x00_rt(rt2x00dev, RT2872) &&
366 !rt2x00_rt(rt2x00dev, RT3070) &&
367 ((len / fw_len) == 1))
368 return FW_BAD_VERSION;
371 * 8kb firmware files must be checked as if it were
372 * 2 separate firmware files.
374 while (offset < len) {
375 if (!rt2800_check_firmware_crc(data + offset, fw_len))
383 EXPORT_SYMBOL_GPL(rt2800_check_firmware);
385 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
386 const u8 *data, const size_t len)
392 * If driver doesn't wake up firmware here,
393 * rt2800_load_firmware will hang forever when interface is up again.
395 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
398 * Wait for stable hardware.
400 if (rt2800_wait_csr_ready(rt2x00dev))
403 if (rt2x00_is_pci(rt2x00dev))
404 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
407 * Disable DMA, will be reenabled later when enabling
410 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®);
411 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
412 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
413 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
414 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
415 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
416 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
419 * Write firmware to the device.
421 rt2800_drv_write_firmware(rt2x00dev, data, len);
424 * Wait for device to stabilize.
426 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
427 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, ®);
428 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
433 if (i == REGISTER_BUSY_COUNT) {
434 ERROR(rt2x00dev, "PBF system register not ready.\n");
439 * Initialize firmware.
441 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
442 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
447 EXPORT_SYMBOL_GPL(rt2800_load_firmware);
449 void rt2800_write_tx_data(struct queue_entry *entry,
450 struct txentry_desc *txdesc)
452 __le32 *txwi = rt2800_drv_get_txwi(entry);
456 * Initialize TX Info descriptor
458 rt2x00_desc_read(txwi, 0, &word);
459 rt2x00_set_field32(&word, TXWI_W0_FRAG,
460 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
461 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
462 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
463 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
464 rt2x00_set_field32(&word, TXWI_W0_TS,
465 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
466 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
467 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
468 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
469 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->txop);
470 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
471 rt2x00_set_field32(&word, TXWI_W0_BW,
472 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
473 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
474 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
475 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
476 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
477 rt2x00_desc_write(txwi, 0, word);
479 rt2x00_desc_read(txwi, 1, &word);
480 rt2x00_set_field32(&word, TXWI_W1_ACK,
481 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
482 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
483 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
484 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
485 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
486 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
487 txdesc->key_idx : 0xff);
488 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
490 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
491 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
492 rt2x00_desc_write(txwi, 1, word);
495 * Always write 0 to IV/EIV fields, hardware will insert the IV
496 * from the IVEIV register when TXD_W3_WIV is set to 0.
497 * When TXD_W3_WIV is set to 1 it will use the IV data
498 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
499 * crypto entry in the registers should be used to encrypt the frame.
501 _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
502 _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
504 EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
506 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
508 int rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
509 int rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
510 int rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
516 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
517 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
518 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
519 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
520 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
521 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
523 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
524 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
525 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
526 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
527 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
531 * Convert the value from the descriptor into the RSSI value
532 * If the value in the descriptor is 0, it is considered invalid
533 * and the default (extremely low) rssi value is assumed
535 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
536 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
537 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
540 * mac80211 only accepts a single RSSI value. Calculating the
541 * average doesn't deliver a fair answer either since -60:-60 would
542 * be considered equally good as -50:-70 while the second is the one
543 * which gives less energy...
545 rssi0 = max(rssi0, rssi1);
546 return max(rssi0, rssi2);
549 void rt2800_process_rxwi(struct queue_entry *entry,
550 struct rxdone_entry_desc *rxdesc)
552 __le32 *rxwi = (__le32 *) entry->skb->data;
555 rt2x00_desc_read(rxwi, 0, &word);
557 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
558 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
560 rt2x00_desc_read(rxwi, 1, &word);
562 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
563 rxdesc->flags |= RX_FLAG_SHORT_GI;
565 if (rt2x00_get_field32(word, RXWI_W1_BW))
566 rxdesc->flags |= RX_FLAG_40MHZ;
569 * Detect RX rate, always use MCS as signal type.
571 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
572 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
573 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
576 * Mask of 0x8 bit to remove the short preamble flag.
578 if (rxdesc->rate_mode == RATE_MODE_CCK)
579 rxdesc->signal &= ~0x8;
581 rt2x00_desc_read(rxwi, 2, &word);
584 * Convert descriptor AGC value to RSSI value.
586 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
589 * Remove RXWI descriptor from start of buffer.
591 skb_pull(entry->skb, RXWI_DESC_SIZE);
593 EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
595 static bool rt2800_txdone_entry_check(struct queue_entry *entry, u32 reg)
600 int tx_wcid, tx_ack, tx_pid;
602 wcid = rt2x00_get_field32(reg, TX_STA_FIFO_WCID);
603 ack = rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED);
604 pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE);
607 * This frames has returned with an IO error,
608 * so the status report is not intended for this
611 if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags)) {
612 rt2x00lib_txdone_noinfo(entry, TXDONE_FAILURE);
617 * Validate if this TX status report is intended for
618 * this entry by comparing the WCID/ACK/PID fields.
620 txwi = rt2800_drv_get_txwi(entry);
622 rt2x00_desc_read(txwi, 1, &word);
623 tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID);
624 tx_ack = rt2x00_get_field32(word, TXWI_W1_ACK);
625 tx_pid = rt2x00_get_field32(word, TXWI_W1_PACKETID);
627 if ((wcid != tx_wcid) || (ack != tx_ack) || (pid != tx_pid)) {
628 WARNING(entry->queue->rt2x00dev,
629 "TX status report missed for queue %d entry %d\n",
630 entry->queue->qid, entry->entry_idx);
631 rt2x00lib_txdone_noinfo(entry, TXDONE_UNKNOWN);
638 void rt2800_txdone_entry(struct queue_entry *entry, u32 status)
640 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
641 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
642 struct txdone_entry_desc txdesc;
649 * Obtain the status about this packet.
652 txwi = rt2800_drv_get_txwi(entry);
653 rt2x00_desc_read(txwi, 0, &word);
655 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
656 ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
658 real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
659 aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
662 * If a frame was meant to be sent as a single non-aggregated MPDU
663 * but ended up in an aggregate the used tx rate doesn't correlate
664 * with the one specified in the TXWI as the whole aggregate is sent
665 * with the same rate.
667 * For example: two frames are sent to rt2x00, the first one sets
668 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
669 * and requests MCS15. If the hw aggregates both frames into one
670 * AMDPU the tx status for both frames will contain MCS7 although
671 * the frame was sent successfully.
673 * Hence, replace the requested rate with the real tx rate to not
674 * confuse the rate control algortihm by providing clearly wrong
677 if (aggr == 1 && ampdu == 0 && real_mcs != mcs) {
678 skbdesc->tx_rate_idx = real_mcs;
683 * Ralink has a retry mechanism using a global fallback
684 * table. We setup this fallback table to try the immediate
685 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
686 * always contains the MCS used for the last transmission, be
687 * it successful or not.
689 if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
691 * Transmission succeeded. The number of retries is
694 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
695 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
698 * Transmission failed. The number of retries is
699 * always 7 in this case (for a total number of 8
702 __set_bit(TXDONE_FAILURE, &txdesc.flags);
703 txdesc.retry = rt2x00dev->long_retry;
707 * the frame was retried at least once
708 * -> hw used fallback rates
711 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
713 rt2x00lib_txdone(entry, &txdesc);
715 EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
717 void rt2800_txdone(struct rt2x00_dev *rt2x00dev)
719 struct data_queue *queue;
720 struct queue_entry *entry;
726 * TX_STA_FIFO is a stack of X entries, hence read TX_STA_FIFO
727 * at most X times and also stop processing once the TX_STA_FIFO_VALID
728 * flag is not set anymore.
730 * The legacy drivers use X=TX_RING_SIZE but state in a comment
731 * that the TX_STA_FIFO stack has a size of 16. We stick to our
732 * tx ring size for now.
734 for (i = 0; i < rt2x00dev->ops->tx->entry_num; i++) {
735 rt2800_register_read(rt2x00dev, TX_STA_FIFO, ®);
736 if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
740 * Skip this entry when it contains an invalid
741 * queue identication number.
743 pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_QUEUE);
747 queue = rt2x00queue_get_queue(rt2x00dev, pid);
748 if (unlikely(!queue))
752 * Inside each queue, we process each entry in a chronological
753 * order. We first check that the queue is not empty.
756 while (!rt2x00queue_empty(queue)) {
757 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
758 if (rt2800_txdone_entry_check(entry, reg))
762 if (!entry || rt2x00queue_empty(queue))
765 rt2800_txdone_entry(entry, reg);
768 EXPORT_SYMBOL_GPL(rt2800_txdone);
770 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
772 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
773 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
774 unsigned int beacon_base;
778 * Disable beaconing while we are reloading the beacon data,
779 * otherwise we might be sending out invalid data.
781 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®);
782 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0);
783 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
786 * Add space for the TXWI in front of the skb.
788 skb_push(entry->skb, TXWI_DESC_SIZE);
789 memset(entry->skb, 0, TXWI_DESC_SIZE);
792 * Register descriptor details in skb frame descriptor.
794 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
795 skbdesc->desc = entry->skb->data;
796 skbdesc->desc_len = TXWI_DESC_SIZE;
799 * Add the TXWI for the beacon to the skb.
801 rt2800_write_tx_data(entry, txdesc);
804 * Dump beacon to userspace through debugfs.
806 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
809 * Write entire beacon with TXWI to register.
811 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
812 rt2800_register_multiwrite(rt2x00dev, beacon_base,
813 entry->skb->data, entry->skb->len);
816 * Enable beaconing again.
818 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 1);
819 rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 1);
820 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 1);
821 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
824 * Clean up beacon skb.
826 dev_kfree_skb_any(entry->skb);
829 EXPORT_SYMBOL_GPL(rt2800_write_beacon);
831 static inline void rt2800_clear_beacon(struct rt2x00_dev *rt2x00dev,
832 unsigned int beacon_base)
837 * For the Beacon base registers we only need to clear
838 * the whole TXWI which (when set to 0) will invalidate
841 for (i = 0; i < TXWI_DESC_SIZE; i += sizeof(__le32))
842 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
845 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
846 const struct rt2x00debug rt2800_rt2x00debug = {
847 .owner = THIS_MODULE,
849 .read = rt2800_register_read,
850 .write = rt2800_register_write,
851 .flags = RT2X00DEBUGFS_OFFSET,
852 .word_base = CSR_REG_BASE,
853 .word_size = sizeof(u32),
854 .word_count = CSR_REG_SIZE / sizeof(u32),
857 .read = rt2x00_eeprom_read,
858 .write = rt2x00_eeprom_write,
859 .word_base = EEPROM_BASE,
860 .word_size = sizeof(u16),
861 .word_count = EEPROM_SIZE / sizeof(u16),
864 .read = rt2800_bbp_read,
865 .write = rt2800_bbp_write,
866 .word_base = BBP_BASE,
867 .word_size = sizeof(u8),
868 .word_count = BBP_SIZE / sizeof(u8),
871 .read = rt2x00_rf_read,
872 .write = rt2800_rf_write,
873 .word_base = RF_BASE,
874 .word_size = sizeof(u32),
875 .word_count = RF_SIZE / sizeof(u32),
878 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
879 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
881 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
885 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, ®);
886 return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
888 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
890 #ifdef CONFIG_RT2X00_LIB_LEDS
891 static void rt2800_brightness_set(struct led_classdev *led_cdev,
892 enum led_brightness brightness)
894 struct rt2x00_led *led =
895 container_of(led_cdev, struct rt2x00_led, led_dev);
896 unsigned int enabled = brightness != LED_OFF;
897 unsigned int bg_mode =
898 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
899 unsigned int polarity =
900 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
901 EEPROM_FREQ_LED_POLARITY);
902 unsigned int ledmode =
903 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
904 EEPROM_FREQ_LED_MODE);
906 if (led->type == LED_TYPE_RADIO) {
907 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
909 } else if (led->type == LED_TYPE_ASSOC) {
910 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
911 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
912 } else if (led->type == LED_TYPE_QUALITY) {
914 * The brightness is divided into 6 levels (0 - 5),
915 * The specs tell us the following levels:
917 * to determine the level in a simple way we can simply
918 * work with bitshifting:
921 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
922 (1 << brightness / (LED_FULL / 6)) - 1,
927 static int rt2800_blink_set(struct led_classdev *led_cdev,
928 unsigned long *delay_on, unsigned long *delay_off)
930 struct rt2x00_led *led =
931 container_of(led_cdev, struct rt2x00_led, led_dev);
934 rt2800_register_read(led->rt2x00dev, LED_CFG, ®);
935 rt2x00_set_field32(®, LED_CFG_ON_PERIOD, *delay_on);
936 rt2x00_set_field32(®, LED_CFG_OFF_PERIOD, *delay_off);
937 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
942 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
943 struct rt2x00_led *led, enum led_type type)
945 led->rt2x00dev = rt2x00dev;
947 led->led_dev.brightness_set = rt2800_brightness_set;
948 led->led_dev.blink_set = rt2800_blink_set;
949 led->flags = LED_INITIALIZED;
951 #endif /* CONFIG_RT2X00_LIB_LEDS */
954 * Configuration handlers.
956 static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
957 struct rt2x00lib_crypto *crypto,
958 struct ieee80211_key_conf *key)
960 struct mac_wcid_entry wcid_entry;
961 struct mac_iveiv_entry iveiv_entry;
965 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
967 if (crypto->cmd == SET_KEY) {
968 rt2800_register_read(rt2x00dev, offset, ®);
969 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB,
970 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
972 * Both the cipher as the BSS Idx numbers are split in a main
973 * value of 3 bits, and a extended field for adding one additional
976 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER,
977 (crypto->cipher & 0x7));
978 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
979 (crypto->cipher & 0x8) >> 3);
980 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX,
981 (crypto->bssidx & 0x7));
982 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
983 (crypto->bssidx & 0x8) >> 3);
984 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
985 rt2800_register_write(rt2x00dev, offset, reg);
987 rt2800_register_write(rt2x00dev, offset, 0);
990 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
992 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
993 if ((crypto->cipher == CIPHER_TKIP) ||
994 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
995 (crypto->cipher == CIPHER_AES))
996 iveiv_entry.iv[3] |= 0x20;
997 iveiv_entry.iv[3] |= key->keyidx << 6;
998 rt2800_register_multiwrite(rt2x00dev, offset,
999 &iveiv_entry, sizeof(iveiv_entry));
1001 offset = MAC_WCID_ENTRY(key->hw_key_idx);
1003 memset(&wcid_entry, 0, sizeof(wcid_entry));
1004 if (crypto->cmd == SET_KEY)
1005 memcpy(&wcid_entry, crypto->address, ETH_ALEN);
1006 rt2800_register_multiwrite(rt2x00dev, offset,
1007 &wcid_entry, sizeof(wcid_entry));
1010 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1011 struct rt2x00lib_crypto *crypto,
1012 struct ieee80211_key_conf *key)
1014 struct hw_key_entry key_entry;
1015 struct rt2x00_field32 field;
1019 if (crypto->cmd == SET_KEY) {
1020 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1022 memcpy(key_entry.key, crypto->key,
1023 sizeof(key_entry.key));
1024 memcpy(key_entry.tx_mic, crypto->tx_mic,
1025 sizeof(key_entry.tx_mic));
1026 memcpy(key_entry.rx_mic, crypto->rx_mic,
1027 sizeof(key_entry.rx_mic));
1029 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1030 rt2800_register_multiwrite(rt2x00dev, offset,
1031 &key_entry, sizeof(key_entry));
1035 * The cipher types are stored over multiple registers
1036 * starting with SHARED_KEY_MODE_BASE each word will have
1037 * 32 bits and contains the cipher types for 2 bssidx each.
1038 * Using the correct defines correctly will cause overhead,
1039 * so just calculate the correct offset.
1041 field.bit_offset = 4 * (key->hw_key_idx % 8);
1042 field.bit_mask = 0x7 << field.bit_offset;
1044 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1046 rt2800_register_read(rt2x00dev, offset, ®);
1047 rt2x00_set_field32(®, field,
1048 (crypto->cmd == SET_KEY) * crypto->cipher);
1049 rt2800_register_write(rt2x00dev, offset, reg);
1052 * Update WCID information
1054 rt2800_config_wcid_attr(rt2x00dev, crypto, key);
1058 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1060 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1061 struct rt2x00lib_crypto *crypto,
1062 struct ieee80211_key_conf *key)
1064 struct hw_key_entry key_entry;
1067 if (crypto->cmd == SET_KEY) {
1069 * 1 pairwise key is possible per AID, this means that the AID
1070 * equals our hw_key_idx. Make sure the WCID starts _after_ the
1071 * last possible shared key entry.
1073 * Since parts of the pairwise key table might be shared with
1074 * the beacon frame buffers 6 & 7 we should only write into the
1075 * first 222 entries.
1077 if (crypto->aid > (222 - 32))
1080 key->hw_key_idx = 32 + crypto->aid;
1082 memcpy(key_entry.key, crypto->key,
1083 sizeof(key_entry.key));
1084 memcpy(key_entry.tx_mic, crypto->tx_mic,
1085 sizeof(key_entry.tx_mic));
1086 memcpy(key_entry.rx_mic, crypto->rx_mic,
1087 sizeof(key_entry.rx_mic));
1089 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1090 rt2800_register_multiwrite(rt2x00dev, offset,
1091 &key_entry, sizeof(key_entry));
1095 * Update WCID information
1097 rt2800_config_wcid_attr(rt2x00dev, crypto, key);
1101 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1103 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1104 const unsigned int filter_flags)
1109 * Start configuration steps.
1110 * Note that the version error will always be dropped
1111 * and broadcast frames will always be accepted since
1112 * there is no filter for it at this time.
1114 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, ®);
1115 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CRC_ERROR,
1116 !(filter_flags & FIF_FCSFAIL));
1117 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PHY_ERROR,
1118 !(filter_flags & FIF_PLCPFAIL));
1119 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_TO_ME,
1120 !(filter_flags & FIF_PROMISC_IN_BSS));
1121 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1122 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1123 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_MULTICAST,
1124 !(filter_flags & FIF_ALLMULTI));
1125 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BROADCAST, 0);
1126 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1127 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END_ACK,
1128 !(filter_flags & FIF_CONTROL));
1129 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END,
1130 !(filter_flags & FIF_CONTROL));
1131 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_ACK,
1132 !(filter_flags & FIF_CONTROL));
1133 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CTS,
1134 !(filter_flags & FIF_CONTROL));
1135 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_RTS,
1136 !(filter_flags & FIF_CONTROL));
1137 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PSPOLL,
1138 !(filter_flags & FIF_PSPOLL));
1139 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BA, 1);
1140 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BAR, 0);
1141 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CNTL,
1142 !(filter_flags & FIF_CONTROL));
1143 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1145 EXPORT_SYMBOL_GPL(rt2800_config_filter);
1147 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1148 struct rt2x00intf_conf *conf, const unsigned int flags)
1151 bool update_bssid = false;
1153 if (flags & CONFIG_UPDATE_TYPE) {
1155 * Clear current synchronisation setup.
1157 rt2800_clear_beacon(rt2x00dev,
1158 HW_BEACON_OFFSET(intf->beacon->entry_idx));
1160 * Enable synchronisation.
1162 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®);
1163 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 1);
1164 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, conf->sync);
1165 rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE,
1166 (conf->sync == TSF_SYNC_ADHOC ||
1167 conf->sync == TSF_SYNC_AP_NONE));
1168 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1171 * Enable pre tbtt interrupt for beaconing modes
1173 rt2800_register_read(rt2x00dev, INT_TIMER_EN, ®);
1174 rt2x00_set_field32(®, INT_TIMER_EN_PRE_TBTT_TIMER,
1175 (conf->sync == TSF_SYNC_AP_NONE));
1176 rt2800_register_write(rt2x00dev, INT_TIMER_EN, reg);
1180 if (flags & CONFIG_UPDATE_MAC) {
1181 if (flags & CONFIG_UPDATE_TYPE &&
1182 conf->sync == TSF_SYNC_AP_NONE) {
1184 * The BSSID register has to be set to our own mac
1185 * address in AP mode.
1187 memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1188 update_bssid = true;
1191 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1192 reg = le32_to_cpu(conf->mac[1]);
1193 rt2x00_set_field32(®, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1194 conf->mac[1] = cpu_to_le32(reg);
1197 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1198 conf->mac, sizeof(conf->mac));
1201 if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
1202 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1203 reg = le32_to_cpu(conf->bssid[1]);
1204 rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1205 rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1206 conf->bssid[1] = cpu_to_le32(reg);
1209 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1210 conf->bssid, sizeof(conf->bssid));
1213 EXPORT_SYMBOL_GPL(rt2800_config_intf);
1215 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1216 struct rt2x00lib_erp *erp)
1218 bool any_sta_nongf = !!(erp->ht_opmode &
1219 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1220 u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1221 u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1222 u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1225 /* default protection rate for HT20: OFDM 24M */
1226 mm20_rate = gf20_rate = 0x4004;
1228 /* default protection rate for HT40: duplicate OFDM 24M */
1229 mm40_rate = gf40_rate = 0x4084;
1231 switch (protection) {
1232 case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1234 * All STAs in this BSS are HT20/40 but there might be
1235 * STAs not supporting greenfield mode.
1236 * => Disable protection for HT transmissions.
1238 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1241 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1243 * All STAs in this BSS are HT20 or HT20/40 but there
1244 * might be STAs not supporting greenfield mode.
1245 * => Protect all HT40 transmissions.
1247 mm20_mode = gf20_mode = 0;
1248 mm40_mode = gf40_mode = 2;
1251 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1253 * Nonmember protection:
1254 * According to 802.11n we _should_ protect all
1255 * HT transmissions (but we don't have to).
1257 * But if cts_protection is enabled we _shall_ protect
1258 * all HT transmissions using a CCK rate.
1260 * And if any station is non GF we _shall_ protect
1263 * We decide to protect everything
1264 * -> fall through to mixed mode.
1266 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1268 * Legacy STAs are present
1269 * => Protect all HT transmissions.
1271 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1274 * If erp protection is needed we have to protect HT
1275 * transmissions with CCK 11M long preamble.
1277 if (erp->cts_protection) {
1278 /* don't duplicate RTS/CTS in CCK mode */
1279 mm20_rate = mm40_rate = 0x0003;
1280 gf20_rate = gf40_rate = 0x0003;
1285 /* check for STAs not supporting greenfield mode */
1287 gf20_mode = gf40_mode = 2;
1289 /* Update HT protection config */
1290 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, ®);
1291 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1292 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1293 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1295 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, ®);
1296 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1297 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1298 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1300 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, ®);
1301 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1302 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1303 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1305 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, ®);
1306 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1307 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1308 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1311 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1316 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1317 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, ®);
1318 rt2x00_set_field32(®, AUTO_RSP_CFG_BAC_ACK_POLICY,
1319 !!erp->short_preamble);
1320 rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE,
1321 !!erp->short_preamble);
1322 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1325 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1326 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, ®);
1327 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL,
1328 erp->cts_protection ? 2 : 0);
1329 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1332 if (changed & BSS_CHANGED_BASIC_RATES) {
1333 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1335 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1338 if (changed & BSS_CHANGED_ERP_SLOT) {
1339 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, ®);
1340 rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME,
1342 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1344 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, ®);
1345 rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, erp->eifs);
1346 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1349 if (changed & BSS_CHANGED_BEACON_INT) {
1350 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®);
1351 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL,
1352 erp->beacon_int * 16);
1353 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1356 if (changed & BSS_CHANGED_HT)
1357 rt2800_config_ht_opmode(rt2x00dev, erp);
1359 EXPORT_SYMBOL_GPL(rt2800_config_erp);
1361 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1366 rt2800_bbp_read(rt2x00dev, 1, &r1);
1367 rt2800_bbp_read(rt2x00dev, 3, &r3);
1370 * Configure the TX antenna.
1372 switch ((int)ant->tx) {
1374 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1377 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1380 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1385 * Configure the RX antenna.
1387 switch ((int)ant->rx) {
1389 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1392 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1395 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1399 rt2800_bbp_write(rt2x00dev, 3, r3);
1400 rt2800_bbp_write(rt2x00dev, 1, r1);
1402 EXPORT_SYMBOL_GPL(rt2800_config_ant);
1404 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1405 struct rt2x00lib_conf *libconf)
1410 if (libconf->rf.channel <= 14) {
1411 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1412 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1413 } else if (libconf->rf.channel <= 64) {
1414 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1415 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1416 } else if (libconf->rf.channel <= 128) {
1417 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1418 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
1420 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1421 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
1424 rt2x00dev->lna_gain = lna_gain;
1427 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1428 struct ieee80211_conf *conf,
1429 struct rf_channel *rf,
1430 struct channel_info *info)
1432 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1434 if (rt2x00dev->default_ant.tx == 1)
1435 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1437 if (rt2x00dev->default_ant.rx == 1) {
1438 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1439 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1440 } else if (rt2x00dev->default_ant.rx == 2)
1441 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1443 if (rf->channel > 14) {
1445 * When TX power is below 0, we should increase it by 7 to
1446 * make it a positive value (Minumum value is -7).
1447 * However this means that values between 0 and 7 have
1448 * double meaning, and we should set a 7DBm boost flag.
1450 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
1451 (info->default_power1 >= 0));
1453 if (info->default_power1 < 0)
1454 info->default_power1 += 7;
1456 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
1458 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
1459 (info->default_power2 >= 0));
1461 if (info->default_power2 < 0)
1462 info->default_power2 += 7;
1464 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
1466 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1467 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
1470 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1472 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1473 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1474 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1475 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1479 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1480 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1481 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1482 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1486 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1487 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1488 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1489 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1492 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1493 struct ieee80211_conf *conf,
1494 struct rf_channel *rf,
1495 struct channel_info *info)
1499 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1500 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
1502 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1503 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1504 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1506 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1507 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
1508 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1510 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1511 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
1512 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1514 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1515 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1516 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1518 rt2800_rfcsr_write(rt2x00dev, 24,
1519 rt2x00dev->calibration[conf_is_ht40(conf)]);
1521 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1522 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1523 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1526 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
1527 struct ieee80211_conf *conf,
1528 struct rf_channel *rf,
1529 struct channel_info *info)
1532 unsigned int tx_pin;
1535 if (rf->channel <= 14) {
1536 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
1537 info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2);
1539 info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1);
1540 info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2);
1543 if (rt2x00_rf(rt2x00dev, RF2020) ||
1544 rt2x00_rf(rt2x00dev, RF3020) ||
1545 rt2x00_rf(rt2x00dev, RF3021) ||
1546 rt2x00_rf(rt2x00dev, RF3022) ||
1547 rt2x00_rf(rt2x00dev, RF3052))
1548 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
1550 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
1553 * Change BBP settings
1555 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
1556 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
1557 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
1558 rt2800_bbp_write(rt2x00dev, 86, 0);
1560 if (rf->channel <= 14) {
1561 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
1562 rt2800_bbp_write(rt2x00dev, 82, 0x62);
1563 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1565 rt2800_bbp_write(rt2x00dev, 82, 0x84);
1566 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1569 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
1571 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1572 rt2800_bbp_write(rt2x00dev, 75, 0x46);
1574 rt2800_bbp_write(rt2x00dev, 75, 0x50);
1577 rt2800_register_read(rt2x00dev, TX_BAND_CFG, ®);
1578 rt2x00_set_field32(®, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
1579 rt2x00_set_field32(®, TX_BAND_CFG_A, rf->channel > 14);
1580 rt2x00_set_field32(®, TX_BAND_CFG_BG, rf->channel <= 14);
1581 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
1585 /* Turn on unused PA or LNA when not using 1T or 1R */
1586 if (rt2x00dev->default_ant.tx != 1) {
1587 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
1588 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
1591 /* Turn on unused PA or LNA when not using 1T or 1R */
1592 if (rt2x00dev->default_ant.rx != 1) {
1593 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
1594 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
1597 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
1598 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
1599 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
1600 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
1601 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
1602 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
1604 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
1606 rt2800_bbp_read(rt2x00dev, 4, &bbp);
1607 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
1608 rt2800_bbp_write(rt2x00dev, 4, bbp);
1610 rt2800_bbp_read(rt2x00dev, 3, &bbp);
1611 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
1612 rt2800_bbp_write(rt2x00dev, 3, bbp);
1614 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
1615 if (conf_is_ht40(conf)) {
1616 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
1617 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1618 rt2800_bbp_write(rt2x00dev, 73, 0x16);
1620 rt2800_bbp_write(rt2x00dev, 69, 0x16);
1621 rt2800_bbp_write(rt2x00dev, 70, 0x08);
1622 rt2800_bbp_write(rt2x00dev, 73, 0x11);
1629 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
1630 const int max_txpower)
1633 u8 max_value = (u8)max_txpower;
1641 * set to normal tx power mode: +/- 0dBm
1643 rt2800_bbp_read(rt2x00dev, 1, &r1);
1644 rt2x00_set_field8(&r1, BBP1_TX_POWER, 0);
1645 rt2800_bbp_write(rt2x00dev, 1, r1);
1648 * The eeprom contains the tx power values for each rate. These
1649 * values map to 100% tx power. Each 16bit word contains four tx
1650 * power values and the order is the same as used in the TX_PWR_CFG
1653 offset = TX_PWR_CFG_0;
1655 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
1656 /* just to be safe */
1657 if (offset > TX_PWR_CFG_4)
1660 rt2800_register_read(rt2x00dev, offset, ®);
1662 /* read the next four txpower values */
1663 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
1666 /* TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
1667 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
1668 * TX_PWR_CFG_4: unknown */
1669 txpower = rt2x00_get_field16(eeprom,
1670 EEPROM_TXPOWER_BYRATE_RATE0);
1671 rt2x00_set_field32(®, TX_PWR_CFG_RATE0,
1672 min(txpower, max_value));
1674 /* TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
1675 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
1676 * TX_PWR_CFG_4: unknown */
1677 txpower = rt2x00_get_field16(eeprom,
1678 EEPROM_TXPOWER_BYRATE_RATE1);
1679 rt2x00_set_field32(®, TX_PWR_CFG_RATE1,
1680 min(txpower, max_value));
1682 /* TX_PWR_CFG_0: 55MBS, TX_PWR_CFG_1: 48MBS,
1683 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
1684 * TX_PWR_CFG_4: unknown */
1685 txpower = rt2x00_get_field16(eeprom,
1686 EEPROM_TXPOWER_BYRATE_RATE2);
1687 rt2x00_set_field32(®, TX_PWR_CFG_RATE2,
1688 min(txpower, max_value));
1690 /* TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
1691 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
1692 * TX_PWR_CFG_4: unknown */
1693 txpower = rt2x00_get_field16(eeprom,
1694 EEPROM_TXPOWER_BYRATE_RATE3);
1695 rt2x00_set_field32(®, TX_PWR_CFG_RATE3,
1696 min(txpower, max_value));
1698 /* read the next four txpower values */
1699 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
1702 /* TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
1703 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
1704 * TX_PWR_CFG_4: unknown */
1705 txpower = rt2x00_get_field16(eeprom,
1706 EEPROM_TXPOWER_BYRATE_RATE0);
1707 rt2x00_set_field32(®, TX_PWR_CFG_RATE4,
1708 min(txpower, max_value));
1710 /* TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
1711 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
1712 * TX_PWR_CFG_4: unknown */
1713 txpower = rt2x00_get_field16(eeprom,
1714 EEPROM_TXPOWER_BYRATE_RATE1);
1715 rt2x00_set_field32(®, TX_PWR_CFG_RATE5,
1716 min(txpower, max_value));
1718 /* TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
1719 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
1720 * TX_PWR_CFG_4: unknown */
1721 txpower = rt2x00_get_field16(eeprom,
1722 EEPROM_TXPOWER_BYRATE_RATE2);
1723 rt2x00_set_field32(®, TX_PWR_CFG_RATE6,
1724 min(txpower, max_value));
1726 /* TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
1727 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
1728 * TX_PWR_CFG_4: unknown */
1729 txpower = rt2x00_get_field16(eeprom,
1730 EEPROM_TXPOWER_BYRATE_RATE3);
1731 rt2x00_set_field32(®, TX_PWR_CFG_RATE7,
1732 min(txpower, max_value));
1734 rt2800_register_write(rt2x00dev, offset, reg);
1736 /* next TX_PWR_CFG register */
1741 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
1742 struct rt2x00lib_conf *libconf)
1746 rt2800_register_read(rt2x00dev, TX_RTY_CFG, ®);
1747 rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT,
1748 libconf->conf->short_frame_max_tx_count);
1749 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT,
1750 libconf->conf->long_frame_max_tx_count);
1751 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
1754 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
1755 struct rt2x00lib_conf *libconf)
1757 enum dev_state state =
1758 (libconf->conf->flags & IEEE80211_CONF_PS) ?
1759 STATE_SLEEP : STATE_AWAKE;
1762 if (state == STATE_SLEEP) {
1763 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1765 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, ®);
1766 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
1767 rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
1768 libconf->conf->listen_interval - 1);
1769 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 1);
1770 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1772 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1774 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, ®);
1775 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
1776 rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1777 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1778 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1780 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1784 void rt2800_config(struct rt2x00_dev *rt2x00dev,
1785 struct rt2x00lib_conf *libconf,
1786 const unsigned int flags)
1788 /* Always recalculate LNA gain before changing configuration */
1789 rt2800_config_lna_gain(rt2x00dev, libconf);
1791 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1792 rt2800_config_channel(rt2x00dev, libconf->conf,
1793 &libconf->rf, &libconf->channel);
1794 if (flags & IEEE80211_CONF_CHANGE_POWER)
1795 rt2800_config_txpower(rt2x00dev, libconf->conf->power_level);
1796 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1797 rt2800_config_retry_limit(rt2x00dev, libconf);
1798 if (flags & IEEE80211_CONF_CHANGE_PS)
1799 rt2800_config_ps(rt2x00dev, libconf);
1801 EXPORT_SYMBOL_GPL(rt2800_config);
1806 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1811 * Update FCS error count from register.
1813 rt2800_register_read(rt2x00dev, RX_STA_CNT0, ®);
1814 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1816 EXPORT_SYMBOL_GPL(rt2800_link_stats);
1818 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1820 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1821 if (rt2x00_rt(rt2x00dev, RT3070) ||
1822 rt2x00_rt(rt2x00dev, RT3071) ||
1823 rt2x00_rt(rt2x00dev, RT3090) ||
1824 rt2x00_rt(rt2x00dev, RT3390))
1825 return 0x1c + (2 * rt2x00dev->lna_gain);
1827 return 0x2e + rt2x00dev->lna_gain;
1830 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1831 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1833 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1836 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
1837 struct link_qual *qual, u8 vgc_level)
1839 if (qual->vgc_level != vgc_level) {
1840 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
1841 qual->vgc_level = vgc_level;
1842 qual->vgc_level_reg = vgc_level;
1846 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1848 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
1850 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
1852 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
1855 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
1859 * When RSSI is better then -80 increase VGC level with 0x10
1861 rt2800_set_vgc(rt2x00dev, qual,
1862 rt2800_get_default_vgc(rt2x00dev) +
1863 ((qual->rssi > -80) * 0x10));
1865 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
1868 * Initialization functions.
1870 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1877 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®);
1878 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1879 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1880 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1881 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1882 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1883 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1885 ret = rt2800_drv_init_registers(rt2x00dev);
1889 rt2800_register_read(rt2x00dev, BCN_OFFSET0, ®);
1890 rt2x00_set_field32(®, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1891 rt2x00_set_field32(®, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1892 rt2x00_set_field32(®, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1893 rt2x00_set_field32(®, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1894 rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
1896 rt2800_register_read(rt2x00dev, BCN_OFFSET1, ®);
1897 rt2x00_set_field32(®, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1898 rt2x00_set_field32(®, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1899 rt2x00_set_field32(®, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1900 rt2x00_set_field32(®, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1901 rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
1903 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1904 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1906 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1908 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®);
1909 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
1910 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 0);
1911 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, 0);
1912 rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 0);
1913 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0);
1914 rt2x00_set_field32(®, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1915 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1917 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
1919 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, ®);
1920 rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, 9);
1921 rt2x00_set_field32(®, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
1922 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1924 if (rt2x00_rt(rt2x00dev, RT3071) ||
1925 rt2x00_rt(rt2x00dev, RT3090) ||
1926 rt2x00_rt(rt2x00dev, RT3390)) {
1927 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1928 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1929 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
1930 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
1931 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
1932 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1933 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
1934 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1937 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1940 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1942 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
1943 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1945 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
1946 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1947 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
1949 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1950 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1952 } else if (rt2800_is_305x_soc(rt2x00dev)) {
1953 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1954 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1955 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000001f);
1957 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1958 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1961 rt2800_register_read(rt2x00dev, TX_LINK_CFG, ®);
1962 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1963 rt2x00_set_field32(®, TX_LINK_CFG_MFB_ENABLE, 0);
1964 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1965 rt2x00_set_field32(®, TX_LINK_CFG_TX_MRQ_EN, 0);
1966 rt2x00_set_field32(®, TX_LINK_CFG_TX_RDG_EN, 0);
1967 rt2x00_set_field32(®, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1968 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB, 0);
1969 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFS, 0);
1970 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
1972 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, ®);
1973 rt2x00_set_field32(®, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1974 rt2x00_set_field32(®, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
1975 rt2x00_set_field32(®, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1976 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1978 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, ®);
1979 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1980 if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
1981 rt2x00_rt(rt2x00dev, RT2883) ||
1982 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
1983 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, 2);
1985 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, 1);
1986 rt2x00_set_field32(®, MAX_LEN_CFG_MIN_PSDU, 0);
1987 rt2x00_set_field32(®, MAX_LEN_CFG_MIN_MPDU, 0);
1988 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1990 rt2800_register_read(rt2x00dev, LED_CFG, ®);
1991 rt2x00_set_field32(®, LED_CFG_ON_PERIOD, 70);
1992 rt2x00_set_field32(®, LED_CFG_OFF_PERIOD, 30);
1993 rt2x00_set_field32(®, LED_CFG_SLOW_BLINK_PERIOD, 3);
1994 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, 3);
1995 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, 3);
1996 rt2x00_set_field32(®, LED_CFG_Y_LED_MODE, 3);
1997 rt2x00_set_field32(®, LED_CFG_LED_POLAR, 1);
1998 rt2800_register_write(rt2x00dev, LED_CFG, reg);
2000 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
2002 rt2800_register_read(rt2x00dev, TX_RTY_CFG, ®);
2003 rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
2004 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
2005 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_THRE, 2000);
2006 rt2x00_set_field32(®, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
2007 rt2x00_set_field32(®, TX_RTY_CFG_AGG_RTY_MODE, 0);
2008 rt2x00_set_field32(®, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
2009 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
2011 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, ®);
2012 rt2x00_set_field32(®, AUTO_RSP_CFG_AUTORESPONDER, 1);
2013 rt2x00_set_field32(®, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
2014 rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MMODE, 0);
2015 rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MREF, 0);
2016 rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, 1);
2017 rt2x00_set_field32(®, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
2018 rt2x00_set_field32(®, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
2019 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
2021 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, ®);
2022 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_RATE, 3);
2023 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_CTRL, 0);
2024 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_NAV, 1);
2025 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2026 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2027 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2028 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2029 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2030 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2031 rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, 1);
2032 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2034 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, ®);
2035 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_RATE, 3);
2036 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, 0);
2037 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_NAV, 1);
2038 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2039 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2040 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2041 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2042 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2043 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2044 rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, 1);
2045 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2047 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, ®);
2048 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
2049 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, 0);
2050 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_NAV, 1);
2051 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2052 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2053 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2054 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2055 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2056 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2057 rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, 0);
2058 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2060 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, ®);
2061 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
2062 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, 0);
2063 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_NAV, 1);
2064 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2065 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2066 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2067 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2068 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2069 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
2070 rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, 0);
2071 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2073 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, ®);
2074 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
2075 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, 0);
2076 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_NAV, 1);
2077 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2078 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2079 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2080 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
2081 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2082 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
2083 rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, 0);
2084 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2086 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, ®);
2087 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
2088 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, 0);
2089 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_NAV, 1);
2090 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
2091 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
2092 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
2093 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
2094 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
2095 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
2096 rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, 0);
2097 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2099 if (rt2x00_is_usb(rt2x00dev)) {
2100 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
2102 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®);
2103 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2104 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2105 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2106 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2107 rt2x00_set_field32(®, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
2108 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
2109 rt2x00_set_field32(®, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
2110 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
2111 rt2x00_set_field32(®, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
2112 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2116 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
2117 * although it is reserved.
2119 rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, ®);
2120 rt2x00_set_field32(®, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
2121 rt2x00_set_field32(®, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
2122 rt2x00_set_field32(®, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
2123 rt2x00_set_field32(®, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
2124 rt2x00_set_field32(®, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
2125 rt2x00_set_field32(®, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
2126 rt2x00_set_field32(®, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
2127 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
2128 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
2129 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CWMIN, 0);
2130 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
2132 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
2134 rt2800_register_read(rt2x00dev, TX_RTS_CFG, ®);
2135 rt2x00_set_field32(®, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
2136 rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES,
2137 IEEE80211_MAX_RTS_THRESHOLD);
2138 rt2x00_set_field32(®, TX_RTS_CFG_RTS_FBK_EN, 0);
2139 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
2141 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
2144 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
2145 * time should be set to 16. However, the original Ralink driver uses
2146 * 16 for both and indeed using a value of 10 for CCK SIFS results in
2147 * connection problems with 11g + CTS protection. Hence, use the same
2148 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
2150 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, ®);
2151 rt2x00_set_field32(®, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
2152 rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
2153 rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
2154 rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, 314);
2155 rt2x00_set_field32(®, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
2156 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
2158 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
2161 * ASIC will keep garbage value after boot, clear encryption keys.
2163 for (i = 0; i < 4; i++)
2164 rt2800_register_write(rt2x00dev,
2165 SHARED_KEY_MODE_ENTRY(i), 0);
2167 for (i = 0; i < 256; i++) {
2168 u32 wcid[2] = { 0xffffffff, 0x00ffffff };
2169 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
2170 wcid, sizeof(wcid));
2172 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
2173 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
2179 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE0);
2180 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE1);
2181 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE2);
2182 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE3);
2183 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE4);
2184 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE5);
2185 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE6);
2186 rt2800_clear_beacon(rt2x00dev, HW_BEACON_BASE7);
2188 if (rt2x00_is_usb(rt2x00dev)) {
2189 rt2800_register_read(rt2x00dev, US_CYC_CNT, ®);
2190 rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 30);
2191 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
2194 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, ®);
2195 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS0FBK, 0);
2196 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS1FBK, 0);
2197 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS2FBK, 1);
2198 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS3FBK, 2);
2199 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS4FBK, 3);
2200 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS5FBK, 4);
2201 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS6FBK, 5);
2202 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS7FBK, 6);
2203 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
2205 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, ®);
2206 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS8FBK, 8);
2207 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS9FBK, 8);
2208 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS10FBK, 9);
2209 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS11FBK, 10);
2210 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS12FBK, 11);
2211 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS13FBK, 12);
2212 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS14FBK, 13);
2213 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS15FBK, 14);
2214 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
2216 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, ®);
2217 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS0FBK, 8);
2218 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS1FBK, 8);
2219 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS2FBK, 9);
2220 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS3FBK, 10);
2221 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS4FBK, 11);
2222 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS5FBK, 12);
2223 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS6FBK, 13);
2224 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS7FBK, 14);
2225 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
2227 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, ®);
2228 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS0FBK, 0);
2229 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS1FBK, 0);
2230 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS2FBK, 1);
2231 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS3FBK, 2);
2232 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
2235 * Do not force the BA window size, we use the TXWI to set it
2237 rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, ®);
2238 rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
2239 rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
2240 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
2243 * We must clear the error counters.
2244 * These registers are cleared on read,
2245 * so we may pass a useless variable to store the value.
2247 rt2800_register_read(rt2x00dev, RX_STA_CNT0, ®);
2248 rt2800_register_read(rt2x00dev, RX_STA_CNT1, ®);
2249 rt2800_register_read(rt2x00dev, RX_STA_CNT2, ®);
2250 rt2800_register_read(rt2x00dev, TX_STA_CNT0, ®);
2251 rt2800_register_read(rt2x00dev, TX_STA_CNT1, ®);
2252 rt2800_register_read(rt2x00dev, TX_STA_CNT2, ®);
2255 * Setup leadtime for pre tbtt interrupt to 6ms
2257 rt2800_register_read(rt2x00dev, INT_TIMER_CFG, ®);
2258 rt2x00_set_field32(®, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
2259 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
2264 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
2269 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2270 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, ®);
2271 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
2274 udelay(REGISTER_BUSY_DELAY);
2277 ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
2281 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
2287 * BBP was enabled after firmware was loaded,
2288 * but we need to reactivate it now.
2290 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
2291 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
2294 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2295 rt2800_bbp_read(rt2x00dev, 0, &value);
2296 if ((value != 0xff) && (value != 0x00))
2298 udelay(REGISTER_BUSY_DELAY);
2301 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
2305 static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
2312 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
2313 rt2800_wait_bbp_ready(rt2x00dev)))
2316 if (rt2800_is_305x_soc(rt2x00dev))
2317 rt2800_bbp_write(rt2x00dev, 31, 0x08);
2319 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
2320 rt2800_bbp_write(rt2x00dev, 66, 0x38);
2322 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
2323 rt2800_bbp_write(rt2x00dev, 69, 0x16);
2324 rt2800_bbp_write(rt2x00dev, 73, 0x12);
2326 rt2800_bbp_write(rt2x00dev, 69, 0x12);
2327 rt2800_bbp_write(rt2x00dev, 73, 0x10);
2330 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
2332 if (rt2x00_rt(rt2x00dev, RT3070) ||
2333 rt2x00_rt(rt2x00dev, RT3071) ||
2334 rt2x00_rt(rt2x00dev, RT3090) ||
2335 rt2x00_rt(rt2x00dev, RT3390)) {
2336 rt2800_bbp_write(rt2x00dev, 79, 0x13);
2337 rt2800_bbp_write(rt2x00dev, 80, 0x05);
2338 rt2800_bbp_write(rt2x00dev, 81, 0x33);
2339 } else if (rt2800_is_305x_soc(rt2x00dev)) {
2340 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
2341 rt2800_bbp_write(rt2x00dev, 80, 0x08);
2343 rt2800_bbp_write(rt2x00dev, 81, 0x37);
2346 rt2800_bbp_write(rt2x00dev, 82, 0x62);
2347 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
2349 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
2350 rt2800_bbp_write(rt2x00dev, 84, 0x19);
2352 rt2800_bbp_write(rt2x00dev, 84, 0x99);
2354 rt2800_bbp_write(rt2x00dev, 86, 0x00);
2355 rt2800_bbp_write(rt2x00dev, 91, 0x04);
2356 rt2800_bbp_write(rt2x00dev, 92, 0x00);
2358 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
2359 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
2360 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
2361 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
2362 rt2800_is_305x_soc(rt2x00dev))
2363 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
2365 rt2800_bbp_write(rt2x00dev, 103, 0x00);
2367 if (rt2800_is_305x_soc(rt2x00dev))
2368 rt2800_bbp_write(rt2x00dev, 105, 0x01);
2370 rt2800_bbp_write(rt2x00dev, 105, 0x05);
2371 rt2800_bbp_write(rt2x00dev, 106, 0x35);
2373 if (rt2x00_rt(rt2x00dev, RT3071) ||
2374 rt2x00_rt(rt2x00dev, RT3090) ||
2375 rt2x00_rt(rt2x00dev, RT3390)) {
2376 rt2800_bbp_read(rt2x00dev, 138, &value);
2378 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2379 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
2381 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
2384 rt2800_bbp_write(rt2x00dev, 138, value);
2388 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
2389 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
2391 if (eeprom != 0xffff && eeprom != 0x0000) {
2392 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
2393 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
2394 rt2800_bbp_write(rt2x00dev, reg_id, value);
2401 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
2402 bool bw40, u8 rfcsr24, u8 filter_target)
2411 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2413 rt2800_bbp_read(rt2x00dev, 4, &bbp);
2414 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
2415 rt2800_bbp_write(rt2x00dev, 4, bbp);
2417 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
2418 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
2419 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
2422 * Set power & frequency of passband test tone
2424 rt2800_bbp_write(rt2x00dev, 24, 0);
2426 for (i = 0; i < 100; i++) {
2427 rt2800_bbp_write(rt2x00dev, 25, 0x90);
2430 rt2800_bbp_read(rt2x00dev, 55, &passband);
2436 * Set power & frequency of stopband test tone
2438 rt2800_bbp_write(rt2x00dev, 24, 0x06);
2440 for (i = 0; i < 100; i++) {
2441 rt2800_bbp_write(rt2x00dev, 25, 0x90);
2444 rt2800_bbp_read(rt2x00dev, 55, &stopband);
2446 if ((passband - stopband) <= filter_target) {
2448 overtuned += ((passband - stopband) == filter_target);
2452 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2455 rfcsr24 -= !!overtuned;
2457 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
2461 static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
2468 if (!rt2x00_rt(rt2x00dev, RT3070) &&
2469 !rt2x00_rt(rt2x00dev, RT3071) &&
2470 !rt2x00_rt(rt2x00dev, RT3090) &&
2471 !rt2x00_rt(rt2x00dev, RT3390) &&
2472 !rt2800_is_305x_soc(rt2x00dev))
2476 * Init RF calibration.
2478 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2479 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2480 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2482 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2483 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2485 if (rt2x00_rt(rt2x00dev, RT3070) ||
2486 rt2x00_rt(rt2x00dev, RT3071) ||
2487 rt2x00_rt(rt2x00dev, RT3090)) {
2488 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2489 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
2490 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
2491 rt2800_rfcsr_write(rt2x00dev, 7, 0x70);
2492 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
2493 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
2494 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2495 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
2496 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2497 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
2498 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
2499 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
2500 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
2501 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
2502 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
2503 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
2504 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
2505 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2506 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
2507 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
2508 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
2509 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
2510 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
2511 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
2512 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2513 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
2514 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
2515 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
2516 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
2517 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
2518 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
2519 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2520 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
2521 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
2522 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2523 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
2524 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
2525 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
2526 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
2527 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
2528 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
2529 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
2530 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
2531 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
2532 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
2533 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
2534 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
2535 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
2536 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
2537 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
2538 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
2539 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
2540 } else if (rt2800_is_305x_soc(rt2x00dev)) {
2541 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
2542 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
2543 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
2544 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
2545 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
2546 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
2547 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
2548 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
2549 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
2550 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
2551 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
2552 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
2553 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
2554 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
2555 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
2556 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
2557 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
2558 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
2559 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
2560 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
2561 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
2562 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
2563 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
2564 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
2565 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
2566 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2567 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
2568 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
2569 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
2570 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
2571 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
2572 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
2576 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
2577 rt2800_register_read(rt2x00dev, LDO_CFG0, ®);
2578 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1);
2579 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3);
2580 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
2581 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
2582 rt2x00_rt(rt2x00dev, RT3090)) {
2583 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2584 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
2585 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2587 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
2589 rt2800_register_read(rt2x00dev, LDO_CFG0, ®);
2590 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1);
2591 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2592 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
2593 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2594 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
2595 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3);
2597 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0);
2599 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
2600 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
2601 rt2800_register_read(rt2x00dev, GPIO_SWITCH, ®);
2602 rt2x00_set_field32(®, GPIO_SWITCH_5, 0);
2603 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
2607 * Set RX Filter calibration for 20MHz and 40MHz
2609 if (rt2x00_rt(rt2x00dev, RT3070)) {
2610 rt2x00dev->calibration[0] =
2611 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
2612 rt2x00dev->calibration[1] =
2613 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
2614 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
2615 rt2x00_rt(rt2x00dev, RT3090) ||
2616 rt2x00_rt(rt2x00dev, RT3390)) {
2617 rt2x00dev->calibration[0] =
2618 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
2619 rt2x00dev->calibration[1] =
2620 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
2624 * Set back to initial state
2626 rt2800_bbp_write(rt2x00dev, 24, 0);
2628 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
2629 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
2630 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
2633 * set BBP back to BW20
2635 rt2800_bbp_read(rt2x00dev, 4, &bbp);
2636 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
2637 rt2800_bbp_write(rt2x00dev, 4, bbp);
2639 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
2640 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2641 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2642 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
2643 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
2645 rt2800_register_read(rt2x00dev, OPT_14_CSR, ®);
2646 rt2x00_set_field32(®, OPT_14_CSR_BIT0, 1);
2647 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
2649 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
2650 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
2651 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2652 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2653 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
2654 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
2655 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
2657 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
2658 if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
2659 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
2660 rt2x00_get_field16(eeprom,
2661 EEPROM_TXMIXER_GAIN_BG_VAL));
2662 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2664 if (rt2x00_rt(rt2x00dev, RT3090)) {
2665 rt2800_bbp_read(rt2x00dev, 138, &bbp);
2667 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2668 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
2669 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
2670 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
2671 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
2673 rt2800_bbp_write(rt2x00dev, 138, bbp);
2676 if (rt2x00_rt(rt2x00dev, RT3071) ||
2677 rt2x00_rt(rt2x00dev, RT3090) ||
2678 rt2x00_rt(rt2x00dev, RT3390)) {
2679 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2680 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2681 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2682 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2683 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2684 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2685 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2687 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
2688 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
2689 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
2691 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
2692 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
2693 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
2695 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
2696 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
2697 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
2700 if (rt2x00_rt(rt2x00dev, RT3070) || rt2x00_rt(rt2x00dev, RT3071)) {
2701 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
2702 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
2703 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E))
2704 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
2706 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
2707 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
2708 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
2709 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
2710 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
2716 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
2722 * Initialize all registers.
2724 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
2725 rt2800_init_registers(rt2x00dev) ||
2726 rt2800_init_bbp(rt2x00dev) ||
2727 rt2800_init_rfcsr(rt2x00dev)))
2731 * Send signal to firmware during boot time.
2733 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
2735 if (rt2x00_is_usb(rt2x00dev) &&
2736 (rt2x00_rt(rt2x00dev, RT3070) ||
2737 rt2x00_rt(rt2x00dev, RT3071) ||
2738 rt2x00_rt(rt2x00dev, RT3572))) {
2740 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
2747 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, ®);
2748 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1);
2749 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0);
2750 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2754 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®);
2755 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
2756 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
2757 rt2x00_set_field32(®, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
2758 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2759 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2761 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, ®);
2762 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1);
2763 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 1);
2764 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2767 * Initialize LED control
2769 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
2770 rt2800_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
2771 word & 0xff, (word >> 8) & 0xff);
2773 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
2774 rt2800_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
2775 word & 0xff, (word >> 8) & 0xff);
2777 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
2778 rt2800_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
2779 word & 0xff, (word >> 8) & 0xff);
2783 EXPORT_SYMBOL_GPL(rt2800_enable_radio);
2785 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
2789 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®);
2790 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2791 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2792 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2793 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2794 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2795 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2797 /* Wait for DMA, ignore error */
2798 rt2800_wait_wpdma_ready(rt2x00dev);
2800 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, ®);
2801 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 0);
2802 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0);
2803 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2805 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0);
2806 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0);
2808 EXPORT_SYMBOL_GPL(rt2800_disable_radio);
2810 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
2814 rt2800_register_read(rt2x00dev, EFUSE_CTRL, ®);
2816 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
2818 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
2820 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
2824 mutex_lock(&rt2x00dev->csr_mutex);
2826 rt2800_register_read_lock(rt2x00dev, EFUSE_CTRL, ®);
2827 rt2x00_set_field32(®, EFUSE_CTRL_ADDRESS_IN, i);
2828 rt2x00_set_field32(®, EFUSE_CTRL_MODE, 0);
2829 rt2x00_set_field32(®, EFUSE_CTRL_KICK, 1);
2830 rt2800_register_write_lock(rt2x00dev, EFUSE_CTRL, reg);
2832 /* Wait until the EEPROM has been loaded */
2833 rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, ®);
2835 /* Apparently the data is read from end to start */
2836 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3,
2837 (u32 *)&rt2x00dev->eeprom[i]);
2838 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2,
2839 (u32 *)&rt2x00dev->eeprom[i + 2]);
2840 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1,
2841 (u32 *)&rt2x00dev->eeprom[i + 4]);
2842 rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0,
2843 (u32 *)&rt2x00dev->eeprom[i + 6]);
2845 mutex_unlock(&rt2x00dev->csr_mutex);
2848 void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
2852 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
2853 rt2800_efuse_read(rt2x00dev, i);
2855 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
2857 int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2861 u8 default_lna_gain;
2864 * Start validation of the data that has been read.
2866 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2867 if (!is_valid_ether_addr(mac)) {
2868 random_ether_addr(mac);
2869 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
2872 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2873 if (word == 0xffff) {
2874 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2875 rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
2876 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
2877 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2878 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2879 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
2880 rt2x00_rt(rt2x00dev, RT2872)) {
2882 * There is a max of 2 RX streams for RT28x0 series
2884 if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
2885 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2886 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2889 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2890 if (word == 0xffff) {
2891 rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
2892 rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
2893 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2894 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2895 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2896 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
2897 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
2898 rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
2899 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
2900 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
2901 rt2x00_set_field16(&word, EEPROM_NIC_ANT_DIVERSITY, 0);
2902 rt2x00_set_field16(&word, EEPROM_NIC_DAC_TEST, 0);
2903 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2904 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2907 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2908 if ((word & 0x00ff) == 0x00ff) {
2909 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2910 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2911 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2913 if ((word & 0xff00) == 0xff00) {
2914 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2915 LED_MODE_TXRX_ACTIVITY);
2916 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2917 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2918 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
2919 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
2920 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
2921 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word);
2925 * During the LNA validation we are going to use
2926 * lna0 as correct value. Note that EEPROM_LNA
2927 * is never validated.
2929 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2930 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2932 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2933 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2934 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2935 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2936 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2937 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2939 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2940 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2941 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2942 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2943 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2944 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2946 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2948 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2949 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2950 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2951 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2952 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2953 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2955 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2956 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2957 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2958 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2959 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2960 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2962 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2964 rt2x00_eeprom_read(rt2x00dev, EEPROM_MAX_TX_POWER, &word);
2965 if (rt2x00_get_field16(word, EEPROM_MAX_TX_POWER_24GHZ) == 0xff)
2966 rt2x00_set_field16(&word, EEPROM_MAX_TX_POWER_24GHZ, MAX_G_TXPOWER);
2967 if (rt2x00_get_field16(word, EEPROM_MAX_TX_POWER_5GHZ) == 0xff)
2968 rt2x00_set_field16(&word, EEPROM_MAX_TX_POWER_5GHZ, MAX_A_TXPOWER);
2969 rt2x00_eeprom_write(rt2x00dev, EEPROM_MAX_TX_POWER, word);
2973 EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
2975 int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
2982 * Read EEPROM word for configuration.
2984 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2987 * Identify RF chipset.
2989 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2990 rt2800_register_read(rt2x00dev, MAC_CSR0, ®);
2992 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
2993 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
2995 if (!rt2x00_rt(rt2x00dev, RT2860) &&
2996 !rt2x00_rt(rt2x00dev, RT2872) &&
2997 !rt2x00_rt(rt2x00dev, RT2883) &&
2998 !rt2x00_rt(rt2x00dev, RT3070) &&
2999 !rt2x00_rt(rt2x00dev, RT3071) &&
3000 !rt2x00_rt(rt2x00dev, RT3090) &&
3001 !rt2x00_rt(rt2x00dev, RT3390) &&
3002 !rt2x00_rt(rt2x00dev, RT3572)) {
3003 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
3007 if (!rt2x00_rf(rt2x00dev, RF2820) &&
3008 !rt2x00_rf(rt2x00dev, RF2850) &&
3009 !rt2x00_rf(rt2x00dev, RF2720) &&
3010 !rt2x00_rf(rt2x00dev, RF2750) &&
3011 !rt2x00_rf(rt2x00dev, RF3020) &&
3012 !rt2x00_rf(rt2x00dev, RF2020) &&
3013 !rt2x00_rf(rt2x00dev, RF3021) &&
3014 !rt2x00_rf(rt2x00dev, RF3022) &&
3015 !rt2x00_rf(rt2x00dev, RF3052)) {
3016 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
3021 * Identify default antenna configuration.
3023 rt2x00dev->default_ant.tx =
3024 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH);
3025 rt2x00dev->default_ant.rx =
3026 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH);
3029 * Read frequency offset and RF programming sequence.
3031 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
3032 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
3035 * Read external LNA informations.
3037 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
3039 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
3040 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
3041 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
3042 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
3045 * Detect if this device has an hardware controlled radio.
3047 if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
3048 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
3051 * Store led settings, for correct led behaviour.
3053 #ifdef CONFIG_RT2X00_LIB_LEDS
3054 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
3055 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
3056 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
3058 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
3059 #endif /* CONFIG_RT2X00_LIB_LEDS */
3063 EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
3066 * RF value list for rt28xx
3067 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
3069 static const struct rf_channel rf_vals[] = {
3070 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
3071 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
3072 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
3073 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
3074 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
3075 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
3076 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
3077 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
3078 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
3079 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
3080 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
3081 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
3082 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
3083 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
3085 /* 802.11 UNI / HyperLan 2 */
3086 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
3087 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
3088 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
3089 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
3090 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
3091 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
3092 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
3093 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
3094 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
3095 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
3096 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
3097 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
3099 /* 802.11 HyperLan 2 */
3100 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
3101 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
3102 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
3103 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
3104 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
3105 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
3106 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
3107 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
3108 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
3109 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
3110 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
3111 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
3112 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
3113 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
3114 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
3115 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
3118 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
3119 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
3120 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
3121 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
3122 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
3123 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
3124 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
3125 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
3126 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
3127 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
3128 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
3131 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
3132 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
3133 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
3134 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
3135 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
3136 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
3137 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
3141 * RF value list for rt3xxx
3142 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
3144 static const struct rf_channel rf_vals_3x[] = {
3160 /* 802.11 UNI / HyperLan 2 */
3174 /* 802.11 HyperLan 2 */
3206 int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
3208 struct hw_mode_spec *spec = &rt2x00dev->spec;
3209 struct channel_info *info;
3210 char *default_power1;
3211 char *default_power2;
3213 unsigned short max_power;
3217 * Disable powersaving as default on PCI devices.
3219 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
3220 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
3223 * Initialize all hw fields.
3225 rt2x00dev->hw->flags =
3226 IEEE80211_HW_SIGNAL_DBM |
3227 IEEE80211_HW_SUPPORTS_PS |
3228 IEEE80211_HW_PS_NULLFUNC_STACK |
3229 IEEE80211_HW_AMPDU_AGGREGATION;
3231 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
3232 * unless we are capable of sending the buffered frames out after the
3233 * DTIM transmission using rt2x00lib_beacondone. This will send out
3234 * multicast and broadcast traffic immediately instead of buffering it
3235 * infinitly and thus dropping it after some time.
3237 if (!rt2x00_is_usb(rt2x00dev))
3238 rt2x00dev->hw->flags |=
3239 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
3241 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
3242 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
3243 rt2x00_eeprom_addr(rt2x00dev,
3244 EEPROM_MAC_ADDR_0));
3247 * As rt2800 has a global fallback table we cannot specify
3248 * more then one tx rate per frame but since the hw will
3249 * try several rates (based on the fallback table) we should
3250 * initialize max_report_rates to the maximum number of rates
3251 * we are going to try. Otherwise mac80211 will truncate our
3252 * reported tx rates and the rc algortihm will end up with
3255 rt2x00dev->hw->max_rates = 1;
3256 rt2x00dev->hw->max_report_rates = 7;
3257 rt2x00dev->hw->max_rate_tries = 1;
3259 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
3262 * Initialize hw_mode information.
3264 spec->supported_bands = SUPPORT_BAND_2GHZ;
3265 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
3267 if (rt2x00_rf(rt2x00dev, RF2820) ||
3268 rt2x00_rf(rt2x00dev, RF2720)) {
3269 spec->num_channels = 14;
3270 spec->channels = rf_vals;
3271 } else if (rt2x00_rf(rt2x00dev, RF2850) ||
3272 rt2x00_rf(rt2x00dev, RF2750)) {
3273 spec->supported_bands |= SUPPORT_BAND_5GHZ;
3274 spec->num_channels = ARRAY_SIZE(rf_vals);
3275 spec->channels = rf_vals;
3276 } else if (rt2x00_rf(rt2x00dev, RF3020) ||
3277 rt2x00_rf(rt2x00dev, RF2020) ||
3278 rt2x00_rf(rt2x00dev, RF3021) ||
3279 rt2x00_rf(rt2x00dev, RF3022)) {
3280 spec->num_channels = 14;
3281 spec->channels = rf_vals_3x;
3282 } else if (rt2x00_rf(rt2x00dev, RF3052)) {
3283 spec->supported_bands |= SUPPORT_BAND_5GHZ;
3284 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
3285 spec->channels = rf_vals_3x;
3289 * Initialize HT information.
3291 if (!rt2x00_rf(rt2x00dev, RF2020))
3292 spec->ht.ht_supported = true;
3294 spec->ht.ht_supported = false;
3297 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
3298 IEEE80211_HT_CAP_GRN_FLD |
3299 IEEE80211_HT_CAP_SGI_20 |
3300 IEEE80211_HT_CAP_SGI_40;
3302 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) >= 2)
3303 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
3306 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) <<
3307 IEEE80211_HT_CAP_RX_STBC_SHIFT;
3309 spec->ht.ampdu_factor = 3;
3310 spec->ht.ampdu_density = 4;
3311 spec->ht.mcs.tx_params =
3312 IEEE80211_HT_MCS_TX_DEFINED |
3313 IEEE80211_HT_MCS_TX_RX_DIFF |
3314 ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
3315 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
3317 switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
3319 spec->ht.mcs.rx_mask[2] = 0xff;
3321 spec->ht.mcs.rx_mask[1] = 0xff;
3323 spec->ht.mcs.rx_mask[0] = 0xff;
3324 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
3329 * Create channel information array
3331 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
3335 spec->channels_info = info;
3337 rt2x00_eeprom_read(rt2x00dev, EEPROM_MAX_TX_POWER, &eeprom);
3338 max_power = rt2x00_get_field16(eeprom, EEPROM_MAX_TX_POWER_24GHZ);
3339 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
3340 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
3342 for (i = 0; i < 14; i++) {
3343 info[i].max_power = max_power;
3344 info[i].default_power1 = TXPOWER_G_FROM_DEV(default_power1[i]);
3345 info[i].default_power2 = TXPOWER_G_FROM_DEV(default_power2[i]);
3348 if (spec->num_channels > 14) {
3349 max_power = rt2x00_get_field16(eeprom, EEPROM_MAX_TX_POWER_5GHZ);
3350 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
3351 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
3353 for (i = 14; i < spec->num_channels; i++) {
3354 info[i].max_power = max_power;
3355 info[i].default_power1 = TXPOWER_A_FROM_DEV(default_power1[i]);
3356 info[i].default_power2 = TXPOWER_A_FROM_DEV(default_power2[i]);
3362 EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
3365 * IEEE80211 stack callback functions.
3367 void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
3370 struct rt2x00_dev *rt2x00dev = hw->priv;
3371 struct mac_iveiv_entry iveiv_entry;
3374 offset = MAC_IVEIV_ENTRY(hw_key_idx);
3375 rt2800_register_multiread(rt2x00dev, offset,
3376 &iveiv_entry, sizeof(iveiv_entry));
3378 memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
3379 memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
3381 EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
3383 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
3385 struct rt2x00_dev *rt2x00dev = hw->priv;
3387 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
3389 rt2800_register_read(rt2x00dev, TX_RTS_CFG, ®);
3390 rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, value);
3391 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
3393 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, ®);
3394 rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, enabled);
3395 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
3397 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, ®);
3398 rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, enabled);
3399 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
3401 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, ®);
3402 rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, enabled);
3403 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
3405 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, ®);
3406 rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, enabled);
3407 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
3409 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, ®);
3410 rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, enabled);
3411 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
3413 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, ®);
3414 rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, enabled);
3415 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
3419 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
3421 int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
3422 const struct ieee80211_tx_queue_params *params)
3424 struct rt2x00_dev *rt2x00dev = hw->priv;
3425 struct data_queue *queue;
3426 struct rt2x00_field32 field;
3432 * First pass the configuration through rt2x00lib, that will
3433 * update the queue settings and validate the input. After that
3434 * we are free to update the registers based on the value
3435 * in the queue parameter.
3437 retval = rt2x00mac_conf_tx(hw, queue_idx, params);
3442 * We only need to perform additional register initialization
3448 queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
3450 /* Update WMM TXOP register */
3451 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
3452 field.bit_offset = (queue_idx & 1) * 16;
3453 field.bit_mask = 0xffff << field.bit_offset;
3455 rt2800_register_read(rt2x00dev, offset, ®);
3456 rt2x00_set_field32(®, field, queue->txop);
3457 rt2800_register_write(rt2x00dev, offset, reg);
3459 /* Update WMM registers */
3460 field.bit_offset = queue_idx * 4;
3461 field.bit_mask = 0xf << field.bit_offset;
3463 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, ®);
3464 rt2x00_set_field32(®, field, queue->aifs);
3465 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
3467 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, ®);
3468 rt2x00_set_field32(®, field, queue->cw_min);
3469 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
3471 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, ®);
3472 rt2x00_set_field32(®, field, queue->cw_max);
3473 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
3475 /* Update EDCA registers */
3476 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
3478 rt2800_register_read(rt2x00dev, offset, ®);
3479 rt2x00_set_field32(®, EDCA_AC0_CFG_TX_OP, queue->txop);
3480 rt2x00_set_field32(®, EDCA_AC0_CFG_AIFSN, queue->aifs);
3481 rt2x00_set_field32(®, EDCA_AC0_CFG_CWMIN, queue->cw_min);
3482 rt2x00_set_field32(®, EDCA_AC0_CFG_CWMAX, queue->cw_max);
3483 rt2800_register_write(rt2x00dev, offset, reg);
3487 EXPORT_SYMBOL_GPL(rt2800_conf_tx);
3489 u64 rt2800_get_tsf(struct ieee80211_hw *hw)
3491 struct rt2x00_dev *rt2x00dev = hw->priv;
3495 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, ®);
3496 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
3497 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, ®);
3498 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
3502 EXPORT_SYMBOL_GPL(rt2800_get_tsf);
3504 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3505 enum ieee80211_ampdu_mlme_action action,
3506 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
3511 case IEEE80211_AMPDU_RX_START:
3512 case IEEE80211_AMPDU_RX_STOP:
3514 * The hw itself takes care of setting up BlockAck mechanisms.
3515 * So, we only have to allow mac80211 to nagotiate a BlockAck
3516 * agreement. Once that is done, the hw will BlockAck incoming
3517 * AMPDUs without further setup.
3520 case IEEE80211_AMPDU_TX_START:
3521 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
3523 case IEEE80211_AMPDU_TX_STOP:
3524 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
3526 case IEEE80211_AMPDU_TX_OPERATIONAL:
3529 WARNING((struct rt2x00_dev *)hw->priv, "Unknown AMPDU action\n");
3534 EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
3536 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
3537 MODULE_VERSION(DRV_VERSION);
3538 MODULE_DESCRIPTION("Ralink RT2800 library");
3539 MODULE_LICENSE("GPL");