drivers/net/wireless/rt2x00/rt2800lib.c

   1 /*
   2         Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
   3         Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
   4         Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
   5         Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
   6
   7         Based on the original rt2800pci.c and rt2800usb.c.
   8           Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
   9           Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
  10           Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
  11           Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
  12           Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
  13           Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
  14           <http://rt2x00.serialmonkey.com>
  15
  16         This program is free software; you can redistribute it and/or modify
  17         it under the terms of the GNU General Public License as published by
  18         the Free Software Foundation; either version 2 of the License, or
  19         (at your option) any later version.
  20
  21         This program is distributed in the hope that it will be useful,
  22         but WITHOUT ANY WARRANTY; without even the implied warranty of
  23         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24         GNU General Public License for more details.
  25
  26         You should have received a copy of the GNU General Public License
  27         along with this program; if not, see <http://www.gnu.org/licenses/>.
  28  */
  29
  30 /*
  31         Module: rt2800lib
  32         Abstract: rt2800 generic device routines.
  33  */
  34
  35 #include <linux/crc-ccitt.h>
  36 #include <linux/kernel.h>
  37 #include <linux/module.h>
  38 #include <linux/slab.h>
  39
  40 #include "rt2x00.h"
  41 #include "rt2800lib.h"
  42 #include "rt2800.h"
  43
  44 /*
  45  * Register access.
  46  * All access to the CSR registers will go through the methods
  47  * rt2800_register_read and rt2800_register_write.
  48  * BBP and RF register require indirect register access,
  49  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  50  * These indirect registers work with busy bits,
  51  * and we will try maximal REGISTER_BUSY_COUNT times to access
  52  * the register while taking a REGISTER_BUSY_DELAY us delay
  53  * between each attampt. When the busy bit is still set at that time,
  54  * the access attempt is considered to have failed,
  55  * and we will print an error.
  56  * The _lock versions must be used if you already hold the csr_mutex
  57  */
  58 #define WAIT_FOR_BBP(__dev, __reg) \
  59         rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
  60 #define WAIT_FOR_RFCSR(__dev, __reg) \
  61         rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
  62 #define WAIT_FOR_RF(__dev, __reg) \
  63         rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
  64 #define WAIT_FOR_MCU(__dev, __reg) \
  65         rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  66                             H2M_MAILBOX_CSR_OWNER, (__reg))
  67
  68 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
  69 {
  70         /* check for rt2872 on SoC */
  71         if (!rt2x00_is_soc(rt2x00dev) ||
  72             !rt2x00_rt(rt2x00dev, RT2872))
  73                 return false;
  74
  75         /* we know for sure that these rf chipsets are used on rt305x boards */
  76         if (rt2x00_rf(rt2x00dev, RF3020) ||
  77             rt2x00_rf(rt2x00dev, RF3021) ||
  78             rt2x00_rf(rt2x00dev, RF3022))
  79                 return true;
  80
  81         rt2x00_warn(rt2x00dev, "Unknown RF chipset on rt305x\n");
  82         return false;
  83 }
  84
  85 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
  86                              const unsigned int word, const u8 value)
  87 {
  88         u32 reg;
  89
  90         mutex_lock(&rt2x00dev->csr_mutex);
  91
  92         /*
  93          * Wait until the BBP becomes available, afterwards we
  94          * can safely write the new data into the register.
  95          */
  96         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  97                 reg = 0;
  98                 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
  99                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 100                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 101                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
 102                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 103
 104                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 105         }
 106
 107         mutex_unlock(&rt2x00dev->csr_mutex);
 108 }
 109
 110 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
 111                             const unsigned int word, u8 *value)
 112 {
 113         u32 reg;
 114
 115         mutex_lock(&rt2x00dev->csr_mutex);
 116
 117         /*
 118          * Wait until the BBP becomes available, afterwards we
 119          * can safely write the read request into the register.
 120          * After the data has been written, we wait until hardware
 121          * returns the correct value, if at any time the register
 122          * doesn't become available in time, reg will be 0xffffffff
 123          * which means we return 0xff to the caller.
 124          */
 125         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 126                 reg = 0;
 127                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 128                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 129                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
 130                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 131
 132                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 133
 134                 WAIT_FOR_BBP(rt2x00dev, &reg);
 135         }
 136
 137         *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
 138
 139         mutex_unlock(&rt2x00dev->csr_mutex);
 140 }
 141
 142 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
 143                                const unsigned int word, const u8 value)
 144 {
 145         u32 reg;
 146
 147         mutex_lock(&rt2x00dev->csr_mutex);
 148
 149         /*
 150          * Wait until the RFCSR becomes available, afterwards we
 151          * can safely write the new data into the register.
 152          */
 153         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 154                 reg = 0;
 155                 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
 156                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 157                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
 158                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 159
 160                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 161         }
 162
 163         mutex_unlock(&rt2x00dev->csr_mutex);
 164 }
 165
 166 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
 167                               const unsigned int word, u8 *value)
 168 {
 169         u32 reg;
 170
 171         mutex_lock(&rt2x00dev->csr_mutex);
 172
 173         /*
 174          * Wait until the RFCSR becomes available, afterwards we
 175          * can safely write the read request into the register.
 176          * After the data has been written, we wait until hardware
 177          * returns the correct value, if at any time the register
 178          * doesn't become available in time, reg will be 0xffffffff
 179          * which means we return 0xff to the caller.
 180          */
 181         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 182                 reg = 0;
 183                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 184                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
 185                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 186
 187                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 188
 189                 WAIT_FOR_RFCSR(rt2x00dev, &reg);
 190         }
 191
 192         *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
 193
 194         mutex_unlock(&rt2x00dev->csr_mutex);
 195 }
 196
 197 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
 198                             const unsigned int word, const u32 value)
 199 {
 200         u32 reg;
 201
 202         mutex_lock(&rt2x00dev->csr_mutex);
 203
 204         /*
 205          * Wait until the RF becomes available, afterwards we
 206          * can safely write the new data into the register.
 207          */
 208         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 209                 reg = 0;
 210                 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
 211                 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
 212                 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
 213                 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
 214
 215                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
 216                 rt2x00_rf_write(rt2x00dev, word, value);
 217         }
 218
 219         mutex_unlock(&rt2x00dev->csr_mutex);
 220 }
 221
 222 static const unsigned int rt2800_eeprom_map[EEPROM_WORD_COUNT] = {
 223         [EEPROM_CHIP_ID]                = 0x0000,
 224         [EEPROM_VERSION]                = 0x0001,
 225         [EEPROM_MAC_ADDR_0]             = 0x0002,
 226         [EEPROM_MAC_ADDR_1]             = 0x0003,
 227         [EEPROM_MAC_ADDR_2]             = 0x0004,
 228         [EEPROM_NIC_CONF0]              = 0x001a,
 229         [EEPROM_NIC_CONF1]              = 0x001b,
 230         [EEPROM_FREQ]                   = 0x001d,
 231         [EEPROM_LED_AG_CONF]            = 0x001e,
 232         [EEPROM_LED_ACT_CONF]           = 0x001f,
 233         [EEPROM_LED_POLARITY]           = 0x0020,
 234         [EEPROM_NIC_CONF2]              = 0x0021,
 235         [EEPROM_LNA]                    = 0x0022,
 236         [EEPROM_RSSI_BG]                = 0x0023,
 237         [EEPROM_RSSI_BG2]               = 0x0024,
 238         [EEPROM_TXMIXER_GAIN_BG]        = 0x0024, /* overlaps with RSSI_BG2 */
 239         [EEPROM_RSSI_A]                 = 0x0025,
 240         [EEPROM_RSSI_A2]                = 0x0026,
 241         [EEPROM_TXMIXER_GAIN_A]         = 0x0026, /* overlaps with RSSI_A2 */
 242         [EEPROM_EIRP_MAX_TX_POWER]      = 0x0027,
 243         [EEPROM_TXPOWER_DELTA]          = 0x0028,
 244         [EEPROM_TXPOWER_BG1]            = 0x0029,
 245         [EEPROM_TXPOWER_BG2]            = 0x0030,
 246         [EEPROM_TSSI_BOUND_BG1]         = 0x0037,
 247         [EEPROM_TSSI_BOUND_BG2]         = 0x0038,
 248         [EEPROM_TSSI_BOUND_BG3]         = 0x0039,
 249         [EEPROM_TSSI_BOUND_BG4]         = 0x003a,
 250         [EEPROM_TSSI_BOUND_BG5]         = 0x003b,
 251         [EEPROM_TXPOWER_A1]             = 0x003c,
 252         [EEPROM_TXPOWER_A2]             = 0x0053,
 253         [EEPROM_TSSI_BOUND_A1]          = 0x006a,
 254         [EEPROM_TSSI_BOUND_A2]          = 0x006b,
 255         [EEPROM_TSSI_BOUND_A3]          = 0x006c,
 256         [EEPROM_TSSI_BOUND_A4]          = 0x006d,
 257         [EEPROM_TSSI_BOUND_A5]          = 0x006e,
 258         [EEPROM_TXPOWER_BYRATE]         = 0x006f,
 259         [EEPROM_BBP_START]              = 0x0078,
 260 };
 261
 262 static const unsigned int rt2800_eeprom_map_ext[EEPROM_WORD_COUNT] = {
 263         [EEPROM_CHIP_ID]                = 0x0000,
 264         [EEPROM_VERSION]                = 0x0001,
 265         [EEPROM_MAC_ADDR_0]             = 0x0002,
 266         [EEPROM_MAC_ADDR_1]             = 0x0003,
 267         [EEPROM_MAC_ADDR_2]             = 0x0004,
 268         [EEPROM_NIC_CONF0]              = 0x001a,
 269         [EEPROM_NIC_CONF1]              = 0x001b,
 270         [EEPROM_NIC_CONF2]              = 0x001c,
 271         [EEPROM_EIRP_MAX_TX_POWER]      = 0x0020,
 272         [EEPROM_FREQ]                   = 0x0022,
 273         [EEPROM_LED_AG_CONF]            = 0x0023,
 274         [EEPROM_LED_ACT_CONF]           = 0x0024,
 275         [EEPROM_LED_POLARITY]           = 0x0025,
 276         [EEPROM_LNA]                    = 0x0026,
 277         [EEPROM_EXT_LNA2]               = 0x0027,
 278         [EEPROM_RSSI_BG]                = 0x0028,
 279         [EEPROM_RSSI_BG2]               = 0x0029,
 280         [EEPROM_RSSI_A]                 = 0x002a,
 281         [EEPROM_RSSI_A2]                = 0x002b,
 282         [EEPROM_TXPOWER_BG1]            = 0x0030,
 283         [EEPROM_TXPOWER_BG2]            = 0x0037,
 284         [EEPROM_EXT_TXPOWER_BG3]        = 0x003e,
 285         [EEPROM_TSSI_BOUND_BG1]         = 0x0045,
 286         [EEPROM_TSSI_BOUND_BG2]         = 0x0046,
 287         [EEPROM_TSSI_BOUND_BG3]         = 0x0047,
 288         [EEPROM_TSSI_BOUND_BG4]         = 0x0048,
 289         [EEPROM_TSSI_BOUND_BG5]         = 0x0049,
 290         [EEPROM_TXPOWER_A1]             = 0x004b,
 291         [EEPROM_TXPOWER_A2]             = 0x0065,
 292         [EEPROM_EXT_TXPOWER_A3]         = 0x007f,
 293         [EEPROM_TSSI_BOUND_A1]          = 0x009a,
 294         [EEPROM_TSSI_BOUND_A2]          = 0x009b,
 295         [EEPROM_TSSI_BOUND_A3]          = 0x009c,
 296         [EEPROM_TSSI_BOUND_A4]          = 0x009d,
 297         [EEPROM_TSSI_BOUND_A5]          = 0x009e,
 298         [EEPROM_TXPOWER_BYRATE]         = 0x00a0,
 299 };
 300
 301 static unsigned int rt2800_eeprom_word_index(struct rt2x00_dev *rt2x00dev,
 302                                              const enum rt2800_eeprom_word word)
 303 {
 304         const unsigned int *map;
 305         unsigned int index;
 306
 307         if (WARN_ONCE(word >= EEPROM_WORD_COUNT,
 308                       "%s: invalid EEPROM word %d\n",
 309                       wiphy_name(rt2x00dev->hw->wiphy), word))
 310                 return 0;
 311
 312         if (rt2x00_rt(rt2x00dev, RT3593))
 313                 map = rt2800_eeprom_map_ext;
 314         else
 315                 map = rt2800_eeprom_map;
 316
 317         index = map[word];
 318
 319         /* Index 0 is valid only for EEPROM_CHIP_ID.
 320          * Otherwise it means that the offset of the
 321          * given word is not initialized in the map,
 322          * or that the field is not usable on the
 323          * actual chipset.
 324          */
 325         WARN_ONCE(word != EEPROM_CHIP_ID && index == 0,
 326                   "%s: invalid access of EEPROM word %d\n",
 327                   wiphy_name(rt2x00dev->hw->wiphy), word);
 328
 329         return index;
 330 }
 331
 332 static void *rt2800_eeprom_addr(struct rt2x00_dev *rt2x00dev,
 333                                 const enum rt2800_eeprom_word word)
 334 {
 335         unsigned int index;
 336
 337         index = rt2800_eeprom_word_index(rt2x00dev, word);
 338         return rt2x00_eeprom_addr(rt2x00dev, index);
 339 }
 340
 341 static void rt2800_eeprom_read(struct rt2x00_dev *rt2x00dev,
 342                                const enum rt2800_eeprom_word word, u16 *data)
 343 {
 344         unsigned int index;
 345
 346         index = rt2800_eeprom_word_index(rt2x00dev, word);
 347         rt2x00_eeprom_read(rt2x00dev, index, data);
 348 }
 349
 350 static void rt2800_eeprom_write(struct rt2x00_dev *rt2x00dev,
 351                                 const enum rt2800_eeprom_word word, u16 data)
 352 {
 353         unsigned int index;
 354
 355         index = rt2800_eeprom_word_index(rt2x00dev, word);
 356         rt2x00_eeprom_write(rt2x00dev, index, data);
 357 }
 358
 359 static void rt2800_eeprom_read_from_array(struct rt2x00_dev *rt2x00dev,
 360                                           const enum rt2800_eeprom_word array,
 361                                           unsigned int offset,
 362                                           u16 *data)
 363 {
 364         unsigned int index;
 365
 366         index = rt2800_eeprom_word_index(rt2x00dev, array);
 367         rt2x00_eeprom_read(rt2x00dev, index + offset, data);
 368 }
 369
 370 static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev)
 371 {
 372         u32 reg;
 373         int i, count;
 374
 375         rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
 376         if (rt2x00_get_field32(reg, WLAN_EN))
 377                 return 0;
 378
 379         rt2x00_set_field32(&reg, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff);
 380         rt2x00_set_field32(&reg, FRC_WL_ANT_SET, 1);
 381         rt2x00_set_field32(&reg, WLAN_CLK_EN, 0);
 382         rt2x00_set_field32(&reg, WLAN_EN, 1);
 383         rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
 384
 385         udelay(REGISTER_BUSY_DELAY);
 386
 387         count = 0;
 388         do {
 389                 /*
 390                  * Check PLL_LD & XTAL_RDY.
 391                  */
 392                 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 393                         rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
 394                         if (rt2x00_get_field32(reg, PLL_LD) &&
 395                             rt2x00_get_field32(reg, XTAL_RDY))
 396                                 break;
 397                         udelay(REGISTER_BUSY_DELAY);
 398                 }
 399
 400                 if (i >= REGISTER_BUSY_COUNT) {
 401
 402                         if (count >= 10)
 403                                 return -EIO;
 404
 405                         rt2800_register_write(rt2x00dev, 0x58, 0x018);
 406                         udelay(REGISTER_BUSY_DELAY);
 407                         rt2800_register_write(rt2x00dev, 0x58, 0x418);
 408                         udelay(REGISTER_BUSY_DELAY);
 409                         rt2800_register_write(rt2x00dev, 0x58, 0x618);
 410                         udelay(REGISTER_BUSY_DELAY);
 411                         count++;
 412                 } else {
 413                         count = 0;
 414                 }
 415
 416                 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
 417                 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 0);
 418                 rt2x00_set_field32(&reg, WLAN_CLK_EN, 1);
 419                 rt2x00_set_field32(&reg, WLAN_RESET, 1);
 420                 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
 421                 udelay(10);
 422                 rt2x00_set_field32(&reg, WLAN_RESET, 0);
 423                 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
 424                 udelay(10);
 425                 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff);
 426         } while (count != 0);
 427
 428         return 0;
 429 }
 430
 431 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
 432                         const u8 command, const u8 token,
 433                         const u8 arg0, const u8 arg1)
 434 {
 435         u32 reg;
 436
 437         /*
 438          * SOC devices don't support MCU requests.
 439          */
 440         if (rt2x00_is_soc(rt2x00dev))
 441                 return;
 442
 443         mutex_lock(&rt2x00dev->csr_mutex);
 444
 445         /*
 446          * Wait until the MCU becomes available, afterwards we
 447          * can safely write the new data into the register.
 448          */
 449         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 450                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 451                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 452                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 453                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 454                 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
 455
 456                 reg = 0;
 457                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 458                 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
 459         }
 460
 461         mutex_unlock(&rt2x00dev->csr_mutex);
 462 }
 463 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
 464
 465 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
 466 {
 467         unsigned int i = 0;
 468         u32 reg;
 469
 470         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 471                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
 472                 if (reg && reg != ~0)
 473                         return 0;
 474                 msleep(1);
 475         }
 476
 477         rt2x00_err(rt2x00dev, "Unstable hardware\n");
 478         return -EBUSY;
 479 }
 480 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
 481
 482 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
 483 {
 484         unsigned int i;
 485         u32 reg;
 486
 487         /*
 488          * Some devices are really slow to respond here. Wait a whole second
 489          * before timing out.
 490          */
 491         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 492                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 493                 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
 494                     !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
 495                         return 0;
 496
 497                 msleep(10);
 498         }
 499
 500         rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg);
 501         return -EACCES;
 502 }
 503 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
 504
 505 void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev)
 506 {
 507         u32 reg;
 508
 509         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 510         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
 511         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
 512         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
 513         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
 514         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
 515         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 516 }
 517 EXPORT_SYMBOL_GPL(rt2800_disable_wpdma);
 518
 519 void rt2800_get_txwi_rxwi_size(struct rt2x00_dev *rt2x00dev,
 520                                unsigned short *txwi_size,
 521                                unsigned short *rxwi_size)
 522 {
 523         switch (rt2x00dev->chip.rt) {
 524         case RT3593:
 525                 *txwi_size = TXWI_DESC_SIZE_4WORDS;
 526                 *rxwi_size = RXWI_DESC_SIZE_5WORDS;
 527                 break;
 528
 529         case RT5592:
 530                 *txwi_size = TXWI_DESC_SIZE_5WORDS;
 531                 *rxwi_size = RXWI_DESC_SIZE_6WORDS;
 532                 break;
 533
 534         default:
 535                 *txwi_size = TXWI_DESC_SIZE_4WORDS;
 536                 *rxwi_size = RXWI_DESC_SIZE_4WORDS;
 537                 break;
 538         }
 539 }
 540 EXPORT_SYMBOL_GPL(rt2800_get_txwi_rxwi_size);
 541
 542 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
 543 {
 544         u16 fw_crc;
 545         u16 crc;
 546
 547         /*
 548          * The last 2 bytes in the firmware array are the crc checksum itself,
 549          * this means that we should never pass those 2 bytes to the crc
 550          * algorithm.
 551          */
 552         fw_crc = (data[len - 2] << 8 | data[len - 1]);
 553
 554         /*
 555          * Use the crc ccitt algorithm.
 556          * This will return the same value as the legacy driver which
 557          * used bit ordering reversion on the both the firmware bytes
 558          * before input input as well as on the final output.
 559          * Obviously using crc ccitt directly is much more efficient.
 560          */
 561         crc = crc_ccitt(~0, data, len - 2);
 562
 563         /*
 564          * There is a small difference between the crc-itu-t + bitrev and
 565          * the crc-ccitt crc calculation. In the latter method the 2 bytes
 566          * will be swapped, use swab16 to convert the crc to the correct
 567          * value.
 568          */
 569         crc = swab16(crc);
 570
 571         return fw_crc == crc;
 572 }
 573
 574 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
 575                           const u8 *data, const size_t len)
 576 {
 577         size_t offset = 0;
 578         size_t fw_len;
 579         bool multiple;
 580
 581         /*
 582          * PCI(e) & SOC devices require firmware with a length
 583          * of 8kb. USB devices require firmware files with a length
 584          * of 4kb. Certain USB chipsets however require different firmware,
 585          * which Ralink only provides attached to the original firmware
 586          * file. Thus for USB devices, firmware files have a length
 587          * which is a multiple of 4kb. The firmware for rt3290 chip also
 588          * have a length which is a multiple of 4kb.
 589          */
 590         if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290))
 591                 fw_len = 4096;
 592         else
 593                 fw_len = 8192;
 594
 595         multiple = true;
 596         /*
 597          * Validate the firmware length
 598          */
 599         if (len != fw_len && (!multiple || (len % fw_len) != 0))
 600                 return FW_BAD_LENGTH;
 601
 602         /*
 603          * Check if the chipset requires one of the upper parts
 604          * of the firmware.
 605          */
 606         if (rt2x00_is_usb(rt2x00dev) &&
 607             !rt2x00_rt(rt2x00dev, RT2860) &&
 608             !rt2x00_rt(rt2x00dev, RT2872) &&
 609             !rt2x00_rt(rt2x00dev, RT3070) &&
 610             ((len / fw_len) == 1))
 611                 return FW_BAD_VERSION;
 612
 613         /*
 614          * 8kb firmware files must be checked as if it were
 615          * 2 separate firmware files.
 616          */
 617         while (offset < len) {
 618                 if (!rt2800_check_firmware_crc(data + offset, fw_len))
 619                         return FW_BAD_CRC;
 620
 621                 offset += fw_len;
 622         }
 623
 624         return FW_OK;
 625 }
 626 EXPORT_SYMBOL_GPL(rt2800_check_firmware);
 627
 628 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
 629                          const u8 *data, const size_t len)
 630 {
 631         unsigned int i;
 632         u32 reg;
 633         int retval;
 634
 635         if (rt2x00_rt(rt2x00dev, RT3290)) {
 636                 retval = rt2800_enable_wlan_rt3290(rt2x00dev);
 637                 if (retval)
 638                         return -EBUSY;
 639         }
 640
 641         /*
 642          * If driver doesn't wake up firmware here,
 643          * rt2800_load_firmware will hang forever when interface is up again.
 644          */
 645         rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
 646
 647         /*
 648          * Wait for stable hardware.
 649          */
 650         if (rt2800_wait_csr_ready(rt2x00dev))
 651                 return -EBUSY;
 652
 653         if (rt2x00_is_pci(rt2x00dev)) {
 654                 if (rt2x00_rt(rt2x00dev, RT3290) ||
 655                     rt2x00_rt(rt2x00dev, RT3572) ||
 656                     rt2x00_rt(rt2x00dev, RT5390) ||
 657                     rt2x00_rt(rt2x00dev, RT5392)) {
 658                         rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
 659                         rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
 660                         rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
 661                         rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
 662                 }
 663                 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
 664         }
 665
 666         rt2800_disable_wpdma(rt2x00dev);
 667
 668         /*
 669          * Write firmware to the device.
 670          */
 671         rt2800_drv_write_firmware(rt2x00dev, data, len);
 672
 673         /*
 674          * Wait for device to stabilize.
 675          */
 676         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 677                 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
 678                 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
 679                         break;
 680                 msleep(1);
 681         }
 682
 683         if (i == REGISTER_BUSY_COUNT) {
 684                 rt2x00_err(rt2x00dev, "PBF system register not ready\n");
 685                 return -EBUSY;
 686         }
 687
 688         /*
 689          * Disable DMA, will be reenabled later when enabling
 690          * the radio.
 691          */
 692         rt2800_disable_wpdma(rt2x00dev);
 693
 694         /*
 695          * Initialize firmware.
 696          */
 697         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
 698         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
 699         if (rt2x00_is_usb(rt2x00dev)) {
 700                 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
 701                 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
 702         }
 703         msleep(1);
 704
 705         return 0;
 706 }
 707 EXPORT_SYMBOL_GPL(rt2800_load_firmware);
 708
 709 void rt2800_write_tx_data(struct queue_entry *entry,
 710                           struct txentry_desc *txdesc)
 711 {
 712         __le32 *txwi = rt2800_drv_get_txwi(entry);
 713         u32 word;
 714         int i;
 715
 716         /*
 717          * Initialize TX Info descriptor
 718          */
 719         rt2x00_desc_read(txwi, 0, &word);
 720         rt2x00_set_field32(&word, TXWI_W0_FRAG,
 721                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
 722         rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
 723                            test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
 724         rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
 725         rt2x00_set_field32(&word, TXWI_W0_TS,
 726                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
 727         rt2x00_set_field32(&word, TXWI_W0_AMPDU,
 728                            test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
 729         rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
 730                            txdesc->u.ht.mpdu_density);
 731         rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
 732         rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
 733         rt2x00_set_field32(&word, TXWI_W0_BW,
 734                            test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
 735         rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
 736                            test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
 737         rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
 738         rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
 739         rt2x00_desc_write(txwi, 0, word);
 740
 741         rt2x00_desc_read(txwi, 1, &word);
 742         rt2x00_set_field32(&word, TXWI_W1_ACK,
 743                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
 744         rt2x00_set_field32(&word, TXWI_W1_NSEQ,
 745                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
 746         rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
 747         rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
 748                            test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
 749                            txdesc->key_idx : txdesc->u.ht.wcid);
 750         rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
 751                            txdesc->length);
 752         rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
 753         rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
 754         rt2x00_desc_write(txwi, 1, word);
 755
 756         /*
 757          * Always write 0 to IV/EIV fields (word 2 and 3), hardware will insert
 758          * the IV from the IVEIV register when TXD_W3_WIV is set to 0.
 759          * When TXD_W3_WIV is set to 1 it will use the IV data
 760          * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
 761          * crypto entry in the registers should be used to encrypt the frame.
 762          *
 763          * Nulify all remaining words as well, we don't know how to program them.
 764          */
 765         for (i = 2; i < entry->queue->winfo_size / sizeof(__le32); i++)
 766                 _rt2x00_desc_write(txwi, i, 0);
 767 }
 768 EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
 769
 770 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
 771 {
 772         s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
 773         s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
 774         s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
 775         u16 eeprom;
 776         u8 offset0;
 777         u8 offset1;
 778         u8 offset2;
 779
 780         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
 781                 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
 782                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
 783                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
 784                 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
 785                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
 786         } else {
 787                 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
 788                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
 789                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
 790                 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
 791                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
 792         }
 793
 794         /*
 795          * Convert the value from the descriptor into the RSSI value
 796          * If the value in the descriptor is 0, it is considered invalid
 797          * and the default (extremely low) rssi value is assumed
 798          */
 799         rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
 800         rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
 801         rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
 802
 803         /*
 804          * mac80211 only accepts a single RSSI value. Calculating the
 805          * average doesn't deliver a fair answer either since -60:-60 would
 806          * be considered equally good as -50:-70 while the second is the one
 807          * which gives less energy...
 808          */
 809         rssi0 = max(rssi0, rssi1);
 810         return (int)max(rssi0, rssi2);
 811 }
 812
 813 void rt2800_process_rxwi(struct queue_entry *entry,
 814                          struct rxdone_entry_desc *rxdesc)
 815 {
 816         __le32 *rxwi = (__le32 *) entry->skb->data;
 817         u32 word;
 818
 819         rt2x00_desc_read(rxwi, 0, &word);
 820
 821         rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
 822         rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
 823
 824         rt2x00_desc_read(rxwi, 1, &word);
 825
 826         if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
 827                 rxdesc->flags |= RX_FLAG_SHORT_GI;
 828
 829         if (rt2x00_get_field32(word, RXWI_W1_BW))
 830                 rxdesc->flags |= RX_FLAG_40MHZ;
 831
 832         /*
 833          * Detect RX rate, always use MCS as signal type.
 834          */
 835         rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
 836         rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
 837         rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
 838
 839         /*
 840          * Mask of 0x8 bit to remove the short preamble flag.
 841          */
 842         if (rxdesc->rate_mode == RATE_MODE_CCK)
 843                 rxdesc->signal &= ~0x8;
 844
 845         rt2x00_desc_read(rxwi, 2, &word);
 846
 847         /*
 848          * Convert descriptor AGC value to RSSI value.
 849          */
 850         rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
 851         /*
 852          * Remove RXWI descriptor from start of the buffer.
 853          */
 854         skb_pull(entry->skb, entry->queue->winfo_size);
 855 }
 856 EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
 857
 858 void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi)
 859 {
 860         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 861         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 862         struct txdone_entry_desc txdesc;
 863         u32 word;
 864         u16 mcs, real_mcs;
 865         int aggr, ampdu;
 866
 867         /*
 868          * Obtain the status about this packet.
 869          */
 870         txdesc.flags = 0;
 871         rt2x00_desc_read(txwi, 0, &word);
 872
 873         mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
 874         ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
 875
 876         real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
 877         aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
 878
 879         /*
 880          * If a frame was meant to be sent as a single non-aggregated MPDU
 881          * but ended up in an aggregate the used tx rate doesn't correlate
 882          * with the one specified in the TXWI as the whole aggregate is sent
 883          * with the same rate.
 884          *
 885          * For example: two frames are sent to rt2x00, the first one sets
 886          * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
 887          * and requests MCS15. If the hw aggregates both frames into one
 888          * AMDPU the tx status for both frames will contain MCS7 although
 889          * the frame was sent successfully.
 890          *
 891          * Hence, replace the requested rate with the real tx rate to not
 892          * confuse the rate control algortihm by providing clearly wrong
 893          * data.
 894          */
 895         if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
 896                 skbdesc->tx_rate_idx = real_mcs;
 897                 mcs = real_mcs;
 898         }
 899
 900         if (aggr == 1 || ampdu == 1)
 901                 __set_bit(TXDONE_AMPDU, &txdesc.flags);
 902
 903         /*
 904          * Ralink has a retry mechanism using a global fallback
 905          * table. We setup this fallback table to try the immediate
 906          * lower rate for all rates. In the TX_STA_FIFO, the MCS field
 907          * always contains the MCS used for the last transmission, be
 908          * it successful or not.
 909          */
 910         if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
 911                 /*
 912                  * Transmission succeeded. The number of retries is
 913                  * mcs - real_mcs
 914                  */
 915                 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
 916                 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
 917         } else {
 918                 /*
 919                  * Transmission failed. The number of retries is
 920                  * always 7 in this case (for a total number of 8
 921                  * frames sent).
 922                  */
 923                 __set_bit(TXDONE_FAILURE, &txdesc.flags);
 924                 txdesc.retry = rt2x00dev->long_retry;
 925         }
 926
 927         /*
 928          * the frame was retried at least once
 929          * -> hw used fallback rates
 930          */
 931         if (txdesc.retry)
 932                 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
 933
 934         rt2x00lib_txdone(entry, &txdesc);
 935 }
 936 EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
 937
 938 static unsigned int rt2800_hw_beacon_base(struct rt2x00_dev *rt2x00dev,
 939                                           unsigned int index)
 940 {
 941         return HW_BEACON_BASE(index);
 942 }
 943
 944 static inline u8 rt2800_get_beacon_offset(struct rt2x00_dev *rt2x00dev,
 945                                           unsigned int index)
 946 {
 947         return BEACON_BASE_TO_OFFSET(rt2800_hw_beacon_base(rt2x00dev, index));
 948 }
 949
 950 static void rt2800_update_beacons_setup(struct rt2x00_dev *rt2x00dev)
 951 {
 952         struct data_queue *queue = rt2x00dev->bcn;
 953         struct queue_entry *entry;
 954         int i, bcn_num = 0;
 955         u64 off, reg = 0;
 956         u32 bssid_dw1;
 957
 958         /*
 959          * Setup offsets of all active beacons in BCN_OFFSET{0,1} registers.
 960          */
 961         for (i = 0; i < queue->limit; i++) {
 962                 entry = &queue->entries[i];
 963                 if (!test_bit(ENTRY_BCN_ENABLED, &entry->flags))
 964                         continue;
 965                 off = rt2800_get_beacon_offset(rt2x00dev, entry->entry_idx);
 966                 reg |= off << (8 * bcn_num);
 967                 bcn_num++;
 968         }
 969
 970         WARN_ON_ONCE(bcn_num != rt2x00dev->intf_beaconing);
 971
 972         rt2800_register_write(rt2x00dev, BCN_OFFSET0, (u32) reg);
 973         rt2800_register_write(rt2x00dev, BCN_OFFSET1, (u32) (reg >> 32));
 974
 975         /*
 976          * H/W sends up to MAC_BSSID_DW1_BSS_BCN_NUM + 1 consecutive beacons.
 977          */
 978         rt2800_register_read(rt2x00dev, MAC_BSSID_DW1, &bssid_dw1);
 979         rt2x00_set_field32(&bssid_dw1, MAC_BSSID_DW1_BSS_BCN_NUM,
 980                            bcn_num > 0 ? bcn_num - 1 : 0);
 981         rt2800_register_write(rt2x00dev, MAC_BSSID_DW1, bssid_dw1);
 982 }
 983
 984 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
 985 {
 986         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 987         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 988         unsigned int beacon_base;
 989         unsigned int padding_len;
 990         u32 orig_reg, reg;
 991         const int txwi_desc_size = entry->queue->winfo_size;
 992
 993         /*
 994          * Disable beaconing while we are reloading the beacon data,
 995          * otherwise we might be sending out invalid data.
 996          */
 997         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 998         orig_reg = reg;
 999         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1000         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1001
1002         /*
1003          * Add space for the TXWI in front of the skb.
1004          */
1005         memset(skb_push(entry->skb, txwi_desc_size), 0, txwi_desc_size);
1006
1007         /*
1008          * Register descriptor details in skb frame descriptor.
1009          */
1010         skbdesc->flags |= SKBDESC_DESC_IN_SKB;
1011         skbdesc->desc = entry->skb->data;
1012         skbdesc->desc_len = txwi_desc_size;
1013
1014         /*
1015          * Add the TXWI for the beacon to the skb.
1016          */
1017         rt2800_write_tx_data(entry, txdesc);
1018
1019         /*
1020          * Dump beacon to userspace through debugfs.
1021          */
1022         rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
1023
1024         /*
1025          * Write entire beacon with TXWI and padding to register.
1026          */
1027         padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
1028         if (padding_len && skb_pad(entry->skb, padding_len)) {
1029                 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n");
1030                 /* skb freed by skb_pad() on failure */
1031                 entry->skb = NULL;
1032                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
1033                 return;
1034         }
1035
1036         beacon_base = rt2800_hw_beacon_base(rt2x00dev, entry->entry_idx);
1037
1038         rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
1039                                    entry->skb->len + padding_len);
1040         __set_bit(ENTRY_BCN_ENABLED, &entry->flags);
1041
1042         /*
1043          * Change global beacons settings.
1044          */
1045         rt2800_update_beacons_setup(rt2x00dev);
1046
1047         /*
1048          * Restore beaconing state.
1049          */
1050         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
1051
1052         /*
1053          * Clean up beacon skb.
1054          */
1055         dev_kfree_skb_any(entry->skb);
1056         entry->skb = NULL;
1057 }
1058 EXPORT_SYMBOL_GPL(rt2800_write_beacon);
1059
1060 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
1061                                                 unsigned int index)
1062 {
1063         int i;
1064         const int txwi_desc_size = rt2x00dev->bcn->winfo_size;
1065         unsigned int beacon_base;
1066
1067         beacon_base = rt2800_hw_beacon_base(rt2x00dev, index);
1068
1069         /*
1070          * For the Beacon base registers we only need to clear
1071          * the whole TXWI which (when set to 0) will invalidate
1072          * the entire beacon.
1073          */
1074         for (i = 0; i < txwi_desc_size; i += sizeof(__le32))
1075                 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
1076 }
1077
1078 void rt2800_clear_beacon(struct queue_entry *entry)
1079 {
1080         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1081         u32 orig_reg, reg;
1082
1083         /*
1084          * Disable beaconing while we are reloading the beacon data,
1085          * otherwise we might be sending out invalid data.
1086          */
1087         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &orig_reg);
1088         reg = orig_reg;
1089         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1090         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1091
1092         /*
1093          * Clear beacon.
1094          */
1095         rt2800_clear_beacon_register(rt2x00dev, entry->entry_idx);
1096         __clear_bit(ENTRY_BCN_ENABLED, &entry->flags);
1097
1098         /*
1099          * Change global beacons settings.
1100          */
1101         rt2800_update_beacons_setup(rt2x00dev);
1102         /*
1103          * Restore beaconing state.
1104          */
1105         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
1106 }
1107 EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
1108
1109 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1110 const struct rt2x00debug rt2800_rt2x00debug = {
1111         .owner  = THIS_MODULE,
1112         .csr    = {
1113                 .read           = rt2800_register_read,
1114                 .write          = rt2800_register_write,
1115                 .flags          = RT2X00DEBUGFS_OFFSET,
1116                 .word_base      = CSR_REG_BASE,
1117                 .word_size      = sizeof(u32),
1118                 .word_count     = CSR_REG_SIZE / sizeof(u32),
1119         },
1120         .eeprom = {
1121                 /* NOTE: The local EEPROM access functions can't
1122                  * be used here, use the generic versions instead.
1123                  */
1124                 .read           = rt2x00_eeprom_read,
1125                 .write          = rt2x00_eeprom_write,
1126                 .word_base      = EEPROM_BASE,
1127                 .word_size      = sizeof(u16),
1128                 .word_count     = EEPROM_SIZE / sizeof(u16),
1129         },
1130         .bbp    = {
1131                 .read           = rt2800_bbp_read,
1132                 .write          = rt2800_bbp_write,
1133                 .word_base      = BBP_BASE,
1134                 .word_size      = sizeof(u8),
1135                 .word_count     = BBP_SIZE / sizeof(u8),
1136         },
1137         .rf     = {
1138                 .read           = rt2x00_rf_read,
1139                 .write          = rt2800_rf_write,
1140                 .word_base      = RF_BASE,
1141                 .word_size      = sizeof(u32),
1142                 .word_count     = RF_SIZE / sizeof(u32),
1143         },
1144         .rfcsr  = {
1145                 .read           = rt2800_rfcsr_read,
1146                 .write          = rt2800_rfcsr_write,
1147                 .word_base      = RFCSR_BASE,
1148                 .word_size      = sizeof(u8),
1149                 .word_count     = RFCSR_SIZE / sizeof(u8),
1150         },
1151 };
1152 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
1153 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1154
1155 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
1156 {
1157         u32 reg;
1158
1159         if (rt2x00_rt(rt2x00dev, RT3290)) {
1160                 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
1161                 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0);
1162         } else {
1163                 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1164                 return rt2x00_get_field32(reg, GPIO_CTRL_VAL2);
1165         }
1166 }
1167 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
1168
1169 #ifdef CONFIG_RT2X00_LIB_LEDS
1170 static void rt2800_brightness_set(struct led_classdev *led_cdev,
1171                                   enum led_brightness brightness)
1172 {
1173         struct rt2x00_led *led =
1174             container_of(led_cdev, struct rt2x00_led, led_dev);
1175         unsigned int enabled = brightness != LED_OFF;
1176         unsigned int bg_mode =
1177             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
1178         unsigned int polarity =
1179                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1180                                    EEPROM_FREQ_LED_POLARITY);
1181         unsigned int ledmode =
1182                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1183                                    EEPROM_FREQ_LED_MODE);
1184         u32 reg;
1185
1186         /* Check for SoC (SOC devices don't support MCU requests) */
1187         if (rt2x00_is_soc(led->rt2x00dev)) {
1188                 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
1189
1190                 /* Set LED Polarity */
1191                 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
1192
1193                 /* Set LED Mode */
1194                 if (led->type == LED_TYPE_RADIO) {
1195                         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
1196                                            enabled ? 3 : 0);
1197                 } else if (led->type == LED_TYPE_ASSOC) {
1198                         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
1199                                            enabled ? 3 : 0);
1200                 } else if (led->type == LED_TYPE_QUALITY) {
1201                         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
1202                                            enabled ? 3 : 0);
1203                 }
1204
1205                 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
1206
1207         } else {
1208                 if (led->type == LED_TYPE_RADIO) {
1209                         rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1210                                               enabled ? 0x20 : 0);
1211                 } else if (led->type == LED_TYPE_ASSOC) {
1212                         rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1213                                               enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
1214                 } else if (led->type == LED_TYPE_QUALITY) {
1215                         /*
1216                          * The brightness is divided into 6 levels (0 - 5),
1217                          * The specs tell us the following levels:
1218                          *      0, 1 ,3, 7, 15, 31
1219                          * to determine the level in a simple way we can simply
1220                          * work with bitshifting:
1221                          *      (1 << level) - 1
1222                          */
1223                         rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
1224                                               (1 << brightness / (LED_FULL / 6)) - 1,
1225                                               polarity);
1226                 }
1227         }
1228 }
1229
1230 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
1231                      struct rt2x00_led *led, enum led_type type)
1232 {
1233         led->rt2x00dev = rt2x00dev;
1234         led->type = type;
1235         led->led_dev.brightness_set = rt2800_brightness_set;
1236         led->flags = LED_INITIALIZED;
1237 }
1238 #endif /* CONFIG_RT2X00_LIB_LEDS */
1239
1240 /*
1241  * Configuration handlers.
1242  */
1243 static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
1244                                const u8 *address,
1245                                int wcid)
1246 {
1247         struct mac_wcid_entry wcid_entry;
1248         u32 offset;
1249
1250         offset = MAC_WCID_ENTRY(wcid);
1251
1252         memset(&wcid_entry, 0xff, sizeof(wcid_entry));
1253         if (address)
1254                 memcpy(wcid_entry.mac, address, ETH_ALEN);
1255
1256         rt2800_register_multiwrite(rt2x00dev, offset,
1257                                       &wcid_entry, sizeof(wcid_entry));
1258 }
1259
1260 static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
1261 {
1262         u32 offset;
1263         offset = MAC_WCID_ATTR_ENTRY(wcid);
1264         rt2800_register_write(rt2x00dev, offset, 0);
1265 }
1266
1267 static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
1268                                            int wcid, u32 bssidx)
1269 {
1270         u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
1271         u32 reg;
1272
1273         /*
1274          * The BSS Idx numbers is split in a main value of 3 bits,
1275          * and a extended field for adding one additional bit to the value.
1276          */
1277         rt2800_register_read(rt2x00dev, offset, &reg);
1278         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
1279         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
1280                            (bssidx & 0x8) >> 3);
1281         rt2800_register_write(rt2x00dev, offset, reg);
1282 }
1283
1284 static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
1285                                            struct rt2x00lib_crypto *crypto,
1286                                            struct ieee80211_key_conf *key)
1287 {
1288         struct mac_iveiv_entry iveiv_entry;
1289         u32 offset;
1290         u32 reg;
1291
1292         offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
1293
1294         if (crypto->cmd == SET_KEY) {
1295                 rt2800_register_read(rt2x00dev, offset, &reg);
1296                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
1297                                    !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
1298                 /*
1299                  * Both the cipher as the BSS Idx numbers are split in a main
1300                  * value of 3 bits, and a extended field for adding one additional
1301                  * bit to the value.
1302                  */
1303                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
1304                                    (crypto->cipher & 0x7));
1305                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
1306                                    (crypto->cipher & 0x8) >> 3);
1307                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
1308                 rt2800_register_write(rt2x00dev, offset, reg);
1309         } else {
1310                 /* Delete the cipher without touching the bssidx */
1311                 rt2800_register_read(rt2x00dev, offset, &reg);
1312                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
1313                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 0);
1314                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
1315                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
1316                 rt2800_register_write(rt2x00dev, offset, reg);
1317         }
1318
1319         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1320
1321         memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1322         if ((crypto->cipher == CIPHER_TKIP) ||
1323             (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1324             (crypto->cipher == CIPHER_AES))
1325                 iveiv_entry.iv[3] |= 0x20;
1326         iveiv_entry.iv[3] |= key->keyidx << 6;
1327         rt2800_register_multiwrite(rt2x00dev, offset,
1328                                       &iveiv_entry, sizeof(iveiv_entry));
1329 }
1330
1331 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1332                              struct rt2x00lib_crypto *crypto,
1333                              struct ieee80211_key_conf *key)
1334 {
1335         struct hw_key_entry key_entry;
1336         struct rt2x00_field32 field;
1337         u32 offset;
1338         u32 reg;
1339
1340         if (crypto->cmd == SET_KEY) {
1341                 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1342
1343                 memcpy(key_entry.key, crypto->key,
1344                        sizeof(key_entry.key));
1345                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1346                        sizeof(key_entry.tx_mic));
1347                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1348                        sizeof(key_entry.rx_mic));
1349
1350                 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1351                 rt2800_register_multiwrite(rt2x00dev, offset,
1352                                               &key_entry, sizeof(key_entry));
1353         }
1354
1355         /*
1356          * The cipher types are stored over multiple registers
1357          * starting with SHARED_KEY_MODE_BASE each word will have
1358          * 32 bits and contains the cipher types for 2 bssidx each.
1359          * Using the correct defines correctly will cause overhead,
1360          * so just calculate the correct offset.
1361          */
1362         field.bit_offset = 4 * (key->hw_key_idx % 8);
1363         field.bit_mask = 0x7 << field.bit_offset;
1364
1365         offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1366
1367         rt2800_register_read(rt2x00dev, offset, &reg);
1368         rt2x00_set_field32(&reg, field,
1369                            (crypto->cmd == SET_KEY) * crypto->cipher);
1370         rt2800_register_write(rt2x00dev, offset, reg);
1371
1372         /*
1373          * Update WCID information
1374          */
1375         rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1376         rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1377                                        crypto->bssidx);
1378         rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1379
1380         return 0;
1381 }
1382 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1383
1384 static inline int rt2800_find_wcid(struct rt2x00_dev *rt2x00dev)
1385 {
1386         struct mac_wcid_entry wcid_entry;
1387         int idx;
1388         u32 offset;
1389
1390         /*
1391          * Search for the first free WCID entry and return the corresponding
1392          * index.
1393          *
1394          * Make sure the WCID starts _after_ the last possible shared key
1395          * entry (>32).
1396          *
1397          * Since parts of the pairwise key table might be shared with
1398          * the beacon frame buffers 6 & 7 we should only write into the
1399          * first 222 entries.
1400          */
1401         for (idx = 33; idx <= 222; idx++) {
1402                 offset = MAC_WCID_ENTRY(idx);
1403                 rt2800_register_multiread(rt2x00dev, offset, &wcid_entry,
1404                                           sizeof(wcid_entry));
1405                 if (is_broadcast_ether_addr(wcid_entry.mac))
1406                         return idx;
1407         }
1408
1409         /*
1410          * Use -1 to indicate that we don't have any more space in the WCID
1411          * table.
1412          */
1413         return -1;
1414 }
1415
1416 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1417                                struct rt2x00lib_crypto *crypto,
1418                                struct ieee80211_key_conf *key)
1419 {
1420         struct hw_key_entry key_entry;
1421         u32 offset;
1422
1423         if (crypto->cmd == SET_KEY) {
1424                 /*
1425                  * Allow key configuration only for STAs that are
1426                  * known by the hw.
1427                  */
1428                 if (crypto->wcid < 0)
1429                         return -ENOSPC;
1430                 key->hw_key_idx = crypto->wcid;
1431
1432                 memcpy(key_entry.key, crypto->key,
1433                        sizeof(key_entry.key));
1434                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1435                        sizeof(key_entry.tx_mic));
1436                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1437                        sizeof(key_entry.rx_mic));
1438
1439                 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1440                 rt2800_register_multiwrite(rt2x00dev, offset,
1441                                               &key_entry, sizeof(key_entry));
1442         }
1443
1444         /*
1445          * Update WCID information
1446          */
1447         rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1448
1449         return 0;
1450 }
1451 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1452
1453 int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif,
1454                    struct ieee80211_sta *sta)
1455 {
1456         int wcid;
1457         struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1458
1459         /*
1460          * Find next free WCID.
1461          */
1462         wcid = rt2800_find_wcid(rt2x00dev);
1463
1464         /*
1465          * Store selected wcid even if it is invalid so that we can
1466          * later decide if the STA is uploaded into the hw.
1467          */
1468         sta_priv->wcid = wcid;
1469
1470         /*
1471          * No space left in the device, however, we can still communicate
1472          * with the STA -> No error.
1473          */
1474         if (wcid < 0)
1475                 return 0;
1476
1477         /*
1478          * Clean up WCID attributes and write STA address to the device.
1479          */
1480         rt2800_delete_wcid_attr(rt2x00dev, wcid);
1481         rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1482         rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1483                                        rt2x00lib_get_bssidx(rt2x00dev, vif));
1484         return 0;
1485 }
1486 EXPORT_SYMBOL_GPL(rt2800_sta_add);
1487
1488 int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, int wcid)
1489 {
1490         /*
1491          * Remove WCID entry, no need to clean the attributes as they will
1492          * get renewed when the WCID is reused.
1493          */
1494         rt2800_config_wcid(rt2x00dev, NULL, wcid);
1495
1496         return 0;
1497 }
1498 EXPORT_SYMBOL_GPL(rt2800_sta_remove);
1499
1500 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1501                           const unsigned int filter_flags)
1502 {
1503         u32 reg;
1504
1505         /*
1506          * Start configuration steps.
1507          * Note that the version error will always be dropped
1508          * and broadcast frames will always be accepted since
1509          * there is no filter for it at this time.
1510          */
1511         rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1512         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1513                            !(filter_flags & FIF_FCSFAIL));
1514         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1515                            !(filter_flags & FIF_PLCPFAIL));
1516         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1517                            !(filter_flags & FIF_PROMISC_IN_BSS));
1518         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1519         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1520         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1521                            !(filter_flags & FIF_ALLMULTI));
1522         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1523         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1524         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1525                            !(filter_flags & FIF_CONTROL));
1526         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1527                            !(filter_flags & FIF_CONTROL));
1528         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1529                            !(filter_flags & FIF_CONTROL));
1530         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1531                            !(filter_flags & FIF_CONTROL));
1532         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1533                            !(filter_flags & FIF_CONTROL));
1534         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1535                            !(filter_flags & FIF_PSPOLL));
1536         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 0);
1537         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR,
1538                            !(filter_flags & FIF_CONTROL));
1539         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1540                            !(filter_flags & FIF_CONTROL));
1541         rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1542 }
1543 EXPORT_SYMBOL_GPL(rt2800_config_filter);
1544
1545 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1546                         struct rt2x00intf_conf *conf, const unsigned int flags)
1547 {
1548         u32 reg;
1549         bool update_bssid = false;
1550
1551         if (flags & CONFIG_UPDATE_TYPE) {
1552                 /*
1553                  * Enable synchronisation.
1554                  */
1555                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1556                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
1557                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1558
1559                 if (conf->sync == TSF_SYNC_AP_NONE) {
1560                         /*
1561                          * Tune beacon queue transmit parameters for AP mode
1562                          */
1563                         rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1564                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1565                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1566                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1567                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1568                         rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1569                 } else {
1570                         rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1571                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1572                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1573                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1574                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1575                         rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1576                 }
1577         }
1578
1579         if (flags & CONFIG_UPDATE_MAC) {
1580                 if (flags & CONFIG_UPDATE_TYPE &&
1581                     conf->sync == TSF_SYNC_AP_NONE) {
1582                         /*
1583                          * The BSSID register has to be set to our own mac
1584                          * address in AP mode.
1585                          */
1586                         memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1587                         update_bssid = true;
1588                 }
1589
1590                 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1591                         reg = le32_to_cpu(conf->mac[1]);
1592                         rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1593                         conf->mac[1] = cpu_to_le32(reg);
1594                 }
1595
1596                 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1597                                               conf->mac, sizeof(conf->mac));
1598         }
1599
1600         if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
1601                 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1602                         reg = le32_to_cpu(conf->bssid[1]);
1603                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1604                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
1605                         conf->bssid[1] = cpu_to_le32(reg);
1606                 }
1607
1608                 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1609                                               conf->bssid, sizeof(conf->bssid));
1610         }
1611 }
1612 EXPORT_SYMBOL_GPL(rt2800_config_intf);
1613
1614 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1615                                     struct rt2x00lib_erp *erp)
1616 {
1617         bool any_sta_nongf = !!(erp->ht_opmode &
1618                                 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1619         u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1620         u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1621         u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1622         u32 reg;
1623
1624         /* default protection rate for HT20: OFDM 24M */
1625         mm20_rate = gf20_rate = 0x4004;
1626
1627         /* default protection rate for HT40: duplicate OFDM 24M */
1628         mm40_rate = gf40_rate = 0x4084;
1629
1630         switch (protection) {
1631         case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1632                 /*
1633                  * All STAs in this BSS are HT20/40 but there might be
1634                  * STAs not supporting greenfield mode.
1635                  * => Disable protection for HT transmissions.
1636                  */
1637                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1638
1639                 break;
1640         case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1641                 /*
1642                  * All STAs in this BSS are HT20 or HT20/40 but there
1643                  * might be STAs not supporting greenfield mode.
1644                  * => Protect all HT40 transmissions.
1645                  */
1646                 mm20_mode = gf20_mode = 0;
1647                 mm40_mode = gf40_mode = 2;
1648
1649                 break;
1650         case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1651                 /*
1652                  * Nonmember protection:
1653                  * According to 802.11n we _should_ protect all
1654                  * HT transmissions (but we don't have to).
1655                  *
1656                  * But if cts_protection is enabled we _shall_ protect
1657                  * all HT transmissions using a CCK rate.
1658                  *
1659                  * And if any station is non GF we _shall_ protect
1660                  * GF transmissions.
1661                  *
1662                  * We decide to protect everything
1663                  * -> fall through to mixed mode.
1664                  */
1665         case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1666                 /*
1667                  * Legacy STAs are present
1668                  * => Protect all HT transmissions.
1669                  */
1670                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1671
1672                 /*
1673                  * If erp protection is needed we have to protect HT
1674                  * transmissions with CCK 11M long preamble.
1675                  */
1676                 if (erp->cts_protection) {
1677                         /* don't duplicate RTS/CTS in CCK mode */
1678                         mm20_rate = mm40_rate = 0x0003;
1679                         gf20_rate = gf40_rate = 0x0003;
1680                 }
1681                 break;
1682         }
1683
1684         /* check for STAs not supporting greenfield mode */
1685         if (any_sta_nongf)
1686                 gf20_mode = gf40_mode = 2;
1687
1688         /* Update HT protection config */
1689         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1690         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1691         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1692         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1693
1694         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1695         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1696         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1697         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1698
1699         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1700         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1701         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1702         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1703
1704         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1705         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1706         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1707         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1708 }
1709
1710 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1711                        u32 changed)
1712 {
1713         u32 reg;
1714
1715         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1716                 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1717                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1718                                    !!erp->short_preamble);
1719                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1720                                    !!erp->short_preamble);
1721                 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1722         }
1723
1724         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1725                 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1726                 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1727                                    erp->cts_protection ? 2 : 0);
1728                 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1729         }
1730
1731         if (changed & BSS_CHANGED_BASIC_RATES) {
1732                 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1733                                          erp->basic_rates);
1734                 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1735         }
1736
1737         if (changed & BSS_CHANGED_ERP_SLOT) {
1738                 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1739                 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1740                                    erp->slot_time);
1741                 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1742
1743                 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1744                 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1745                 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1746         }
1747
1748         if (changed & BSS_CHANGED_BEACON_INT) {
1749                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1750                 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1751                                    erp->beacon_int * 16);
1752                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1753         }
1754
1755         if (changed & BSS_CHANGED_HT)
1756                 rt2800_config_ht_opmode(rt2x00dev, erp);
1757 }
1758 EXPORT_SYMBOL_GPL(rt2800_config_erp);
1759
1760 static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
1761 {
1762         u32 reg;
1763         u16 eeprom;
1764         u8 led_ctrl, led_g_mode, led_r_mode;
1765
1766         rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
1767         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1768                 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
1769                 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
1770         } else {
1771                 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
1772                 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
1773         }
1774         rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1775
1776         rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1777         led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
1778         led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
1779         if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
1780             led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
1781                 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1782                 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
1783                 if (led_ctrl == 0 || led_ctrl > 0x40) {
1784                         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
1785                         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
1786                         rt2800_register_write(rt2x00dev, LED_CFG, reg);
1787                 } else {
1788                         rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
1789                                            (led_g_mode << 2) | led_r_mode, 1);
1790                 }
1791         }
1792 }
1793
1794 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1795                                      enum antenna ant)
1796 {
1797         u32 reg;
1798         u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1799         u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1800
1801         if (rt2x00_is_pci(rt2x00dev)) {
1802                 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1803                 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1804                 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1805         } else if (rt2x00_is_usb(rt2x00dev))
1806                 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1807                                    eesk_pin, 0);
1808
1809         rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1810         rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
1811         rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, gpio_bit3);
1812         rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
1813 }
1814
1815 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1816 {
1817         u8 r1;
1818         u8 r3;
1819         u16 eeprom;
1820
1821         rt2800_bbp_read(rt2x00dev, 1, &r1);
1822         rt2800_bbp_read(rt2x00dev, 3, &r3);
1823
1824         if (rt2x00_rt(rt2x00dev, RT3572) &&
1825             rt2x00_has_cap_bt_coexist(rt2x00dev))
1826                 rt2800_config_3572bt_ant(rt2x00dev);
1827
1828         /*
1829          * Configure the TX antenna.
1830          */
1831         switch (ant->tx_chain_num) {
1832         case 1:
1833                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1834                 break;
1835         case 2:
1836                 if (rt2x00_rt(rt2x00dev, RT3572) &&
1837                     rt2x00_has_cap_bt_coexist(rt2x00dev))
1838                         rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
1839                 else
1840                         rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1841                 break;
1842         case 3:
1843                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1844                 break;
1845         }
1846
1847         /*
1848          * Configure the RX antenna.
1849          */
1850         switch (ant->rx_chain_num) {
1851         case 1:
1852                 if (rt2x00_rt(rt2x00dev, RT3070) ||
1853                     rt2x00_rt(rt2x00dev, RT3090) ||
1854                     rt2x00_rt(rt2x00dev, RT3352) ||
1855                     rt2x00_rt(rt2x00dev, RT3390)) {
1856                         rt2800_eeprom_read(rt2x00dev,
1857                                            EEPROM_NIC_CONF1, &eeprom);
1858                         if (rt2x00_get_field16(eeprom,
1859                                                 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1860                                 rt2800_set_ant_diversity(rt2x00dev,
1861                                                 rt2x00dev->default_ant.rx);
1862                 }
1863                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1864                 break;
1865         case 2:
1866                 if (rt2x00_rt(rt2x00dev, RT3572) &&
1867                     rt2x00_has_cap_bt_coexist(rt2x00dev)) {
1868                         rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
1869                         rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
1870                                 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
1871                         rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
1872                 } else {
1873                         rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1874                 }
1875                 break;
1876         case 3:
1877                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1878                 break;
1879         }
1880
1881         rt2800_bbp_write(rt2x00dev, 3, r3);
1882         rt2800_bbp_write(rt2x00dev, 1, r1);
1883
1884         if (rt2x00_rt(rt2x00dev, RT3593)) {
1885                 if (ant->rx_chain_num == 1)
1886                         rt2800_bbp_write(rt2x00dev, 86, 0x00);
1887                 else
1888                         rt2800_bbp_write(rt2x00dev, 86, 0x46);
1889         }
1890 }
1891 EXPORT_SYMBOL_GPL(rt2800_config_ant);
1892
1893 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1894                                    struct rt2x00lib_conf *libconf)
1895 {
1896         u16 eeprom;
1897         short lna_gain;
1898
1899         if (libconf->rf.channel <= 14) {
1900                 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1901                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1902         } else if (libconf->rf.channel <= 64) {
1903                 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1904                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1905         } else if (libconf->rf.channel <= 128) {
1906                 if (rt2x00_rt(rt2x00dev, RT3593)) {
1907                         rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &eeprom);
1908                         lna_gain = rt2x00_get_field16(eeprom,
1909                                                       EEPROM_EXT_LNA2_A1);
1910                 } else {
1911                         rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1912                         lna_gain = rt2x00_get_field16(eeprom,
1913                                                       EEPROM_RSSI_BG2_LNA_A1);
1914                 }
1915         } else {
1916                 if (rt2x00_rt(rt2x00dev, RT3593)) {
1917                         rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &eeprom);
1918                         lna_gain = rt2x00_get_field16(eeprom,
1919                                                       EEPROM_EXT_LNA2_A2);
1920                 } else {
1921                         rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1922                         lna_gain = rt2x00_get_field16(eeprom,
1923                                                       EEPROM_RSSI_A2_LNA_A2);
1924                 }
1925         }
1926
1927         rt2x00dev->lna_gain = lna_gain;
1928 }
1929
1930 #define FREQ_OFFSET_BOUND       0x5f
1931
1932 static void rt2800_adjust_freq_offset(struct rt2x00_dev *rt2x00dev)
1933 {
1934         u8 freq_offset, prev_freq_offset;
1935         u8 rfcsr, prev_rfcsr;
1936
1937         freq_offset = rt2x00_get_field8(rt2x00dev->freq_offset, RFCSR17_CODE);
1938         freq_offset = min_t(u8, freq_offset, FREQ_OFFSET_BOUND);
1939
1940         rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1941         prev_rfcsr = rfcsr;
1942
1943         rt2x00_set_field8(&rfcsr, RFCSR17_CODE, freq_offset);
1944         if (rfcsr == prev_rfcsr)
1945                 return;
1946
1947         if (rt2x00_is_usb(rt2x00dev)) {
1948                 rt2800_mcu_request(rt2x00dev, MCU_FREQ_OFFSET, 0xff,
1949                                    freq_offset, prev_rfcsr);
1950                 return;
1951         }
1952
1953         prev_freq_offset = rt2x00_get_field8(prev_rfcsr, RFCSR17_CODE);
1954         while (prev_freq_offset != freq_offset) {
1955                 if (prev_freq_offset < freq_offset)
1956                         prev_freq_offset++;
1957                 else
1958                         prev_freq_offset--;
1959
1960                 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, prev_freq_offset);
1961                 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
1962
1963                 usleep_range(1000, 1500);
1964         }
1965 }
1966
1967 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1968                                          struct ieee80211_conf *conf,
1969                                          struct rf_channel *rf,
1970                                          struct channel_info *info)
1971 {
1972         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1973
1974         if (rt2x00dev->default_ant.tx_chain_num == 1)
1975                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1976
1977         if (rt2x00dev->default_ant.rx_chain_num == 1) {
1978                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1979                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1980         } else if (rt2x00dev->default_ant.rx_chain_num == 2)
1981                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1982
1983         if (rf->channel > 14) {
1984                 /*
1985                  * When TX power is below 0, we should increase it by 7 to
1986                  * make it a positive value (Minimum value is -7).
1987                  * However this means that values between 0 and 7 have
1988                  * double meaning, and we should set a 7DBm boost flag.
1989                  */
1990                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
1991                                    (info->default_power1 >= 0));
1992
1993                 if (info->default_power1 < 0)
1994                         info->default_power1 += 7;
1995
1996                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
1997
1998                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
1999                                    (info->default_power2 >= 0));
2000
2001                 if (info->default_power2 < 0)
2002                         info->default_power2 += 7;
2003
2004                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
2005         } else {
2006                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
2007                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
2008         }
2009
2010         rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
2011
2012         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2013         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2014         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
2015         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2016
2017         udelay(200);
2018
2019         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2020         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2021         rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
2022         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2023
2024         udelay(200);
2025
2026         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2027         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2028         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
2029         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2030 }
2031
2032 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
2033                                          struct ieee80211_conf *conf,
2034                                          struct rf_channel *rf,
2035                                          struct channel_info *info)
2036 {
2037         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2038         u8 rfcsr, calib_tx, calib_rx;
2039
2040         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
2041
2042         rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2043         rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
2044         rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2045
2046         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2047         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
2048         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2049
2050         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
2051         rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
2052         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2053
2054         rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
2055         rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
2056         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
2057
2058         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2059         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2060         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
2061                           rt2x00dev->default_ant.rx_chain_num <= 1);
2062         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD,
2063                           rt2x00dev->default_ant.rx_chain_num <= 2);
2064         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2065         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
2066                           rt2x00dev->default_ant.tx_chain_num <= 1);
2067         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD,
2068                           rt2x00dev->default_ant.tx_chain_num <= 2);
2069         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2070
2071         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
2072         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2073         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2074
2075         if (rt2x00_rt(rt2x00dev, RT3390)) {
2076                 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f;
2077                 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f;
2078         } else {
2079                 if (conf_is_ht40(conf)) {
2080                         calib_tx = drv_data->calibration_bw40;
2081                         calib_rx = drv_data->calibration_bw40;
2082                 } else {
2083                         calib_tx = drv_data->calibration_bw20;
2084                         calib_rx = drv_data->calibration_bw20;
2085                 }
2086         }
2087
2088         rt2800_rfcsr_read(rt2x00dev, 24, &rfcsr);
2089         rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx);
2090         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
2091
2092         rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
2093         rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx);
2094         rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2095
2096         rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2097         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2098         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2099
2100         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2101         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2102         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2103         msleep(1);
2104         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2105         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2106 }
2107
2108 static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
2109                                          struct ieee80211_conf *conf,
2110                                          struct rf_channel *rf,
2111                                          struct channel_info *info)
2112 {
2113         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2114         u8 rfcsr;
2115         u32 reg;
2116
2117         if (rf->channel <= 14) {
2118                 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2119                 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
2120         } else {
2121                 rt2800_bbp_write(rt2x00dev, 25, 0x09);
2122                 rt2800_bbp_write(rt2x00dev, 26, 0xff);
2123         }
2124
2125         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
2126         rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
2127
2128         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2129         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
2130         if (rf->channel <= 14)
2131                 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
2132         else
2133                 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
2134         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2135
2136         rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr);
2137         if (rf->channel <= 14)
2138                 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
2139         else
2140                 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
2141         rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
2142
2143         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
2144         if (rf->channel <= 14) {
2145                 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
2146                 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
2147                                   info->default_power1);
2148         } else {
2149                 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
2150                 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
2151                                 (info->default_power1 & 0x3) |
2152                                 ((info->default_power1 & 0xC) << 1));
2153         }
2154         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2155
2156         rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
2157         if (rf->channel <= 14) {
2158                 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
2159                 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
2160                                   info->default_power2);
2161         } else {
2162                 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
2163                 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
2164                                 (info->default_power2 & 0x3) |
2165                                 ((info->default_power2 & 0xC) << 1));
2166         }
2167         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
2168
2169         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2170         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2171         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2172         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2173         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2174         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2175         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2176         if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
2177                 if (rf->channel <= 14) {
2178                         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2179                         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2180                 }
2181                 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2182                 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2183         } else {
2184                 switch (rt2x00dev->default_ant.tx_chain_num) {
2185                 case 1:
2186                         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2187                 case 2:
2188                         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2189                         break;
2190                 }
2191
2192                 switch (rt2x00dev->default_ant.rx_chain_num) {
2193                 case 1:
2194                         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2195                 case 2:
2196                         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2197                         break;
2198                 }
2199         }
2200         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2201
2202         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
2203         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2204         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2205
2206         if (conf_is_ht40(conf)) {
2207                 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
2208                 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
2209         } else {
2210                 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
2211                 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
2212         }
2213
2214         if (rf->channel <= 14) {
2215                 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
2216                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
2217                 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2218                 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
2219                 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
2220                 rfcsr = 0x4c;
2221                 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2222                                   drv_data->txmixer_gain_24g);
2223                 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
2224                 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2225                 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
2226                 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
2227                 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
2228                 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
2229                 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
2230                 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
2231         } else {
2232                 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2233                 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1);
2234                 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0);
2235                 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1);
2236                 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0);
2237                 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2238                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
2239                 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2240                 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
2241                 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
2242                 rfcsr = 0x7a;
2243                 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2244                                   drv_data->txmixer_gain_5g);
2245                 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
2246                 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2247                 if (rf->channel <= 64) {
2248                         rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
2249                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
2250                         rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
2251                 } else if (rf->channel <= 128) {
2252                         rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
2253                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
2254                         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2255                 } else {
2256                         rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
2257                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
2258                         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2259                 }
2260                 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
2261                 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
2262                 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
2263         }
2264
2265         rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
2266         rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
2267         if (rf->channel <= 14)
2268                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
2269         else
2270                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 0);
2271         rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
2272
2273         rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2274         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2275         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2276 }
2277
2278 static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev,
2279                                          struct ieee80211_conf *conf,
2280                                          struct rf_channel *rf,
2281                                          struct channel_info *info)
2282 {
2283         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2284         u8 txrx_agc_fc;
2285         u8 txrx_h20m;
2286         u8 rfcsr;
2287         u8 bbp;
2288         const bool txbf_enabled = false; /* TODO */
2289
2290         /* TODO: use TX{0,1,2}FinePowerControl values from EEPROM */
2291         rt2800_bbp_read(rt2x00dev, 109, &bbp);
2292         rt2x00_set_field8(&bbp, BBP109_TX0_POWER, 0);
2293         rt2x00_set_field8(&bbp, BBP109_TX1_POWER, 0);
2294         rt2800_bbp_write(rt2x00dev, 109, bbp);
2295
2296         rt2800_bbp_read(rt2x00dev, 110, &bbp);
2297         rt2x00_set_field8(&bbp, BBP110_TX2_POWER, 0);
2298         rt2800_bbp_write(rt2x00dev, 110, bbp);
2299
2300         if (rf->channel <= 14) {
2301                 /* Restore BBP 25 & 26 for 2.4 GHz */
2302                 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2303                 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
2304         } else {
2305                 /* Hard code BBP 25 & 26 for 5GHz */
2306
2307                 /* Enable IQ Phase correction */
2308                 rt2800_bbp_write(rt2x00dev, 25, 0x09);
2309                 /* Setup IQ Phase correction value */
2310                 rt2800_bbp_write(rt2x00dev, 26, 0xff);
2311         }
2312
2313         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2314         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3 & 0xf);
2315
2316         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2317         rt2x00_set_field8(&rfcsr, RFCSR11_R, (rf->rf2 & 0x3));
2318         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2319
2320         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2321         rt2x00_set_field8(&rfcsr, RFCSR11_PLL_IDOH, 1);
2322         if (rf->channel <= 14)
2323                 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 1);
2324         else
2325                 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 2);
2326         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2327
2328         rt2800_rfcsr_read(rt2x00dev, 53, &rfcsr);
2329         if (rf->channel <= 14) {
2330                 rfcsr = 0;
2331                 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
2332                                   info->default_power1 & 0x1f);
2333         } else {
2334                 if (rt2x00_is_usb(rt2x00dev))
2335                         rfcsr = 0x40;
2336
2337                 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
2338                                   ((info->default_power1 & 0x18) << 1) |
2339                                   (info->default_power1 & 7));
2340         }
2341         rt2800_rfcsr_write(rt2x00dev, 53, rfcsr);
2342
2343         rt2800_rfcsr_read(rt2x00dev, 55, &rfcsr);
2344         if (rf->channel <= 14) {
2345                 rfcsr = 0;
2346                 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
2347                                   info->default_power2 & 0x1f);
2348         } else {
2349                 if (rt2x00_is_usb(rt2x00dev))
2350                         rfcsr = 0x40;
2351
2352                 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
2353                                   ((info->default_power2 & 0x18) << 1) |
2354                                   (info->default_power2 & 7));
2355         }
2356         rt2800_rfcsr_write(rt2x00dev, 55, rfcsr);
2357
2358         rt2800_rfcsr_read(rt2x00dev, 54, &rfcsr);
2359         if (rf->channel <= 14) {
2360                 rfcsr = 0;
2361                 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
2362                                   info->default_power3 & 0x1f);
2363         } else {
2364                 if (rt2x00_is_usb(rt2x00dev))
2365                         rfcsr = 0x40;
2366
2367                 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
2368                                   ((info->default_power3 & 0x18) << 1) |
2369                                   (info->default_power3 & 7));
2370         }
2371         rt2800_rfcsr_write(rt2x00dev, 54, rfcsr);
2372
2373         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2374         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2375         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2376         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2377         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2378         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2379         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2380         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2381         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2382
2383         switch (rt2x00dev->default_ant.tx_chain_num) {
2384         case 3:
2385                 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2386                 /* fallthrough */
2387         case 2:
2388                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2389                 /* fallthrough */
2390         case 1:
2391                 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2392                 break;
2393         }
2394
2395         switch (rt2x00dev->default_ant.rx_chain_num) {
2396         case 3:
2397                 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2398                 /* fallthrough */
2399         case 2:
2400                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2401                 /* fallthrough */
2402         case 1:
2403                 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2404                 break;
2405         }
2406         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2407
2408         rt2800_adjust_freq_offset(rt2x00dev);
2409
2410         if (conf_is_ht40(conf)) {
2411                 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw40,
2412                                                 RFCSR24_TX_AGC_FC);
2413                 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw40,
2414                                               RFCSR24_TX_H20M);
2415         } else {
2416                 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw20,
2417                                                 RFCSR24_TX_AGC_FC);
2418                 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw20,
2419                                               RFCSR24_TX_H20M);
2420         }
2421
2422         /* NOTE: the reference driver does not writes the new value
2423          * back to RFCSR 32
2424          */
2425         rt2800_rfcsr_read(rt2x00dev, 32, &rfcsr);
2426         rt2x00_set_field8(&rfcsr, RFCSR32_TX_AGC_FC, txrx_agc_fc);
2427
2428         if (rf->channel <= 14)
2429                 rfcsr = 0xa0;
2430         else
2431                 rfcsr = 0x80;
2432         rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2433
2434         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2435         rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, txrx_h20m);
2436         rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, txrx_h20m);
2437         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2438
2439         /* Band selection */
2440         rt2800_rfcsr_read(rt2x00dev, 36, &rfcsr);
2441         if (rf->channel <= 14)
2442                 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1);
2443         else
2444                 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0);
2445         rt2800_rfcsr_write(rt2x00dev, 36, rfcsr);
2446
2447         rt2800_rfcsr_read(rt2x00dev, 34, &rfcsr);
2448         if (rf->channel <= 14)
2449                 rfcsr = 0x3c;
2450         else
2451                 rfcsr = 0x20;
2452         rt2800_rfcsr_write(rt2x00dev, 34, rfcsr);
2453
2454         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
2455         if (rf->channel <= 14)
2456                 rfcsr = 0x1a;
2457         else
2458                 rfcsr = 0x12;
2459         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2460
2461         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2462         if (rf->channel >= 1 && rf->channel <= 14)
2463                 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
2464         else if (rf->channel >= 36 && rf->channel <= 64)
2465                 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
2466         else if (rf->channel >= 100 && rf->channel <= 128)
2467                 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
2468         else
2469                 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
2470         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2471
2472         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2473         rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
2474         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2475
2476         rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
2477
2478         if (rf->channel <= 14) {
2479                 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
2480                 rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
2481         } else {
2482                 rt2800_rfcsr_write(rt2x00dev, 10, 0xd8);
2483                 rt2800_rfcsr_write(rt2x00dev, 13, 0x23);
2484         }
2485
2486         rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr);
2487         rt2x00_set_field8(&rfcsr, RFCSR51_BITS01, 1);
2488         rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
2489
2490         rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr);
2491         if (rf->channel <= 14) {
2492                 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 5);
2493                 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 3);
2494         } else {
2495                 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 4);
2496                 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 2);
2497         }
2498         rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
2499
2500         rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2501         if (rf->channel <= 14)
2502                 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 3);
2503         else
2504                 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 2);
2505
2506         if (txbf_enabled)
2507                 rt2x00_set_field8(&rfcsr, RFCSR49_TX_DIV, 1);
2508
2509         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2510
2511         rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2512         rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO1_EN, 0);
2513         rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2514
2515         rt2800_rfcsr_read(rt2x00dev, 57, &rfcsr);
2516         if (rf->channel <= 14)
2517                 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x1b);
2518         else
2519                 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x0f);
2520         rt2800_rfcsr_write(rt2x00dev, 57, rfcsr);
2521
2522         if (rf->channel <= 14) {
2523                 rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
2524                 rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
2525         } else {
2526                 rt2800_rfcsr_write(rt2x00dev, 44, 0x9b);
2527                 rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
2528         }
2529
2530         /* Initiate VCO calibration */
2531         rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2532         if (rf->channel <= 14) {
2533                 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2534         } else {
2535                 rt2x00_set_field8(&rfcsr, RFCSR3_BIT1, 1);
2536                 rt2x00_set_field8(&rfcsr, RFCSR3_BIT2, 1);
2537                 rt2x00_set_field8(&rfcsr, RFCSR3_BIT3, 1);
2538                 rt2x00_set_field8(&rfcsr, RFCSR3_BIT4, 1);
2539                 rt2x00_set_field8(&rfcsr, RFCSR3_BIT5, 1);
2540                 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2541         }
2542         rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2543
2544         if (rf->channel >= 1 && rf->channel <= 14) {
2545                 rfcsr = 0x23;
2546                 if (txbf_enabled)
2547                         rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2548                 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2549
2550                 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
2551         } else if (rf->channel >= 36 && rf->channel <= 64) {
2552                 rfcsr = 0x36;
2553                 if (txbf_enabled)
2554                         rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2555                 rt2800_rfcsr_write(rt2x00dev, 39, 0x36);
2556
2557                 rt2800_rfcsr_write(rt2x00dev, 45, 0xeb);
2558         } else if (rf->channel >= 100 && rf->channel <= 128) {
2559                 rfcsr = 0x32;
2560                 if (txbf_enabled)
2561                         rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2562                 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2563
2564                 rt2800_rfcsr_write(rt2x00dev, 45, 0xb3);
2565         } else {
2566                 rfcsr = 0x30;
2567                 if (txbf_enabled)
2568                         rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2569                 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2570
2571                 rt2800_rfcsr_write(rt2x00dev, 45, 0x9b);
2572         }
2573 }
2574
2575 #define POWER_BOUND             0x27
2576 #define POWER_BOUND_5G          0x2b
2577
2578 static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
2579                                          struct ieee80211_conf *conf,
2580                                          struct rf_channel *rf,
2581                                          struct channel_info *info)
2582 {
2583         u8 rfcsr;
2584
2585         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2586         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2587         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2588         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2589         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2590
2591         rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2592         if (info->default_power1 > POWER_BOUND)
2593                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
2594         else
2595                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2596         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2597
2598         rt2800_adjust_freq_offset(rt2x00dev);
2599
2600         if (rf->channel <= 14) {
2601                 if (rf->channel == 6)
2602                         rt2800_bbp_write(rt2x00dev, 68, 0x0c);
2603                 else
2604                         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
2605
2606                 if (rf->channel >= 1 && rf->channel <= 6)
2607                         rt2800_bbp_write(rt2x00dev, 59, 0x0f);
2608                 else if (rf->channel >= 7 && rf->channel <= 11)
2609                         rt2800_bbp_write(rt2x00dev, 59, 0x0e);
2610                 else if (rf->channel >= 12 && rf->channel <= 14)
2611                         rt2800_bbp_write(rt2x00dev, 59, 0x0d);
2612         }
2613 }
2614
2615 static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev,
2616                                          struct ieee80211_conf *conf,
2617                                          struct rf_channel *rf,
2618                                          struct channel_info *info)
2619 {
2620         u8 rfcsr;
2621
2622         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2623         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2624
2625         rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
2626         rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
2627         rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
2628
2629         if (info->default_power1 > POWER_BOUND)
2630                 rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND);
2631         else
2632                 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1);
2633
2634         if (info->default_power2 > POWER_BOUND)
2635                 rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND);
2636         else
2637                 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2);
2638
2639         rt2800_adjust_freq_offset(rt2x00dev);
2640
2641         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2642         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2643         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2644
2645         if ( rt2x00dev->default_ant.tx_chain_num == 2 )
2646                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2647         else
2648                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2649
2650         if ( rt2x00dev->default_ant.rx_chain_num == 2 )
2651                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2652         else
2653                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2654
2655         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2656         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2657
2658         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2659
2660         rt2800_rfcsr_write(rt2x00dev, 31, 80);
2661 }
2662
2663 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
2664                                          struct ieee80211_conf *conf,
2665                                          struct rf_channel *rf,
2666                                          struct channel_info *info)
2667 {
2668         u8 rfcsr;
2669
2670         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2671         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2672         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2673         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2674         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2675
2676         rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2677         if (info->default_power1 > POWER_BOUND)
2678                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
2679         else
2680                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2681         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2682
2683         if (rt2x00_rt(rt2x00dev, RT5392)) {
2684                 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2685                 if (info->default_power2 > POWER_BOUND)
2686                         rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND);
2687                 else
2688                         rt2x00_set_field8(&rfcsr, RFCSR50_TX,
2689                                           info->default_power2);
2690                 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2691         }
2692
2693         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2694         if (rt2x00_rt(rt2x00dev, RT5392)) {
2695                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2696                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2697         }
2698         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2699         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2700         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2701         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2702         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2703
2704         rt2800_adjust_freq_offset(rt2x00dev);
2705
2706         if (rf->channel <= 14) {
2707                 int idx = rf->channel-1;
2708
2709                 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
2710                         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2711                                 /* r55/r59 value array of channel 1~14 */
2712                                 static const char r55_bt_rev[] = {0x83, 0x83,
2713                                         0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
2714                                         0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
2715                                 static const char r59_bt_rev[] = {0x0e, 0x0e,
2716                                         0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
2717                                         0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
2718
2719                                 rt2800_rfcsr_write(rt2x00dev, 55,
2720                                                    r55_bt_rev[idx]);
2721                                 rt2800_rfcsr_write(rt2x00dev, 59,
2722                                                    r59_bt_rev[idx]);
2723                         } else {
2724                                 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
2725                                         0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
2726                                         0x88, 0x88, 0x86, 0x85, 0x84};
2727
2728                                 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
2729                         }
2730                 } else {
2731                         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2732                                 static const char r55_nonbt_rev[] = {0x23, 0x23,
2733                                         0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
2734                                         0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
2735                                 static const char r59_nonbt_rev[] = {0x07, 0x07,
2736                                         0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
2737                                         0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
2738
2739                                 rt2800_rfcsr_write(rt2x00dev, 55,
2740                                                    r55_nonbt_rev[idx]);
2741                                 rt2800_rfcsr_write(rt2x00dev, 59,
2742                                                    r59_nonbt_rev[idx]);
2743                         } else if (rt2x00_rt(rt2x00dev, RT5390) ||
2744                                    rt2x00_rt(rt2x00dev, RT5392)) {
2745                                 static const char r59_non_bt[] = {0x8f, 0x8f,
2746                                         0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
2747                                         0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
2748
2749                                 rt2800_rfcsr_write(rt2x00dev, 59,
2750                                                    r59_non_bt[idx]);
2751                         }
2752                 }
2753         }
2754 }
2755
2756 static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev,
2757                                          struct ieee80211_conf *conf,
2758                                          struct rf_channel *rf,
2759                                          struct channel_info *info)
2760 {
2761         u8 rfcsr, ep_reg;
2762         u32 reg;
2763         int power_bound;
2764
2765         /* TODO */
2766         const bool is_11b = false;
2767         const bool is_type_ep = false;
2768
2769         rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
2770         rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL,
2771                            (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0);
2772         rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
2773
2774         /* Order of values on rf_channel entry: N, K, mod, R */
2775         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff);
2776
2777         rt2800_rfcsr_read(rt2x00dev,  9, &rfcsr);
2778         rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf);
2779         rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8);
2780         rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2);
2781         rt2800_rfcsr_write(rt2x00dev, 9, rfcsr);
2782
2783         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2784         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1);
2785         rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3);
2786         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2787
2788         if (rf->channel <= 14) {
2789                 rt2800_rfcsr_write(rt2x00dev, 10, 0x90);
2790                 /* FIXME: RF11 owerwrite ? */
2791                 rt2800_rfcsr_write(rt2x00dev, 11, 0x4A);
2792                 rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
2793                 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2794                 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2795                 rt2800_rfcsr_write(rt2x00dev, 24, 0x4A);
2796                 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
2797                 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2798                 rt2800_rfcsr_write(rt2x00dev, 36, 0x80);
2799                 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
2800                 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
2801                 rt2800_rfcsr_write(rt2x00dev, 39, 0x1B);
2802                 rt2800_rfcsr_write(rt2x00dev, 40, 0x0D);
2803                 rt2800_rfcsr_write(rt2x00dev, 41, 0x9B);
2804                 rt2800_rfcsr_write(rt2x00dev, 42, 0xD5);
2805                 rt2800_rfcsr_write(rt2x00dev, 43, 0x72);
2806                 rt2800_rfcsr_write(rt2x00dev, 44, 0x0E);
2807                 rt2800_rfcsr_write(rt2x00dev, 45, 0xA2);
2808                 rt2800_rfcsr_write(rt2x00dev, 46, 0x6B);
2809                 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
2810                 rt2800_rfcsr_write(rt2x00dev, 51, 0x3E);
2811                 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
2812                 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
2813                 rt2800_rfcsr_write(rt2x00dev, 56, 0xA1);
2814                 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
2815                 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
2816                 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
2817                 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
2818                 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
2819
2820                 /* TODO RF27 <- tssi */
2821
2822                 rfcsr = rf->channel <= 10 ? 0x07 : 0x06;
2823                 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2824                 rt2800_rfcsr_write(rt2x00dev, 59, rfcsr);
2825
2826                 if (is_11b) {
2827                         /* CCK */
2828                         rt2800_rfcsr_write(rt2x00dev, 31, 0xF8);
2829                         rt2800_rfcsr_write(rt2x00dev, 32, 0xC0);
2830                         if (is_type_ep)
2831                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x06);
2832                         else
2833                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x47);
2834                 } else {
2835                         /* OFDM */
2836                         if (is_type_ep)
2837                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x03);
2838                         else
2839                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
2840                 }
2841
2842                 power_bound = POWER_BOUND;
2843                 ep_reg = 0x2;
2844         } else {
2845                 rt2800_rfcsr_write(rt2x00dev, 10, 0x97);
2846                 /* FIMXE: RF11 overwrite */
2847                 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
2848                 rt2800_rfcsr_write(rt2x00dev, 25, 0xBF);
2849                 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2850                 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
2851                 rt2800_rfcsr_write(rt2x00dev, 37, 0x04);
2852                 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
2853                 rt2800_rfcsr_write(rt2x00dev, 40, 0x42);
2854                 rt2800_rfcsr_write(rt2x00dev, 41, 0xBB);
2855                 rt2800_rfcsr_write(rt2x00dev, 42, 0xD7);
2856                 rt2800_rfcsr_write(rt2x00dev, 45, 0x41);
2857                 rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
2858                 rt2800_rfcsr_write(rt2x00dev, 57, 0x77);
2859                 rt2800_rfcsr_write(rt2x00dev, 60, 0x05);
2860                 rt2800_rfcsr_write(rt2x00dev, 61, 0x01);
2861
2862                 /* TODO RF27 <- tssi */
2863
2864                 if (rf->channel >= 36 && rf->channel <= 64) {
2865
2866                         rt2800_rfcsr_write(rt2x00dev, 12, 0x2E);
2867                         rt2800_rfcsr_write(rt2x00dev, 13, 0x22);
2868                         rt2800_rfcsr_write(rt2x00dev, 22, 0x60);
2869                         rt2800_rfcsr_write(rt2x00dev, 23, 0x7F);
2870                         if (rf->channel <= 50)
2871                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x09);
2872                         else if (rf->channel >= 52)
2873                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x07);
2874                         rt2800_rfcsr_write(rt2x00dev, 39, 0x1C);
2875                         rt2800_rfcsr_write(rt2x00dev, 43, 0x5B);
2876                         rt2800_rfcsr_write(rt2x00dev, 44, 0X40);
2877                         rt2800_rfcsr_write(rt2x00dev, 46, 0X00);
2878                         rt2800_rfcsr_write(rt2x00dev, 51, 0xFE);
2879                         rt2800_rfcsr_write(rt2x00dev, 52, 0x0C);
2880                         rt2800_rfcsr_write(rt2x00dev, 54, 0xF8);
2881                         if (rf->channel <= 50) {
2882                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x06),
2883                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xD3);
2884                         } else if (rf->channel >= 52) {
2885                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x04);
2886                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2887                         }
2888
2889                         rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2890                         rt2800_rfcsr_write(rt2x00dev, 59, 0x7F);
2891                         rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2892
2893                 } else if (rf->channel >= 100 && rf->channel <= 165) {
2894
2895                         rt2800_rfcsr_write(rt2x00dev, 12, 0x0E);
2896                         rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2897                         rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2898                         if (rf->channel <= 153) {
2899                                 rt2800_rfcsr_write(rt2x00dev, 23, 0x3C);
2900                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x06);
2901                         } else if (rf->channel >= 155) {
2902                                 rt2800_rfcsr_write(rt2x00dev, 23, 0x38);
2903                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x05);
2904                         }
2905                         if (rf->channel <= 138) {
2906                                 rt2800_rfcsr_write(rt2x00dev, 39, 0x1A);
2907                                 rt2800_rfcsr_write(rt2x00dev, 43, 0x3B);
2908                                 rt2800_rfcsr_write(rt2x00dev, 44, 0x20);
2909                                 rt2800_rfcsr_write(rt2x00dev, 46, 0x18);
2910                         } else if (rf->channel >= 140) {
2911                                 rt2800_rfcsr_write(rt2x00dev, 39, 0x18);
2912                                 rt2800_rfcsr_write(rt2x00dev, 43, 0x1B);
2913                                 rt2800_rfcsr_write(rt2x00dev, 44, 0x10);
2914                                 rt2800_rfcsr_write(rt2x00dev, 46, 0X08);
2915                         }
2916                         if (rf->channel <= 124)
2917                                 rt2800_rfcsr_write(rt2x00dev, 51, 0xFC);
2918                         else if (rf->channel >= 126)
2919                                 rt2800_rfcsr_write(rt2x00dev, 51, 0xEC);
2920                         if (rf->channel <= 138)
2921                                 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2922                         else if (rf->channel >= 140)
2923                                 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2924                         rt2800_rfcsr_write(rt2x00dev, 54, 0xEB);
2925                         if (rf->channel <= 138)
2926                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x01);
2927                         else if (rf->channel >= 140)
2928                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x00);
2929                         if (rf->channel <= 128)
2930                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2931                         else if (rf->channel >= 130)
2932                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xAB);
2933                         if (rf->channel <= 116)
2934                                 rt2800_rfcsr_write(rt2x00dev, 58, 0x1D);
2935                         else if (rf->channel >= 118)
2936                                 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2937                         if (rf->channel <= 138)
2938                                 rt2800_rfcsr_write(rt2x00dev, 59, 0x3F);
2939                         else if (rf->channel >= 140)
2940                                 rt2800_rfcsr_write(rt2x00dev, 59, 0x7C);
2941                         if (rf->channel <= 116)
2942                                 rt2800_rfcsr_write(rt2x00dev, 62, 0x1D);
2943                         else if (rf->channel >= 118)
2944                                 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2945                 }
2946
2947                 power_bound = POWER_BOUND_5G;
2948                 ep_reg = 0x3;
2949         }
2950
2951         rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2952         if (info->default_power1 > power_bound)
2953                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound);
2954         else
2955                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2956         if (is_type_ep)
2957                 rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg);
2958         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2959
2960         rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2961         if (info->default_power2 > power_bound)
2962                 rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound);
2963         else
2964                 rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2);
2965         if (is_type_ep)
2966                 rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg);
2967         rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2968
2969         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2970         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2971         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2972
2973         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD,
2974                           rt2x00dev->default_ant.tx_chain_num >= 1);
2975         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
2976                           rt2x00dev->default_ant.tx_chain_num == 2);
2977         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2978
2979         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD,
2980                           rt2x00dev->default_ant.rx_chain_num >= 1);
2981         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
2982                           rt2x00dev->default_ant.rx_chain_num == 2);
2983         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2984
2985         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2986         rt2800_rfcsr_write(rt2x00dev, 6, 0xe4);
2987
2988         if (conf_is_ht40(conf))
2989                 rt2800_rfcsr_write(rt2x00dev, 30, 0x16);
2990         else
2991                 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
2992
2993         if (!is_11b) {
2994                 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
2995                 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
2996         }
2997
2998         /* TODO proper frequency adjustment */
2999         rt2800_adjust_freq_offset(rt2x00dev);
3000
3001         /* TODO merge with others */
3002         rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
3003         rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
3004         rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3005
3006         /* BBP settings */
3007         rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3008         rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3009         rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3010
3011         rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18);
3012         rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08);
3013         rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38);
3014         rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92);
3015
3016         /* GLRT band configuration */
3017         rt2800_bbp_write(rt2x00dev, 195, 128);
3018         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0);
3019         rt2800_bbp_write(rt2x00dev, 195, 129);
3020         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E);
3021         rt2800_bbp_write(rt2x00dev, 195, 130);
3022         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28);
3023         rt2800_bbp_write(rt2x00dev, 195, 131);
3024         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20);
3025         rt2800_bbp_write(rt2x00dev, 195, 133);
3026         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F);
3027         rt2800_bbp_write(rt2x00dev, 195, 124);
3028         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F);
3029 }
3030
3031 static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev,
3032                                            const unsigned int word,
3033                                            const u8 value)
3034 {
3035         u8 chain, reg;
3036
3037         for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) {
3038                 rt2800_bbp_read(rt2x00dev, 27, &reg);
3039                 rt2x00_set_field8(&reg,  BBP27_RX_CHAIN_SEL, chain);
3040                 rt2800_bbp_write(rt2x00dev, 27, reg);
3041
3042                 rt2800_bbp_write(rt2x00dev, word, value);
3043         }
3044 }
3045
3046 static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel)
3047 {
3048         u8 cal;
3049
3050         /* TX0 IQ Gain */
3051         rt2800_bbp_write(rt2x00dev, 158, 0x2c);
3052         if (channel <= 14)
3053                 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX0_2G);
3054         else if (channel >= 36 && channel <= 64)
3055                 cal = rt2x00_eeprom_byte(rt2x00dev,
3056                                          EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G);
3057         else if (channel >= 100 && channel <= 138)
3058                 cal = rt2x00_eeprom_byte(rt2x00dev,
3059                                          EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G);
3060         else if (channel >= 140 && channel <= 165)
3061                 cal = rt2x00_eeprom_byte(rt2x00dev,
3062                                          EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G);
3063         else
3064                 cal = 0;
3065         rt2800_bbp_write(rt2x00dev, 159, cal);
3066
3067         /* TX0 IQ Phase */
3068         rt2800_bbp_write(rt2x00dev, 158, 0x2d);
3069         if (channel <= 14)
3070                 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX0_2G);
3071         else if (channel >= 36 && channel <= 64)
3072                 cal = rt2x00_eeprom_byte(rt2x00dev,
3073                                          EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G);
3074         else if (channel >= 100 && channel <= 138)
3075                 cal = rt2x00_eeprom_byte(rt2x00dev,
3076                                          EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G);
3077         else if (channel >= 140 && channel <= 165)
3078                 cal = rt2x00_eeprom_byte(rt2x00dev,
3079                                          EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G);
3080         else
3081                 cal = 0;
3082         rt2800_bbp_write(rt2x00dev, 159, cal);
3083
3084         /* TX1 IQ Gain */
3085         rt2800_bbp_write(rt2x00dev, 158, 0x4a);
3086         if (channel <= 14)
3087                 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX1_2G);
3088         else if (channel >= 36 && channel <= 64)
3089                 cal = rt2x00_eeprom_byte(rt2x00dev,
3090                                          EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G);
3091         else if (channel >= 100 && channel <= 138)
3092                 cal = rt2x00_eeprom_byte(rt2x00dev,
3093                                          EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G);
3094         else if (channel >= 140 && channel <= 165)
3095                 cal = rt2x00_eeprom_byte(rt2x00dev,
3096                                          EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G);
3097         else
3098                 cal = 0;
3099         rt2800_bbp_write(rt2x00dev, 159, cal);
3100
3101         /* TX1 IQ Phase */
3102         rt2800_bbp_write(rt2x00dev, 158, 0x4b);
3103         if (channel <= 14)
3104                 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX1_2G);
3105         else if (channel >= 36 && channel <= 64)
3106                 cal = rt2x00_eeprom_byte(rt2x00dev,
3107                                          EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G);
3108         else if (channel >= 100 && channel <= 138)
3109                 cal = rt2x00_eeprom_byte(rt2x00dev,
3110                                          EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G);
3111         else if (channel >= 140 && channel <= 165)
3112                 cal = rt2x00_eeprom_byte(rt2x00dev,
3113                                          EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G);
3114         else
3115                 cal = 0;
3116         rt2800_bbp_write(rt2x00dev, 159, cal);
3117
3118         /* FIXME: possible RX0, RX1 callibration ? */
3119
3120         /* RF IQ compensation control */
3121         rt2800_bbp_write(rt2x00dev, 158, 0x04);
3122         cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_COMPENSATION_CONTROL);
3123         rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
3124
3125         /* RF IQ imbalance compensation control */
3126         rt2800_bbp_write(rt2x00dev, 158, 0x03);
3127         cal = rt2x00_eeprom_byte(rt2x00dev,
3128                                  EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL);
3129         rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
3130 }
3131
3132 static char rt2800_txpower_to_dev(struct rt2x00_dev *rt2x00dev,
3133                                   unsigned int channel,
3134                                   char txpower)
3135 {
3136         if (rt2x00_rt(rt2x00dev, RT3593))
3137                 txpower = rt2x00_get_field8(txpower, EEPROM_TXPOWER_ALC);
3138
3139         if (channel <= 14)
3140                 return clamp_t(char, txpower, MIN_G_TXPOWER, MAX_G_TXPOWER);
3141
3142         if (rt2x00_rt(rt2x00dev, RT3593))
3143                 return clamp_t(char, txpower, MIN_A_TXPOWER_3593,
3144                                MAX_A_TXPOWER_3593);
3145         else
3146                 return clamp_t(char, txpower, MIN_A_TXPOWER, MAX_A_TXPOWER);
3147 }
3148
3149 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
3150                                   struct ieee80211_conf *conf,
3151                                   struct rf_channel *rf,
3152                                   struct channel_info *info)
3153 {
3154         u32 reg;
3155         unsigned int tx_pin;
3156         u8 bbp, rfcsr;
3157
3158         info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3159                                                      info->default_power1);
3160         info->default_power2 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3161                                                      info->default_power2);
3162         if (rt2x00dev->default_ant.tx_chain_num > 2)
3163                 info->default_power3 =
3164                         rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3165                                               info->default_power3);
3166
3167         switch (rt2x00dev->chip.rf) {
3168         case RF2020:
3169         case RF3020:
3170         case RF3021:
3171         case RF3022:
3172         case RF3320:
3173                 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
3174                 break;
3175         case RF3052:
3176                 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
3177                 break;
3178         case RF3053:
3179                 rt2800_config_channel_rf3053(rt2x00dev, conf, rf, info);
3180                 break;
3181         case RF3290:
3182                 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
3183                 break;
3184         case RF3322:
3185                 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
3186                 break;
3187         case RF3070:
3188         case RF5360:
3189         case RF5370:
3190         case RF5372:
3191         case RF5390:
3192         case RF5392:
3193                 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
3194                 break;
3195         case RF5592:
3196                 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info);
3197                 break;
3198         default:
3199                 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
3200         }
3201
3202         if (rt2x00_rf(rt2x00dev, RF3070) ||
3203             rt2x00_rf(rt2x00dev, RF3290) ||
3204             rt2x00_rf(rt2x00dev, RF3322) ||
3205             rt2x00_rf(rt2x00dev, RF5360) ||
3206             rt2x00_rf(rt2x00dev, RF5370) ||
3207             rt2x00_rf(rt2x00dev, RF5372) ||
3208             rt2x00_rf(rt2x00dev, RF5390) ||
3209             rt2x00_rf(rt2x00dev, RF5392)) {
3210                 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3211                 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
3212                 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
3213                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3214
3215                 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
3216                 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
3217                 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3218         }
3219
3220         /*
3221          * Change BBP settings
3222          */
3223         if (rt2x00_rt(rt2x00dev, RT3352)) {
3224                 rt2800_bbp_write(rt2x00dev, 27, 0x0);
3225                 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
3226                 rt2800_bbp_write(rt2x00dev, 27, 0x20);
3227                 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
3228         } else if (rt2x00_rt(rt2x00dev, RT3593)) {
3229                 if (rf->channel > 14) {
3230                         /* Disable CCK Packet detection on 5GHz */
3231                         rt2800_bbp_write(rt2x00dev, 70, 0x00);
3232                 } else {
3233                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3234                 }
3235
3236                 if (conf_is_ht40(conf))
3237                         rt2800_bbp_write(rt2x00dev, 105, 0x04);
3238                 else
3239                         rt2800_bbp_write(rt2x00dev, 105, 0x34);
3240
3241                 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3242                 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3243                 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3244                 rt2800_bbp_write(rt2x00dev, 77, 0x98);
3245         } else {
3246                 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3247                 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3248                 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3249                 rt2800_bbp_write(rt2x00dev, 86, 0);
3250         }
3251
3252         if (rf->channel <= 14) {
3253                 if (!rt2x00_rt(rt2x00dev, RT5390) &&
3254                     !rt2x00_rt(rt2x00dev, RT5392)) {
3255                         if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
3256                                 rt2800_bbp_write(rt2x00dev, 82, 0x62);
3257                                 rt2800_bbp_write(rt2x00dev, 75, 0x46);
3258                         } else {
3259                                 if (rt2x00_rt(rt2x00dev, RT3593))
3260                                         rt2800_bbp_write(rt2x00dev, 82, 0x62);
3261                                 else
3262                                         rt2800_bbp_write(rt2x00dev, 82, 0x84);
3263                                 rt2800_bbp_write(rt2x00dev, 75, 0x50);
3264                         }
3265                         if (rt2x00_rt(rt2x00dev, RT3593))
3266                                 rt2800_bbp_write(rt2x00dev, 83, 0x8a);
3267                 }
3268
3269         } else {
3270                 if (rt2x00_rt(rt2x00dev, RT3572))
3271                         rt2800_bbp_write(rt2x00dev, 82, 0x94);
3272                 else if (rt2x00_rt(rt2x00dev, RT3593))
3273                         rt2800_bbp_write(rt2x00dev, 82, 0x82);
3274                 else
3275                         rt2800_bbp_write(rt2x00dev, 82, 0xf2);
3276
3277                 if (rt2x00_rt(rt2x00dev, RT3593))
3278                         rt2800_bbp_write(rt2x00dev, 83, 0x9a);
3279
3280                 if (rt2x00_has_cap_external_lna_a(rt2x00dev))
3281                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
3282                 else
3283                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
3284         }
3285
3286         rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
3287         rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
3288         rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
3289         rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
3290         rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
3291
3292         if (rt2x00_rt(rt2x00dev, RT3572))
3293                 rt2800_rfcsr_write(rt2x00dev, 8, 0);
3294
3295         tx_pin = 0;
3296
3297         switch (rt2x00dev->default_ant.tx_chain_num) {
3298         case 3:
3299                 /* Turn on tertiary PAs */
3300                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN,
3301                                    rf->channel > 14);
3302                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN,
3303                                    rf->channel <= 14);
3304                 /* fall-through */
3305         case 2:
3306                 /* Turn on secondary PAs */
3307                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
3308                                    rf->channel > 14);
3309                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
3310                                    rf->channel <= 14);
3311                 /* fall-through */
3312         case 1:
3313                 /* Turn on primary PAs */
3314                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN,
3315                                    rf->channel > 14);
3316                 if (rt2x00_has_cap_bt_coexist(rt2x00dev))
3317                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
3318                 else
3319                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
3320                                            rf->channel <= 14);
3321                 break;
3322         }
3323
3324         switch (rt2x00dev->default_ant.rx_chain_num) {
3325         case 3:
3326                 /* Turn on tertiary LNAs */
3327                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A2_EN, 1);
3328                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G2_EN, 1);
3329                 /* fall-through */
3330         case 2:
3331                 /* Turn on secondary LNAs */
3332                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
3333                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
3334                 /* fall-through */
3335         case 1:
3336                 /* Turn on primary LNAs */
3337                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
3338                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
3339                 break;
3340         }
3341
3342         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
3343         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
3344
3345         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
3346
3347         if (rt2x00_rt(rt2x00dev, RT3572)) {
3348                 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
3349
3350                 /* AGC init */
3351                 if (rf->channel <= 14)
3352                         reg = 0x1c + (2 * rt2x00dev->lna_gain);
3353                 else
3354                         reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
3355
3356                 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
3357         }
3358
3359         if (rt2x00_rt(rt2x00dev, RT3593)) {
3360                 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
3361
3362                 /* Band selection */
3363                 if (rt2x00_is_usb(rt2x00dev) ||
3364                     rt2x00_is_pcie(rt2x00dev)) {
3365                         /* GPIO #8 controls all paths */
3366                         rt2x00_set_field32(&reg, GPIO_CTRL_DIR8, 0);
3367                         if (rf->channel <= 14)
3368                                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 1);
3369                         else
3370                                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 0);
3371                 }
3372
3373                 /* LNA PE control. */
3374                 if (rt2x00_is_usb(rt2x00dev)) {
3375                         /* GPIO #4 controls PE0 and PE1,
3376                          * GPIO #7 controls PE2
3377                          */
3378                         rt2x00_set_field32(&reg, GPIO_CTRL_DIR4, 0);
3379                         rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
3380
3381                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL4, 1);
3382                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
3383                 } else if (rt2x00_is_pcie(rt2x00dev)) {
3384                         /* GPIO #4 controls PE0, PE1 and PE2 */
3385                         rt2x00_set_field32(&reg, GPIO_CTRL_DIR4, 0);
3386                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL4, 1);
3387                 }
3388
3389                 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
3390
3391                 /* AGC init */
3392                 if (rf->channel <= 14)
3393                         reg = 0x1c + 2 * rt2x00dev->lna_gain;
3394                 else
3395                         reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
3396
3397                 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
3398
3399                 usleep_range(1000, 1500);
3400         }
3401
3402         if (rt2x00_rt(rt2x00dev, RT5592)) {
3403                 rt2800_bbp_write(rt2x00dev, 195, 141);
3404                 rt2800_bbp_write(rt2x00dev, 196, conf_is_ht40(conf) ? 0x10 : 0x1a);
3405
3406                 /* AGC init */
3407                 reg = (rf->channel <= 14 ? 0x1c : 0x24) + 2 * rt2x00dev->lna_gain;
3408                 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
3409
3410                 rt2800_iq_calibrate(rt2x00dev, rf->channel);
3411         }
3412
3413         rt2800_bbp_read(rt2x00dev, 4, &bbp);
3414         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
3415         rt2800_bbp_write(rt2x00dev, 4, bbp);
3416
3417         rt2800_bbp_read(rt2x00dev, 3, &bbp);
3418         rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
3419         rt2800_bbp_write(rt2x00dev, 3, bbp);
3420
3421         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
3422                 if (conf_is_ht40(conf)) {
3423                         rt2800_bbp_write(rt2x00dev, 69, 0x1a);
3424                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3425                         rt2800_bbp_write(rt2x00dev, 73, 0x16);
3426                 } else {
3427                         rt2800_bbp_write(rt2x00dev, 69, 0x16);
3428                         rt2800_bbp_write(rt2x00dev, 70, 0x08);
3429                         rt2800_bbp_write(rt2x00dev, 73, 0x11);
3430                 }
3431         }
3432
3433         msleep(1);
3434
3435         /*
3436          * Clear channel statistic counters
3437          */
3438         rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
3439         rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
3440         rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
3441
3442         /*
3443          * Clear update flag
3444          */
3445         if (rt2x00_rt(rt2x00dev, RT3352)) {
3446                 rt2800_bbp_read(rt2x00dev, 49, &bbp);
3447                 rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0);
3448                 rt2800_bbp_write(rt2x00dev, 49, bbp);
3449         }
3450 }
3451
3452 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
3453 {
3454         u8 tssi_bounds[9];
3455         u8 current_tssi;
3456         u16 eeprom;
3457         u8 step;
3458         int i;
3459
3460         /*
3461          * First check if temperature compensation is supported.
3462          */
3463         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3464         if (!rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC))
3465                 return 0;
3466
3467         /*
3468          * Read TSSI boundaries for temperature compensation from
3469          * the EEPROM.
3470          *
3471          * Array idx               0    1    2    3    4    5    6    7    8
3472          * Matching Delta value   -4   -3   -2   -1    0   +1   +2   +3   +4
3473          * Example TSSI bounds  0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
3474          */
3475         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
3476                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
3477                 tssi_bounds[0] = rt2x00_get_field16(eeprom,
3478                                         EEPROM_TSSI_BOUND_BG1_MINUS4);
3479                 tssi_bounds[1] = rt2x00_get_field16(eeprom,
3480                                         EEPROM_TSSI_BOUND_BG1_MINUS3);
3481
3482                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
3483                 tssi_bounds[2] = rt2x00_get_field16(eeprom,
3484                                         EEPROM_TSSI_BOUND_BG2_MINUS2);
3485                 tssi_bounds[3] = rt2x00_get_field16(eeprom,
3486                                         EEPROM_TSSI_BOUND_BG2_MINUS1);
3487
3488                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
3489                 tssi_bounds[4] = rt2x00_get_field16(eeprom,
3490                                         EEPROM_TSSI_BOUND_BG3_REF);
3491                 tssi_bounds[5] = rt2x00_get_field16(eeprom,
3492                                         EEPROM_TSSI_BOUND_BG3_PLUS1);
3493
3494                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
3495                 tssi_bounds[6] = rt2x00_get_field16(eeprom,
3496                                         EEPROM_TSSI_BOUND_BG4_PLUS2);
3497                 tssi_bounds[7] = rt2x00_get_field16(eeprom,
3498                                         EEPROM_TSSI_BOUND_BG4_PLUS3);
3499
3500                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
3501                 tssi_bounds[8] = rt2x00_get_field16(eeprom,
3502                                         EEPROM_TSSI_BOUND_BG5_PLUS4);
3503
3504                 step = rt2x00_get_field16(eeprom,
3505                                           EEPROM_TSSI_BOUND_BG5_AGC_STEP);
3506         } else {
3507                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
3508                 tssi_bounds[0] = rt2x00_get_field16(eeprom,
3509                                         EEPROM_TSSI_BOUND_A1_MINUS4);
3510                 tssi_bounds[1] = rt2x00_get_field16(eeprom,
3511                                         EEPROM_TSSI_BOUND_A1_MINUS3);
3512
3513                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
3514                 tssi_bounds[2] = rt2x00_get_field16(eeprom,
3515                                         EEPROM_TSSI_BOUND_A2_MINUS2);
3516                 tssi_bounds[3] = rt2x00_get_field16(eeprom,
3517                                         EEPROM_TSSI_BOUND_A2_MINUS1);
3518
3519                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
3520                 tssi_bounds[4] = rt2x00_get_field16(eeprom,
3521                                         EEPROM_TSSI_BOUND_A3_REF);
3522                 tssi_bounds[5] = rt2x00_get_field16(eeprom,
3523                                         EEPROM_TSSI_BOUND_A3_PLUS1);
3524
3525                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
3526                 tssi_bounds[6] = rt2x00_get_field16(eeprom,
3527                                         EEPROM_TSSI_BOUND_A4_PLUS2);
3528                 tssi_bounds[7] = rt2x00_get_field16(eeprom,
3529                                         EEPROM_TSSI_BOUND_A4_PLUS3);
3530
3531                 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
3532                 tssi_bounds[8] = rt2x00_get_field16(eeprom,
3533                                         EEPROM_TSSI_BOUND_A5_PLUS4);
3534
3535                 step = rt2x00_get_field16(eeprom,
3536                                           EEPROM_TSSI_BOUND_A5_AGC_STEP);
3537         }
3538
3539         /*
3540          * Check if temperature compensation is supported.
3541          */
3542         if (tssi_bounds[4] == 0xff || step == 0xff)
3543                 return 0;
3544
3545         /*
3546          * Read current TSSI (BBP 49).
3547          */
3548         rt2800_bbp_read(rt2x00dev, 49, &current_tssi);
3549
3550         /*
3551          * Compare TSSI value (BBP49) with the compensation boundaries
3552          * from the EEPROM and increase or decrease tx power.
3553          */
3554         for (i = 0; i <= 3; i++) {
3555                 if (current_tssi > tssi_bounds[i])
3556                         break;
3557         }
3558
3559         if (i == 4) {
3560                 for (i = 8; i >= 5; i--) {
3561                         if (current_tssi < tssi_bounds[i])
3562                                 break;
3563                 }
3564         }
3565
3566         return (i - 4) * step;
3567 }
3568
3569 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
3570                                       enum ieee80211_band band)
3571 {
3572         u16 eeprom;
3573         u8 comp_en;
3574         u8 comp_type;
3575         int comp_value = 0;
3576
3577         rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
3578
3579         /*
3580          * HT40 compensation not required.
3581          */
3582         if (eeprom == 0xffff ||
3583             !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
3584                 return 0;
3585
3586         if (band == IEEE80211_BAND_2GHZ) {
3587                 comp_en = rt2x00_get_field16(eeprom,
3588                                  EEPROM_TXPOWER_DELTA_ENABLE_2G);
3589                 if (comp_en) {
3590                         comp_type = rt2x00_get_field16(eeprom,
3591                                            EEPROM_TXPOWER_DELTA_TYPE_2G);
3592                         comp_value = rt2x00_get_field16(eeprom,
3593                                             EEPROM_TXPOWER_DELTA_VALUE_2G);
3594                         if (!comp_type)
3595                                 comp_value = -comp_value;
3596                 }
3597         } else {
3598                 comp_en = rt2x00_get_field16(eeprom,
3599                                  EEPROM_TXPOWER_DELTA_ENABLE_5G);
3600                 if (comp_en) {
3601                         comp_type = rt2x00_get_field16(eeprom,
3602                                            EEPROM_TXPOWER_DELTA_TYPE_5G);
3603                         comp_value = rt2x00_get_field16(eeprom,
3604                                             EEPROM_TXPOWER_DELTA_VALUE_5G);
3605                         if (!comp_type)
3606                                 comp_value = -comp_value;
3607                 }
3608         }
3609
3610         return comp_value;
3611 }
3612
3613 static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev,
3614                                         int power_level, int max_power)
3615 {
3616         int delta;
3617
3618         if (rt2x00_has_cap_power_limit(rt2x00dev))
3619                 return 0;
3620
3621         /*
3622          * XXX: We don't know the maximum transmit power of our hardware since
3623          * the EEPROM doesn't expose it. We only know that we are calibrated
3624          * to 100% tx power.
3625          *
3626          * Hence, we assume the regulatory limit that cfg80211 calulated for
3627          * the current channel is our maximum and if we are requested to lower
3628          * the value we just reduce our tx power accordingly.
3629          */
3630         delta = power_level - max_power;
3631         return min(delta, 0);
3632 }
3633
3634 static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
3635                                    enum ieee80211_band band, int power_level,
3636                                    u8 txpower, int delta)
3637 {
3638         u16 eeprom;
3639         u8 criterion;
3640         u8 eirp_txpower;
3641         u8 eirp_txpower_criterion;
3642         u8 reg_limit;
3643
3644         if (rt2x00_rt(rt2x00dev, RT3593))
3645                 return min_t(u8, txpower, 0xc);
3646
3647         if (rt2x00_has_cap_power_limit(rt2x00dev)) {
3648                 /*
3649                  * Check if eirp txpower exceed txpower_limit.
3650                  * We use OFDM 6M as criterion and its eirp txpower
3651                  * is stored at EEPROM_EIRP_MAX_TX_POWER.
3652                  * .11b data rate need add additional 4dbm
3653                  * when calculating eirp txpower.
3654                  */
3655                 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3656                                               1, &eeprom);
3657                 criterion = rt2x00_get_field16(eeprom,
3658                                                EEPROM_TXPOWER_BYRATE_RATE0);
3659
3660                 rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER,
3661                                    &eeprom);
3662
3663                 if (band == IEEE80211_BAND_2GHZ)
3664                         eirp_txpower_criterion = rt2x00_get_field16(eeprom,
3665                                                  EEPROM_EIRP_MAX_TX_POWER_2GHZ);
3666                 else
3667                         eirp_txpower_criterion = rt2x00_get_field16(eeprom,
3668                                                  EEPROM_EIRP_MAX_TX_POWER_5GHZ);
3669
3670                 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
3671                                (is_rate_b ? 4 : 0) + delta;
3672
3673                 reg_limit = (eirp_txpower > power_level) ?
3674                                         (eirp_txpower - power_level) : 0;
3675         } else
3676                 reg_limit = 0;
3677
3678         txpower = max(0, txpower + delta - reg_limit);
3679         return min_t(u8, txpower, 0xc);
3680 }
3681
3682
3683 enum {
3684         TX_PWR_CFG_0_IDX,
3685         TX_PWR_CFG_1_IDX,
3686         TX_PWR_CFG_2_IDX,
3687         TX_PWR_CFG_3_IDX,
3688         TX_PWR_CFG_4_IDX,
3689         TX_PWR_CFG_5_IDX,
3690         TX_PWR_CFG_6_IDX,
3691         TX_PWR_CFG_7_IDX,
3692         TX_PWR_CFG_8_IDX,
3693         TX_PWR_CFG_9_IDX,
3694         TX_PWR_CFG_0_EXT_IDX,
3695         TX_PWR_CFG_1_EXT_IDX,
3696         TX_PWR_CFG_2_EXT_IDX,
3697         TX_PWR_CFG_3_EXT_IDX,
3698         TX_PWR_CFG_4_EXT_IDX,
3699         TX_PWR_CFG_IDX_COUNT,
3700 };
3701
3702 static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev,
3703                                          struct ieee80211_channel *chan,
3704                                          int power_level)
3705 {
3706         u8 txpower;
3707         u16 eeprom;
3708         u32 regs[TX_PWR_CFG_IDX_COUNT];
3709         unsigned int offset;
3710         enum ieee80211_band band = chan->band;
3711         int delta;
3712         int i;
3713
3714         memset(regs, '\0', sizeof(regs));
3715
3716         /* TODO: adapt TX power reduction from the rt28xx code */
3717
3718         /* calculate temperature compensation delta */
3719         delta = rt2800_get_gain_calibration_delta(rt2x00dev);
3720
3721         if (band == IEEE80211_BAND_5GHZ)
3722                 offset = 16;
3723         else
3724                 offset = 0;
3725
3726         if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
3727                 offset += 8;
3728
3729         /* read the next four txpower values */
3730         rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3731                                       offset, &eeprom);
3732
3733         /* CCK 1MBS,2MBS */
3734         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3735         txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
3736                                             txpower, delta);
3737         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3738                            TX_PWR_CFG_0_CCK1_CH0, txpower);
3739         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3740                            TX_PWR_CFG_0_CCK1_CH1, txpower);
3741         rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3742                            TX_PWR_CFG_0_EXT_CCK1_CH2, txpower);
3743
3744         /* CCK 5.5MBS,11MBS */
3745         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3746         txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
3747                                             txpower, delta);
3748         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3749                            TX_PWR_CFG_0_CCK5_CH0, txpower);
3750         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3751                            TX_PWR_CFG_0_CCK5_CH1, txpower);
3752         rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3753                            TX_PWR_CFG_0_EXT_CCK5_CH2, txpower);
3754
3755         /* OFDM 6MBS,9MBS */
3756         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3757         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3758                                             txpower, delta);
3759         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3760                            TX_PWR_CFG_0_OFDM6_CH0, txpower);
3761         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3762                            TX_PWR_CFG_0_OFDM6_CH1, txpower);
3763         rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3764                            TX_PWR_CFG_0_EXT_OFDM6_CH2, txpower);
3765
3766         /* OFDM 12MBS,18MBS */
3767         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3768         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3769                                             txpower, delta);
3770         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3771                            TX_PWR_CFG_0_OFDM12_CH0, txpower);
3772         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
3773                            TX_PWR_CFG_0_OFDM12_CH1, txpower);
3774         rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
3775                            TX_PWR_CFG_0_EXT_OFDM12_CH2, txpower);
3776
3777         /* read the next four txpower values */
3778         rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3779                                       offset + 1, &eeprom);
3780
3781         /* OFDM 24MBS,36MBS */
3782         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3783         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3784                                             txpower, delta);
3785         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3786                            TX_PWR_CFG_1_OFDM24_CH0, txpower);
3787         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3788                            TX_PWR_CFG_1_OFDM24_CH1, txpower);
3789         rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3790                            TX_PWR_CFG_1_EXT_OFDM24_CH2, txpower);
3791
3792         /* OFDM 48MBS */
3793         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3794         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3795                                             txpower, delta);
3796         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3797                            TX_PWR_CFG_1_OFDM48_CH0, txpower);
3798         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3799                            TX_PWR_CFG_1_OFDM48_CH1, txpower);
3800         rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3801                            TX_PWR_CFG_1_EXT_OFDM48_CH2, txpower);
3802
3803         /* OFDM 54MBS */
3804         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3805         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3806                                             txpower, delta);
3807         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3808                            TX_PWR_CFG_7_OFDM54_CH0, txpower);
3809         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3810                            TX_PWR_CFG_7_OFDM54_CH1, txpower);
3811         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3812                            TX_PWR_CFG_7_OFDM54_CH2, txpower);
3813
3814         /* read the next four txpower values */
3815         rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3816                                       offset + 2, &eeprom);
3817
3818         /* MCS 0,1 */
3819         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3820         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3821                                             txpower, delta);
3822         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3823                            TX_PWR_CFG_1_MCS0_CH0, txpower);
3824         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3825                            TX_PWR_CFG_1_MCS0_CH1, txpower);
3826         rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3827                            TX_PWR_CFG_1_EXT_MCS0_CH2, txpower);
3828
3829         /* MCS 2,3 */
3830         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3831         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3832                                             txpower, delta);
3833         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3834                            TX_PWR_CFG_1_MCS2_CH0, txpower);
3835         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
3836                            TX_PWR_CFG_1_MCS2_CH1, txpower);
3837         rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
3838                            TX_PWR_CFG_1_EXT_MCS2_CH2, txpower);
3839
3840         /* MCS 4,5 */
3841         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3842         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3843                                             txpower, delta);
3844         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3845                            TX_PWR_CFG_2_MCS4_CH0, txpower);
3846         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3847                            TX_PWR_CFG_2_MCS4_CH1, txpower);
3848         rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3849                            TX_PWR_CFG_2_EXT_MCS4_CH2, txpower);
3850
3851         /* MCS 6 */
3852         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3853         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3854                                             txpower, delta);
3855         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3856                            TX_PWR_CFG_2_MCS6_CH0, txpower);
3857         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3858                            TX_PWR_CFG_2_MCS6_CH1, txpower);
3859         rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3860                            TX_PWR_CFG_2_EXT_MCS6_CH2, txpower);
3861
3862         /* read the next four txpower values */
3863         rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3864                                       offset + 3, &eeprom);
3865
3866         /* MCS 7 */
3867         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3868         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3869                                             txpower, delta);
3870         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3871                            TX_PWR_CFG_7_MCS7_CH0, txpower);
3872         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3873                            TX_PWR_CFG_7_MCS7_CH1, txpower);
3874         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
3875                            TX_PWR_CFG_7_MCS7_CH2, txpower);
3876
3877         /* MCS 8,9 */
3878         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3879         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3880                                             txpower, delta);
3881         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3882                            TX_PWR_CFG_2_MCS8_CH0, txpower);
3883         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3884                            TX_PWR_CFG_2_MCS8_CH1, txpower);
3885         rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3886                            TX_PWR_CFG_2_EXT_MCS8_CH2, txpower);
3887
3888         /* MCS 10,11 */
3889         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3890         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3891                                             txpower, delta);
3892         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3893                            TX_PWR_CFG_2_MCS10_CH0, txpower);
3894         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
3895                            TX_PWR_CFG_2_MCS10_CH1, txpower);
3896         rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
3897                            TX_PWR_CFG_2_EXT_MCS10_CH2, txpower);
3898
3899         /* MCS 12,13 */
3900         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3901         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3902                                             txpower, delta);
3903         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3904                            TX_PWR_CFG_3_MCS12_CH0, txpower);
3905         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3906                            TX_PWR_CFG_3_MCS12_CH1, txpower);
3907         rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3908                            TX_PWR_CFG_3_EXT_MCS12_CH2, txpower);
3909
3910         /* read the next four txpower values */
3911         rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3912                                       offset + 4, &eeprom);
3913
3914         /* MCS 14 */
3915         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3916         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3917                                             txpower, delta);
3918         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3919                            TX_PWR_CFG_3_MCS14_CH0, txpower);
3920         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
3921                            TX_PWR_CFG_3_MCS14_CH1, txpower);
3922         rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
3923                            TX_PWR_CFG_3_EXT_MCS14_CH2, txpower);
3924
3925         /* MCS 15 */
3926         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3927         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3928                                             txpower, delta);
3929         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3930                            TX_PWR_CFG_8_MCS15_CH0, txpower);
3931         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3932                            TX_PWR_CFG_8_MCS15_CH1, txpower);
3933         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3934                            TX_PWR_CFG_8_MCS15_CH2, txpower);
3935
3936         /* MCS 16,17 */
3937         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3938         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3939                                             txpower, delta);
3940         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3941                            TX_PWR_CFG_5_MCS16_CH0, txpower);
3942         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3943                            TX_PWR_CFG_5_MCS16_CH1, txpower);
3944         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3945                            TX_PWR_CFG_5_MCS16_CH2, txpower);
3946
3947         /* MCS 18,19 */
3948         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3949         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3950                                             txpower, delta);
3951         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3952                            TX_PWR_CFG_5_MCS18_CH0, txpower);
3953         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3954                            TX_PWR_CFG_5_MCS18_CH1, txpower);
3955         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
3956                            TX_PWR_CFG_5_MCS18_CH2, txpower);
3957
3958         /* read the next four txpower values */
3959         rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3960                                       offset + 5, &eeprom);
3961
3962         /* MCS 20,21 */
3963         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3964         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3965                                             txpower, delta);
3966         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3967                            TX_PWR_CFG_6_MCS20_CH0, txpower);
3968         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3969                            TX_PWR_CFG_6_MCS20_CH1, txpower);
3970         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3971                            TX_PWR_CFG_6_MCS20_CH2, txpower);
3972
3973         /* MCS 22 */
3974         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3975         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3976                                             txpower, delta);
3977         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3978                            TX_PWR_CFG_6_MCS22_CH0, txpower);
3979         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3980                            TX_PWR_CFG_6_MCS22_CH1, txpower);
3981         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
3982                            TX_PWR_CFG_6_MCS22_CH2, txpower);
3983
3984         /* MCS 23 */
3985         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3986         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3987                                             txpower, delta);
3988         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3989                            TX_PWR_CFG_8_MCS23_CH0, txpower);
3990         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3991                            TX_PWR_CFG_8_MCS23_CH1, txpower);
3992         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
3993                            TX_PWR_CFG_8_MCS23_CH2, txpower);
3994
3995         /* read the next four txpower values */
3996         rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3997                                       offset + 6, &eeprom);
3998
3999         /* STBC, MCS 0,1 */
4000         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4001         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4002                                             txpower, delta);
4003         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4004                            TX_PWR_CFG_3_STBC0_CH0, txpower);
4005         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4006                            TX_PWR_CFG_3_STBC0_CH1, txpower);
4007         rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
4008                            TX_PWR_CFG_3_EXT_STBC0_CH2, txpower);
4009
4010         /* STBC, MCS 2,3 */
4011         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4012         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4013                                             txpower, delta);
4014         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4015                            TX_PWR_CFG_3_STBC2_CH0, txpower);
4016         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4017                            TX_PWR_CFG_3_STBC2_CH1, txpower);
4018         rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
4019                            TX_PWR_CFG_3_EXT_STBC2_CH2, txpower);
4020
4021         /* STBC, MCS 4,5 */
4022         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4023         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4024                                             txpower, delta);
4025         rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE0, txpower);
4026         rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE1, txpower);
4027         rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE0,
4028                            txpower);
4029
4030         /* STBC, MCS 6 */
4031         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4032         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4033                                             txpower, delta);
4034         rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE2, txpower);
4035         rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE3, txpower);
4036         rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE2,
4037                            txpower);
4038
4039         /* read the next four txpower values */
4040         rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4041                                       offset + 7, &eeprom);
4042
4043         /* STBC, MCS 7 */
4044         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4045         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4046                                             txpower, delta);
4047         rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
4048                            TX_PWR_CFG_9_STBC7_CH0, txpower);
4049         rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
4050                            TX_PWR_CFG_9_STBC7_CH1, txpower);
4051         rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
4052                            TX_PWR_CFG_9_STBC7_CH2, txpower);
4053
4054         rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, regs[TX_PWR_CFG_0_IDX]);
4055         rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, regs[TX_PWR_CFG_1_IDX]);
4056         rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, regs[TX_PWR_CFG_2_IDX]);
4057         rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, regs[TX_PWR_CFG_3_IDX]);
4058         rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, regs[TX_PWR_CFG_4_IDX]);
4059         rt2800_register_write(rt2x00dev, TX_PWR_CFG_5, regs[TX_PWR_CFG_5_IDX]);
4060         rt2800_register_write(rt2x00dev, TX_PWR_CFG_6, regs[TX_PWR_CFG_6_IDX]);
4061         rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, regs[TX_PWR_CFG_7_IDX]);
4062         rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, regs[TX_PWR_CFG_8_IDX]);
4063         rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, regs[TX_PWR_CFG_9_IDX]);
4064
4065         rt2800_register_write(rt2x00dev, TX_PWR_CFG_0_EXT,
4066                               regs[TX_PWR_CFG_0_EXT_IDX]);
4067         rt2800_register_write(rt2x00dev, TX_PWR_CFG_1_EXT,
4068                               regs[TX_PWR_CFG_1_EXT_IDX]);
4069         rt2800_register_write(rt2x00dev, TX_PWR_CFG_2_EXT,
4070                               regs[TX_PWR_CFG_2_EXT_IDX]);
4071         rt2800_register_write(rt2x00dev, TX_PWR_CFG_3_EXT,
4072                               regs[TX_PWR_CFG_3_EXT_IDX]);
4073         rt2800_register_write(rt2x00dev, TX_PWR_CFG_4_EXT,
4074                               regs[TX_PWR_CFG_4_EXT_IDX]);
4075
4076         for (i = 0; i < TX_PWR_CFG_IDX_COUNT; i++)
4077                 rt2x00_dbg(rt2x00dev,
4078                            "band:%cGHz, BW:%c0MHz, TX_PWR_CFG_%d%s = %08lx\n",
4079                            (band == IEEE80211_BAND_5GHZ) ? '5' : '2',
4080                            (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) ?
4081                                                                 '4' : '2',
4082                            (i > TX_PWR_CFG_9_IDX) ?
4083                                         (i - TX_PWR_CFG_9_IDX - 1) : i,
4084                            (i > TX_PWR_CFG_9_IDX) ? "_EXT" : "",
4085                            (unsigned long) regs[i]);
4086 }
4087
4088 /*
4089  * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and
4090  * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values,
4091  * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power
4092  * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm.
4093  * Reference per rate transmit power values are located in the EEPROM at
4094  * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to
4095  * current conditions (i.e. band, bandwidth, temperature, user settings).
4096  */
4097 static void rt2800_config_txpower_rt28xx(struct rt2x00_dev *rt2x00dev,
4098                                          struct ieee80211_channel *chan,
4099                                          int power_level)
4100 {
4101         u8 txpower, r1;
4102         u16 eeprom;
4103         u32 reg, offset;
4104         int i, is_rate_b, delta, power_ctrl;
4105         enum ieee80211_band band = chan->band;
4106
4107         /*
4108          * Calculate HT40 compensation. For 40MHz we need to add or subtract
4109          * value read from EEPROM (different for 2GHz and for 5GHz).
4110          */
4111         delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
4112
4113         /*
4114          * Calculate temperature compensation. Depends on measurement of current
4115          * TSSI (Transmitter Signal Strength Indication) we know TX power (due
4116          * to temperature or maybe other factors) is smaller or bigger than
4117          * expected. We adjust it, based on TSSI reference and boundaries values
4118          * provided in EEPROM.
4119          */
4120         delta += rt2800_get_gain_calibration_delta(rt2x00dev);
4121
4122         /*
4123          * Decrease power according to user settings, on devices with unknown
4124          * maximum tx power. For other devices we take user power_level into
4125          * consideration on rt2800_compensate_txpower().
4126          */
4127         delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level,
4128                                               chan->max_power);
4129
4130         /*
4131          * BBP_R1 controls TX power for all rates, it allow to set the following
4132          * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively.
4133          *
4134          * TODO: we do not use +6 dBm option to do not increase power beyond
4135          * regulatory limit, however this could be utilized for devices with
4136          * CAPABILITY_POWER_LIMIT.
4137          *
4138          * TODO: add different temperature compensation code for RT3290 & RT5390
4139          * to allow to use BBP_R1 for those chips.
4140          */
4141         if (!rt2x00_rt(rt2x00dev, RT3290) &&
4142             !rt2x00_rt(rt2x00dev, RT5390)) {
4143                 rt2800_bbp_read(rt2x00dev, 1, &r1);
4144                 if (delta <= -12) {
4145                         power_ctrl = 2;
4146                         delta += 12;
4147                 } else if (delta <= -6) {
4148                         power_ctrl = 1;
4149                         delta += 6;
4150                 } else {
4151                         power_ctrl = 0;
4152                 }
4153                 rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl);
4154                 rt2800_bbp_write(rt2x00dev, 1, r1);
4155         }
4156
4157         offset = TX_PWR_CFG_0;
4158
4159         for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
4160                 /* just to be safe */
4161                 if (offset > TX_PWR_CFG_4)
4162                         break;
4163
4164                 rt2800_register_read(rt2x00dev, offset, &reg);
4165
4166                 /* read the next four txpower values */
4167                 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4168                                               i, &eeprom);
4169
4170                 is_rate_b = i ? 0 : 1;
4171                 /*
4172                  * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
4173                  * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
4174                  * TX_PWR_CFG_4: unknown
4175                  */
4176                 txpower = rt2x00_get_field16(eeprom,
4177                                              EEPROM_TXPOWER_BYRATE_RATE0);
4178                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4179                                              power_level, txpower, delta);
4180                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
4181
4182                 /*
4183                  * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
4184                  * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
4185                  * TX_PWR_CFG_4: unknown
4186                  */
4187                 txpower = rt2x00_get_field16(eeprom,
4188                                              EEPROM_TXPOWER_BYRATE_RATE1);
4189                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4190                                              power_level, txpower, delta);
4191                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
4192
4193                 /*
4194                  * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
4195                  * TX_PWR_CFG_2: MCS6,  TX_PWR_CFG_3: MCS14,
4196                  * TX_PWR_CFG_4: unknown
4197                  */
4198                 txpower = rt2x00_get_field16(eeprom,
4199                                              EEPROM_TXPOWER_BYRATE_RATE2);
4200                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4201                                              power_level, txpower, delta);
4202                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
4203
4204                 /*
4205                  * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
4206                  * TX_PWR_CFG_2: MCS7,  TX_PWR_CFG_3: MCS15,
4207                  * TX_PWR_CFG_4: unknown
4208                  */
4209                 txpower = rt2x00_get_field16(eeprom,
4210                                              EEPROM_TXPOWER_BYRATE_RATE3);
4211                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4212                                              power_level, txpower, delta);
4213                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
4214
4215                 /* read the next four txpower values */
4216                 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4217                                               i + 1, &eeprom);
4218
4219                 is_rate_b = 0;
4220                 /*
4221                  * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
4222                  * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
4223                  * TX_PWR_CFG_4: unknown
4224                  */
4225                 txpower = rt2x00_get_field16(eeprom,
4226                                              EEPROM_TXPOWER_BYRATE_RATE0);
4227                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4228                                              power_level, txpower, delta);
4229                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
4230
4231                 /*
4232                  * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
4233                  * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
4234                  * TX_PWR_CFG_4: unknown
4235                  */
4236                 txpower = rt2x00_get_field16(eeprom,
4237                                              EEPROM_TXPOWER_BYRATE_RATE1);
4238                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4239                                              power_level, txpower, delta);
4240                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
4241
4242                 /*
4243                  * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
4244                  * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
4245                  * TX_PWR_CFG_4: unknown
4246                  */
4247                 txpower = rt2x00_get_field16(eeprom,
4248                                              EEPROM_TXPOWER_BYRATE_RATE2);
4249                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4250                                              power_level, txpower, delta);
4251                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
4252
4253                 /*
4254                  * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
4255                  * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
4256                  * TX_PWR_CFG_4: unknown
4257                  */
4258                 txpower = rt2x00_get_field16(eeprom,
4259                                              EEPROM_TXPOWER_BYRATE_RATE3);
4260                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4261                                              power_level, txpower, delta);
4262                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
4263
4264                 rt2800_register_write(rt2x00dev, offset, reg);
4265
4266                 /* next TX_PWR_CFG register */
4267                 offset += 4;
4268         }
4269 }
4270
4271 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
4272                                   struct ieee80211_channel *chan,
4273                                   int power_level)
4274 {
4275         if (rt2x00_rt(rt2x00dev, RT3593))
4276                 rt2800_config_txpower_rt3593(rt2x00dev, chan, power_level);
4277         else
4278                 rt2800_config_txpower_rt28xx(rt2x00dev, chan, power_level);
4279 }
4280
4281 void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
4282 {
4283         rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.chandef.chan,
4284                               rt2x00dev->tx_power);
4285 }
4286 EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
4287
4288 void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
4289 {
4290         u32     tx_pin;
4291         u8      rfcsr;
4292
4293         /*
4294          * A voltage-controlled oscillator(VCO) is an electronic oscillator
4295          * designed to be controlled in oscillation frequency by a voltage
4296          * input. Maybe the temperature will affect the frequency of
4297          * oscillation to be shifted. The VCO calibration will be called
4298          * periodically to adjust the frequency to be precision.
4299         */
4300
4301         rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
4302         tx_pin &= TX_PIN_CFG_PA_PE_DISABLE;
4303         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
4304
4305         switch (rt2x00dev->chip.rf) {
4306         case RF2020:
4307         case RF3020:
4308         case RF3021:
4309         case RF3022:
4310         case RF3320:
4311         case RF3052:
4312                 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
4313                 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
4314                 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
4315                 break;
4316         case RF3053:
4317         case RF3070:
4318         case RF3290:
4319         case RF5360:
4320         case RF5370:
4321         case RF5372:
4322         case RF5390:
4323         case RF5392:
4324                 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
4325                 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
4326                 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
4327                 break;
4328         default:
4329                 return;
4330         }
4331
4332         mdelay(1);
4333
4334         rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
4335         if (rt2x00dev->rf_channel <= 14) {
4336                 switch (rt2x00dev->default_ant.tx_chain_num) {
4337                 case 3:
4338                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1);
4339                         /* fall through */
4340                 case 2:
4341                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
4342                         /* fall through */
4343                 case 1:
4344                 default:
4345                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
4346                         break;
4347                 }
4348         } else {
4349                 switch (rt2x00dev->default_ant.tx_chain_num) {
4350                 case 3:
4351                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1);
4352                         /* fall through */
4353                 case 2:
4354                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
4355                         /* fall through */
4356                 case 1:
4357                 default:
4358                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
4359                         break;
4360                 }
4361         }
4362         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
4363
4364 }
4365 EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
4366
4367 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
4368                                       struct rt2x00lib_conf *libconf)
4369 {
4370         u32 reg;
4371
4372         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
4373         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
4374                            libconf->conf->short_frame_max_tx_count);
4375         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
4376                            libconf->conf->long_frame_max_tx_count);
4377         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
4378 }
4379
4380 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
4381                              struct rt2x00lib_conf *libconf)
4382 {
4383         enum dev_state state =
4384             (libconf->conf->flags & IEEE80211_CONF_PS) ?
4385                 STATE_SLEEP : STATE_AWAKE;
4386         u32 reg;
4387
4388         if (state == STATE_SLEEP) {
4389                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
4390
4391                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
4392                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
4393                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
4394                                    libconf->conf->listen_interval - 1);
4395                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
4396                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
4397
4398                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
4399         } else {
4400                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
4401                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
4402                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
4403                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
4404                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
4405
4406                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
4407         }
4408 }
4409
4410 void rt2800_config(struct rt2x00_dev *rt2x00dev,
4411                    struct rt2x00lib_conf *libconf,
4412                    const unsigned int flags)
4413 {
4414         /* Always recalculate LNA gain before changing configuration */
4415         rt2800_config_lna_gain(rt2x00dev, libconf);
4416
4417         if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
4418                 rt2800_config_channel(rt2x00dev, libconf->conf,
4419                                       &libconf->rf, &libconf->channel);
4420                 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
4421                                       libconf->conf->power_level);
4422         }
4423         if (flags & IEEE80211_CONF_CHANGE_POWER)
4424                 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
4425                                       libconf->conf->power_level);
4426         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
4427                 rt2800_config_retry_limit(rt2x00dev, libconf);
4428         if (flags & IEEE80211_CONF_CHANGE_PS)
4429                 rt2800_config_ps(rt2x00dev, libconf);
4430 }
4431 EXPORT_SYMBOL_GPL(rt2800_config);
4432
4433 /*
4434  * Link tuning
4435  */
4436 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
4437 {
4438         u32 reg;
4439
4440         /*
4441          * Update FCS error count from register.
4442          */
4443         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
4444         qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
4445 }
4446 EXPORT_SYMBOL_GPL(rt2800_link_stats);
4447
4448 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
4449 {
4450         u8 vgc;
4451
4452         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
4453                 if (rt2x00_rt(rt2x00dev, RT3070) ||
4454                     rt2x00_rt(rt2x00dev, RT3071) ||
4455                     rt2x00_rt(rt2x00dev, RT3090) ||
4456                     rt2x00_rt(rt2x00dev, RT3290) ||
4457                     rt2x00_rt(rt2x00dev, RT3390) ||
4458                     rt2x00_rt(rt2x00dev, RT3572) ||
4459                     rt2x00_rt(rt2x00dev, RT3593) ||
4460                     rt2x00_rt(rt2x00dev, RT5390) ||
4461                     rt2x00_rt(rt2x00dev, RT5392) ||
4462                     rt2x00_rt(rt2x00dev, RT5592))
4463                         vgc = 0x1c + (2 * rt2x00dev->lna_gain);
4464                 else
4465                         vgc = 0x2e + rt2x00dev->lna_gain;
4466         } else { /* 5GHZ band */
4467                 if (rt2x00_rt(rt2x00dev, RT3593))
4468                         vgc = 0x20 + (rt2x00dev->lna_gain * 5) / 3;
4469                 else if (rt2x00_rt(rt2x00dev, RT5592))
4470                         vgc = 0x24 + (2 * rt2x00dev->lna_gain);
4471                 else {
4472                         if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
4473                                 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
4474                         else
4475                                 vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
4476                 }
4477         }
4478
4479         return vgc;
4480 }
4481
4482 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
4483                                   struct link_qual *qual, u8 vgc_level)
4484 {
4485         if (qual->vgc_level != vgc_level) {
4486                 if (rt2x00_rt(rt2x00dev, RT3572) ||
4487                     rt2x00_rt(rt2x00dev, RT3593)) {
4488                         rt2800_bbp_write_with_rx_chain(rt2x00dev, 66,
4489                                                        vgc_level);
4490                 } else if (rt2x00_rt(rt2x00dev, RT5592)) {
4491                         rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a);
4492                         rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, vgc_level);
4493                 } else {
4494                         rt2800_bbp_write(rt2x00dev, 66, vgc_level);
4495                 }
4496
4497                 qual->vgc_level = vgc_level;
4498                 qual->vgc_level_reg = vgc_level;
4499         }
4500 }
4501
4502 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
4503 {
4504         rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
4505 }
4506 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
4507
4508 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
4509                        const u32 count)
4510 {
4511         u8 vgc;
4512
4513         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
4514                 return;
4515
4516         /* When RSSI is better than a certain threshold, increase VGC
4517          * with a chip specific value in order to improve the balance
4518          * between sensibility and noise isolation.
4519          */
4520
4521         vgc = rt2800_get_default_vgc(rt2x00dev);
4522
4523         switch (rt2x00dev->chip.rt) {
4524         case RT3572:
4525         case RT3593:
4526                 if (qual->rssi > -65) {
4527                         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ)
4528                                 vgc += 0x20;
4529                         else
4530                                 vgc += 0x10;
4531                 }
4532                 break;
4533
4534         case RT5592:
4535                 if (qual->rssi > -65)
4536                         vgc += 0x20;
4537                 break;
4538
4539         default:
4540                 if (qual->rssi > -80)
4541                         vgc += 0x10;
4542                 break;
4543         }
4544
4545         rt2800_set_vgc(rt2x00dev, qual, vgc);
4546 }
4547 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
4548
4549 /*
4550  * Initialization functions.
4551  */
4552 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
4553 {
4554         u32 reg;
4555         u16 eeprom;
4556         unsigned int i;
4557         int ret;
4558
4559         rt2800_disable_wpdma(rt2x00dev);
4560
4561         ret = rt2800_drv_init_registers(rt2x00dev);
4562         if (ret)
4563                 return ret;
4564
4565         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
4566         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
4567
4568         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
4569
4570         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
4571         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
4572         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
4573         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
4574         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
4575         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
4576         rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
4577         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
4578
4579         rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
4580
4581         rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
4582         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
4583         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
4584         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
4585
4586         if (rt2x00_rt(rt2x00dev, RT3290)) {
4587                 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
4588                 if (rt2x00_get_field32(reg, WLAN_EN) == 1) {
4589                         rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 1);
4590                         rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
4591                 }
4592
4593                 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
4594                 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) {
4595                         rt2x00_set_field32(&reg, LDO0_EN, 1);
4596                         rt2x00_set_field32(&reg, LDO_BGSEL, 3);
4597                         rt2800_register_write(rt2x00dev, CMB_CTRL, reg);
4598                 }
4599
4600                 rt2800_register_read(rt2x00dev, OSC_CTRL, &reg);
4601                 rt2x00_set_field32(&reg, OSC_ROSC_EN, 1);
4602                 rt2x00_set_field32(&reg, OSC_CAL_REQ, 1);
4603                 rt2x00_set_field32(&reg, OSC_REF_CYCLE, 0x27);
4604                 rt2800_register_write(rt2x00dev, OSC_CTRL, reg);
4605
4606                 rt2800_register_read(rt2x00dev, COEX_CFG0, &reg);
4607                 rt2x00_set_field32(&reg, COEX_CFG_ANT, 0x5e);
4608                 rt2800_register_write(rt2x00dev, COEX_CFG0, reg);
4609
4610                 rt2800_register_read(rt2x00dev, COEX_CFG2, &reg);
4611                 rt2x00_set_field32(&reg, BT_COEX_CFG1, 0x00);
4612                 rt2x00_set_field32(&reg, BT_COEX_CFG0, 0x17);
4613                 rt2x00_set_field32(&reg, WL_COEX_CFG1, 0x93);
4614                 rt2x00_set_field32(&reg, WL_COEX_CFG0, 0x7f);
4615                 rt2800_register_write(rt2x00dev, COEX_CFG2, reg);
4616
4617                 rt2800_register_read(rt2x00dev, PLL_CTRL, &reg);
4618                 rt2x00_set_field32(&reg, PLL_CONTROL, 1);
4619                 rt2800_register_write(rt2x00dev, PLL_CTRL, reg);
4620         }
4621
4622         if (rt2x00_rt(rt2x00dev, RT3071) ||
4623             rt2x00_rt(rt2x00dev, RT3090) ||
4624             rt2x00_rt(rt2x00dev, RT3290) ||
4625             rt2x00_rt(rt2x00dev, RT3390)) {
4626
4627                 if (rt2x00_rt(rt2x00dev, RT3290))
4628                         rt2800_register_write(rt2x00dev, TX_SW_CFG0,
4629                                               0x00000404);
4630                 else
4631                         rt2800_register_write(rt2x00dev, TX_SW_CFG0,
4632                                               0x00000400);
4633
4634                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4635                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4636                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
4637                     rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
4638                         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
4639                                            &eeprom);
4640                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
4641                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4642                                                       0x0000002c);
4643                         else
4644                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4645                                                       0x0000000f);
4646                 } else {
4647                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
4648                 }
4649         } else if (rt2x00_rt(rt2x00dev, RT3070)) {
4650                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
4651
4652                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
4653                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4654                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
4655                 } else {
4656                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4657                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
4658                 }
4659         } else if (rt2800_is_305x_soc(rt2x00dev)) {
4660                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
4661                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4662                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
4663         } else if (rt2x00_rt(rt2x00dev, RT3352)) {
4664                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
4665                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4666                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
4667         } else if (rt2x00_rt(rt2x00dev, RT3572)) {
4668                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
4669                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4670         } else if (rt2x00_rt(rt2x00dev, RT3593)) {
4671                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
4672                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4673                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3593, REV_RT3593E)) {
4674                         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
4675                                            &eeprom);
4676                         if (rt2x00_get_field16(eeprom,
4677                                                EEPROM_NIC_CONF1_DAC_TEST))
4678                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4679                                                       0x0000001f);
4680                         else
4681                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4682                                                       0x0000000f);
4683                 } else {
4684                         rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4685                                               0x00000000);
4686                 }
4687         } else if (rt2x00_rt(rt2x00dev, RT5390) ||
4688                    rt2x00_rt(rt2x00dev, RT5392) ||
4689                    rt2x00_rt(rt2x00dev, RT5592)) {
4690                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
4691                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4692                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
4693         } else {
4694                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
4695                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4696         }
4697
4698         rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
4699         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
4700         rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
4701         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
4702         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
4703         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
4704         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
4705         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
4706         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
4707         rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
4708
4709         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
4710         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
4711         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
4712         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
4713         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
4714
4715         rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
4716         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
4717         if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
4718             rt2x00_rt(rt2x00dev, RT2883) ||
4719             rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
4720                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
4721         else
4722                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
4723         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
4724         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
4725         rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
4726
4727         rt2800_register_read(rt2x00dev, LED_CFG, &reg);
4728         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
4729         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
4730         rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
4731         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
4732         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
4733         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
4734         rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
4735         rt2800_register_write(rt2x00dev, LED_CFG, reg);
4736
4737         rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
4738
4739         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
4740         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
4741         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
4742         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
4743         rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
4744         rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
4745         rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
4746         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
4747
4748         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
4749         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
4750         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
4751         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
4752         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
4753         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
4754         rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
4755         rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
4756         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
4757
4758         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
4759         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
4760         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
4761         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
4762         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4763         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4764         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4765         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
4766         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4767         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
4768         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
4769         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
4770
4771         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
4772         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
4773         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
4774         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
4775         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4776         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4777         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4778         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
4779         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4780         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
4781         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
4782         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
4783
4784         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
4785         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
4786         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
4787         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
4788         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4789         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4790         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4791         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
4792         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4793         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
4794         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
4795         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
4796
4797         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
4798         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
4799         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
4800         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
4801         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4802         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4803         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4804         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
4805         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4806         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
4807         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
4808         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
4809
4810         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
4811         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
4812         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
4813         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
4814         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4815         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4816         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4817         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
4818         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4819         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
4820         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
4821         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
4822
4823         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
4824         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
4825         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
4826         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
4827         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4828         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4829         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4830         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
4831         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4832         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
4833         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
4834         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
4835
4836         if (rt2x00_is_usb(rt2x00dev)) {
4837                 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
4838
4839                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
4840                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
4841                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
4842                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
4843                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
4844                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
4845                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
4846                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
4847                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
4848                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
4849                 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
4850         }
4851
4852         /*
4853          * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
4854          * although it is reserved.
4855          */
4856         rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
4857         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
4858         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
4859         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
4860         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
4861         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
4862         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
4863         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
4864         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
4865         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
4866         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
4867         rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
4868
4869         reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002;
4870         rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg);
4871
4872         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
4873         rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
4874         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
4875                            IEEE80211_MAX_RTS_THRESHOLD);
4876         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
4877         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
4878
4879         rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
4880
4881         /*
4882          * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
4883          * time should be set to 16. However, the original Ralink driver uses
4884          * 16 for both and indeed using a value of 10 for CCK SIFS results in
4885          * connection problems with 11g + CTS protection. Hence, use the same
4886          * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
4887          */
4888         rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
4889         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
4890         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
4891         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
4892         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
4893         rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
4894         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
4895
4896         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
4897
4898         /*
4899          * ASIC will keep garbage value after boot, clear encryption keys.
4900          */
4901         for (i = 0; i < 4; i++)
4902                 rt2800_register_write(rt2x00dev,
4903                                          SHARED_KEY_MODE_ENTRY(i), 0);
4904
4905         for (i = 0; i < 256; i++) {
4906                 rt2800_config_wcid(rt2x00dev, NULL, i);
4907                 rt2800_delete_wcid_attr(rt2x00dev, i);
4908                 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
4909         }
4910
4911         /*
4912          * Clear all beacons
4913          */
4914         for (i = 0; i < 8; i++)
4915                 rt2800_clear_beacon_register(rt2x00dev, i);
4916
4917         if (rt2x00_is_usb(rt2x00dev)) {
4918                 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
4919                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
4920                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
4921         } else if (rt2x00_is_pcie(rt2x00dev)) {
4922                 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
4923                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
4924                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
4925         }
4926
4927         rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
4928         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
4929         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
4930         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
4931         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
4932         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
4933         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
4934         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
4935         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
4936         rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
4937
4938         rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
4939         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
4940         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
4941         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
4942         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
4943         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
4944         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
4945         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
4946         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
4947         rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
4948
4949         rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
4950         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
4951         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
4952         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
4953         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
4954         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
4955         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
4956         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
4957         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
4958         rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
4959
4960         rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
4961         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
4962         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
4963         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
4964         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
4965         rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
4966
4967         /*
4968          * Do not force the BA window size, we use the TXWI to set it
4969          */
4970         rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
4971         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
4972         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
4973         rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
4974
4975         /*
4976          * We must clear the error counters.
4977          * These registers are cleared on read,
4978          * so we may pass a useless variable to store the value.
4979          */
4980         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
4981         rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
4982         rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
4983         rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
4984         rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
4985         rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
4986
4987         /*
4988          * Setup leadtime for pre tbtt interrupt to 6ms
4989          */
4990         rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
4991         rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
4992         rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
4993
4994         /*
4995          * Set up channel statistics timer
4996          */
4997         rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
4998         rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
4999         rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
5000         rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
5001         rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
5002         rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
5003         rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
5004
5005         return 0;
5006 }
5007
5008 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
5009 {
5010         unsigned int i;
5011         u32 reg;
5012
5013         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
5014                 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
5015                 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
5016                         return 0;
5017
5018                 udelay(REGISTER_BUSY_DELAY);
5019         }
5020
5021         rt2x00_err(rt2x00dev, "BBP/RF register access failed, aborting\n");
5022         return -EACCES;
5023 }
5024
5025 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
5026 {
5027         unsigned int i;
5028         u8 value;
5029
5030         /*
5031          * BBP was enabled after firmware was loaded,
5032          * but we need to reactivate it now.
5033          */
5034         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
5035         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
5036         msleep(1);
5037
5038         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
5039                 rt2800_bbp_read(rt2x00dev, 0, &value);
5040                 if ((value != 0xff) && (value != 0x00))
5041                         return 0;
5042                 udelay(REGISTER_BUSY_DELAY);
5043         }
5044
5045         rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
5046         return -EACCES;
5047 }
5048
5049 static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev)
5050 {
5051         u8 value;
5052
5053         rt2800_bbp_read(rt2x00dev, 4, &value);
5054         rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
5055         rt2800_bbp_write(rt2x00dev, 4, value);
5056 }
5057
5058 static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev)
5059 {
5060         rt2800_bbp_write(rt2x00dev, 142, 1);
5061         rt2800_bbp_write(rt2x00dev, 143, 57);
5062 }
5063
5064 static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev)
5065 {
5066         const u8 glrt_table[] = {
5067                 0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */
5068                 0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */
5069                 0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */
5070                 0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */
5071                 0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */
5072                 0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */
5073                 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */
5074                 0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */
5075                 0x2E, 0x36, 0x30, 0x6E,                                     /* 208 ~ 211 */
5076         };
5077         int i;
5078
5079         for (i = 0; i < ARRAY_SIZE(glrt_table); i++) {
5080                 rt2800_bbp_write(rt2x00dev, 195, 128 + i);
5081                 rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]);
5082         }
5083 };
5084
5085 static void rt2800_init_bbp_early(struct rt2x00_dev *rt2x00dev)
5086 {
5087         rt2800_bbp_write(rt2x00dev, 65, 0x2C);
5088         rt2800_bbp_write(rt2x00dev, 66, 0x38);
5089         rt2800_bbp_write(rt2x00dev, 68, 0x0B);
5090         rt2800_bbp_write(rt2x00dev, 69, 0x12);
5091         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5092         rt2800_bbp_write(rt2x00dev, 73, 0x10);
5093         rt2800_bbp_write(rt2x00dev, 81, 0x37);
5094         rt2800_bbp_write(rt2x00dev, 82, 0x62);
5095         rt2800_bbp_write(rt2x00dev, 83, 0x6A);
5096         rt2800_bbp_write(rt2x00dev, 84, 0x99);
5097         rt2800_bbp_write(rt2x00dev, 86, 0x00);
5098         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5099         rt2800_bbp_write(rt2x00dev, 92, 0x00);
5100         rt2800_bbp_write(rt2x00dev, 103, 0x00);
5101         rt2800_bbp_write(rt2x00dev, 105, 0x05);
5102         rt2800_bbp_write(rt2x00dev, 106, 0x35);
5103 }
5104
5105 static void rt2800_disable_unused_dac_adc(struct rt2x00_dev *rt2x00dev)
5106 {
5107         u16 eeprom;
5108         u8 value;
5109
5110         rt2800_bbp_read(rt2x00dev, 138, &value);
5111         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5112         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5113                 value |= 0x20;
5114         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5115                 value &= ~0x02;
5116         rt2800_bbp_write(rt2x00dev, 138, value);
5117 }
5118
5119 static void rt2800_init_bbp_305x_soc(struct rt2x00_dev *rt2x00dev)
5120 {
5121         rt2800_bbp_write(rt2x00dev, 31, 0x08);
5122
5123         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5124         rt2800_bbp_write(rt2x00dev, 66, 0x38);
5125
5126         rt2800_bbp_write(rt2x00dev, 69, 0x12);
5127         rt2800_bbp_write(rt2x00dev, 73, 0x10);
5128
5129         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5130
5131         rt2800_bbp_write(rt2x00dev, 78, 0x0e);
5132         rt2800_bbp_write(rt2x00dev, 80, 0x08);
5133
5134         rt2800_bbp_write(rt2x00dev, 82, 0x62);
5135
5136         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5137
5138         rt2800_bbp_write(rt2x00dev, 84, 0x99);
5139
5140         rt2800_bbp_write(rt2x00dev, 86, 0x00);
5141
5142         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5143
5144         rt2800_bbp_write(rt2x00dev, 92, 0x00);
5145
5146         rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5147
5148         rt2800_bbp_write(rt2x00dev, 105, 0x01);
5149
5150         rt2800_bbp_write(rt2x00dev, 106, 0x35);
5151 }
5152
5153 static void rt2800_init_bbp_28xx(struct rt2x00_dev *rt2x00dev)
5154 {
5155         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5156         rt2800_bbp_write(rt2x00dev, 66, 0x38);
5157
5158         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
5159                 rt2800_bbp_write(rt2x00dev, 69, 0x16);
5160                 rt2800_bbp_write(rt2x00dev, 73, 0x12);
5161         } else {
5162                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5163                 rt2800_bbp_write(rt2x00dev, 73, 0x10);
5164         }
5165
5166         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5167
5168         rt2800_bbp_write(rt2x00dev, 81, 0x37);
5169
5170         rt2800_bbp_write(rt2x00dev, 82, 0x62);
5171
5172         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5173
5174         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
5175                 rt2800_bbp_write(rt2x00dev, 84, 0x19);
5176         else
5177                 rt2800_bbp_write(rt2x00dev, 84, 0x99);
5178
5179         rt2800_bbp_write(rt2x00dev, 86, 0x00);
5180
5181         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5182
5183         rt2800_bbp_write(rt2x00dev, 92, 0x00);
5184
5185         rt2800_bbp_write(rt2x00dev, 103, 0x00);
5186
5187         rt2800_bbp_write(rt2x00dev, 105, 0x05);
5188
5189         rt2800_bbp_write(rt2x00dev, 106, 0x35);
5190 }
5191
5192 static void rt2800_init_bbp_30xx(struct rt2x00_dev *rt2x00dev)
5193 {
5194         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5195         rt2800_bbp_write(rt2x00dev, 66, 0x38);
5196
5197         rt2800_bbp_write(rt2x00dev, 69, 0x12);
5198         rt2800_bbp_write(rt2x00dev, 73, 0x10);
5199
5200         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5201
5202         rt2800_bbp_write(rt2x00dev, 79, 0x13);
5203         rt2800_bbp_write(rt2x00dev, 80, 0x05);
5204         rt2800_bbp_write(rt2x00dev, 81, 0x33);
5205
5206         rt2800_bbp_write(rt2x00dev, 82, 0x62);
5207
5208         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5209
5210         rt2800_bbp_write(rt2x00dev, 84, 0x99);
5211
5212         rt2800_bbp_write(rt2x00dev, 86, 0x00);
5213
5214         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5215
5216         rt2800_bbp_write(rt2x00dev, 92, 0x00);
5217
5218         if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
5219             rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
5220             rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E))
5221                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5222         else
5223                 rt2800_bbp_write(rt2x00dev, 103, 0x00);
5224
5225         rt2800_bbp_write(rt2x00dev, 105, 0x05);
5226
5227         rt2800_bbp_write(rt2x00dev, 106, 0x35);
5228
5229         if (rt2x00_rt(rt2x00dev, RT3071) ||
5230             rt2x00_rt(rt2x00dev, RT3090))
5231                 rt2800_disable_unused_dac_adc(rt2x00dev);
5232 }
5233
5234 static void rt2800_init_bbp_3290(struct rt2x00_dev *rt2x00dev)
5235 {
5236         u8 value;
5237
5238         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5239
5240         rt2800_bbp_write(rt2x00dev, 31, 0x08);
5241
5242         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5243         rt2800_bbp_write(rt2x00dev, 66, 0x38);
5244
5245         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
5246
5247         rt2800_bbp_write(rt2x00dev, 69, 0x12);
5248         rt2800_bbp_write(rt2x00dev, 73, 0x13);
5249         rt2800_bbp_write(rt2x00dev, 75, 0x46);
5250         rt2800_bbp_write(rt2x00dev, 76, 0x28);
5251
5252         rt2800_bbp_write(rt2x00dev, 77, 0x58);
5253
5254         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5255
5256         rt2800_bbp_write(rt2x00dev, 74, 0x0b);
5257         rt2800_bbp_write(rt2x00dev, 79, 0x18);
5258         rt2800_bbp_write(rt2x00dev, 80, 0x09);
5259         rt2800_bbp_write(rt2x00dev, 81, 0x33);
5260
5261         rt2800_bbp_write(rt2x00dev, 82, 0x62);
5262
5263         rt2800_bbp_write(rt2x00dev, 83, 0x7a);
5264
5265         rt2800_bbp_write(rt2x00dev, 84, 0x9a);
5266
5267         rt2800_bbp_write(rt2x00dev, 86, 0x38);
5268
5269         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5270
5271         rt2800_bbp_write(rt2x00dev, 92, 0x02);
5272
5273         rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5274
5275         rt2800_bbp_write(rt2x00dev, 104, 0x92);
5276
5277         rt2800_bbp_write(rt2x00dev, 105, 0x1c);
5278
5279         rt2800_bbp_write(rt2x00dev, 106, 0x03);
5280
5281         rt2800_bbp_write(rt2x00dev, 128, 0x12);
5282
5283         rt2800_bbp_write(rt2x00dev, 67, 0x24);
5284         rt2800_bbp_write(rt2x00dev, 143, 0x04);
5285         rt2800_bbp_write(rt2x00dev, 142, 0x99);
5286         rt2800_bbp_write(rt2x00dev, 150, 0x30);
5287         rt2800_bbp_write(rt2x00dev, 151, 0x2e);
5288         rt2800_bbp_write(rt2x00dev, 152, 0x20);
5289         rt2800_bbp_write(rt2x00dev, 153, 0x34);
5290         rt2800_bbp_write(rt2x00dev, 154, 0x40);
5291         rt2800_bbp_write(rt2x00dev, 155, 0x3b);
5292         rt2800_bbp_write(rt2x00dev, 253, 0x04);
5293
5294         rt2800_bbp_read(rt2x00dev, 47, &value);
5295         rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1);
5296         rt2800_bbp_write(rt2x00dev, 47, value);
5297
5298         /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */
5299         rt2800_bbp_read(rt2x00dev, 3, &value);
5300         rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1);
5301         rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1);
5302         rt2800_bbp_write(rt2x00dev, 3, value);
5303 }
5304
5305 static void rt2800_init_bbp_3352(struct rt2x00_dev *rt2x00dev)
5306 {
5307         rt2800_bbp_write(rt2x00dev, 3, 0x00);
5308         rt2800_bbp_write(rt2x00dev, 4, 0x50);
5309
5310         rt2800_bbp_write(rt2x00dev, 31, 0x08);
5311
5312         rt2800_bbp_write(rt2x00dev, 47, 0x48);
5313
5314         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5315         rt2800_bbp_write(rt2x00dev, 66, 0x38);
5316
5317         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
5318
5319         rt2800_bbp_write(rt2x00dev, 69, 0x12);
5320         rt2800_bbp_write(rt2x00dev, 73, 0x13);
5321         rt2800_bbp_write(rt2x00dev, 75, 0x46);
5322         rt2800_bbp_write(rt2x00dev, 76, 0x28);
5323
5324         rt2800_bbp_write(rt2x00dev, 77, 0x59);
5325
5326         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5327
5328         rt2800_bbp_write(rt2x00dev, 78, 0x0e);
5329         rt2800_bbp_write(rt2x00dev, 80, 0x08);
5330         rt2800_bbp_write(rt2x00dev, 81, 0x37);
5331
5332         rt2800_bbp_write(rt2x00dev, 82, 0x62);
5333
5334         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5335
5336         rt2800_bbp_write(rt2x00dev, 84, 0x99);
5337
5338         rt2800_bbp_write(rt2x00dev, 86, 0x38);
5339
5340         rt2800_bbp_write(rt2x00dev, 88, 0x90);
5341
5342         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5343
5344         rt2800_bbp_write(rt2x00dev, 92, 0x02);
5345
5346         rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5347
5348         rt2800_bbp_write(rt2x00dev, 104, 0x92);
5349
5350         rt2800_bbp_write(rt2x00dev, 105, 0x34);
5351
5352         rt2800_bbp_write(rt2x00dev, 106, 0x05);
5353
5354         rt2800_bbp_write(rt2x00dev, 120, 0x50);
5355
5356         rt2800_bbp_write(rt2x00dev, 137, 0x0f);
5357
5358         rt2800_bbp_write(rt2x00dev, 163, 0xbd);
5359         /* Set ITxBF timeout to 0x9c40=1000msec */
5360         rt2800_bbp_write(rt2x00dev, 179, 0x02);
5361         rt2800_bbp_write(rt2x00dev, 180, 0x00);
5362         rt2800_bbp_write(rt2x00dev, 182, 0x40);
5363         rt2800_bbp_write(rt2x00dev, 180, 0x01);
5364         rt2800_bbp_write(rt2x00dev, 182, 0x9c);
5365         rt2800_bbp_write(rt2x00dev, 179, 0x00);
5366         /* Reprogram the inband interface to put right values in RXWI */
5367         rt2800_bbp_write(rt2x00dev, 142, 0x04);
5368         rt2800_bbp_write(rt2x00dev, 143, 0x3b);
5369         rt2800_bbp_write(rt2x00dev, 142, 0x06);
5370         rt2800_bbp_write(rt2x00dev, 143, 0xa0);
5371         rt2800_bbp_write(rt2x00dev, 142, 0x07);
5372         rt2800_bbp_write(rt2x00dev, 143, 0xa1);
5373         rt2800_bbp_write(rt2x00dev, 142, 0x08);
5374         rt2800_bbp_write(rt2x00dev, 143, 0xa2);
5375
5376         rt2800_bbp_write(rt2x00dev, 148, 0xc8);
5377 }
5378
5379 static void rt2800_init_bbp_3390(struct rt2x00_dev *rt2x00dev)
5380 {
5381         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5382         rt2800_bbp_write(rt2x00dev, 66, 0x38);
5383
5384         rt2800_bbp_write(rt2x00dev, 69, 0x12);
5385         rt2800_bbp_write(rt2x00dev, 73, 0x10);
5386
5387         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5388
5389         rt2800_bbp_write(rt2x00dev, 79, 0x13);
5390         rt2800_bbp_write(rt2x00dev, 80, 0x05);
5391         rt2800_bbp_write(rt2x00dev, 81, 0x33);
5392
5393         rt2800_bbp_write(rt2x00dev, 82, 0x62);
5394
5395         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5396
5397         rt2800_bbp_write(rt2x00dev, 84, 0x99);
5398
5399         rt2800_bbp_write(rt2x00dev, 86, 0x00);
5400
5401         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5402
5403         rt2800_bbp_write(rt2x00dev, 92, 0x00);
5404
5405         if (rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E))
5406                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5407         else
5408                 rt2800_bbp_write(rt2x00dev, 103, 0x00);
5409
5410         rt2800_bbp_write(rt2x00dev, 105, 0x05);
5411
5412         rt2800_bbp_write(rt2x00dev, 106, 0x35);
5413
5414         rt2800_disable_unused_dac_adc(rt2x00dev);
5415 }
5416
5417 static void rt2800_init_bbp_3572(struct rt2x00_dev *rt2x00dev)
5418 {
5419         rt2800_bbp_write(rt2x00dev, 31, 0x08);
5420
5421         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5422         rt2800_bbp_write(rt2x00dev, 66, 0x38);
5423
5424         rt2800_bbp_write(rt2x00dev, 69, 0x12);
5425         rt2800_bbp_write(rt2x00dev, 73, 0x10);
5426
5427         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5428
5429         rt2800_bbp_write(rt2x00dev, 79, 0x13);
5430         rt2800_bbp_write(rt2x00dev, 80, 0x05);
5431         rt2800_bbp_write(rt2x00dev, 81, 0x33);
5432
5433         rt2800_bbp_write(rt2x00dev, 82, 0x62);
5434
5435         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5436
5437         rt2800_bbp_write(rt2x00dev, 84, 0x99);
5438
5439         rt2800_bbp_write(rt2x00dev, 86, 0x00);
5440
5441         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5442
5443         rt2800_bbp_write(rt2x00dev, 92, 0x00);
5444
5445         rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5446
5447         rt2800_bbp_write(rt2x00dev, 105, 0x05);
5448
5449         rt2800_bbp_write(rt2x00dev, 106, 0x35);
5450
5451         rt2800_disable_unused_dac_adc(rt2x00dev);
5452 }
5453
5454 static void rt2800_init_bbp_3593(struct rt2x00_dev *rt2x00dev)
5455 {
5456         rt2800_init_bbp_early(rt2x00dev);
5457
5458         rt2800_bbp_write(rt2x00dev, 79, 0x13);
5459         rt2800_bbp_write(rt2x00dev, 80, 0x05);
5460         rt2800_bbp_write(rt2x00dev, 81, 0x33);
5461         rt2800_bbp_write(rt2x00dev, 137, 0x0f);
5462
5463         rt2800_bbp_write(rt2x00dev, 84, 0x19);
5464
5465         /* Enable DC filter */
5466         if (rt2x00_rt_rev_gte(rt2x00dev, RT3593, REV_RT3593E))
5467                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5468 }
5469
5470 static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev)
5471 {
5472         int ant, div_mode;
5473         u16 eeprom;
5474         u8 value;
5475
5476         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5477
5478         rt2800_bbp_write(rt2x00dev, 31, 0x08);
5479
5480         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5481         rt2800_bbp_write(rt2x00dev, 66, 0x38);
5482
5483         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
5484
5485         rt2800_bbp_write(rt2x00dev, 69, 0x12);
5486         rt2800_bbp_write(rt2x00dev, 73, 0x13);
5487         rt2800_bbp_write(rt2x00dev, 75, 0x46);
5488         rt2800_bbp_write(rt2x00dev, 76, 0x28);
5489
5490         rt2800_bbp_write(rt2x00dev, 77, 0x59);
5491
5492         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5493
5494         rt2800_bbp_write(rt2x00dev, 79, 0x13);
5495         rt2800_bbp_write(rt2x00dev, 80, 0x05);
5496         rt2800_bbp_write(rt2x00dev, 81, 0x33);
5497
5498         rt2800_bbp_write(rt2x00dev, 82, 0x62);
5499
5500         rt2800_bbp_write(rt2x00dev, 83, 0x7a);
5501
5502         rt2800_bbp_write(rt2x00dev, 84, 0x9a);
5503
5504         rt2800_bbp_write(rt2x00dev, 86, 0x38);
5505
5506         if (rt2x00_rt(rt2x00dev, RT5392))
5507                 rt2800_bbp_write(rt2x00dev, 88, 0x90);
5508
5509         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5510
5511         rt2800_bbp_write(rt2x00dev, 92, 0x02);
5512
5513         if (rt2x00_rt(rt2x00dev, RT5392)) {
5514                 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
5515                 rt2800_bbp_write(rt2x00dev, 98, 0x12);
5516         }
5517
5518         rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5519
5520         rt2800_bbp_write(rt2x00dev, 104, 0x92);
5521
5522         rt2800_bbp_write(rt2x00dev, 105, 0x3c);
5523
5524         if (rt2x00_rt(rt2x00dev, RT5390))
5525                 rt2800_bbp_write(rt2x00dev, 106, 0x03);
5526         else if (rt2x00_rt(rt2x00dev, RT5392))
5527                 rt2800_bbp_write(rt2x00dev, 106, 0x12);
5528         else
5529                 WARN_ON(1);
5530
5531         rt2800_bbp_write(rt2x00dev, 128, 0x12);
5532
5533         if (rt2x00_rt(rt2x00dev, RT5392)) {
5534                 rt2800_bbp_write(rt2x00dev, 134, 0xd0);
5535                 rt2800_bbp_write(rt2x00dev, 135, 0xf6);
5536         }
5537
5538         rt2800_disable_unused_dac_adc(rt2x00dev);
5539
5540         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
5541         div_mode = rt2x00_get_field16(eeprom,
5542                                       EEPROM_NIC_CONF1_ANT_DIVERSITY);
5543         ant = (div_mode == 3) ? 1 : 0;
5544
5545         /* check if this is a Bluetooth combo card */
5546         if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
5547                 u32 reg;
5548
5549                 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
5550                 rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
5551                 rt2x00_set_field32(&reg, GPIO_CTRL_DIR6, 0);
5552                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 0);
5553                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 0);
5554                 if (ant == 0)
5555                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 1);
5556                 else if (ant == 1)
5557                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 1);
5558                 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
5559         }
5560
5561         /* This chip has hardware antenna diversity*/
5562         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
5563                 rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */
5564                 rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */
5565                 rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */
5566         }
5567
5568         rt2800_bbp_read(rt2x00dev, 152, &value);
5569         if (ant == 0)
5570                 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
5571         else
5572                 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
5573         rt2800_bbp_write(rt2x00dev, 152, value);
5574
5575         rt2800_init_freq_calibration(rt2x00dev);
5576 }
5577
5578 static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev)
5579 {
5580         int ant, div_mode;
5581         u16 eeprom;
5582         u8 value;
5583
5584         rt2800_init_bbp_early(rt2x00dev);
5585
5586         rt2800_bbp_read(rt2x00dev, 105, &value);
5587         rt2x00_set_field8(&value, BBP105_MLD,
5588                           rt2x00dev->default_ant.rx_chain_num == 2);
5589         rt2800_bbp_write(rt2x00dev, 105, value);
5590
5591         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5592
5593         rt2800_bbp_write(rt2x00dev, 20, 0x06);
5594         rt2800_bbp_write(rt2x00dev, 31, 0x08);
5595         rt2800_bbp_write(rt2x00dev, 65, 0x2C);
5596         rt2800_bbp_write(rt2x00dev, 68, 0xDD);
5597         rt2800_bbp_write(rt2x00dev, 69, 0x1A);
5598         rt2800_bbp_write(rt2x00dev, 70, 0x05);
5599         rt2800_bbp_write(rt2x00dev, 73, 0x13);
5600         rt2800_bbp_write(rt2x00dev, 74, 0x0F);
5601         rt2800_bbp_write(rt2x00dev, 75, 0x4F);
5602         rt2800_bbp_write(rt2x00dev, 76, 0x28);
5603         rt2800_bbp_write(rt2x00dev, 77, 0x59);
5604         rt2800_bbp_write(rt2x00dev, 84, 0x9A);
5605         rt2800_bbp_write(rt2x00dev, 86, 0x38);
5606         rt2800_bbp_write(rt2x00dev, 88, 0x90);
5607         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5608         rt2800_bbp_write(rt2x00dev, 92, 0x02);
5609         rt2800_bbp_write(rt2x00dev, 95, 0x9a);
5610         rt2800_bbp_write(rt2x00dev, 98, 0x12);
5611         rt2800_bbp_write(rt2x00dev, 103, 0xC0);
5612         rt2800_bbp_write(rt2x00dev, 104, 0x92);
5613         /* FIXME BBP105 owerwrite */
5614         rt2800_bbp_write(rt2x00dev, 105, 0x3C);
5615         rt2800_bbp_write(rt2x00dev, 106, 0x35);
5616         rt2800_bbp_write(rt2x00dev, 128, 0x12);
5617         rt2800_bbp_write(rt2x00dev, 134, 0xD0);
5618         rt2800_bbp_write(rt2x00dev, 135, 0xF6);
5619         rt2800_bbp_write(rt2x00dev, 137, 0x0F);
5620
5621         /* Initialize GLRT (Generalized Likehood Radio Test) */
5622         rt2800_init_bbp_5592_glrt(rt2x00dev);
5623
5624         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5625
5626         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
5627         div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY);
5628         ant = (div_mode == 3) ? 1 : 0;
5629         rt2800_bbp_read(rt2x00dev, 152, &value);
5630         if (ant == 0) {
5631                 /* Main antenna */
5632                 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
5633         } else {
5634                 /* Auxiliary antenna */
5635                 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
5636         }
5637         rt2800_bbp_write(rt2x00dev, 152, value);
5638
5639         if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) {
5640                 rt2800_bbp_read(rt2x00dev, 254, &value);
5641                 rt2x00_set_field8(&value, BBP254_BIT7, 1);
5642                 rt2800_bbp_write(rt2x00dev, 254, value);
5643         }
5644
5645         rt2800_init_freq_calibration(rt2x00dev);
5646
5647         rt2800_bbp_write(rt2x00dev, 84, 0x19);
5648         if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
5649                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5650 }
5651
5652 static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
5653 {
5654         unsigned int i;
5655         u16 eeprom;
5656         u8 reg_id;
5657         u8 value;
5658
5659         if (rt2800_is_305x_soc(rt2x00dev))
5660                 rt2800_init_bbp_305x_soc(rt2x00dev);
5661
5662         switch (rt2x00dev->chip.rt) {
5663         case RT2860:
5664         case RT2872:
5665         case RT2883:
5666                 rt2800_init_bbp_28xx(rt2x00dev);
5667                 break;
5668         case RT3070:
5669         case RT3071:
5670         case RT3090:
5671                 rt2800_init_bbp_30xx(rt2x00dev);
5672                 break;
5673         case RT3290:
5674                 rt2800_init_bbp_3290(rt2x00dev);
5675                 break;
5676         case RT3352:
5677                 rt2800_init_bbp_3352(rt2x00dev);
5678                 break;
5679         case RT3390:
5680                 rt2800_init_bbp_3390(rt2x00dev);
5681                 break;
5682         case RT3572:
5683                 rt2800_init_bbp_3572(rt2x00dev);
5684                 break;
5685         case RT3593:
5686                 rt2800_init_bbp_3593(rt2x00dev);
5687                 return;
5688         case RT5390:
5689         case RT5392:
5690                 rt2800_init_bbp_53xx(rt2x00dev);
5691                 break;
5692         case RT5592:
5693                 rt2800_init_bbp_5592(rt2x00dev);
5694                 return;
5695         }
5696
5697         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
5698                 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_BBP_START, i,
5699                                               &eeprom);
5700
5701                 if (eeprom != 0xffff && eeprom != 0x0000) {
5702                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
5703                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
5704                         rt2800_bbp_write(rt2x00dev, reg_id, value);
5705                 }
5706         }
5707 }
5708
5709 static void rt2800_led_open_drain_enable(struct rt2x00_dev *rt2x00dev)
5710 {
5711         u32 reg;
5712
5713         rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
5714         rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
5715         rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
5716 }
5717
5718 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, bool bw40,
5719                                 u8 filter_target)
5720 {
5721         unsigned int i;
5722         u8 bbp;
5723         u8 rfcsr;
5724         u8 passband;
5725         u8 stopband;
5726         u8 overtuned = 0;
5727         u8 rfcsr24 = (bw40) ? 0x27 : 0x07;
5728
5729         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
5730
5731         rt2800_bbp_read(rt2x00dev, 4, &bbp);
5732         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
5733         rt2800_bbp_write(rt2x00dev, 4, bbp);
5734
5735         rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
5736         rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
5737         rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
5738
5739         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
5740         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
5741         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
5742
5743         /*
5744          * Set power & frequency of passband test tone
5745          */
5746         rt2800_bbp_write(rt2x00dev, 24, 0);
5747
5748         for (i = 0; i < 100; i++) {
5749                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
5750                 msleep(1);
5751
5752                 rt2800_bbp_read(rt2x00dev, 55, &passband);
5753                 if (passband)
5754                         break;
5755         }
5756
5757         /*
5758          * Set power & frequency of stopband test tone
5759          */
5760         rt2800_bbp_write(rt2x00dev, 24, 0x06);
5761
5762         for (i = 0; i < 100; i++) {
5763                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
5764                 msleep(1);
5765
5766                 rt2800_bbp_read(rt2x00dev, 55, &stopband);
5767
5768                 if ((passband - stopband) <= filter_target) {
5769                         rfcsr24++;
5770                         overtuned += ((passband - stopband) == filter_target);
5771                 } else
5772                         break;
5773
5774                 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
5775         }
5776
5777         rfcsr24 -= !!overtuned;
5778
5779         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
5780         return rfcsr24;
5781 }
5782
5783 static void rt2800_rf_init_calibration(struct rt2x00_dev *rt2x00dev,
5784                                        const unsigned int rf_reg)
5785 {
5786         u8 rfcsr;
5787
5788         rt2800_rfcsr_read(rt2x00dev, rf_reg, &rfcsr);
5789         rt2x00_set_field8(&rfcsr, FIELD8(0x80), 1);
5790         rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
5791         msleep(1);
5792         rt2x00_set_field8(&rfcsr, FIELD8(0x80), 0);
5793         rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
5794 }
5795
5796 static void rt2800_rx_filter_calibration(struct rt2x00_dev *rt2x00dev)
5797 {
5798         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5799         u8 filter_tgt_bw20;
5800         u8 filter_tgt_bw40;
5801         u8 rfcsr, bbp;
5802
5803         /*
5804          * TODO: sync filter_tgt values with vendor driver
5805          */
5806         if (rt2x00_rt(rt2x00dev, RT3070)) {
5807                 filter_tgt_bw20 = 0x16;
5808                 filter_tgt_bw40 = 0x19;
5809         } else {
5810                 filter_tgt_bw20 = 0x13;
5811                 filter_tgt_bw40 = 0x15;
5812         }
5813
5814         drv_data->calibration_bw20 =
5815                 rt2800_init_rx_filter(rt2x00dev, false, filter_tgt_bw20);
5816         drv_data->calibration_bw40 =
5817                 rt2800_init_rx_filter(rt2x00dev, true, filter_tgt_bw40);
5818
5819         /*
5820          * Save BBP 25 & 26 values for later use in channel switching (for 3052)
5821          */
5822         rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
5823         rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
5824
5825         /*
5826          * Set back to initial state
5827          */
5828         rt2800_bbp_write(rt2x00dev, 24, 0);
5829
5830         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
5831         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
5832         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
5833
5834         /*
5835          * Set BBP back to BW20
5836          */
5837         rt2800_bbp_read(rt2x00dev, 4, &bbp);
5838         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
5839         rt2800_bbp_write(rt2x00dev, 4, bbp);
5840 }
5841
5842 static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev)
5843 {
5844         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5845         u8 min_gain, rfcsr, bbp;
5846         u16 eeprom;
5847
5848         rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
5849
5850         rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
5851         if (rt2x00_rt(rt2x00dev, RT3070) ||
5852             rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
5853             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
5854             rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
5855                 if (!rt2x00_has_cap_external_lna_bg(rt2x00dev))
5856                         rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
5857         }
5858
5859         min_gain = rt2x00_rt(rt2x00dev, RT3070) ? 1 : 2;
5860         if (drv_data->txmixer_gain_24g >= min_gain) {
5861                 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
5862                                   drv_data->txmixer_gain_24g);
5863         }
5864
5865         rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
5866
5867         if (rt2x00_rt(rt2x00dev, RT3090)) {
5868                 /*  Turn off unused DAC1 and ADC1 to reduce power consumption */
5869                 rt2800_bbp_read(rt2x00dev, 138, &bbp);
5870                 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5871                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5872                         rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
5873                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5874                         rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
5875                 rt2800_bbp_write(rt2x00dev, 138, bbp);
5876         }
5877
5878         if (rt2x00_rt(rt2x00dev, RT3070)) {
5879                 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
5880                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
5881                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
5882                 else
5883                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
5884                 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
5885                 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
5886                 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
5887                 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
5888         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
5889                    rt2x00_rt(rt2x00dev, RT3090) ||
5890                    rt2x00_rt(rt2x00dev, RT3390)) {
5891                 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
5892                 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
5893                 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
5894                 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
5895                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
5896                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
5897                 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
5898
5899                 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
5900                 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
5901                 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
5902
5903                 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
5904                 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
5905                 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
5906
5907                 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
5908                 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
5909                 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
5910         }
5911 }
5912
5913 static void rt2800_normal_mode_setup_3593(struct rt2x00_dev *rt2x00dev)
5914 {
5915         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5916         u8 rfcsr;
5917         u8 tx_gain;
5918
5919         rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
5920         rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO2_EN, 0);
5921         rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
5922
5923         rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr);
5924         tx_gain = rt2x00_get_field8(drv_data->txmixer_gain_24g,
5925                                     RFCSR17_TXMIXER_GAIN);
5926         rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, tx_gain);
5927         rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
5928
5929         rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
5930         rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
5931         rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
5932
5933         rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
5934         rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
5935         rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
5936
5937         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
5938         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
5939         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
5940         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
5941
5942         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
5943         rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
5944         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
5945
5946         /* TODO: enable stream mode */
5947 }
5948
5949 static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev *rt2x00dev)
5950 {
5951         u8 reg;
5952         u16 eeprom;
5953
5954         /*  Turn off unused DAC1 and ADC1 to reduce power consumption */
5955         rt2800_bbp_read(rt2x00dev, 138, &reg);
5956         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5957         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5958                 rt2x00_set_field8(&reg, BBP138_RX_ADC1, 0);
5959         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5960                 rt2x00_set_field8(&reg, BBP138_TX_DAC1, 1);
5961         rt2800_bbp_write(rt2x00dev, 138, reg);
5962
5963         rt2800_rfcsr_read(rt2x00dev, 38, &reg);
5964         rt2x00_set_field8(&reg, RFCSR38_RX_LO1_EN, 0);
5965         rt2800_rfcsr_write(rt2x00dev, 38, reg);
5966
5967         rt2800_rfcsr_read(rt2x00dev, 39, &reg);
5968         rt2x00_set_field8(&reg, RFCSR39_RX_LO2_EN, 0);
5969         rt2800_rfcsr_write(rt2x00dev, 39, reg);
5970
5971         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5972
5973         rt2800_rfcsr_read(rt2x00dev, 30, &reg);
5974         rt2x00_set_field8(&reg, RFCSR30_RX_VCM, 2);
5975         rt2800_rfcsr_write(rt2x00dev, 30, reg);
5976 }
5977
5978 static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev)
5979 {
5980         rt2800_rf_init_calibration(rt2x00dev, 30);
5981
5982         rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
5983         rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
5984         rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
5985         rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
5986         rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
5987         rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
5988         rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
5989         rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
5990         rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
5991         rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
5992         rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
5993         rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
5994         rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
5995         rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
5996         rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
5997         rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
5998         rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
5999         rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
6000         rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
6001         rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
6002         rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
6003         rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
6004         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
6005         rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
6006         rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
6007         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
6008         rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
6009         rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
6010         rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
6011         rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
6012         rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
6013         rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
6014 }
6015
6016 static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev)
6017 {
6018         u8 rfcsr;
6019         u16 eeprom;
6020         u32 reg;
6021
6022         /* XXX vendor driver do this only for 3070 */
6023         rt2800_rf_init_calibration(rt2x00dev, 30);
6024
6025         rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
6026         rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
6027         rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
6028         rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
6029         rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
6030         rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
6031         rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
6032         rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
6033         rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
6034         rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
6035         rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
6036         rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
6037         rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
6038         rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
6039         rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
6040         rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
6041         rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
6042         rt2800_rfcsr_write(rt2x00dev, 25, 0x03);
6043         rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
6044
6045         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
6046                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6047                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6048                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6049                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6050         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
6051                    rt2x00_rt(rt2x00dev, RT3090)) {
6052                 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
6053
6054                 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
6055                 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
6056                 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
6057
6058                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6059                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6060                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
6061                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
6062                         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
6063                                            &eeprom);
6064                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
6065                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6066                         else
6067                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
6068                 }
6069                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6070
6071                 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
6072                 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
6073                 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
6074         }
6075
6076         rt2800_rx_filter_calibration(rt2x00dev);
6077
6078         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
6079             rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
6080             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E))
6081                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
6082
6083         rt2800_led_open_drain_enable(rt2x00dev);
6084         rt2800_normal_mode_setup_3xxx(rt2x00dev);
6085 }
6086
6087 static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev)
6088 {
6089         u8 rfcsr;
6090
6091         rt2800_rf_init_calibration(rt2x00dev, 2);
6092
6093         rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
6094         rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6095         rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
6096         rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
6097         rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
6098         rt2800_rfcsr_write(rt2x00dev, 8, 0xf3);
6099         rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
6100         rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
6101         rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
6102         rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
6103         rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
6104         rt2800_rfcsr_write(rt2x00dev, 18, 0x02);
6105         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6106         rt2800_rfcsr_write(rt2x00dev, 25, 0x83);
6107         rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
6108         rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
6109         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6110         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6111         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6112         rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
6113         rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
6114         rt2800_rfcsr_write(rt2x00dev, 34, 0x05);
6115         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6116         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
6117         rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
6118         rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
6119         rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
6120         rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
6121         rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
6122         rt2800_rfcsr_write(rt2x00dev, 43, 0x7b);
6123         rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
6124         rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
6125         rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
6126         rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
6127         rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
6128         rt2800_rfcsr_write(rt2x00dev, 49, 0x98);
6129         rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
6130         rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
6131         rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
6132         rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
6133         rt2800_rfcsr_write(rt2x00dev, 56, 0x02);
6134         rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
6135         rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
6136         rt2800_rfcsr_write(rt2x00dev, 59, 0x09);
6137         rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
6138         rt2800_rfcsr_write(rt2x00dev, 61, 0xc1);
6139
6140         rt2800_rfcsr_read(rt2x00dev, 29, &rfcsr);
6141         rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3);
6142         rt2800_rfcsr_write(rt2x00dev, 29, rfcsr);
6143
6144         rt2800_led_open_drain_enable(rt2x00dev);
6145         rt2800_normal_mode_setup_3xxx(rt2x00dev);
6146 }
6147
6148 static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev)
6149 {
6150         rt2800_rf_init_calibration(rt2x00dev, 30);
6151
6152         rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
6153         rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
6154         rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
6155         rt2800_rfcsr_write(rt2x00dev, 3, 0x18);
6156         rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
6157         rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
6158         rt2800_rfcsr_write(rt2x00dev, 6, 0x33);
6159         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6160         rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
6161         rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
6162         rt2800_rfcsr_write(rt2x00dev, 10, 0xd2);
6163         rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
6164         rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
6165         rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
6166         rt2800_rfcsr_write(rt2x00dev, 14, 0x5a);
6167         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6168         rt2800_rfcsr_write(rt2x00dev, 16, 0x01);
6169         rt2800_rfcsr_write(rt2x00dev, 18, 0x45);
6170         rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
6171         rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
6172         rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
6173         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
6174         rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
6175         rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
6176         rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
6177         rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
6178         rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
6179         rt2800_rfcsr_write(rt2x00dev, 28, 0x03);
6180         rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
6181         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6182         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6183         rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
6184         rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
6185         rt2800_rfcsr_write(rt2x00dev, 34, 0x01);
6186         rt2800_rfcsr_write(rt2x00dev, 35, 0x03);
6187         rt2800_rfcsr_write(rt2x00dev, 36, 0xbd);
6188         rt2800_rfcsr_write(rt2x00dev, 37, 0x3c);
6189         rt2800_rfcsr_write(rt2x00dev, 38, 0x5f);
6190         rt2800_rfcsr_write(rt2x00dev, 39, 0xc5);
6191         rt2800_rfcsr_write(rt2x00dev, 40, 0x33);
6192         rt2800_rfcsr_write(rt2x00dev, 41, 0x5b);
6193         rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
6194         rt2800_rfcsr_write(rt2x00dev, 43, 0xdb);
6195         rt2800_rfcsr_write(rt2x00dev, 44, 0xdb);
6196         rt2800_rfcsr_write(rt2x00dev, 45, 0xdb);
6197         rt2800_rfcsr_write(rt2x00dev, 46, 0xdd);
6198         rt2800_rfcsr_write(rt2x00dev, 47, 0x0d);
6199         rt2800_rfcsr_write(rt2x00dev, 48, 0x14);
6200         rt2800_rfcsr_write(rt2x00dev, 49, 0x00);
6201         rt2800_rfcsr_write(rt2x00dev, 50, 0x2d);
6202         rt2800_rfcsr_write(rt2x00dev, 51, 0x7f);
6203         rt2800_rfcsr_write(rt2x00dev, 52, 0x00);
6204         rt2800_rfcsr_write(rt2x00dev, 53, 0x52);
6205         rt2800_rfcsr_write(rt2x00dev, 54, 0x1b);
6206         rt2800_rfcsr_write(rt2x00dev, 55, 0x7f);
6207         rt2800_rfcsr_write(rt2x00dev, 56, 0x00);
6208         rt2800_rfcsr_write(rt2x00dev, 57, 0x52);
6209         rt2800_rfcsr_write(rt2x00dev, 58, 0x1b);
6210         rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
6211         rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
6212         rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
6213         rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
6214         rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
6215
6216         rt2800_rx_filter_calibration(rt2x00dev);
6217         rt2800_led_open_drain_enable(rt2x00dev);
6218         rt2800_normal_mode_setup_3xxx(rt2x00dev);
6219 }
6220
6221 static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev)
6222 {
6223         u32 reg;
6224
6225         rt2800_rf_init_calibration(rt2x00dev, 30);
6226
6227         rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
6228         rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
6229         rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
6230         rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
6231         rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
6232         rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
6233         rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
6234         rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
6235         rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
6236         rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
6237         rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
6238         rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
6239         rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
6240         rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
6241         rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
6242         rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
6243         rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
6244         rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
6245         rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
6246         rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
6247         rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
6248         rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
6249         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
6250         rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
6251         rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
6252         rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
6253         rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
6254         rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
6255         rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
6256         rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
6257         rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
6258         rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
6259
6260         rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
6261         rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
6262         rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
6263
6264         rt2800_rx_filter_calibration(rt2x00dev);
6265
6266         if (rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
6267                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
6268
6269         rt2800_led_open_drain_enable(rt2x00dev);
6270         rt2800_normal_mode_setup_3xxx(rt2x00dev);
6271 }
6272
6273 static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev)
6274 {
6275         u8 rfcsr;
6276         u32 reg;
6277
6278         rt2800_rf_init_calibration(rt2x00dev, 30);
6279
6280         rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
6281         rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
6282         rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
6283         rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
6284         rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
6285         rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
6286         rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
6287         rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
6288         rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
6289         rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
6290         rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
6291         rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
6292         rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
6293         rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
6294         rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
6295         rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
6296         rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
6297         rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
6298         rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
6299         rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
6300         rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
6301         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
6302         rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
6303         rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
6304         rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
6305         rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
6306         rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
6307         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6308         rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
6309         rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
6310         rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
6311
6312         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
6313         rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
6314         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
6315
6316         rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6317         rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6318         rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6319         rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6320         msleep(1);
6321         rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6322         rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
6323         rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6324         rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6325
6326         rt2800_rx_filter_calibration(rt2x00dev);
6327         rt2800_led_open_drain_enable(rt2x00dev);
6328         rt2800_normal_mode_setup_3xxx(rt2x00dev);
6329 }
6330
6331 static void rt3593_post_bbp_init(struct rt2x00_dev *rt2x00dev)
6332 {
6333         u8 bbp;
6334         bool txbf_enabled = false; /* FIXME */
6335
6336         rt2800_bbp_read(rt2x00dev, 105, &bbp);
6337         if (rt2x00dev->default_ant.rx_chain_num == 1)
6338                 rt2x00_set_field8(&bbp, BBP105_MLD, 0);
6339         else
6340                 rt2x00_set_field8(&bbp, BBP105_MLD, 1);
6341         rt2800_bbp_write(rt2x00dev, 105, bbp);
6342
6343         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6344
6345         rt2800_bbp_write(rt2x00dev, 92, 0x02);
6346         rt2800_bbp_write(rt2x00dev, 82, 0x82);
6347         rt2800_bbp_write(rt2x00dev, 106, 0x05);
6348         rt2800_bbp_write(rt2x00dev, 104, 0x92);
6349         rt2800_bbp_write(rt2x00dev, 88, 0x90);
6350         rt2800_bbp_write(rt2x00dev, 148, 0xc8);
6351         rt2800_bbp_write(rt2x00dev, 47, 0x48);
6352         rt2800_bbp_write(rt2x00dev, 120, 0x50);
6353
6354         if (txbf_enabled)
6355                 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
6356         else
6357                 rt2800_bbp_write(rt2x00dev, 163, 0x9d);
6358
6359         /* SNR mapping */
6360         rt2800_bbp_write(rt2x00dev, 142, 6);
6361         rt2800_bbp_write(rt2x00dev, 143, 160);
6362         rt2800_bbp_write(rt2x00dev, 142, 7);
6363         rt2800_bbp_write(rt2x00dev, 143, 161);
6364         rt2800_bbp_write(rt2x00dev, 142, 8);
6365         rt2800_bbp_write(rt2x00dev, 143, 162);
6366
6367         /* ADC/DAC control */
6368         rt2800_bbp_write(rt2x00dev, 31, 0x08);
6369
6370         /* RX AGC energy lower bound in log2 */
6371         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
6372
6373         /* FIXME: BBP 105 owerwrite? */
6374         rt2800_bbp_write(rt2x00dev, 105, 0x04);
6375
6376 }
6377
6378 static void rt2800_init_rfcsr_3593(struct rt2x00_dev *rt2x00dev)
6379 {
6380         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
6381         u32 reg;
6382         u8 rfcsr;
6383
6384         /* Disable GPIO #4 and #7 function for LAN PE control */
6385         rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
6386         rt2x00_set_field32(&reg, GPIO_SWITCH_4, 0);
6387         rt2x00_set_field32(&reg, GPIO_SWITCH_7, 0);
6388         rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
6389
6390         /* Initialize default register values */
6391         rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
6392         rt2800_rfcsr_write(rt2x00dev, 3, 0x80);
6393         rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
6394         rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
6395         rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
6396         rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
6397         rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
6398         rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
6399         rt2800_rfcsr_write(rt2x00dev, 12, 0x4e);
6400         rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
6401         rt2800_rfcsr_write(rt2x00dev, 18, 0x40);
6402         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6403         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6404         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6405         rt2800_rfcsr_write(rt2x00dev, 32, 0x78);
6406         rt2800_rfcsr_write(rt2x00dev, 33, 0x3b);
6407         rt2800_rfcsr_write(rt2x00dev, 34, 0x3c);
6408         rt2800_rfcsr_write(rt2x00dev, 35, 0xe0);
6409         rt2800_rfcsr_write(rt2x00dev, 38, 0x86);
6410         rt2800_rfcsr_write(rt2x00dev, 39, 0x23);
6411         rt2800_rfcsr_write(rt2x00dev, 44, 0xd3);
6412         rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
6413         rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
6414         rt2800_rfcsr_write(rt2x00dev, 49, 0x8e);
6415         rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
6416         rt2800_rfcsr_write(rt2x00dev, 51, 0x75);
6417         rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
6418         rt2800_rfcsr_write(rt2x00dev, 53, 0x18);
6419         rt2800_rfcsr_write(rt2x00dev, 54, 0x18);
6420         rt2800_rfcsr_write(rt2x00dev, 55, 0x18);
6421         rt2800_rfcsr_write(rt2x00dev, 56, 0xdb);
6422         rt2800_rfcsr_write(rt2x00dev, 57, 0x6e);
6423
6424         /* Initiate calibration */
6425         /* TODO: use rt2800_rf_init_calibration ? */
6426         rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
6427         rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
6428         rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
6429
6430         rt2800_adjust_freq_offset(rt2x00dev);
6431
6432         rt2800_rfcsr_read(rt2x00dev, 18, &rfcsr);
6433         rt2x00_set_field8(&rfcsr, RFCSR18_XO_TUNE_BYPASS, 1);
6434         rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
6435
6436         rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6437         rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6438         rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6439         rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6440         usleep_range(1000, 1500);
6441         rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
6442         rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
6443         rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6444
6445         /* Set initial values for RX filter calibration */
6446         drv_data->calibration_bw20 = 0x1f;
6447         drv_data->calibration_bw40 = 0x2f;
6448
6449         /* Save BBP 25 & 26 values for later use in channel switching */
6450         rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
6451         rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
6452
6453         rt2800_led_open_drain_enable(rt2x00dev);
6454         rt2800_normal_mode_setup_3593(rt2x00dev);
6455
6456         rt3593_post_bbp_init(rt2x00dev);
6457
6458         /* TODO: enable stream mode support */
6459 }
6460
6461 static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
6462 {
6463         rt2800_rf_init_calibration(rt2x00dev, 2);
6464
6465         rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
6466         rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6467         rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
6468         rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
6469         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6470                 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
6471         else
6472                 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
6473         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6474         rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
6475         rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
6476         rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
6477         rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
6478         rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
6479         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6480         rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
6481         rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
6482         rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
6483
6484         rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
6485         rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
6486         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6487         rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
6488         rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
6489         if (rt2x00_is_usb(rt2x00dev) &&
6490             rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6491                 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
6492         else
6493                 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
6494         rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
6495         rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
6496         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6497         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6498
6499         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6500         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6501         rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
6502         rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
6503         rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
6504         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6505         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
6506         rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
6507         rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
6508         rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
6509
6510         rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
6511         rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
6512         rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
6513         rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
6514         rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
6515         rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
6516         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6517                 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
6518         else
6519                 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
6520         rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
6521         rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
6522         rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
6523
6524         rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
6525         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6526                 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
6527         else
6528                 rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
6529         rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
6530         rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
6531         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6532                 rt2800_rfcsr_write(rt2x00dev, 56, 0x42);
6533         else
6534                 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
6535         rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
6536         rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
6537         rt2800_rfcsr_write(rt2x00dev, 59, 0x8f);
6538
6539         rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
6540         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
6541                 if (rt2x00_is_usb(rt2x00dev))
6542                         rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
6543                 else
6544                         rt2800_rfcsr_write(rt2x00dev, 61, 0xd5);
6545         } else {
6546                 if (rt2x00_is_usb(rt2x00dev))
6547                         rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
6548                 else
6549                         rt2800_rfcsr_write(rt2x00dev, 61, 0xb5);
6550         }
6551         rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
6552         rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
6553
6554         rt2800_normal_mode_setup_5xxx(rt2x00dev);
6555
6556         rt2800_led_open_drain_enable(rt2x00dev);
6557 }
6558
6559 static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev)
6560 {
6561         rt2800_rf_init_calibration(rt2x00dev, 2);
6562
6563         rt2800_rfcsr_write(rt2x00dev, 1, 0x17);
6564         rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
6565         rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
6566         rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
6567         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6568         rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
6569         rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
6570         rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
6571         rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
6572         rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
6573         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6574         rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
6575         rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
6576         rt2800_rfcsr_write(rt2x00dev, 19, 0x4d);
6577         rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
6578         rt2800_rfcsr_write(rt2x00dev, 21, 0x8d);
6579         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6580         rt2800_rfcsr_write(rt2x00dev, 23, 0x0b);
6581         rt2800_rfcsr_write(rt2x00dev, 24, 0x44);
6582         rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
6583         rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
6584         rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
6585         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6586         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6587         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6588         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6589         rt2800_rfcsr_write(rt2x00dev, 32, 0x20);
6590         rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
6591         rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
6592         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6593         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
6594         rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
6595         rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
6596         rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
6597         rt2800_rfcsr_write(rt2x00dev, 40, 0x0f);
6598         rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
6599         rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
6600         rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
6601         rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
6602         rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
6603         rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
6604         rt2800_rfcsr_write(rt2x00dev, 47, 0x0c);
6605         rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
6606         rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
6607         rt2800_rfcsr_write(rt2x00dev, 50, 0x94);
6608         rt2800_rfcsr_write(rt2x00dev, 51, 0x3a);
6609         rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
6610         rt2800_rfcsr_write(rt2x00dev, 53, 0x44);
6611         rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
6612         rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
6613         rt2800_rfcsr_write(rt2x00dev, 56, 0xa1);
6614         rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
6615         rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
6616         rt2800_rfcsr_write(rt2x00dev, 59, 0x07);
6617         rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
6618         rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
6619         rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
6620         rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
6621
6622         rt2800_normal_mode_setup_5xxx(rt2x00dev);
6623
6624         rt2800_led_open_drain_enable(rt2x00dev);
6625 }
6626
6627 static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev)
6628 {
6629         rt2800_rf_init_calibration(rt2x00dev, 30);
6630
6631         rt2800_rfcsr_write(rt2x00dev, 1, 0x3F);
6632         rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
6633         rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
6634         rt2800_rfcsr_write(rt2x00dev, 6, 0xE4);
6635         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6636         rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
6637         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6638         rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
6639         rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
6640         rt2800_rfcsr_write(rt2x00dev, 19, 0x4D);
6641         rt2800_rfcsr_write(rt2x00dev, 20, 0x10);
6642         rt2800_rfcsr_write(rt2x00dev, 21, 0x8D);
6643         rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
6644         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6645         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6646         rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
6647         rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
6648         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6649         rt2800_rfcsr_write(rt2x00dev, 47, 0x0C);
6650         rt2800_rfcsr_write(rt2x00dev, 53, 0x22);
6651         rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
6652
6653         rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6654         msleep(1);
6655
6656         rt2800_adjust_freq_offset(rt2x00dev);
6657
6658         /* Enable DC filter */
6659         if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
6660                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6661
6662         rt2800_normal_mode_setup_5xxx(rt2x00dev);
6663
6664         if (rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C))
6665                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
6666
6667         rt2800_led_open_drain_enable(rt2x00dev);
6668 }
6669
6670 static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
6671 {
6672         if (rt2800_is_305x_soc(rt2x00dev)) {
6673                 rt2800_init_rfcsr_305x_soc(rt2x00dev);
6674                 return;
6675         }
6676
6677         switch (rt2x00dev->chip.rt) {
6678         case RT3070:
6679         case RT3071:
6680         case RT3090:
6681                 rt2800_init_rfcsr_30xx(rt2x00dev);
6682                 break;
6683         case RT3290:
6684                 rt2800_init_rfcsr_3290(rt2x00dev);
6685                 break;
6686         case RT3352:
6687                 rt2800_init_rfcsr_3352(rt2x00dev);
6688                 break;
6689         case RT3390:
6690                 rt2800_init_rfcsr_3390(rt2x00dev);
6691                 break;
6692         case RT3572:
6693                 rt2800_init_rfcsr_3572(rt2x00dev);
6694                 break;
6695         case RT3593:
6696                 rt2800_init_rfcsr_3593(rt2x00dev);
6697                 break;
6698         case RT5390:
6699                 rt2800_init_rfcsr_5390(rt2x00dev);
6700                 break;
6701         case RT5392:
6702                 rt2800_init_rfcsr_5392(rt2x00dev);
6703                 break;
6704         case RT5592:
6705                 rt2800_init_rfcsr_5592(rt2x00dev);
6706                 break;
6707         }
6708 }
6709
6710 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
6711 {
6712         u32 reg;
6713         u16 word;
6714
6715         /*
6716          * Initialize MAC registers.
6717          */
6718         if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
6719                      rt2800_init_registers(rt2x00dev)))
6720                 return -EIO;
6721
6722         /*
6723          * Wait BBP/RF to wake up.
6724          */
6725         if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev)))
6726                 return -EIO;
6727
6728         /*
6729          * Send signal during boot time to initialize firmware.
6730          */
6731         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
6732         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
6733         if (rt2x00_is_usb(rt2x00dev))
6734                 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
6735         rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
6736         msleep(1);
6737
6738         /*
6739          * Make sure BBP is up and running.
6740          */
6741         if (unlikely(rt2800_wait_bbp_ready(rt2x00dev)))
6742                 return -EIO;
6743
6744         /*
6745          * Initialize BBP/RF registers.
6746          */
6747         rt2800_init_bbp(rt2x00dev);
6748         rt2800_init_rfcsr(rt2x00dev);
6749
6750         if (rt2x00_is_usb(rt2x00dev) &&
6751             (rt2x00_rt(rt2x00dev, RT3070) ||
6752              rt2x00_rt(rt2x00dev, RT3071) ||
6753              rt2x00_rt(rt2x00dev, RT3572))) {
6754                 udelay(200);
6755                 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
6756                 udelay(10);
6757         }
6758
6759         /*
6760          * Enable RX.
6761          */
6762         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
6763         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
6764         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
6765         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
6766
6767         udelay(50);
6768
6769         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
6770         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
6771         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
6772         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
6773         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
6774         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
6775
6776         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
6777         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
6778         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
6779         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
6780
6781         /*
6782          * Initialize LED control
6783          */
6784         rt2800_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
6785         rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
6786                            word & 0xff, (word >> 8) & 0xff);
6787
6788         rt2800_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
6789         rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
6790                            word & 0xff, (word >> 8) & 0xff);
6791
6792         rt2800_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
6793         rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
6794                            word & 0xff, (word >> 8) & 0xff);
6795
6796         return 0;
6797 }
6798 EXPORT_SYMBOL_GPL(rt2800_enable_radio);
6799
6800 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
6801 {
6802         u32 reg;
6803
6804         rt2800_disable_wpdma(rt2x00dev);
6805
6806         /* Wait for DMA, ignore error */
6807         rt2800_wait_wpdma_ready(rt2x00dev);
6808
6809         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
6810         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
6811         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
6812         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
6813 }
6814 EXPORT_SYMBOL_GPL(rt2800_disable_radio);
6815
6816 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
6817 {
6818         u32 reg;
6819         u16 efuse_ctrl_reg;
6820
6821         if (rt2x00_rt(rt2x00dev, RT3290))
6822                 efuse_ctrl_reg = EFUSE_CTRL_3290;
6823         else
6824                 efuse_ctrl_reg = EFUSE_CTRL;
6825
6826         rt2800_register_read(rt2x00dev, efuse_ctrl_reg, &reg);
6827         return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
6828 }
6829 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
6830
6831 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
6832 {
6833         u32 reg;
6834         u16 efuse_ctrl_reg;
6835         u16 efuse_data0_reg;
6836         u16 efuse_data1_reg;
6837         u16 efuse_data2_reg;
6838         u16 efuse_data3_reg;
6839
6840         if (rt2x00_rt(rt2x00dev, RT3290)) {
6841                 efuse_ctrl_reg = EFUSE_CTRL_3290;
6842                 efuse_data0_reg = EFUSE_DATA0_3290;
6843                 efuse_data1_reg = EFUSE_DATA1_3290;
6844                 efuse_data2_reg = EFUSE_DATA2_3290;
6845                 efuse_data3_reg = EFUSE_DATA3_3290;
6846         } else {
6847                 efuse_ctrl_reg = EFUSE_CTRL;
6848                 efuse_data0_reg = EFUSE_DATA0;
6849                 efuse_data1_reg = EFUSE_DATA1;
6850                 efuse_data2_reg = EFUSE_DATA2;
6851                 efuse_data3_reg = EFUSE_DATA3;
6852         }
6853         mutex_lock(&rt2x00dev->csr_mutex);
6854
6855         rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg, &reg);
6856         rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
6857         rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
6858         rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
6859         rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg);
6860
6861         /* Wait until the EEPROM has been loaded */
6862         rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, &reg);
6863         /* Apparently the data is read from end to start */
6864         rt2800_register_read_lock(rt2x00dev, efuse_data3_reg, &reg);
6865         /* The returned value is in CPU order, but eeprom is le */
6866         *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
6867         rt2800_register_read_lock(rt2x00dev, efuse_data2_reg, &reg);
6868         *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
6869         rt2800_register_read_lock(rt2x00dev, efuse_data1_reg, &reg);
6870         *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
6871         rt2800_register_read_lock(rt2x00dev, efuse_data0_reg, &reg);
6872         *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
6873
6874         mutex_unlock(&rt2x00dev->csr_mutex);
6875 }
6876
6877 int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
6878 {
6879         unsigned int i;
6880
6881         for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
6882                 rt2800_efuse_read(rt2x00dev, i);
6883
6884         return 0;
6885 }
6886 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
6887
6888 static u8 rt2800_get_txmixer_gain_24g(struct rt2x00_dev *rt2x00dev)
6889 {
6890         u16 word;
6891
6892         if (rt2x00_rt(rt2x00dev, RT3593))
6893                 return 0;
6894
6895         rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &word);
6896         if ((word & 0x00ff) != 0x00ff)
6897                 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL);
6898
6899         return 0;
6900 }
6901
6902 static u8 rt2800_get_txmixer_gain_5g(struct rt2x00_dev *rt2x00dev)
6903 {
6904         u16 word;
6905
6906         if (rt2x00_rt(rt2x00dev, RT3593))
6907                 return 0;
6908
6909         rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A, &word);
6910         if ((word & 0x00ff) != 0x00ff)
6911                 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL);
6912
6913         return 0;
6914 }
6915
6916 static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
6917 {
6918         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
6919         u16 word;
6920         u8 *mac;
6921         u8 default_lna_gain;
6922         int retval;
6923
6924         /*
6925          * Read the EEPROM.
6926          */
6927         retval = rt2800_read_eeprom(rt2x00dev);
6928         if (retval)
6929                 return retval;
6930
6931         /*
6932          * Start validation of the data that has been read.
6933          */
6934         mac = rt2800_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
6935         if (!is_valid_ether_addr(mac)) {
6936                 eth_random_addr(mac);
6937                 rt2x00_eeprom_dbg(rt2x00dev, "MAC: %pM\n", mac);
6938         }
6939
6940         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
6941         if (word == 0xffff) {
6942                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
6943                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
6944                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
6945                 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
6946                 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word);
6947         } else if (rt2x00_rt(rt2x00dev, RT2860) ||
6948                    rt2x00_rt(rt2x00dev, RT2872)) {
6949                 /*
6950                  * There is a max of 2 RX streams for RT28x0 series
6951                  */
6952                 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
6953                         rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
6954                 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
6955         }
6956
6957         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
6958         if (word == 0xffff) {
6959                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
6960                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
6961                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
6962                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
6963                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
6964                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
6965                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
6966                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
6967                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
6968                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
6969                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
6970                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
6971                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
6972                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
6973                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
6974                 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
6975                 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word);
6976         }
6977
6978         rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
6979         if ((word & 0x00ff) == 0x00ff) {
6980                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
6981                 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
6982                 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word);
6983         }
6984         if ((word & 0xff00) == 0xff00) {
6985                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
6986                                    LED_MODE_TXRX_ACTIVITY);
6987                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
6988                 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
6989                 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
6990                 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
6991                 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
6992                 rt2x00_eeprom_dbg(rt2x00dev, "Led Mode: 0x%04x\n", word);
6993         }
6994
6995         /*
6996          * During the LNA validation we are going to use
6997          * lna0 as correct value. Note that EEPROM_LNA
6998          * is never validated.
6999          */
7000         rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
7001         default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
7002
7003         rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
7004         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
7005                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
7006         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
7007                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
7008         rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
7009
7010         drv_data->txmixer_gain_24g = rt2800_get_txmixer_gain_24g(rt2x00dev);
7011
7012         rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
7013         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
7014                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
7015         if (!rt2x00_rt(rt2x00dev, RT3593)) {
7016                 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
7017                     rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
7018                         rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
7019                                            default_lna_gain);
7020         }
7021         rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
7022
7023         drv_data->txmixer_gain_5g = rt2800_get_txmixer_gain_5g(rt2x00dev);
7024
7025         rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
7026         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
7027                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
7028         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
7029                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
7030         rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
7031
7032         rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
7033         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
7034                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
7035         if (!rt2x00_rt(rt2x00dev, RT3593)) {
7036                 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
7037                     rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
7038                         rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
7039                                            default_lna_gain);
7040         }
7041         rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
7042
7043         if (rt2x00_rt(rt2x00dev, RT3593)) {
7044                 rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &word);
7045                 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0x00 ||
7046                     rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0xff)
7047                         rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
7048                                            default_lna_gain);
7049                 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0x00 ||
7050                     rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0xff)
7051                         rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
7052                                            default_lna_gain);
7053                 rt2800_eeprom_write(rt2x00dev, EEPROM_EXT_LNA2, word);
7054         }
7055
7056         return 0;
7057 }
7058
7059 static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
7060 {
7061         u16 value;
7062         u16 eeprom;
7063         u16 rf;
7064
7065         /*
7066          * Read EEPROM word for configuration.
7067          */
7068         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
7069
7070         /*
7071          * Identify RF chipset by EEPROM value
7072          * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
7073          * RT53xx: defined in "EEPROM_CHIP_ID" field
7074          */
7075         if (rt2x00_rt(rt2x00dev, RT3290) ||
7076             rt2x00_rt(rt2x00dev, RT5390) ||
7077             rt2x00_rt(rt2x00dev, RT5392))
7078                 rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &rf);
7079         else
7080                 rf = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
7081
7082         switch (rf) {
7083         case RF2820:
7084         case RF2850:
7085         case RF2720:
7086         case RF2750:
7087         case RF3020:
7088         case RF2020:
7089         case RF3021:
7090         case RF3022:
7091         case RF3052:
7092         case RF3053:
7093         case RF3070:
7094         case RF3290:
7095         case RF3320:
7096         case RF3322:
7097         case RF5360:
7098         case RF5370:
7099         case RF5372:
7100         case RF5390:
7101         case RF5392:
7102         case RF5592:
7103                 break;
7104         default:
7105                 rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n",
7106                            rf);
7107                 return -ENODEV;
7108         }
7109
7110         rt2x00_set_rf(rt2x00dev, rf);
7111
7112         /*
7113          * Identify default antenna configuration.
7114          */
7115         rt2x00dev->default_ant.tx_chain_num =
7116             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
7117         rt2x00dev->default_ant.rx_chain_num =
7118             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
7119
7120         rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
7121
7122         if (rt2x00_rt(rt2x00dev, RT3070) ||
7123             rt2x00_rt(rt2x00dev, RT3090) ||
7124             rt2x00_rt(rt2x00dev, RT3352) ||
7125             rt2x00_rt(rt2x00dev, RT3390)) {
7126                 value = rt2x00_get_field16(eeprom,
7127                                 EEPROM_NIC_CONF1_ANT_DIVERSITY);
7128                 switch (value) {
7129                 case 0:
7130                 case 1:
7131                 case 2:
7132                         rt2x00dev->default_ant.tx = ANTENNA_A;
7133                         rt2x00dev->default_ant.rx = ANTENNA_A;
7134                         break;
7135                 case 3:
7136                         rt2x00dev->default_ant.tx = ANTENNA_A;
7137                         rt2x00dev->default_ant.rx = ANTENNA_B;
7138                         break;
7139                 }
7140         } else {
7141                 rt2x00dev->default_ant.tx = ANTENNA_A;
7142                 rt2x00dev->default_ant.rx = ANTENNA_A;
7143         }
7144
7145         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
7146                 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */
7147                 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */
7148         }
7149
7150         /*
7151          * Determine external LNA informations.
7152          */
7153         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
7154                 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
7155         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
7156                 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
7157
7158         /*
7159          * Detect if this device has an hardware controlled radio.
7160          */
7161         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
7162                 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
7163
7164         /*
7165          * Detect if this device has Bluetooth co-existence.
7166          */
7167         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
7168                 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
7169
7170         /*
7171          * Read frequency offset and RF programming sequence.
7172          */
7173         rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
7174         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
7175
7176         /*
7177          * Store led settings, for correct led behaviour.
7178          */
7179 #ifdef CONFIG_RT2X00_LIB_LEDS
7180         rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
7181         rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
7182         rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
7183
7184         rt2x00dev->led_mcu_reg = eeprom;
7185 #endif /* CONFIG_RT2X00_LIB_LEDS */
7186
7187         /*
7188          * Check if support EIRP tx power limit feature.
7189          */
7190         rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
7191
7192         if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
7193                                         EIRP_MAX_TX_POWER_LIMIT)
7194                 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
7195
7196         return 0;
7197 }
7198
7199 /*
7200  * RF value list for rt28xx
7201  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
7202  */
7203 static const struct rf_channel rf_vals[] = {
7204         { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
7205         { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
7206         { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
7207         { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
7208         { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
7209         { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
7210         { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
7211         { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
7212         { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
7213         { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
7214         { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
7215         { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
7216         { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
7217         { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
7218
7219         /* 802.11 UNI / HyperLan 2 */
7220         { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
7221         { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
7222         { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
7223         { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
7224         { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
7225         { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
7226         { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
7227         { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
7228         { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
7229         { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
7230         { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
7231         { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
7232
7233         /* 802.11 HyperLan 2 */
7234         { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
7235         { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
7236         { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
7237         { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
7238         { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
7239         { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
7240         { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
7241         { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
7242         { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
7243         { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
7244         { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
7245         { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
7246         { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
7247         { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
7248         { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
7249         { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
7250
7251         /* 802.11 UNII */
7252         { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
7253         { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
7254         { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
7255         { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
7256         { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
7257         { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
7258         { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
7259         { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
7260         { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
7261         { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
7262         { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
7263
7264         /* 802.11 Japan */
7265         { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
7266         { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
7267         { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
7268         { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
7269         { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
7270         { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
7271         { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
7272 };
7273
7274 /*
7275  * RF value list for rt3xxx
7276  * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052 & RF3053)
7277  */
7278 static const struct rf_channel rf_vals_3x[] = {
7279         {1,  241, 2, 2 },
7280         {2,  241, 2, 7 },
7281         {3,  242, 2, 2 },
7282         {4,  242, 2, 7 },
7283         {5,  243, 2, 2 },
7284         {6,  243, 2, 7 },
7285         {7,  244, 2, 2 },
7286         {8,  244, 2, 7 },
7287         {9,  245, 2, 2 },
7288         {10, 245, 2, 7 },
7289         {11, 246, 2, 2 },
7290         {12, 246, 2, 7 },
7291         {13, 247, 2, 2 },
7292         {14, 248, 2, 4 },
7293
7294         /* 802.11 UNI / HyperLan 2 */
7295         {36, 0x56, 0, 4},
7296         {38, 0x56, 0, 6},
7297         {40, 0x56, 0, 8},
7298         {44, 0x57, 0, 0},
7299         {46, 0x57, 0, 2},
7300         {48, 0x57, 0, 4},
7301         {52, 0x57, 0, 8},
7302         {54, 0x57, 0, 10},
7303         {56, 0x58, 0, 0},
7304         {60, 0x58, 0, 4},
7305         {62, 0x58, 0, 6},
7306         {64, 0x58, 0, 8},
7307
7308         /* 802.11 HyperLan 2 */
7309         {100, 0x5b, 0, 8},
7310         {102, 0x5b, 0, 10},
7311         {104, 0x5c, 0, 0},
7312         {108, 0x5c, 0, 4},
7313         {110, 0x5c, 0, 6},
7314         {112, 0x5c, 0, 8},
7315         {116, 0x5d, 0, 0},
7316         {118, 0x5d, 0, 2},
7317         {120, 0x5d, 0, 4},
7318         {124, 0x5d, 0, 8},
7319         {126, 0x5d, 0, 10},
7320         {128, 0x5e, 0, 0},
7321         {132, 0x5e, 0, 4},
7322         {134, 0x5e, 0, 6},
7323         {136, 0x5e, 0, 8},
7324         {140, 0x5f, 0, 0},
7325
7326         /* 802.11 UNII */
7327         {149, 0x5f, 0, 9},
7328         {151, 0x5f, 0, 11},
7329         {153, 0x60, 0, 1},
7330         {157, 0x60, 0, 5},
7331         {159, 0x60, 0, 7},
7332         {161, 0x60, 0, 9},
7333         {165, 0x61, 0, 1},
7334         {167, 0x61, 0, 3},
7335         {169, 0x61, 0, 5},
7336         {171, 0x61, 0, 7},
7337         {173, 0x61, 0, 9},
7338 };
7339
7340 static const struct rf_channel rf_vals_5592_xtal20[] = {
7341         /* Channel, N, K, mod, R */
7342         {1, 482, 4, 10, 3},
7343         {2, 483, 4, 10, 3},
7344         {3, 484, 4, 10, 3},
7345         {4, 485, 4, 10, 3},
7346         {5, 486, 4, 10, 3},
7347         {6, 487, 4, 10, 3},
7348         {7, 488, 4, 10, 3},
7349         {8, 489, 4, 10, 3},
7350         {9, 490, 4, 10, 3},
7351         {10, 491, 4, 10, 3},
7352         {11, 492, 4, 10, 3},
7353         {12, 493, 4, 10, 3},
7354         {13, 494, 4, 10, 3},
7355         {14, 496, 8, 10, 3},
7356         {36, 172, 8, 12, 1},
7357         {38, 173, 0, 12, 1},
7358         {40, 173, 4, 12, 1},
7359         {42, 173, 8, 12, 1},
7360         {44, 174, 0, 12, 1},
7361         {46, 174, 4, 12, 1},
7362         {48, 174, 8, 12, 1},
7363         {50, 175, 0, 12, 1},
7364         {52, 175, 4, 12, 1},
7365         {54, 175, 8, 12, 1},
7366         {56, 176, 0, 12, 1},
7367         {58, 176, 4, 12, 1},
7368         {60, 176, 8, 12, 1},
7369         {62, 177, 0, 12, 1},
7370         {64, 177, 4, 12, 1},
7371         {100, 183, 4, 12, 1},
7372         {102, 183, 8, 12, 1},
7373         {104, 184, 0, 12, 1},
7374         {106, 184, 4, 12, 1},
7375         {108, 184, 8, 12, 1},
7376         {110, 185, 0, 12, 1},
7377         {112, 185, 4, 12, 1},
7378         {114, 185, 8, 12, 1},
7379         {116, 186, 0, 12, 1},
7380         {118, 186, 4, 12, 1},
7381         {120, 186, 8, 12, 1},
7382         {122, 187, 0, 12, 1},
7383         {124, 187, 4, 12, 1},
7384         {126, 187, 8, 12, 1},
7385         {128, 188, 0, 12, 1},
7386         {130, 188, 4, 12, 1},
7387         {132, 188, 8, 12, 1},
7388         {134, 189, 0, 12, 1},
7389         {136, 189, 4, 12, 1},
7390         {138, 189, 8, 12, 1},
7391         {140, 190, 0, 12, 1},
7392         {149, 191, 6, 12, 1},
7393         {151, 191, 10, 12, 1},
7394         {153, 192, 2, 12, 1},
7395         {155, 192, 6, 12, 1},
7396         {157, 192, 10, 12, 1},
7397         {159, 193, 2, 12, 1},
7398         {161, 193, 6, 12, 1},
7399         {165, 194, 2, 12, 1},
7400         {184, 164, 0, 12, 1},
7401         {188, 164, 4, 12, 1},
7402         {192, 165, 8, 12, 1},
7403         {196, 166, 0, 12, 1},
7404 };
7405
7406 static const struct rf_channel rf_vals_5592_xtal40[] = {
7407         /* Channel, N, K, mod, R */
7408         {1, 241, 2, 10, 3},
7409         {2, 241, 7, 10, 3},
7410         {3, 242, 2, 10, 3},
7411         {4, 242, 7, 10, 3},
7412         {5, 243, 2, 10, 3},
7413         {6, 243, 7, 10, 3},
7414         {7, 244, 2, 10, 3},
7415         {8, 244, 7, 10, 3},
7416         {9, 245, 2, 10, 3},
7417         {10, 245, 7, 10, 3},
7418         {11, 246, 2, 10, 3},
7419         {12, 246, 7, 10, 3},
7420         {13, 247, 2, 10, 3},
7421         {14, 248, 4, 10, 3},
7422         {36, 86, 4, 12, 1},
7423         {38, 86, 6, 12, 1},
7424         {40, 86, 8, 12, 1},
7425         {42, 86, 10, 12, 1},
7426         {44, 87, 0, 12, 1},
7427         {46, 87, 2, 12, 1},
7428         {48, 87, 4, 12, 1},
7429         {50, 87, 6, 12, 1},
7430         {52, 87, 8, 12, 1},
7431         {54, 87, 10, 12, 1},
7432         {56, 88, 0, 12, 1},
7433         {58, 88, 2, 12, 1},
7434         {60, 88, 4, 12, 1},
7435         {62, 88, 6, 12, 1},
7436         {64, 88, 8, 12, 1},
7437         {100, 91, 8, 12, 1},
7438         {102, 91, 10, 12, 1},
7439         {104, 92, 0, 12, 1},
7440         {106, 92, 2, 12, 1},
7441         {108, 92, 4, 12, 1},
7442         {110, 92, 6, 12, 1},
7443         {112, 92, 8, 12, 1},
7444         {114, 92, 10, 12, 1},
7445         {116, 93, 0, 12, 1},
7446         {118, 93, 2, 12, 1},
7447         {120, 93, 4, 12, 1},
7448         {122, 93, 6, 12, 1},
7449         {124, 93, 8, 12, 1},
7450         {126, 93, 10, 12, 1},
7451         {128, 94, 0, 12, 1},
7452         {130, 94, 2, 12, 1},
7453         {132, 94, 4, 12, 1},
7454         {134, 94, 6, 12, 1},
7455         {136, 94, 8, 12, 1},
7456         {138, 94, 10, 12, 1},
7457         {140, 95, 0, 12, 1},
7458         {149, 95, 9, 12, 1},
7459         {151, 95, 11, 12, 1},
7460         {153, 96, 1, 12, 1},
7461         {155, 96, 3, 12, 1},
7462         {157, 96, 5, 12, 1},
7463         {159, 96, 7, 12, 1},
7464         {161, 96, 9, 12, 1},
7465         {165, 97, 1, 12, 1},
7466         {184, 82, 0, 12, 1},
7467         {188, 82, 4, 12, 1},
7468         {192, 82, 8, 12, 1},
7469         {196, 83, 0, 12, 1},
7470 };
7471
7472 static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
7473 {
7474         struct hw_mode_spec *spec = &rt2x00dev->spec;
7475         struct channel_info *info;
7476         char *default_power1;
7477         char *default_power2;
7478         char *default_power3;
7479         unsigned int i;
7480         u32 reg;
7481
7482         /*
7483          * Disable powersaving as default.
7484          */
7485         rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
7486
7487         /*
7488          * Initialize all hw fields.
7489          */
7490         rt2x00dev->hw->flags =
7491             IEEE80211_HW_SIGNAL_DBM |
7492             IEEE80211_HW_SUPPORTS_PS |
7493             IEEE80211_HW_PS_NULLFUNC_STACK |
7494             IEEE80211_HW_AMPDU_AGGREGATION |
7495             IEEE80211_HW_REPORTS_TX_ACK_STATUS |
7496             IEEE80211_HW_SUPPORTS_HT_CCK_RATES;
7497
7498         /*
7499          * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
7500          * unless we are capable of sending the buffered frames out after the
7501          * DTIM transmission using rt2x00lib_beacondone. This will send out
7502          * multicast and broadcast traffic immediately instead of buffering it
7503          * infinitly and thus dropping it after some time.
7504          */
7505         if (!rt2x00_is_usb(rt2x00dev))
7506                 rt2x00dev->hw->flags |=
7507                         IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
7508
7509         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
7510         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
7511                                 rt2800_eeprom_addr(rt2x00dev,
7512                                                    EEPROM_MAC_ADDR_0));
7513
7514         /*
7515          * As rt2800 has a global fallback table we cannot specify
7516          * more then one tx rate per frame but since the hw will
7517          * try several rates (based on the fallback table) we should
7518          * initialize max_report_rates to the maximum number of rates
7519          * we are going to try. Otherwise mac80211 will truncate our
7520          * reported tx rates and the rc algortihm will end up with
7521          * incorrect data.
7522          */
7523         rt2x00dev->hw->max_rates = 1;
7524         rt2x00dev->hw->max_report_rates = 7;
7525         rt2x00dev->hw->max_rate_tries = 1;
7526
7527         /*
7528          * Initialize hw_mode information.
7529          */
7530         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
7531
7532         switch (rt2x00dev->chip.rf) {
7533         case RF2720:
7534         case RF2820:
7535                 spec->num_channels = 14;
7536                 spec->channels = rf_vals;
7537                 break;
7538
7539         case RF2750:
7540         case RF2850:
7541                 spec->num_channels = ARRAY_SIZE(rf_vals);
7542                 spec->channels = rf_vals;
7543                 break;
7544
7545         case RF2020:
7546         case RF3020:
7547         case RF3021:
7548         case RF3022:
7549         case RF3070:
7550         case RF3290:
7551         case RF3320:
7552         case RF3322:
7553         case RF5360:
7554         case RF5370:
7555         case RF5372:
7556         case RF5390:
7557         case RF5392:
7558                 spec->num_channels = 14;
7559                 spec->channels = rf_vals_3x;
7560                 break;
7561
7562         case RF3052:
7563         case RF3053:
7564                 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
7565                 spec->channels = rf_vals_3x;
7566                 break;
7567
7568         case RF5592:
7569                 rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX, &reg);
7570                 if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) {
7571                         spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40);
7572                         spec->channels = rf_vals_5592_xtal40;
7573                 } else {
7574                         spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20);
7575                         spec->channels = rf_vals_5592_xtal20;
7576                 }
7577                 break;
7578         }
7579
7580         if (WARN_ON_ONCE(!spec->channels))
7581                 return -ENODEV;
7582
7583         spec->supported_bands = SUPPORT_BAND_2GHZ;
7584         if (spec->num_channels > 14)
7585                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
7586
7587         /*
7588          * Initialize HT information.
7589          */
7590         if (!rt2x00_rf(rt2x00dev, RF2020))
7591                 spec->ht.ht_supported = true;
7592         else
7593                 spec->ht.ht_supported = false;
7594
7595         spec->ht.cap =
7596             IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
7597             IEEE80211_HT_CAP_GRN_FLD |
7598             IEEE80211_HT_CAP_SGI_20 |
7599             IEEE80211_HT_CAP_SGI_40;
7600
7601         if (rt2x00dev->default_ant.tx_chain_num >= 2)
7602                 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
7603
7604         spec->ht.cap |= rt2x00dev->default_ant.rx_chain_num <<
7605                         IEEE80211_HT_CAP_RX_STBC_SHIFT;
7606
7607         spec->ht.ampdu_factor = 3;
7608         spec->ht.ampdu_density = 4;
7609         spec->ht.mcs.tx_params =
7610             IEEE80211_HT_MCS_TX_DEFINED |
7611             IEEE80211_HT_MCS_TX_RX_DIFF |
7612             ((rt2x00dev->default_ant.tx_chain_num - 1) <<
7613              IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
7614
7615         switch (rt2x00dev->default_ant.rx_chain_num) {
7616         case 3:
7617                 spec->ht.mcs.rx_mask[2] = 0xff;
7618         case 2:
7619                 spec->ht.mcs.rx_mask[1] = 0xff;
7620         case 1:
7621                 spec->ht.mcs.rx_mask[0] = 0xff;
7622                 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
7623                 break;
7624         }
7625
7626         /*
7627          * Create channel information array
7628          */
7629         info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
7630         if (!info)
7631                 return -ENOMEM;
7632
7633         spec->channels_info = info;
7634
7635         default_power1 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
7636         default_power2 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
7637
7638         if (rt2x00dev->default_ant.tx_chain_num > 2)
7639                 default_power3 = rt2800_eeprom_addr(rt2x00dev,
7640                                                     EEPROM_EXT_TXPOWER_BG3);
7641         else
7642                 default_power3 = NULL;
7643
7644         for (i = 0; i < 14; i++) {
7645                 info[i].default_power1 = default_power1[i];
7646                 info[i].default_power2 = default_power2[i];
7647                 if (default_power3)
7648                         info[i].default_power3 = default_power3[i];
7649         }
7650
7651         if (spec->num_channels > 14) {
7652                 default_power1 = rt2800_eeprom_addr(rt2x00dev,
7653                                                     EEPROM_TXPOWER_A1);
7654                 default_power2 = rt2800_eeprom_addr(rt2x00dev,
7655                                                     EEPROM_TXPOWER_A2);
7656
7657                 if (rt2x00dev->default_ant.tx_chain_num > 2)
7658                         default_power3 =
7659                                 rt2800_eeprom_addr(rt2x00dev,
7660                                                    EEPROM_EXT_TXPOWER_A3);
7661                 else
7662                         default_power3 = NULL;
7663
7664                 for (i = 14; i < spec->num_channels; i++) {
7665                         info[i].default_power1 = default_power1[i - 14];
7666                         info[i].default_power2 = default_power2[i - 14];
7667                         if (default_power3)
7668                                 info[i].default_power3 = default_power3[i - 14];
7669                 }
7670         }
7671
7672         switch (rt2x00dev->chip.rf) {
7673         case RF2020:
7674         case RF3020:
7675         case RF3021:
7676         case RF3022:
7677         case RF3320:
7678         case RF3052:
7679         case RF3053:
7680         case RF3070:
7681         case RF3290:
7682         case RF5360:
7683         case RF5370:
7684         case RF5372:
7685         case RF5390:
7686         case RF5392:
7687                 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
7688                 break;
7689         }
7690
7691         return 0;
7692 }
7693
7694 static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev)
7695 {
7696         u32 reg;
7697         u32 rt;
7698         u32 rev;
7699
7700         if (rt2x00_rt(rt2x00dev, RT3290))
7701                 rt2800_register_read(rt2x00dev, MAC_CSR0_3290, &reg);
7702         else
7703                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
7704
7705         rt = rt2x00_get_field32(reg, MAC_CSR0_CHIPSET);
7706         rev = rt2x00_get_field32(reg, MAC_CSR0_REVISION);
7707
7708         switch (rt) {
7709         case RT2860:
7710         case RT2872:
7711         case RT2883:
7712         case RT3070:
7713         case RT3071:
7714         case RT3090:
7715         case RT3290:
7716         case RT3352:
7717         case RT3390:
7718         case RT3572:
7719         case RT3593:
7720         case RT5390:
7721         case RT5392:
7722         case RT5592:
7723                 break;
7724         default:
7725                 rt2x00_err(rt2x00dev, "Invalid RT chipset 0x%04x, rev %04x detected\n",
7726                            rt, rev);
7727                 return -ENODEV;
7728         }
7729
7730         rt2x00_set_rt(rt2x00dev, rt, rev);
7731
7732         return 0;
7733 }
7734
7735 int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev)
7736 {
7737         int retval;
7738         u32 reg;
7739
7740         retval = rt2800_probe_rt(rt2x00dev);
7741         if (retval)
7742                 return retval;
7743
7744         /*
7745          * Allocate eeprom data.
7746          */
7747         retval = rt2800_validate_eeprom(rt2x00dev);
7748         if (retval)
7749                 return retval;
7750
7751         retval = rt2800_init_eeprom(rt2x00dev);
7752         if (retval)
7753                 return retval;
7754
7755         /*
7756          * Enable rfkill polling by setting GPIO direction of the
7757          * rfkill switch GPIO pin correctly.
7758          */
7759         rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
7760         rt2x00_set_field32(&reg, GPIO_CTRL_DIR2, 1);
7761         rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
7762
7763         /*
7764          * Initialize hw specifications.
7765          */
7766         retval = rt2800_probe_hw_mode(rt2x00dev);
7767         if (retval)
7768                 return retval;
7769
7770         /*
7771          * Set device capabilities.
7772          */
7773         __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
7774         __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
7775         if (!rt2x00_is_usb(rt2x00dev))
7776                 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
7777
7778         /*
7779          * Set device requirements.
7780          */
7781         if (!rt2x00_is_soc(rt2x00dev))
7782                 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
7783         __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
7784         __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
7785         if (!rt2800_hwcrypt_disabled(rt2x00dev))
7786                 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
7787         __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
7788         __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
7789         if (rt2x00_is_usb(rt2x00dev))
7790                 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
7791         else {
7792                 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
7793                 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
7794         }
7795
7796         /*
7797          * Set the rssi offset.
7798          */
7799         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
7800
7801         return 0;
7802 }
7803 EXPORT_SYMBOL_GPL(rt2800_probe_hw);
7804
7805 /*
7806  * IEEE80211 stack callback functions.
7807  */
7808 void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
7809                          u16 *iv16)
7810 {
7811         struct rt2x00_dev *rt2x00dev = hw->priv;
7812         struct mac_iveiv_entry iveiv_entry;
7813         u32 offset;
7814
7815         offset = MAC_IVEIV_ENTRY(hw_key_idx);
7816         rt2800_register_multiread(rt2x00dev, offset,
7817                                       &iveiv_entry, sizeof(iveiv_entry));
7818
7819         memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
7820         memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
7821 }
7822 EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
7823
7824 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
7825 {
7826         struct rt2x00_dev *rt2x00dev = hw->priv;
7827         u32 reg;
7828         bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
7829
7830         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
7831         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
7832         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
7833
7834         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
7835         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
7836         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
7837
7838         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
7839         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
7840         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
7841
7842         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
7843         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
7844         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
7845
7846         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
7847         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
7848         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
7849
7850         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
7851         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
7852         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
7853
7854         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
7855         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
7856         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
7857
7858         return 0;
7859 }
7860 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
7861
7862 int rt2800_conf_tx(struct ieee80211_hw *hw,
7863                    struct ieee80211_vif *vif, u16 queue_idx,
7864                    const struct ieee80211_tx_queue_params *params)
7865 {
7866         struct rt2x00_dev *rt2x00dev = hw->priv;
7867         struct data_queue *queue;
7868         struct rt2x00_field32 field;
7869         int retval;
7870         u32 reg;
7871         u32 offset;
7872
7873         /*
7874          * First pass the configuration through rt2x00lib, that will
7875          * update the queue settings and validate the input. After that
7876          * we are free to update the registers based on the value
7877          * in the queue parameter.
7878          */
7879         retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
7880         if (retval)
7881                 return retval;
7882
7883         /*
7884          * We only need to perform additional register initialization
7885          * for WMM queues/
7886          */
7887         if (queue_idx >= 4)
7888                 return 0;
7889
7890         queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
7891
7892         /* Update WMM TXOP register */
7893         offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
7894         field.bit_offset = (queue_idx & 1) * 16;
7895         field.bit_mask = 0xffff << field.bit_offset;
7896
7897         rt2800_register_read(rt2x00dev, offset, &reg);
7898         rt2x00_set_field32(&reg, field, queue->txop);
7899         rt2800_register_write(rt2x00dev, offset, reg);
7900
7901         /* Update WMM registers */
7902         field.bit_offset = queue_idx * 4;
7903         field.bit_mask = 0xf << field.bit_offset;
7904
7905         rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
7906         rt2x00_set_field32(&reg, field, queue->aifs);
7907         rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
7908
7909         rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
7910         rt2x00_set_field32(&reg, field, queue->cw_min);
7911         rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
7912
7913         rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
7914         rt2x00_set_field32(&reg, field, queue->cw_max);
7915         rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
7916
7917         /* Update EDCA registers */
7918         offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
7919
7920         rt2800_register_read(rt2x00dev, offset, &reg);
7921         rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
7922         rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
7923         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
7924         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
7925         rt2800_register_write(rt2x00dev, offset, reg);
7926
7927         return 0;
7928 }
7929 EXPORT_SYMBOL_GPL(rt2800_conf_tx);
7930
7931 u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
7932 {
7933         struct rt2x00_dev *rt2x00dev = hw->priv;
7934         u64 tsf;
7935         u32 reg;
7936
7937         rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
7938         tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
7939         rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
7940         tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
7941
7942         return tsf;
7943 }
7944 EXPORT_SYMBOL_GPL(rt2800_get_tsf);
7945
7946 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
7947                         enum ieee80211_ampdu_mlme_action action,
7948                         struct ieee80211_sta *sta, u16 tid, u16 *ssn,
7949                         u8 buf_size)
7950 {
7951         struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
7952         int ret = 0;
7953
7954         /*
7955          * Don't allow aggregation for stations the hardware isn't aware
7956          * of because tx status reports for frames to an unknown station
7957          * always contain wcid=255 and thus we can't distinguish between
7958          * multiple stations which leads to unwanted situations when the
7959          * hw reorders frames due to aggregation.
7960          */
7961         if (sta_priv->wcid < 0)
7962                 return 1;
7963
7964         switch (action) {
7965         case IEEE80211_AMPDU_RX_START:
7966         case IEEE80211_AMPDU_RX_STOP:
7967                 /*
7968                  * The hw itself takes care of setting up BlockAck mechanisms.
7969                  * So, we only have to allow mac80211 to nagotiate a BlockAck
7970                  * agreement. Once that is done, the hw will BlockAck incoming
7971                  * AMPDUs without further setup.
7972                  */
7973                 break;
7974         case IEEE80211_AMPDU_TX_START:
7975                 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
7976                 break;
7977         case IEEE80211_AMPDU_TX_STOP_CONT:
7978         case IEEE80211_AMPDU_TX_STOP_FLUSH:
7979         case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
7980                 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
7981                 break;
7982         case IEEE80211_AMPDU_TX_OPERATIONAL:
7983                 break;
7984         default:
7985                 rt2x00_warn((struct rt2x00_dev *)hw->priv,
7986                             "Unknown AMPDU action\n");
7987         }
7988
7989         return ret;
7990 }
7991 EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
7992
7993 int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
7994                       struct survey_info *survey)
7995 {
7996         struct rt2x00_dev *rt2x00dev = hw->priv;
7997         struct ieee80211_conf *conf = &hw->conf;
7998         u32 idle, busy, busy_ext;
7999
8000         if (idx != 0)
8001                 return -ENOENT;
8002
8003         survey->channel = conf->chandef.chan;
8004
8005         rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
8006         rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
8007         rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
8008
8009         if (idle || busy) {
8010                 survey->filled = SURVEY_INFO_CHANNEL_TIME |
8011                                  SURVEY_INFO_CHANNEL_TIME_BUSY |
8012                                  SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
8013
8014                 survey->channel_time = (idle + busy) / 1000;
8015                 survey->channel_time_busy = busy / 1000;
8016                 survey->channel_time_ext_busy = busy_ext / 1000;
8017         }
8018
8019         if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
8020                 survey->filled |= SURVEY_INFO_IN_USE;
8021
8022         return 0;
8023
8024 }
8025 EXPORT_SYMBOL_GPL(rt2800_get_survey);
8026
8027 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
8028 MODULE_VERSION(DRV_VERSION);
8029 MODULE_DESCRIPTION("Ralink RT2800 library");
8030 MODULE_LICENSE("GPL");