drivers/net/wireless/rt2x00/rt2800lib.c

   1 /*
   2         Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
   3
   4         Based on the original rt2800pci.c and rt2800usb.c.
   5           Copyright (C) 2009 Ivo van Doorn <IvDoorn@gmail.com>
   6           Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
   7           Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
   8           Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
   9           Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
  10           Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
  11           Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
  12           <http://rt2x00.serialmonkey.com>
  13
  14         This program is free software; you can redistribute it and/or modify
  15         it under the terms of the GNU General Public License as published by
  16         the Free Software Foundation; either version 2 of the License, or
  17         (at your option) any later version.
  18
  19         This program is distributed in the hope that it will be useful,
  20         but WITHOUT ANY WARRANTY; without even the implied warranty of
  21         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22         GNU General Public License for more details.
  23
  24         You should have received a copy of the GNU General Public License
  25         along with this program; if not, write to the
  26         Free Software Foundation, Inc.,
  27         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  28  */
  29
  30 /*
  31         Module: rt2800lib
  32         Abstract: rt2800 generic device routines.
  33  */
  34
  35 #include <linux/kernel.h>
  36 #include <linux/module.h>
  37
  38 #include "rt2x00.h"
  39 #ifdef CONFIG_RT2800USB
  40 #include "rt2x00usb.h"
  41 #endif
  42 #include "rt2800lib.h"
  43 #include "rt2800.h"
  44 #include "rt2800usb.h"
  45
  46 MODULE_AUTHOR("Bartlomiej Zolnierkiewicz");
  47 MODULE_DESCRIPTION("rt2800 library");
  48 MODULE_LICENSE("GPL");
  49
  50 /*
  51  * Register access.
  52  * All access to the CSR registers will go through the methods
  53  * rt2800_register_read and rt2800_register_write.
  54  * BBP and RF register require indirect register access,
  55  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  56  * These indirect registers work with busy bits,
  57  * and we will try maximal REGISTER_BUSY_COUNT times to access
  58  * the register while taking a REGISTER_BUSY_DELAY us delay
  59  * between each attampt. When the busy bit is still set at that time,
  60  * the access attempt is considered to have failed,
  61  * and we will print an error.
  62  * The _lock versions must be used if you already hold the csr_mutex
  63  */
  64 #define WAIT_FOR_BBP(__dev, __reg) \
  65         rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
  66 #define WAIT_FOR_RFCSR(__dev, __reg) \
  67         rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
  68 #define WAIT_FOR_RF(__dev, __reg) \
  69         rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
  70 #define WAIT_FOR_MCU(__dev, __reg) \
  71         rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  72                             H2M_MAILBOX_CSR_OWNER, (__reg))
  73
  74 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
  75                              const unsigned int word, const u8 value)
  76 {
  77         u32 reg;
  78
  79         mutex_lock(&rt2x00dev->csr_mutex);
  80
  81         /*
  82          * Wait until the BBP becomes available, afterwards we
  83          * can safely write the new data into the register.
  84          */
  85         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  86                 reg = 0;
  87                 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
  88                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
  89                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
  90                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
  91                 if (rt2x00_intf_is_pci(rt2x00dev))
  92                         rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
  93
  94                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
  95         }
  96
  97         mutex_unlock(&rt2x00dev->csr_mutex);
  98 }
  99
 100 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
 101                             const unsigned int word, u8 *value)
 102 {
 103         u32 reg;
 104
 105         mutex_lock(&rt2x00dev->csr_mutex);
 106
 107         /*
 108          * Wait until the BBP becomes available, afterwards we
 109          * can safely write the read request into the register.
 110          * After the data has been written, we wait until hardware
 111          * returns the correct value, if at any time the register
 112          * doesn't become available in time, reg will be 0xffffffff
 113          * which means we return 0xff to the caller.
 114          */
 115         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 116                 reg = 0;
 117                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 118                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 119                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
 120                 if (rt2x00_intf_is_pci(rt2x00dev))
 121                         rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 122
 123                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 124
 125                 WAIT_FOR_BBP(rt2x00dev, &reg);
 126         }
 127
 128         *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
 129
 130         mutex_unlock(&rt2x00dev->csr_mutex);
 131 }
 132
 133 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
 134                                const unsigned int word, const u8 value)
 135 {
 136         u32 reg;
 137
 138         mutex_lock(&rt2x00dev->csr_mutex);
 139
 140         /*
 141          * Wait until the RFCSR becomes available, afterwards we
 142          * can safely write the new data into the register.
 143          */
 144         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 145                 reg = 0;
 146                 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
 147                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 148                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
 149                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 150
 151                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 152         }
 153
 154         mutex_unlock(&rt2x00dev->csr_mutex);
 155 }
 156
 157 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
 158                               const unsigned int word, u8 *value)
 159 {
 160         u32 reg;
 161
 162         mutex_lock(&rt2x00dev->csr_mutex);
 163
 164         /*
 165          * Wait until the RFCSR becomes available, afterwards we
 166          * can safely write the read request into the register.
 167          * After the data has been written, we wait until hardware
 168          * returns the correct value, if at any time the register
 169          * doesn't become available in time, reg will be 0xffffffff
 170          * which means we return 0xff to the caller.
 171          */
 172         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 173                 reg = 0;
 174                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 175                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
 176                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 177
 178                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 179
 180                 WAIT_FOR_RFCSR(rt2x00dev, &reg);
 181         }
 182
 183         *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
 184
 185         mutex_unlock(&rt2x00dev->csr_mutex);
 186 }
 187
 188 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
 189                             const unsigned int word, const u32 value)
 190 {
 191         u32 reg;
 192
 193         mutex_lock(&rt2x00dev->csr_mutex);
 194
 195         /*
 196          * Wait until the RF becomes available, afterwards we
 197          * can safely write the new data into the register.
 198          */
 199         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 200                 reg = 0;
 201                 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
 202                 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
 203                 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
 204                 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
 205
 206                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
 207                 rt2x00_rf_write(rt2x00dev, word, value);
 208         }
 209
 210         mutex_unlock(&rt2x00dev->csr_mutex);
 211 }
 212
 213 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
 214                         const u8 command, const u8 token,
 215                         const u8 arg0, const u8 arg1)
 216 {
 217         u32 reg;
 218
 219         if (rt2x00_intf_is_pci(rt2x00dev)) {
 220                 /*
 221                 * RT2880 and RT3052 don't support MCU requests.
 222                 */
 223                 if (rt2x00_rt(&rt2x00dev->chip, RT2880) ||
 224                     rt2x00_rt(&rt2x00dev->chip, RT3052))
 225                         return;
 226         }
 227
 228         mutex_lock(&rt2x00dev->csr_mutex);
 229
 230         /*
 231          * Wait until the MCU becomes available, afterwards we
 232          * can safely write the new data into the register.
 233          */
 234         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 235                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 236                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 237                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 238                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 239                 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
 240
 241                 reg = 0;
 242                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 243                 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
 244         }
 245
 246         mutex_unlock(&rt2x00dev->csr_mutex);
 247 }
 248 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
 249
 250 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 251 const struct rt2x00debug rt2800_rt2x00debug = {
 252         .owner  = THIS_MODULE,
 253         .csr    = {
 254                 .read           = rt2800_register_read,
 255                 .write          = rt2800_register_write,
 256                 .flags          = RT2X00DEBUGFS_OFFSET,
 257                 .word_base      = CSR_REG_BASE,
 258                 .word_size      = sizeof(u32),
 259                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 260         },
 261         .eeprom = {
 262                 .read           = rt2x00_eeprom_read,
 263                 .write          = rt2x00_eeprom_write,
 264                 .word_base      = EEPROM_BASE,
 265                 .word_size      = sizeof(u16),
 266                 .word_count     = EEPROM_SIZE / sizeof(u16),
 267         },
 268         .bbp    = {
 269                 .read           = rt2800_bbp_read,
 270                 .write          = rt2800_bbp_write,
 271                 .word_base      = BBP_BASE,
 272                 .word_size      = sizeof(u8),
 273                 .word_count     = BBP_SIZE / sizeof(u8),
 274         },
 275         .rf     = {
 276                 .read           = rt2x00_rf_read,
 277                 .write          = rt2800_rf_write,
 278                 .word_base      = RF_BASE,
 279                 .word_size      = sizeof(u32),
 280                 .word_count     = RF_SIZE / sizeof(u32),
 281         },
 282 };
 283 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
 284 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 285
 286 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 287 {
 288         u32 reg;
 289
 290         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
 291         return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
 292 }
 293 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
 294
 295 #ifdef CONFIG_RT2X00_LIB_LEDS
 296 static void rt2800_brightness_set(struct led_classdev *led_cdev,
 297                                   enum led_brightness brightness)
 298 {
 299         struct rt2x00_led *led =
 300             container_of(led_cdev, struct rt2x00_led, led_dev);
 301         unsigned int enabled = brightness != LED_OFF;
 302         unsigned int bg_mode =
 303             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 304         unsigned int polarity =
 305                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 306                                    EEPROM_FREQ_LED_POLARITY);
 307         unsigned int ledmode =
 308                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 309                                    EEPROM_FREQ_LED_MODE);
 310
 311         if (led->type == LED_TYPE_RADIO) {
 312                 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 313                                       enabled ? 0x20 : 0);
 314         } else if (led->type == LED_TYPE_ASSOC) {
 315                 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 316                                       enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
 317         } else if (led->type == LED_TYPE_QUALITY) {
 318                 /*
 319                  * The brightness is divided into 6 levels (0 - 5),
 320                  * The specs tell us the following levels:
 321                  *      0, 1 ,3, 7, 15, 31
 322                  * to determine the level in a simple way we can simply
 323                  * work with bitshifting:
 324                  *      (1 << level) - 1
 325                  */
 326                 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
 327                                       (1 << brightness / (LED_FULL / 6)) - 1,
 328                                       polarity);
 329         }
 330 }
 331
 332 static int rt2800_blink_set(struct led_classdev *led_cdev,
 333                             unsigned long *delay_on, unsigned long *delay_off)
 334 {
 335         struct rt2x00_led *led =
 336             container_of(led_cdev, struct rt2x00_led, led_dev);
 337         u32 reg;
 338
 339         rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
 340         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
 341         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
 342         rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
 343         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
 344         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 12);
 345         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
 346         rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
 347         rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
 348
 349         return 0;
 350 }
 351
 352 void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
 353                      struct rt2x00_led *led, enum led_type type)
 354 {
 355         led->rt2x00dev = rt2x00dev;
 356         led->type = type;
 357         led->led_dev.brightness_set = rt2800_brightness_set;
 358         led->led_dev.blink_set = rt2800_blink_set;
 359         led->flags = LED_INITIALIZED;
 360 }
 361 EXPORT_SYMBOL_GPL(rt2800_init_led);
 362 #endif /* CONFIG_RT2X00_LIB_LEDS */
 363
 364 /*
 365  * Configuration handlers.
 366  */
 367 static void rt2800_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
 368                                     struct rt2x00lib_crypto *crypto,
 369                                     struct ieee80211_key_conf *key)
 370 {
 371         struct mac_wcid_entry wcid_entry;
 372         struct mac_iveiv_entry iveiv_entry;
 373         u32 offset;
 374         u32 reg;
 375
 376         offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
 377
 378         rt2800_register_read(rt2x00dev, offset, &reg);
 379         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
 380                            !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
 381         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
 382                            (crypto->cmd == SET_KEY) * crypto->cipher);
 383         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
 384                            (crypto->cmd == SET_KEY) * crypto->bssidx);
 385         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
 386         rt2800_register_write(rt2x00dev, offset, reg);
 387
 388         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
 389
 390         memset(&iveiv_entry, 0, sizeof(iveiv_entry));
 391         if ((crypto->cipher == CIPHER_TKIP) ||
 392             (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
 393             (crypto->cipher == CIPHER_AES))
 394                 iveiv_entry.iv[3] |= 0x20;
 395         iveiv_entry.iv[3] |= key->keyidx << 6;
 396         rt2800_register_multiwrite(rt2x00dev, offset,
 397                                       &iveiv_entry, sizeof(iveiv_entry));
 398
 399         offset = MAC_WCID_ENTRY(key->hw_key_idx);
 400
 401         memset(&wcid_entry, 0, sizeof(wcid_entry));
 402         if (crypto->cmd == SET_KEY)
 403                 memcpy(&wcid_entry, crypto->address, ETH_ALEN);
 404         rt2800_register_multiwrite(rt2x00dev, offset,
 405                                       &wcid_entry, sizeof(wcid_entry));
 406 }
 407
 408 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
 409                              struct rt2x00lib_crypto *crypto,
 410                              struct ieee80211_key_conf *key)
 411 {
 412         struct hw_key_entry key_entry;
 413         struct rt2x00_field32 field;
 414         u32 offset;
 415         u32 reg;
 416
 417         if (crypto->cmd == SET_KEY) {
 418                 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
 419
 420                 memcpy(key_entry.key, crypto->key,
 421                        sizeof(key_entry.key));
 422                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 423                        sizeof(key_entry.tx_mic));
 424                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 425                        sizeof(key_entry.rx_mic));
 426
 427                 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
 428                 rt2800_register_multiwrite(rt2x00dev, offset,
 429                                               &key_entry, sizeof(key_entry));
 430         }
 431
 432         /*
 433          * The cipher types are stored over multiple registers
 434          * starting with SHARED_KEY_MODE_BASE each word will have
 435          * 32 bits and contains the cipher types for 2 bssidx each.
 436          * Using the correct defines correctly will cause overhead,
 437          * so just calculate the correct offset.
 438          */
 439         field.bit_offset = 4 * (key->hw_key_idx % 8);
 440         field.bit_mask = 0x7 << field.bit_offset;
 441
 442         offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
 443
 444         rt2800_register_read(rt2x00dev, offset, &reg);
 445         rt2x00_set_field32(&reg, field,
 446                            (crypto->cmd == SET_KEY) * crypto->cipher);
 447         rt2800_register_write(rt2x00dev, offset, reg);
 448
 449         /*
 450          * Update WCID information
 451          */
 452         rt2800_config_wcid_attr(rt2x00dev, crypto, key);
 453
 454         return 0;
 455 }
 456 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
 457
 458 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
 459                                struct rt2x00lib_crypto *crypto,
 460                                struct ieee80211_key_conf *key)
 461 {
 462         struct hw_key_entry key_entry;
 463         u32 offset;
 464
 465         if (crypto->cmd == SET_KEY) {
 466                 /*
 467                  * 1 pairwise key is possible per AID, this means that the AID
 468                  * equals our hw_key_idx. Make sure the WCID starts _after_ the
 469                  * last possible shared key entry.
 470                  */
 471                 if (crypto->aid > (256 - 32))
 472                         return -ENOSPC;
 473
 474                 key->hw_key_idx = 32 + crypto->aid;
 475
 476                 memcpy(key_entry.key, crypto->key,
 477                        sizeof(key_entry.key));
 478                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 479                        sizeof(key_entry.tx_mic));
 480                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 481                        sizeof(key_entry.rx_mic));
 482
 483                 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
 484                 rt2800_register_multiwrite(rt2x00dev, offset,
 485                                               &key_entry, sizeof(key_entry));
 486         }
 487
 488         /*
 489          * Update WCID information
 490          */
 491         rt2800_config_wcid_attr(rt2x00dev, crypto, key);
 492
 493         return 0;
 494 }
 495 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
 496
 497 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
 498                           const unsigned int filter_flags)
 499 {
 500         u32 reg;
 501
 502         /*
 503          * Start configuration steps.
 504          * Note that the version error will always be dropped
 505          * and broadcast frames will always be accepted since
 506          * there is no filter for it at this time.
 507          */
 508         rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
 509         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
 510                            !(filter_flags & FIF_FCSFAIL));
 511         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
 512                            !(filter_flags & FIF_PLCPFAIL));
 513         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
 514                            !(filter_flags & FIF_PROMISC_IN_BSS));
 515         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
 516         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
 517         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
 518                            !(filter_flags & FIF_ALLMULTI));
 519         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
 520         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
 521         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
 522                            !(filter_flags & FIF_CONTROL));
 523         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
 524                            !(filter_flags & FIF_CONTROL));
 525         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
 526                            !(filter_flags & FIF_CONTROL));
 527         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
 528                            !(filter_flags & FIF_CONTROL));
 529         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
 530                            !(filter_flags & FIF_CONTROL));
 531         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
 532                            !(filter_flags & FIF_PSPOLL));
 533         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
 534         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
 535         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
 536                            !(filter_flags & FIF_CONTROL));
 537         rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
 538 }
 539 EXPORT_SYMBOL_GPL(rt2800_config_filter);
 540
 541 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
 542                         struct rt2x00intf_conf *conf, const unsigned int flags)
 543 {
 544         unsigned int beacon_base;
 545         u32 reg;
 546
 547         if (flags & CONFIG_UPDATE_TYPE) {
 548                 /*
 549                  * Clear current synchronisation setup.
 550                  * For the Beacon base registers we only need to clear
 551                  * the first byte since that byte contains the VALID and OWNER
 552                  * bits which (when set to 0) will invalidate the entire beacon.
 553                  */
 554                 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
 555                 rt2800_register_write(rt2x00dev, beacon_base, 0);
 556
 557                 /*
 558                  * Enable synchronisation.
 559                  */
 560                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 561                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
 562                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
 563                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
 564                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 565         }
 566
 567         if (flags & CONFIG_UPDATE_MAC) {
 568                 reg = le32_to_cpu(conf->mac[1]);
 569                 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
 570                 conf->mac[1] = cpu_to_le32(reg);
 571
 572                 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
 573                                               conf->mac, sizeof(conf->mac));
 574         }
 575
 576         if (flags & CONFIG_UPDATE_BSSID) {
 577                 reg = le32_to_cpu(conf->bssid[1]);
 578                 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
 579                 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
 580                 conf->bssid[1] = cpu_to_le32(reg);
 581
 582                 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
 583                                               conf->bssid, sizeof(conf->bssid));
 584         }
 585 }
 586 EXPORT_SYMBOL_GPL(rt2800_config_intf);
 587
 588 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp)
 589 {
 590         u32 reg;
 591
 592         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
 593         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 0x20);
 594         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
 595
 596         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
 597         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
 598                            !!erp->short_preamble);
 599         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
 600                            !!erp->short_preamble);
 601         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
 602
 603         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
 604         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
 605                            erp->cts_protection ? 2 : 0);
 606         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
 607
 608         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
 609                                  erp->basic_rates);
 610         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
 611
 612         rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
 613         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
 614         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
 615         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
 616
 617         rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
 618         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
 619         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
 620         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
 621         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
 622         rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
 623         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
 624
 625         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 626         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
 627                            erp->beacon_int * 16);
 628         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 629 }
 630 EXPORT_SYMBOL_GPL(rt2800_config_erp);
 631
 632 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
 633 {
 634         u8 r1;
 635         u8 r3;
 636
 637         rt2800_bbp_read(rt2x00dev, 1, &r1);
 638         rt2800_bbp_read(rt2x00dev, 3, &r3);
 639
 640         /*
 641          * Configure the TX antenna.
 642          */
 643         switch ((int)ant->tx) {
 644         case 1:
 645                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
 646                 if (rt2x00_intf_is_pci(rt2x00dev))
 647                         rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
 648                 break;
 649         case 2:
 650                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
 651                 break;
 652         case 3:
 653                 /* Do nothing */
 654                 break;
 655         }
 656
 657         /*
 658          * Configure the RX antenna.
 659          */
 660         switch ((int)ant->rx) {
 661         case 1:
 662                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
 663                 break;
 664         case 2:
 665                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
 666                 break;
 667         case 3:
 668                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
 669                 break;
 670         }
 671
 672         rt2800_bbp_write(rt2x00dev, 3, r3);
 673         rt2800_bbp_write(rt2x00dev, 1, r1);
 674 }
 675 EXPORT_SYMBOL_GPL(rt2800_config_ant);
 676
 677 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
 678                                    struct rt2x00lib_conf *libconf)
 679 {
 680         u16 eeprom;
 681         short lna_gain;
 682
 683         if (libconf->rf.channel <= 14) {
 684                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
 685                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
 686         } else if (libconf->rf.channel <= 64) {
 687                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
 688                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
 689         } else if (libconf->rf.channel <= 128) {
 690                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
 691                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
 692         } else {
 693                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
 694                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
 695         }
 696
 697         rt2x00dev->lna_gain = lna_gain;
 698 }
 699
 700 static void rt2800_config_channel_rt2x(struct rt2x00_dev *rt2x00dev,
 701                                        struct ieee80211_conf *conf,
 702                                        struct rf_channel *rf,
 703                                        struct channel_info *info)
 704 {
 705         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
 706
 707         if (rt2x00dev->default_ant.tx == 1)
 708                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
 709
 710         if (rt2x00dev->default_ant.rx == 1) {
 711                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
 712                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
 713         } else if (rt2x00dev->default_ant.rx == 2)
 714                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
 715
 716         if (rf->channel > 14) {
 717                 /*
 718                  * When TX power is below 0, we should increase it by 7 to
 719                  * make it a positive value (Minumum value is -7).
 720                  * However this means that values between 0 and 7 have
 721                  * double meaning, and we should set a 7DBm boost flag.
 722                  */
 723                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
 724                                    (info->tx_power1 >= 0));
 725
 726                 if (info->tx_power1 < 0)
 727                         info->tx_power1 += 7;
 728
 729                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
 730                                    TXPOWER_A_TO_DEV(info->tx_power1));
 731
 732                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
 733                                    (info->tx_power2 >= 0));
 734
 735                 if (info->tx_power2 < 0)
 736                         info->tx_power2 += 7;
 737
 738                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
 739                                    TXPOWER_A_TO_DEV(info->tx_power2));
 740         } else {
 741                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
 742                                    TXPOWER_G_TO_DEV(info->tx_power1));
 743                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
 744                                    TXPOWER_G_TO_DEV(info->tx_power2));
 745         }
 746
 747         rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
 748
 749         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
 750         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
 751         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 752         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
 753
 754         udelay(200);
 755
 756         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
 757         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
 758         rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
 759         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
 760
 761         udelay(200);
 762
 763         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
 764         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
 765         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 766         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
 767 }
 768
 769 static void rt2800_config_channel_rt3x(struct rt2x00_dev *rt2x00dev,
 770                                        struct ieee80211_conf *conf,
 771                                        struct rf_channel *rf,
 772                                        struct channel_info *info)
 773 {
 774         u8 rfcsr;
 775
 776         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
 777         rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
 778
 779         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
 780         rt2x00_set_field8(&rfcsr, RFCSR6_R, rf->rf2);
 781         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
 782
 783         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
 784         rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
 785                           TXPOWER_G_TO_DEV(info->tx_power1));
 786         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
 787
 788         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
 789         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
 790         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
 791
 792         rt2800_rfcsr_write(rt2x00dev, 24,
 793                               rt2x00dev->calibration[conf_is_ht40(conf)]);
 794
 795         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
 796         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
 797         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
 798 }
 799
 800 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
 801                                   struct ieee80211_conf *conf,
 802                                   struct rf_channel *rf,
 803                                   struct channel_info *info)
 804 {
 805         u32 reg;
 806         unsigned int tx_pin;
 807         u8 bbp;
 808
 809         if (rt2x00_rt(&rt2x00dev->chip, RT3070) &&
 810             (rt2x00_rf(&rt2x00dev->chip, RF2020) ||
 811              rt2x00_rf(&rt2x00dev->chip, RF3020) ||
 812              rt2x00_rf(&rt2x00dev->chip, RF3021) ||
 813              rt2x00_rf(&rt2x00dev->chip, RF3022)))
 814                 rt2800_config_channel_rt3x(rt2x00dev, conf, rf, info);
 815         else
 816                 rt2800_config_channel_rt2x(rt2x00dev, conf, rf, info);
 817
 818         /*
 819          * Change BBP settings
 820          */
 821         rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
 822         rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
 823         rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
 824         rt2800_bbp_write(rt2x00dev, 86, 0);
 825
 826         if (rf->channel <= 14) {
 827                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
 828                         rt2800_bbp_write(rt2x00dev, 82, 0x62);
 829                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
 830                 } else {
 831                         rt2800_bbp_write(rt2x00dev, 82, 0x84);
 832                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
 833                 }
 834         } else {
 835                 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
 836
 837                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
 838                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
 839                 else
 840                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
 841         }
 842
 843         rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
 844         rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_PLUS, conf_is_ht40_plus(conf));
 845         rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
 846         rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
 847         rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
 848
 849         tx_pin = 0;
 850
 851         /* Turn on unused PA or LNA when not using 1T or 1R */
 852         if (rt2x00dev->default_ant.tx != 1) {
 853                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
 854                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
 855         }
 856
 857         /* Turn on unused PA or LNA when not using 1T or 1R */
 858         if (rt2x00dev->default_ant.rx != 1) {
 859                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
 860                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
 861         }
 862
 863         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
 864         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
 865         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
 866         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
 867         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
 868         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
 869
 870         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
 871
 872         rt2800_bbp_read(rt2x00dev, 4, &bbp);
 873         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
 874         rt2800_bbp_write(rt2x00dev, 4, bbp);
 875
 876         rt2800_bbp_read(rt2x00dev, 3, &bbp);
 877         rt2x00_set_field8(&bbp, BBP3_HT40_PLUS, conf_is_ht40_plus(conf));
 878         rt2800_bbp_write(rt2x00dev, 3, bbp);
 879
 880         if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
 881                 if (conf_is_ht40(conf)) {
 882                         rt2800_bbp_write(rt2x00dev, 69, 0x1a);
 883                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
 884                         rt2800_bbp_write(rt2x00dev, 73, 0x16);
 885                 } else {
 886                         rt2800_bbp_write(rt2x00dev, 69, 0x16);
 887                         rt2800_bbp_write(rt2x00dev, 70, 0x08);
 888                         rt2800_bbp_write(rt2x00dev, 73, 0x11);
 889                 }
 890         }
 891
 892         msleep(1);
 893 }
 894
 895 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
 896                                   const int txpower)
 897 {
 898         u32 reg;
 899         u32 value = TXPOWER_G_TO_DEV(txpower);
 900         u8 r1;
 901
 902         rt2800_bbp_read(rt2x00dev, 1, &r1);
 903         rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
 904         rt2800_bbp_write(rt2x00dev, 1, r1);
 905
 906         rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
 907         rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
 908         rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
 909         rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
 910         rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
 911         rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
 912         rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
 913         rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
 914         rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
 915         rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
 916
 917         rt2800_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
 918         rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
 919         rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
 920         rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
 921         rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
 922         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
 923         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
 924         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
 925         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
 926         rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
 927
 928         rt2800_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
 929         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
 930         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
 931         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
 932         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
 933         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
 934         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
 935         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
 936         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
 937         rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
 938
 939         rt2800_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
 940         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
 941         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
 942         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
 943         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
 944         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
 945         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
 946         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
 947         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
 948         rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
 949
 950         rt2800_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
 951         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
 952         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
 953         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
 954         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
 955         rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
 956 }
 957
 958 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
 959                                       struct rt2x00lib_conf *libconf)
 960 {
 961         u32 reg;
 962
 963         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
 964         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
 965                            libconf->conf->short_frame_max_tx_count);
 966         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
 967                            libconf->conf->long_frame_max_tx_count);
 968         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
 969         rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
 970         rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
 971         rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
 972         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
 973 }
 974
 975 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
 976                              struct rt2x00lib_conf *libconf)
 977 {
 978         enum dev_state state =
 979             (libconf->conf->flags & IEEE80211_CONF_PS) ?
 980                 STATE_SLEEP : STATE_AWAKE;
 981         u32 reg;
 982
 983         if (state == STATE_SLEEP) {
 984                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
 985
 986                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
 987                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
 988                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
 989                                    libconf->conf->listen_interval - 1);
 990                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
 991                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
 992
 993                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
 994         } else {
 995                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
 996
 997                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
 998                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
 999                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1000                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1001                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1002         }
1003 }
1004
1005 void rt2800_config(struct rt2x00_dev *rt2x00dev,
1006                    struct rt2x00lib_conf *libconf,
1007                    const unsigned int flags)
1008 {
1009         /* Always recalculate LNA gain before changing configuration */
1010         rt2800_config_lna_gain(rt2x00dev, libconf);
1011
1012         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1013                 rt2800_config_channel(rt2x00dev, libconf->conf,
1014                                       &libconf->rf, &libconf->channel);
1015         if (flags & IEEE80211_CONF_CHANGE_POWER)
1016                 rt2800_config_txpower(rt2x00dev, libconf->conf->power_level);
1017         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1018                 rt2800_config_retry_limit(rt2x00dev, libconf);
1019         if (flags & IEEE80211_CONF_CHANGE_PS)
1020                 rt2800_config_ps(rt2x00dev, libconf);
1021 }
1022 EXPORT_SYMBOL_GPL(rt2800_config);
1023
1024 /*
1025  * Link tuning
1026  */
1027 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1028 {
1029         u32 reg;
1030
1031         /*
1032          * Update FCS error count from register.
1033          */
1034         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1035         qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1036 }
1037 EXPORT_SYMBOL_GPL(rt2800_link_stats);
1038
1039 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1040 {
1041         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1042                 if (rt2x00_intf_is_usb(rt2x00dev) &&
1043                     rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION)
1044                         return 0x1c + (2 * rt2x00dev->lna_gain);
1045                 else
1046                         return 0x2e + rt2x00dev->lna_gain;
1047         }
1048
1049         if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1050                 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1051         else
1052                 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1053 }
1054
1055 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
1056                                   struct link_qual *qual, u8 vgc_level)
1057 {
1058         if (qual->vgc_level != vgc_level) {
1059                 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
1060                 qual->vgc_level = vgc_level;
1061                 qual->vgc_level_reg = vgc_level;
1062         }
1063 }
1064
1065 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
1066 {
1067         rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
1068 }
1069 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
1070
1071 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
1072                        const u32 count)
1073 {
1074         if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION)
1075                 return;
1076
1077         /*
1078          * When RSSI is better then -80 increase VGC level with 0x10
1079          */
1080         rt2800_set_vgc(rt2x00dev, qual,
1081                        rt2800_get_default_vgc(rt2x00dev) +
1082                        ((qual->rssi > -80) * 0x10));
1083 }
1084 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
1085
1086 /*
1087  * Initialization functions.
1088  */
1089 int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1090 {
1091         u32 reg;
1092         unsigned int i;
1093
1094         if (rt2x00_intf_is_usb(rt2x00dev)) {
1095                 /*
1096                  * Wait until BBP and RF are ready.
1097                  */
1098                 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1099                         rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
1100                         if (reg && reg != ~0)
1101                                 break;
1102                         msleep(1);
1103                 }
1104
1105                 if (i == REGISTER_BUSY_COUNT) {
1106                         ERROR(rt2x00dev, "Unstable hardware.\n");
1107                         return -EBUSY;
1108                 }
1109
1110                 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1111                 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL,
1112                                       reg & ~0x00002000);
1113         } else if (rt2x00_intf_is_pci(rt2x00dev))
1114                 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1115
1116         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1117         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1118         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1119         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1120
1121         if (rt2x00_intf_is_usb(rt2x00dev)) {
1122                 rt2800_register_write(rt2x00dev, USB_DMA_CFG, 0x00000000);
1123 #ifdef CONFIG_RT2800USB
1124                 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
1125                                             USB_MODE_RESET, REGISTER_TIMEOUT);
1126 #endif
1127         }
1128
1129         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1130
1131         rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1132         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1133         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1134         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1135         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1136         rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
1137
1138         rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1139         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1140         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1141         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1142         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1143         rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
1144
1145         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1146         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1147
1148         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1149
1150         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1151         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1152         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1153         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1154         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1155         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1156         rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1157         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1158
1159         if (rt2x00_intf_is_usb(rt2x00dev) &&
1160             rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
1161                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1162                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1163                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1164         } else {
1165                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1166                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1167         }
1168
1169         rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1170         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1171         rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1172         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1173         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1174         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1175         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1176         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1177         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1178         rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
1179
1180         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1181         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1182         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1183         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1184
1185         rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1186         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1187         if (rt2x00_rev(&rt2x00dev->chip) >= RT2880E_VERSION &&
1188             rt2x00_rev(&rt2x00dev->chip) < RT3070_VERSION)
1189                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1190         else
1191                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1192         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1193         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1194         rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1195
1196         rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1197
1198         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1199         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1200         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1201         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1202         rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1203         rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1204         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1205
1206         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1207         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 8);
1208         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1209         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1210         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1211         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1212         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1213         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1214         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1215         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1216         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1217
1218         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1219         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 8);
1220         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1221         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1222         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1223         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1224         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1225         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1226         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1227         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1228         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1229
1230         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1231         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1232         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1233         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1234         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1235         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1236         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1237         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1238         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1239         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1240         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1241
1242         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1243         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1244         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
1245         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1246         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1247         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1248         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1249         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1250         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1251         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1252         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1253
1254         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1255         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1256         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1257         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1258         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1259         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1260         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1261         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1262         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1263         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1264         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1265
1266         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1267         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1268         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1269         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1270         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1271         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1272         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1273         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1274         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1275         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1276         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1277
1278         if (rt2x00_intf_is_usb(rt2x00dev)) {
1279                 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
1280
1281                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1282                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1283                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1284                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1285                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1286                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
1287                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
1288                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
1289                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
1290                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
1291                 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1292         }
1293
1294         rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1295         rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1296
1297         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1298         rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1299         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1300                            IEEE80211_MAX_RTS_THRESHOLD);
1301         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1302         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
1303
1304         rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1305         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1306
1307         /*
1308          * ASIC will keep garbage value after boot, clear encryption keys.
1309          */
1310         for (i = 0; i < 4; i++)
1311                 rt2800_register_write(rt2x00dev,
1312                                          SHARED_KEY_MODE_ENTRY(i), 0);
1313
1314         for (i = 0; i < 256; i++) {
1315                 u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1316                 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1317                                               wcid, sizeof(wcid));
1318
1319                 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1320                 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1321         }
1322
1323         /*
1324          * Clear all beacons
1325          * For the Beacon base registers we only need to clear
1326          * the first byte since that byte contains the VALID and OWNER
1327          * bits which (when set to 0) will invalidate the entire beacon.
1328          */
1329         rt2800_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1330         rt2800_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1331         rt2800_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1332         rt2800_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1333         rt2800_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1334         rt2800_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1335         rt2800_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1336         rt2800_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1337
1338         if (rt2x00_intf_is_usb(rt2x00dev)) {
1339                 rt2800_register_read(rt2x00dev, USB_CYC_CFG, &reg);
1340                 rt2x00_set_field32(&reg, USB_CYC_CFG_CLOCK_CYCLE, 30);
1341                 rt2800_register_write(rt2x00dev, USB_CYC_CFG, reg);
1342         }
1343
1344         rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1345         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1346         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1347         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1348         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1349         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1350         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1351         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1352         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1353         rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1354
1355         rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1356         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1357         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1358         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1359         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1360         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1361         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1362         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1363         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1364         rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1365
1366         rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1367         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1368         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1369         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
1370         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
1371         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
1372         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
1373         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
1374         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
1375         rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1376
1377         rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1378         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1379         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1380         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1381         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1382         rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1383
1384         /*
1385          * We must clear the error counters.
1386          * These registers are cleared on read,
1387          * so we may pass a useless variable to store the value.
1388          */
1389         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1390         rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1391         rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1392         rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1393         rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1394         rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1395
1396         return 0;
1397 }
1398 EXPORT_SYMBOL_GPL(rt2800_init_registers);
1399
1400 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1401 {
1402         unsigned int i;
1403         u32 reg;
1404
1405         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1406                 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1407                 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1408                         return 0;
1409
1410                 udelay(REGISTER_BUSY_DELAY);
1411         }
1412
1413         ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1414         return -EACCES;
1415 }
1416
1417 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1418 {
1419         unsigned int i;
1420         u8 value;
1421
1422         /*
1423          * BBP was enabled after firmware was loaded,
1424          * but we need to reactivate it now.
1425          */
1426         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1427         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1428         msleep(1);
1429
1430         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1431                 rt2800_bbp_read(rt2x00dev, 0, &value);
1432                 if ((value != 0xff) && (value != 0x00))
1433                         return 0;
1434                 udelay(REGISTER_BUSY_DELAY);
1435         }
1436
1437         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1438         return -EACCES;
1439 }
1440
1441 int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
1442 {
1443         unsigned int i;
1444         u16 eeprom;
1445         u8 reg_id;
1446         u8 value;
1447
1448         if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
1449                      rt2800_wait_bbp_ready(rt2x00dev)))
1450                 return -EACCES;
1451
1452         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
1453         rt2800_bbp_write(rt2x00dev, 66, 0x38);
1454         rt2800_bbp_write(rt2x00dev, 69, 0x12);
1455         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1456         rt2800_bbp_write(rt2x00dev, 73, 0x10);
1457         rt2800_bbp_write(rt2x00dev, 81, 0x37);
1458         rt2800_bbp_write(rt2x00dev, 82, 0x62);
1459         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
1460         rt2800_bbp_write(rt2x00dev, 84, 0x99);
1461         rt2800_bbp_write(rt2x00dev, 86, 0x00);
1462         rt2800_bbp_write(rt2x00dev, 91, 0x04);
1463         rt2800_bbp_write(rt2x00dev, 92, 0x00);
1464         rt2800_bbp_write(rt2x00dev, 103, 0x00);
1465         rt2800_bbp_write(rt2x00dev, 105, 0x05);
1466
1467         if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
1468                 rt2800_bbp_write(rt2x00dev, 69, 0x16);
1469                 rt2800_bbp_write(rt2x00dev, 73, 0x12);
1470         }
1471
1472         if (rt2x00_rev(&rt2x00dev->chip) > RT2860D_VERSION)
1473                 rt2800_bbp_write(rt2x00dev, 84, 0x19);
1474
1475         if (rt2x00_intf_is_usb(rt2x00dev) &&
1476             rt2x00_rev(&rt2x00dev->chip) == RT3070_VERSION) {
1477                 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1478                 rt2800_bbp_write(rt2x00dev, 84, 0x99);
1479                 rt2800_bbp_write(rt2x00dev, 105, 0x05);
1480         }
1481
1482         if (rt2x00_intf_is_pci(rt2x00dev) &&
1483             rt2x00_rt(&rt2x00dev->chip, RT3052)) {
1484                 rt2800_bbp_write(rt2x00dev, 31, 0x08);
1485                 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
1486                 rt2800_bbp_write(rt2x00dev, 80, 0x08);
1487         }
1488
1489         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1490                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1491
1492                 if (eeprom != 0xffff && eeprom != 0x0000) {
1493                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1494                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1495                         rt2800_bbp_write(rt2x00dev, reg_id, value);
1496                 }
1497         }
1498
1499         return 0;
1500 }
1501 EXPORT_SYMBOL_GPL(rt2800_init_bbp);
1502
1503 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
1504                                 bool bw40, u8 rfcsr24, u8 filter_target)
1505 {
1506         unsigned int i;
1507         u8 bbp;
1508         u8 rfcsr;
1509         u8 passband;
1510         u8 stopband;
1511         u8 overtuned = 0;
1512
1513         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1514
1515         rt2800_bbp_read(rt2x00dev, 4, &bbp);
1516         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
1517         rt2800_bbp_write(rt2x00dev, 4, bbp);
1518
1519         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
1520         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
1521         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
1522
1523         /*
1524          * Set power & frequency of passband test tone
1525          */
1526         rt2800_bbp_write(rt2x00dev, 24, 0);
1527
1528         for (i = 0; i < 100; i++) {
1529                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
1530                 msleep(1);
1531
1532                 rt2800_bbp_read(rt2x00dev, 55, &passband);
1533                 if (passband)
1534                         break;
1535         }
1536
1537         /*
1538          * Set power & frequency of stopband test tone
1539          */
1540         rt2800_bbp_write(rt2x00dev, 24, 0x06);
1541
1542         for (i = 0; i < 100; i++) {
1543                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
1544                 msleep(1);
1545
1546                 rt2800_bbp_read(rt2x00dev, 55, &stopband);
1547
1548                 if ((passband - stopband) <= filter_target) {
1549                         rfcsr24++;
1550                         overtuned += ((passband - stopband) == filter_target);
1551                 } else
1552                         break;
1553
1554                 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1555         }
1556
1557         rfcsr24 -= !!overtuned;
1558
1559         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1560         return rfcsr24;
1561 }
1562
1563 int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1564 {
1565         u8 rfcsr;
1566         u8 bbp;
1567
1568         if (rt2x00_intf_is_usb(rt2x00dev) &&
1569             rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
1570                 return 0;
1571
1572         if (rt2x00_intf_is_pci(rt2x00dev)) {
1573                 if (!rt2x00_rf(&rt2x00dev->chip, RF3020) &&
1574                     !rt2x00_rf(&rt2x00dev->chip, RF3021) &&
1575                     !rt2x00_rf(&rt2x00dev->chip, RF3022))
1576                         return 0;
1577         }
1578
1579         /*
1580          * Init RF calibration.
1581          */
1582         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1583         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1584         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1585         msleep(1);
1586         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1587         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1588
1589         if (rt2x00_intf_is_usb(rt2x00dev)) {
1590                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1591                 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
1592                 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
1593                 rt2800_rfcsr_write(rt2x00dev, 7, 0x70);
1594                 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
1595                 rt2800_rfcsr_write(rt2x00dev, 10, 0x71);
1596                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1597                 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
1598                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1599                 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
1600                 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
1601                 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
1602                 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
1603                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
1604                 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
1605                 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
1606                 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
1607                 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1608                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
1609                 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
1610         } else if (rt2x00_intf_is_pci(rt2x00dev)) {
1611                 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
1612                 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
1613                 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
1614                 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
1615                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1616                 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
1617                 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
1618                 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
1619                 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
1620                 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
1621                 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
1622                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1623                 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
1624                 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
1625                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1626                 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
1627                 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
1628                 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
1629                 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
1630                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
1631                 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
1632                 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
1633                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
1634                 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
1635                 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
1636                 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1637                 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
1638                 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
1639                 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
1640                 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
1641         }
1642
1643         /*
1644          * Set RX Filter calibration for 20MHz and 40MHz
1645          */
1646         rt2x00dev->calibration[0] =
1647             rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
1648         rt2x00dev->calibration[1] =
1649             rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
1650
1651         /*
1652          * Set back to initial state
1653          */
1654         rt2800_bbp_write(rt2x00dev, 24, 0);
1655
1656         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
1657         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
1658         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
1659
1660         /*
1661          * set BBP back to BW20
1662          */
1663         rt2800_bbp_read(rt2x00dev, 4, &bbp);
1664         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
1665         rt2800_bbp_write(rt2x00dev, 4, bbp);
1666
1667         return 0;
1668 }
1669 EXPORT_SYMBOL_GPL(rt2800_init_rfcsr);
1670
1671 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
1672 {
1673         u32 reg;
1674
1675         rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
1676
1677         return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
1678 }
1679 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
1680
1681 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
1682 {
1683         u32 reg;
1684
1685         rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
1686         rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
1687         rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
1688         rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
1689         rt2800_register_write(rt2x00dev, EFUSE_CTRL, reg);
1690
1691         /* Wait until the EEPROM has been loaded */
1692         rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
1693
1694         /* Apparently the data is read from end to start */
1695         rt2800_register_read(rt2x00dev, EFUSE_DATA3,
1696                                 (u32 *)&rt2x00dev->eeprom[i]);
1697         rt2800_register_read(rt2x00dev, EFUSE_DATA2,
1698                                 (u32 *)&rt2x00dev->eeprom[i + 2]);
1699         rt2800_register_read(rt2x00dev, EFUSE_DATA1,
1700                                 (u32 *)&rt2x00dev->eeprom[i + 4]);
1701         rt2800_register_read(rt2x00dev, EFUSE_DATA0,
1702                                 (u32 *)&rt2x00dev->eeprom[i + 6]);
1703 }
1704
1705 void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
1706 {
1707         unsigned int i;
1708
1709         for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
1710                 rt2800_efuse_read(rt2x00dev, i);
1711 }
1712 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
1713
1714 int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1715 {
1716         u16 word;
1717         u8 *mac;
1718         u8 default_lna_gain;
1719
1720         /*
1721          * Start validation of the data that has been read.
1722          */
1723         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1724         if (!is_valid_ether_addr(mac)) {
1725                 random_ether_addr(mac);
1726                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
1727         }
1728
1729         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1730         if (word == 0xffff) {
1731                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
1732                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
1733                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
1734                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1735                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1736         } else if (rt2x00_rev(&rt2x00dev->chip) < RT2883_VERSION) {
1737                 /*
1738                  * There is a max of 2 RX streams for RT28x0 series
1739                  */
1740                 if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
1741                         rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
1742                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1743         }
1744
1745         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1746         if (word == 0xffff) {
1747                 rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
1748                 rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
1749                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
1750                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
1751                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1752                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
1753                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
1754                 rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
1755                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
1756                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
1757                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1758                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1759         }
1760
1761         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1762         if ((word & 0x00ff) == 0x00ff) {
1763                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1764                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
1765                                    LED_MODE_TXRX_ACTIVITY);
1766                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
1767                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1768                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
1769                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
1770                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
1771                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1772         }
1773
1774         /*
1775          * During the LNA validation we are going to use
1776          * lna0 as correct value. Note that EEPROM_LNA
1777          * is never validated.
1778          */
1779         rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
1780         default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
1781
1782         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
1783         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
1784                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
1785         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
1786                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
1787         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
1788
1789         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
1790         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
1791                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
1792         if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
1793             rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
1794                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
1795                                    default_lna_gain);
1796         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
1797
1798         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
1799         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
1800                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
1801         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
1802                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
1803         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
1804
1805         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
1806         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
1807                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
1808         if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
1809             rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
1810                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
1811                                    default_lna_gain);
1812         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
1813
1814         return 0;
1815 }
1816 EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
1817
1818 int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
1819 {
1820         u32 reg;
1821         u16 value;
1822         u16 eeprom;
1823
1824         /*
1825          * Read EEPROM word for configuration.
1826          */
1827         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1828
1829         /*
1830          * Identify RF chipset.
1831          */
1832         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1833         rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
1834
1835         rt2x00_set_chip_rf(rt2x00dev, value, reg);
1836
1837         if (rt2x00_intf_is_usb(rt2x00dev)) {
1838                 struct rt2x00_chip *chip = &rt2x00dev->chip;
1839
1840                 /*
1841                  * The check for rt2860 is not a typo, some rt2870 hardware
1842                  * identifies itself as rt2860 in the CSR register.
1843                  */
1844                 if (rt2x00_check_rev(chip, 0xfff00000, 0x28600000) ||
1845                     rt2x00_check_rev(chip, 0xfff00000, 0x28700000) ||
1846                     rt2x00_check_rev(chip, 0xfff00000, 0x28800000)) {
1847                         rt2x00_set_chip_rt(rt2x00dev, RT2870);
1848                 } else if (rt2x00_check_rev(chip, 0xffff0000, 0x30700000)) {
1849                         rt2x00_set_chip_rt(rt2x00dev, RT3070);
1850                 } else {
1851                         ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
1852                         return -ENODEV;
1853                 }
1854         }
1855
1856         if (!rt2x00_rf(&rt2x00dev->chip, RF2820) &&
1857             !rt2x00_rf(&rt2x00dev->chip, RF2850) &&
1858             !rt2x00_rf(&rt2x00dev->chip, RF2720) &&
1859             !rt2x00_rf(&rt2x00dev->chip, RF2750) &&
1860             !rt2x00_rf(&rt2x00dev->chip, RF3020) &&
1861             !rt2x00_rf(&rt2x00dev->chip, RF2020) &&
1862             !rt2x00_rf(&rt2x00dev->chip, RF3021) &&
1863             !rt2x00_rf(&rt2x00dev->chip, RF3022)) {
1864                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1865                 return -ENODEV;
1866         }
1867
1868         /*
1869          * Identify default antenna configuration.
1870          */
1871         rt2x00dev->default_ant.tx =
1872             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH);
1873         rt2x00dev->default_ant.rx =
1874             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH);
1875
1876         /*
1877          * Read frequency offset and RF programming sequence.
1878          */
1879         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1880         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1881
1882         /*
1883          * Read external LNA informations.
1884          */
1885         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1886
1887         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
1888                 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1889         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
1890                 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1891
1892         /*
1893          * Detect if this device has an hardware controlled radio.
1894          */
1895         if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
1896                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1897
1898         /*
1899          * Store led settings, for correct led behaviour.
1900          */
1901 #ifdef CONFIG_RT2X00_LIB_LEDS
1902         rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1903         rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
1904         rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
1905
1906         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
1907 #endif /* CONFIG_RT2X00_LIB_LEDS */
1908
1909         return 0;
1910 }
1911 EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
1912
1913 /*
1914  * RF value list for rt28x0
1915  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
1916  */
1917 static const struct rf_channel rf_vals[] = {
1918         { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
1919         { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
1920         { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
1921         { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
1922         { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
1923         { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
1924         { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
1925         { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
1926         { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
1927         { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
1928         { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
1929         { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
1930         { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
1931         { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
1932
1933         /* 802.11 UNI / HyperLan 2 */
1934         { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
1935         { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
1936         { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
1937         { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
1938         { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
1939         { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
1940         { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
1941         { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
1942         { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
1943         { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
1944         { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
1945         { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
1946
1947         /* 802.11 HyperLan 2 */
1948         { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
1949         { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
1950         { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
1951         { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
1952         { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
1953         { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
1954         { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
1955         { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
1956         { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
1957         { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
1958         { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
1959         { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
1960         { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
1961         { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
1962         { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
1963         { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
1964
1965         /* 802.11 UNII */
1966         { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
1967         { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
1968         { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
1969         { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
1970         { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
1971         { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
1972         { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
1973         { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
1974         { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
1975         { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
1976         { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
1977
1978         /* 802.11 Japan */
1979         { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
1980         { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
1981         { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
1982         { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
1983         { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
1984         { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
1985         { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
1986 };
1987
1988 /*
1989  * RF value list for rt3070
1990  * Supports: 2.4 GHz
1991  */
1992 static const struct rf_channel rf_vals_3070[] = {
1993         {1,  241, 2, 2 },
1994         {2,  241, 2, 7 },
1995         {3,  242, 2, 2 },
1996         {4,  242, 2, 7 },
1997         {5,  243, 2, 2 },
1998         {6,  243, 2, 7 },
1999         {7,  244, 2, 2 },
2000         {8,  244, 2, 7 },
2001         {9,  245, 2, 2 },
2002         {10, 245, 2, 7 },
2003         {11, 246, 2, 2 },
2004         {12, 246, 2, 7 },
2005         {13, 247, 2, 2 },
2006         {14, 248, 2, 4 },
2007 };
2008
2009 int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2010 {
2011         struct rt2x00_chip *chip = &rt2x00dev->chip;
2012         struct hw_mode_spec *spec = &rt2x00dev->spec;
2013         struct channel_info *info;
2014         char *tx_power1;
2015         char *tx_power2;
2016         unsigned int i;
2017         u16 eeprom;
2018
2019         /*
2020          * Initialize all hw fields.
2021          */
2022         rt2x00dev->hw->flags =
2023             IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2024             IEEE80211_HW_SIGNAL_DBM |
2025             IEEE80211_HW_SUPPORTS_PS |
2026             IEEE80211_HW_PS_NULLFUNC_STACK;
2027
2028         if (rt2x00_intf_is_usb(rt2x00dev))
2029                 rt2x00dev->hw->extra_tx_headroom =
2030                         TXINFO_DESC_SIZE + TXWI_DESC_SIZE;
2031         else if (rt2x00_intf_is_pci(rt2x00dev))
2032                 rt2x00dev->hw->extra_tx_headroom = TXWI_DESC_SIZE;
2033
2034         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2035         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2036                                 rt2x00_eeprom_addr(rt2x00dev,
2037                                                    EEPROM_MAC_ADDR_0));
2038
2039         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2040
2041         /*
2042          * Initialize hw_mode information.
2043          */
2044         spec->supported_bands = SUPPORT_BAND_2GHZ;
2045         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2046
2047         if (rt2x00_rf(chip, RF2820) ||
2048             rt2x00_rf(chip, RF2720) ||
2049             (rt2x00_intf_is_pci(rt2x00dev) &&
2050              (rt2x00_rf(chip, RF3020) ||
2051               rt2x00_rf(chip, RF3021) ||
2052               rt2x00_rf(chip, RF3022) ||
2053               rt2x00_rf(chip, RF2020) ||
2054               rt2x00_rf(chip, RF3052)))) {
2055                 spec->num_channels = 14;
2056                 spec->channels = rf_vals;
2057         } else if (rt2x00_rf(chip, RF2850) ||
2058                    rt2x00_rf(chip, RF2750)) {
2059                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2060                 spec->num_channels = ARRAY_SIZE(rf_vals);
2061                 spec->channels = rf_vals;
2062         } else if (rt2x00_intf_is_usb(rt2x00dev) &&
2063                     (rt2x00_rf(chip, RF3020) ||
2064                      rt2x00_rf(chip, RF2020) ||
2065                      rt2x00_rf(chip, RF3021) ||
2066                      rt2x00_rf(chip, RF3022))) {
2067                 spec->num_channels = ARRAY_SIZE(rf_vals_3070);
2068                 spec->channels = rf_vals_3070;
2069         }
2070
2071         /*
2072          * Initialize HT information.
2073          */
2074         spec->ht.ht_supported = true;
2075         spec->ht.cap =
2076             IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
2077             IEEE80211_HT_CAP_GRN_FLD |
2078             IEEE80211_HT_CAP_SGI_20 |
2079             IEEE80211_HT_CAP_SGI_40 |
2080             IEEE80211_HT_CAP_TX_STBC |
2081             IEEE80211_HT_CAP_RX_STBC |
2082             IEEE80211_HT_CAP_PSMP_SUPPORT;
2083         spec->ht.ampdu_factor = 3;
2084         spec->ht.ampdu_density = 4;
2085         spec->ht.mcs.tx_params =
2086             IEEE80211_HT_MCS_TX_DEFINED |
2087             IEEE80211_HT_MCS_TX_RX_DIFF |
2088             ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
2089                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
2090
2091         switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
2092         case 3:
2093                 spec->ht.mcs.rx_mask[2] = 0xff;
2094         case 2:
2095                 spec->ht.mcs.rx_mask[1] = 0xff;
2096         case 1:
2097                 spec->ht.mcs.rx_mask[0] = 0xff;
2098                 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
2099                 break;
2100         }
2101
2102         /*
2103          * Create channel information array
2104          */
2105         info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2106         if (!info)
2107                 return -ENOMEM;
2108
2109         spec->channels_info = info;
2110
2111         tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2112         tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2113
2114         for (i = 0; i < 14; i++) {
2115                 info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
2116                 info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
2117         }
2118
2119         if (spec->num_channels > 14) {
2120                 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2121                 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2122
2123                 for (i = 14; i < spec->num_channels; i++) {
2124                         info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
2125                         info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
2126                 }
2127         }
2128
2129         return 0;
2130 }
2131 EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
2132
2133 /*
2134  * IEEE80211 stack callback functions.
2135  */
2136 static void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
2137                                 u32 *iv32, u16 *iv16)
2138 {
2139         struct rt2x00_dev *rt2x00dev = hw->priv;
2140         struct mac_iveiv_entry iveiv_entry;
2141         u32 offset;
2142
2143         offset = MAC_IVEIV_ENTRY(hw_key_idx);
2144         rt2800_register_multiread(rt2x00dev, offset,
2145                                       &iveiv_entry, sizeof(iveiv_entry));
2146
2147         memcpy(&iveiv_entry.iv[0], iv16, sizeof(iv16));
2148         memcpy(&iveiv_entry.iv[4], iv32, sizeof(iv32));
2149 }
2150
2151 static int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2152 {
2153         struct rt2x00_dev *rt2x00dev = hw->priv;
2154         u32 reg;
2155         bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
2156
2157         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2158         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
2159         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
2160
2161         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2162         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
2163         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2164
2165         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2166         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
2167         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2168
2169         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2170         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
2171         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2172
2173         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2174         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
2175         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2176
2177         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2178         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
2179         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2180
2181         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2182         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
2183         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2184
2185         return 0;
2186 }
2187
2188 static int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2189                           const struct ieee80211_tx_queue_params *params)
2190 {
2191         struct rt2x00_dev *rt2x00dev = hw->priv;
2192         struct data_queue *queue;
2193         struct rt2x00_field32 field;
2194         int retval;
2195         u32 reg;
2196         u32 offset;
2197
2198         /*
2199          * First pass the configuration through rt2x00lib, that will
2200          * update the queue settings and validate the input. After that
2201          * we are free to update the registers based on the value
2202          * in the queue parameter.
2203          */
2204         retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2205         if (retval)
2206                 return retval;
2207
2208         /*
2209          * We only need to perform additional register initialization
2210          * for WMM queues/
2211          */
2212         if (queue_idx >= 4)
2213                 return 0;
2214
2215         queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2216
2217         /* Update WMM TXOP register */
2218         offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
2219         field.bit_offset = (queue_idx & 1) * 16;
2220         field.bit_mask = 0xffff << field.bit_offset;
2221
2222         rt2800_register_read(rt2x00dev, offset, &reg);
2223         rt2x00_set_field32(&reg, field, queue->txop);
2224         rt2800_register_write(rt2x00dev, offset, reg);
2225
2226         /* Update WMM registers */
2227         field.bit_offset = queue_idx * 4;
2228         field.bit_mask = 0xf << field.bit_offset;
2229
2230         rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
2231         rt2x00_set_field32(&reg, field, queue->aifs);
2232         rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
2233
2234         rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
2235         rt2x00_set_field32(&reg, field, queue->cw_min);
2236         rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
2237
2238         rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
2239         rt2x00_set_field32(&reg, field, queue->cw_max);
2240         rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
2241
2242         /* Update EDCA registers */
2243         offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
2244
2245         rt2800_register_read(rt2x00dev, offset, &reg);
2246         rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
2247         rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
2248         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
2249         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
2250         rt2800_register_write(rt2x00dev, offset, reg);
2251
2252         return 0;
2253 }
2254
2255 static u64 rt2800_get_tsf(struct ieee80211_hw *hw)
2256 {
2257         struct rt2x00_dev *rt2x00dev = hw->priv;
2258         u64 tsf;
2259         u32 reg;
2260
2261         rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
2262         tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
2263         rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
2264         tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
2265
2266         return tsf;
2267 }
2268
2269 const struct ieee80211_ops rt2800_mac80211_ops = {
2270         .tx                     = rt2x00mac_tx,
2271         .start                  = rt2x00mac_start,
2272         .stop                   = rt2x00mac_stop,
2273         .add_interface          = rt2x00mac_add_interface,
2274         .remove_interface       = rt2x00mac_remove_interface,
2275         .config                 = rt2x00mac_config,
2276         .configure_filter       = rt2x00mac_configure_filter,
2277         .set_tim                = rt2x00mac_set_tim,
2278         .set_key                = rt2x00mac_set_key,
2279         .get_stats              = rt2x00mac_get_stats,
2280         .get_tkip_seq           = rt2800_get_tkip_seq,
2281         .set_rts_threshold      = rt2800_set_rts_threshold,
2282         .bss_info_changed       = rt2x00mac_bss_info_changed,
2283         .conf_tx                = rt2800_conf_tx,
2284         .get_tx_stats           = rt2x00mac_get_tx_stats,
2285         .get_tsf                = rt2800_get_tsf,
2286         .rfkill_poll            = rt2x00mac_rfkill_poll,
2287 };
2288 EXPORT_SYMBOL_GPL(rt2800_mac80211_ops);