drivers/net/wireless/rt2x00/rt2400pci.c

   1 /*
   2         Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt2400pci
  23         Abstract: rt2400pci device specific routines.
  24         Supported chipsets: RT2460.
  25  */
  26
  27 #include <linux/delay.h>
  28 #include <linux/etherdevice.h>
  29 #include <linux/init.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/pci.h>
  33 #include <linux/eeprom_93cx6.h>
  34
  35 #include "rt2x00.h"
  36 #include "rt2x00pci.h"
  37 #include "rt2400pci.h"
  38
  39 /*
  40  * Register access.
  41  * All access to the CSR registers will go through the methods
  42  * rt2x00pci_register_read and rt2x00pci_register_write.
  43  * BBP and RF register require indirect register access,
  44  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  45  * These indirect registers work with busy bits,
  46  * and we will try maximal REGISTER_BUSY_COUNT times to access
  47  * the register while taking a REGISTER_BUSY_DELAY us delay
  48  * between each attampt. When the busy bit is still set at that time,
  49  * the access attempt is considered to have failed,
  50  * and we will print an error.
  51  */
  52 static u32 rt2400pci_bbp_check(struct rt2x00_dev *rt2x00dev)
  53 {
  54         u32 reg;
  55         unsigned int i;
  56
  57         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  58                 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
  59                 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
  60                         break;
  61                 udelay(REGISTER_BUSY_DELAY);
  62         }
  63
  64         return reg;
  65 }
  66
  67 static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
  68                                 const unsigned int word, const u8 value)
  69 {
  70         u32 reg;
  71
  72         /*
  73          * Wait until the BBP becomes ready.
  74          */
  75         reg = rt2400pci_bbp_check(rt2x00dev);
  76         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
  77                 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
  78                 return;
  79         }
  80
  81         /*
  82          * Write the data into the BBP.
  83          */
  84         reg = 0;
  85         rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
  86         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
  87         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
  88         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
  89
  90         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
  91 }
  92
  93 static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
  94                                const unsigned int word, u8 *value)
  95 {
  96         u32 reg;
  97
  98         /*
  99          * Wait until the BBP becomes ready.
 100          */
 101         reg = rt2400pci_bbp_check(rt2x00dev);
 102         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
 103                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
 104                 return;
 105         }
 106
 107         /*
 108          * Write the request into the BBP.
 109          */
 110         reg = 0;
 111         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
 112         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
 113         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
 114
 115         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
 116
 117         /*
 118          * Wait until the BBP becomes ready.
 119          */
 120         reg = rt2400pci_bbp_check(rt2x00dev);
 121         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
 122                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
 123                 *value = 0xff;
 124                 return;
 125         }
 126
 127         *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
 128 }
 129
 130 static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
 131                                const unsigned int word, const u32 value)
 132 {
 133         u32 reg;
 134         unsigned int i;
 135
 136         if (!word)
 137                 return;
 138
 139         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 140                 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
 141                 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
 142                         goto rf_write;
 143                 udelay(REGISTER_BUSY_DELAY);
 144         }
 145
 146         ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
 147         return;
 148
 149 rf_write:
 150         reg = 0;
 151         rt2x00_set_field32(&reg, RFCSR_VALUE, value);
 152         rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
 153         rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
 154         rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
 155
 156         rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
 157         rt2x00_rf_write(rt2x00dev, word, value);
 158 }
 159
 160 static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 161 {
 162         struct rt2x00_dev *rt2x00dev = eeprom->data;
 163         u32 reg;
 164
 165         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
 166
 167         eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
 168         eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
 169         eeprom->reg_data_clock =
 170             !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
 171         eeprom->reg_chip_select =
 172             !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
 173 }
 174
 175 static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 176 {
 177         struct rt2x00_dev *rt2x00dev = eeprom->data;
 178         u32 reg = 0;
 179
 180         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
 181         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
 182         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
 183                            !!eeprom->reg_data_clock);
 184         rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
 185                            !!eeprom->reg_chip_select);
 186
 187         rt2x00pci_register_write(rt2x00dev, CSR21, reg);
 188 }
 189
 190 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 191 #define CSR_OFFSET(__word)      ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
 192
 193 static void rt2400pci_read_csr(struct rt2x00_dev *rt2x00dev,
 194                                const unsigned int word, u32 *data)
 195 {
 196         rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
 197 }
 198
 199 static void rt2400pci_write_csr(struct rt2x00_dev *rt2x00dev,
 200                                 const unsigned int word, u32 data)
 201 {
 202         rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
 203 }
 204
 205 static const struct rt2x00debug rt2400pci_rt2x00debug = {
 206         .owner  = THIS_MODULE,
 207         .csr    = {
 208                 .read           = rt2400pci_read_csr,
 209                 .write          = rt2400pci_write_csr,
 210                 .word_size      = sizeof(u32),
 211                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 212         },
 213         .eeprom = {
 214                 .read           = rt2x00_eeprom_read,
 215                 .write          = rt2x00_eeprom_write,
 216                 .word_size      = sizeof(u16),
 217                 .word_count     = EEPROM_SIZE / sizeof(u16),
 218         },
 219         .bbp    = {
 220                 .read           = rt2400pci_bbp_read,
 221                 .write          = rt2400pci_bbp_write,
 222                 .word_size      = sizeof(u8),
 223                 .word_count     = BBP_SIZE / sizeof(u8),
 224         },
 225         .rf     = {
 226                 .read           = rt2x00_rf_read,
 227                 .write          = rt2400pci_rf_write,
 228                 .word_size      = sizeof(u32),
 229                 .word_count     = RF_SIZE / sizeof(u32),
 230         },
 231 };
 232 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 233
 234 #ifdef CONFIG_RT2400PCI_RFKILL
 235 static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 236 {
 237         u32 reg;
 238
 239         rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
 240         return rt2x00_get_field32(reg, GPIOCSR_BIT0);
 241 }
 242 #else
 243 #define rt2400pci_rfkill_poll   NULL
 244 #endif /* CONFIG_RT2400PCI_RFKILL */
 245
 246 /*
 247  * Configuration handlers.
 248  */
 249 static void rt2400pci_config_mac_addr(struct rt2x00_dev *rt2x00dev,
 250                                       __le32 *mac)
 251 {
 252         rt2x00pci_register_multiwrite(rt2x00dev, CSR3, mac,
 253                                       (2 * sizeof(__le32)));
 254 }
 255
 256 static void rt2400pci_config_bssid(struct rt2x00_dev *rt2x00dev,
 257                                    __le32 *bssid)
 258 {
 259         rt2x00pci_register_multiwrite(rt2x00dev, CSR5, bssid,
 260                                       (2 * sizeof(__le32)));
 261 }
 262
 263 static void rt2400pci_config_type(struct rt2x00_dev *rt2x00dev, const int type,
 264                                   const int tsf_sync)
 265 {
 266         u32 reg;
 267
 268         rt2x00pci_register_write(rt2x00dev, CSR14, 0);
 269
 270         /*
 271          * Enable beacon config
 272          */
 273         rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
 274         rt2x00_set_field32(&reg, BCNCSR1_PRELOAD,
 275                            PREAMBLE + get_duration(IEEE80211_HEADER, 20));
 276         rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
 277
 278         /*
 279          * Enable synchronisation.
 280          */
 281         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
 282         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
 283         rt2x00_set_field32(&reg, CSR14_TBCN, (tsf_sync == TSF_SYNC_BEACON));
 284         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
 285         rt2x00_set_field32(&reg, CSR14_TSF_SYNC, tsf_sync);
 286         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
 287 }
 288
 289 static void rt2400pci_config_preamble(struct rt2x00_dev *rt2x00dev,
 290                                       const int short_preamble,
 291                                       const int ack_timeout,
 292                                       const int ack_consume_time)
 293 {
 294         int preamble_mask;
 295         u32 reg;
 296
 297         /*
 298          * When short preamble is enabled, we should set bit 0x08
 299          */
 300         preamble_mask = short_preamble << 3;
 301
 302         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
 303         rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, ack_timeout);
 304         rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, ack_consume_time);
 305         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
 306
 307         rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
 308         rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00 | preamble_mask);
 309         rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
 310         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
 311         rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
 312
 313         rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
 314         rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
 315         rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
 316         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
 317         rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
 318
 319         rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
 320         rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
 321         rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
 322         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
 323         rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
 324
 325         rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
 326         rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
 327         rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
 328         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
 329         rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
 330 }
 331
 332 static void rt2400pci_config_phymode(struct rt2x00_dev *rt2x00dev,
 333                                      const int basic_rate_mask)
 334 {
 335         rt2x00pci_register_write(rt2x00dev, ARCSR1, basic_rate_mask);
 336 }
 337
 338 static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
 339                                      struct rf_channel *rf)
 340 {
 341         /*
 342          * Switch on tuning bits.
 343          */
 344         rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
 345         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
 346
 347         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
 348         rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
 349         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
 350
 351         /*
 352          * RF2420 chipset don't need any additional actions.
 353          */
 354         if (rt2x00_rf(&rt2x00dev->chip, RF2420))
 355                 return;
 356
 357         /*
 358          * For the RT2421 chipsets we need to write an invalid
 359          * reference clock rate to activate auto_tune.
 360          * After that we set the value back to the correct channel.
 361          */
 362         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
 363         rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
 364         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
 365
 366         msleep(1);
 367
 368         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
 369         rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
 370         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
 371
 372         msleep(1);
 373
 374         /*
 375          * Switch off tuning bits.
 376          */
 377         rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
 378         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
 379
 380         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
 381         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
 382
 383         /*
 384          * Clear false CRC during channel switch.
 385          */
 386         rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
 387 }
 388
 389 static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
 390 {
 391         rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
 392 }
 393
 394 static void rt2400pci_config_antenna(struct rt2x00_dev *rt2x00dev,
 395                                      struct antenna_setup *ant)
 396 {
 397         u8 r1;
 398         u8 r4;
 399
 400         rt2400pci_bbp_read(rt2x00dev, 4, &r4);
 401         rt2400pci_bbp_read(rt2x00dev, 1, &r1);
 402
 403         /*
 404          * Configure the TX antenna.
 405          */
 406         switch (ant->tx) {
 407         case ANTENNA_HW_DIVERSITY:
 408                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
 409                 break;
 410         case ANTENNA_A:
 411                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
 412                 break;
 413         case ANTENNA_SW_DIVERSITY:
 414                 /*
 415                  * NOTE: We should never come here because rt2x00lib is
 416                  * supposed to catch this and send us the correct antenna
 417                  * explicitely. However we are nog going to bug about this.
 418                  * Instead, just default to antenna B.
 419                  */
 420         case ANTENNA_B:
 421                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
 422                 break;
 423         }
 424
 425         /*
 426          * Configure the RX antenna.
 427          */
 428         switch (ant->rx) {
 429         case ANTENNA_HW_DIVERSITY:
 430                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
 431                 break;
 432         case ANTENNA_A:
 433                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
 434                 break;
 435         case ANTENNA_SW_DIVERSITY:
 436                 /*
 437                  * NOTE: We should never come here because rt2x00lib is
 438                  * supposed to catch this and send us the correct antenna
 439                  * explicitely. However we are nog going to bug about this.
 440                  * Instead, just default to antenna B.
 441                  */
 442         case ANTENNA_B:
 443                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
 444                 break;
 445         }
 446
 447         rt2400pci_bbp_write(rt2x00dev, 4, r4);
 448         rt2400pci_bbp_write(rt2x00dev, 1, r1);
 449 }
 450
 451 static void rt2400pci_config_duration(struct rt2x00_dev *rt2x00dev,
 452                                       struct rt2x00lib_conf *libconf)
 453 {
 454         u32 reg;
 455
 456         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 457         rt2x00_set_field32(&reg, CSR11_SLOT_TIME, libconf->slot_time);
 458         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 459
 460         rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
 461         rt2x00_set_field32(&reg, CSR18_SIFS, libconf->sifs);
 462         rt2x00_set_field32(&reg, CSR18_PIFS, libconf->pifs);
 463         rt2x00pci_register_write(rt2x00dev, CSR18, reg);
 464
 465         rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
 466         rt2x00_set_field32(&reg, CSR19_DIFS, libconf->difs);
 467         rt2x00_set_field32(&reg, CSR19_EIFS, libconf->eifs);
 468         rt2x00pci_register_write(rt2x00dev, CSR19, reg);
 469
 470         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
 471         rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
 472         rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
 473         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
 474
 475         rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
 476         rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
 477                            libconf->conf->beacon_int * 16);
 478         rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
 479                            libconf->conf->beacon_int * 16);
 480         rt2x00pci_register_write(rt2x00dev, CSR12, reg);
 481 }
 482
 483 static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
 484                              const unsigned int flags,
 485                              struct rt2x00lib_conf *libconf)
 486 {
 487         if (flags & CONFIG_UPDATE_PHYMODE)
 488                 rt2400pci_config_phymode(rt2x00dev, libconf->basic_rates);
 489         if (flags & CONFIG_UPDATE_CHANNEL)
 490                 rt2400pci_config_channel(rt2x00dev, &libconf->rf);
 491         if (flags & CONFIG_UPDATE_TXPOWER)
 492                 rt2400pci_config_txpower(rt2x00dev,
 493                                          libconf->conf->power_level);
 494         if (flags & CONFIG_UPDATE_ANTENNA)
 495                 rt2400pci_config_antenna(rt2x00dev, &libconf->ant);
 496         if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
 497                 rt2400pci_config_duration(rt2x00dev, libconf);
 498 }
 499
 500 static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
 501                                 struct ieee80211_tx_queue_params *params)
 502 {
 503         u32 reg;
 504
 505         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 506         rt2x00_set_field32(&reg, CSR11_CWMIN, params->cw_min);
 507         rt2x00_set_field32(&reg, CSR11_CWMAX, params->cw_max);
 508         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 509 }
 510
 511 /*
 512  * LED functions.
 513  */
 514 static void rt2400pci_enable_led(struct rt2x00_dev *rt2x00dev)
 515 {
 516         u32 reg;
 517
 518         rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
 519
 520         rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, 70);
 521         rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, 30);
 522         rt2x00_set_field32(&reg, LEDCSR_LINK,
 523                            (rt2x00dev->led_mode != LED_MODE_ASUS));
 524         rt2x00_set_field32(&reg, LEDCSR_ACTIVITY,
 525                            (rt2x00dev->led_mode != LED_MODE_TXRX_ACTIVITY));
 526         rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
 527 }
 528
 529 static void rt2400pci_disable_led(struct rt2x00_dev *rt2x00dev)
 530 {
 531         u32 reg;
 532
 533         rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
 534         rt2x00_set_field32(&reg, LEDCSR_LINK, 0);
 535         rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 0);
 536         rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
 537 }
 538
 539 /*
 540  * Link tuning
 541  */
 542 static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
 543                                  struct link_qual *qual)
 544 {
 545         u32 reg;
 546         u8 bbp;
 547
 548         /*
 549          * Update FCS error count from register.
 550          */
 551         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 552         qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
 553
 554         /*
 555          * Update False CCA count from register.
 556          */
 557         rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
 558         qual->false_cca = bbp;
 559 }
 560
 561 static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
 562 {
 563         rt2400pci_bbp_write(rt2x00dev, 13, 0x08);
 564         rt2x00dev->link.vgc_level = 0x08;
 565 }
 566
 567 static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev)
 568 {
 569         u8 reg;
 570
 571         /*
 572          * The link tuner should not run longer then 60 seconds,
 573          * and should run once every 2 seconds.
 574          */
 575         if (rt2x00dev->link.count > 60 || !(rt2x00dev->link.count & 1))
 576                 return;
 577
 578         /*
 579          * Base r13 link tuning on the false cca count.
 580          */
 581         rt2400pci_bbp_read(rt2x00dev, 13, &reg);
 582
 583         if (rt2x00dev->link.qual.false_cca > 512 && reg < 0x20) {
 584                 rt2400pci_bbp_write(rt2x00dev, 13, ++reg);
 585                 rt2x00dev->link.vgc_level = reg;
 586         } else if (rt2x00dev->link.qual.false_cca < 100 && reg > 0x08) {
 587                 rt2400pci_bbp_write(rt2x00dev, 13, --reg);
 588                 rt2x00dev->link.vgc_level = reg;
 589         }
 590 }
 591
 592 /*
 593  * Initialization functions.
 594  */
 595 static void rt2400pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
 596                                    struct data_entry *entry)
 597 {
 598         __le32 *rxd = entry->priv;
 599         u32 word;
 600
 601         rt2x00_desc_read(rxd, 2, &word);
 602         rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, entry->ring->data_size);
 603         rt2x00_desc_write(rxd, 2, word);
 604
 605         rt2x00_desc_read(rxd, 1, &word);
 606         rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, entry->data_dma);
 607         rt2x00_desc_write(rxd, 1, word);
 608
 609         rt2x00_desc_read(rxd, 0, &word);
 610         rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
 611         rt2x00_desc_write(rxd, 0, word);
 612 }
 613
 614 static void rt2400pci_init_txentry(struct rt2x00_dev *rt2x00dev,
 615                                    struct data_entry *entry)
 616 {
 617         __le32 *txd = entry->priv;
 618         u32 word;
 619
 620         rt2x00_desc_read(txd, 1, &word);
 621         rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, entry->data_dma);
 622         rt2x00_desc_write(txd, 1, word);
 623
 624         rt2x00_desc_read(txd, 2, &word);
 625         rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH, entry->ring->data_size);
 626         rt2x00_desc_write(txd, 2, word);
 627
 628         rt2x00_desc_read(txd, 0, &word);
 629         rt2x00_set_field32(&word, TXD_W0_VALID, 0);
 630         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
 631         rt2x00_desc_write(txd, 0, word);
 632 }
 633
 634 static int rt2400pci_init_rings(struct rt2x00_dev *rt2x00dev)
 635 {
 636         u32 reg;
 637
 638         /*
 639          * Initialize registers.
 640          */
 641         rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
 642         rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE,
 643                            rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].desc_size);
 644         rt2x00_set_field32(&reg, TXCSR2_NUM_TXD,
 645                            rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].stats.limit);
 646         rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM,
 647                            rt2x00dev->bcn[1].stats.limit);
 648         rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO,
 649                            rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].stats.limit);
 650         rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
 651
 652         rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
 653         rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
 654                            rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].data_dma);
 655         rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
 656
 657         rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
 658         rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
 659                            rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].data_dma);
 660         rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
 661
 662         rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
 663         rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
 664                            rt2x00dev->bcn[1].data_dma);
 665         rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
 666
 667         rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
 668         rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
 669                            rt2x00dev->bcn[0].data_dma);
 670         rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
 671
 672         rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
 673         rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
 674         rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->stats.limit);
 675         rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
 676
 677         rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
 678         rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
 679                            rt2x00dev->rx->data_dma);
 680         rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
 681
 682         return 0;
 683 }
 684
 685 static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
 686 {
 687         u32 reg;
 688
 689         rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
 690         rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
 691         rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20);
 692         rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
 693
 694         rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
 695         rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
 696         rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
 697         rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
 698         rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
 699
 700         rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
 701         rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
 702                            (rt2x00dev->rx->data_size / 128));
 703         rt2x00pci_register_write(rt2x00dev, CSR9, reg);
 704
 705         rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
 706
 707         rt2x00pci_register_read(rt2x00dev, ARCSR0, &reg);
 708         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
 709         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
 710         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
 711         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
 712         rt2x00pci_register_write(rt2x00dev, ARCSR0, reg);
 713
 714         rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
 715         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
 716         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
 717         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
 718         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
 719         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
 720         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
 721         rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
 722
 723         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
 724
 725         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
 726                 return -EBUSY;
 727
 728         rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
 729         rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
 730
 731         rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
 732         rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
 733         rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
 734
 735         rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
 736         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
 737         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
 738         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
 739         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
 740         rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
 741
 742         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 743         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
 744         rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
 745         rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
 746         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 747
 748         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 749         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
 750         rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
 751         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 752
 753         /*
 754          * We must clear the FCS and FIFO error count.
 755          * These registers are cleared on read,
 756          * so we may pass a useless variable to store the value.
 757          */
 758         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 759         rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
 760
 761         return 0;
 762 }
 763
 764 static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
 765 {
 766         unsigned int i;
 767         u16 eeprom;
 768         u8 reg_id;
 769         u8 value;
 770
 771         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 772                 rt2400pci_bbp_read(rt2x00dev, 0, &value);
 773                 if ((value != 0xff) && (value != 0x00))
 774                         goto continue_csr_init;
 775                 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
 776                 udelay(REGISTER_BUSY_DELAY);
 777         }
 778
 779         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
 780         return -EACCES;
 781
 782 continue_csr_init:
 783         rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
 784         rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
 785         rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
 786         rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
 787         rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
 788         rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
 789         rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
 790         rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
 791         rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
 792         rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
 793         rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
 794         rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
 795         rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
 796         rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
 797
 798         DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
 799         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
 800                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
 801
 802                 if (eeprom != 0xffff && eeprom != 0x0000) {
 803                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
 804                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
 805                         DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
 806                               reg_id, value);
 807                         rt2400pci_bbp_write(rt2x00dev, reg_id, value);
 808                 }
 809         }
 810         DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
 811
 812         return 0;
 813 }
 814
 815 /*
 816  * Device state switch handlers.
 817  */
 818 static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
 819                                 enum dev_state state)
 820 {
 821         u32 reg;
 822
 823         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
 824         rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
 825                            state == STATE_RADIO_RX_OFF);
 826         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
 827 }
 828
 829 static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
 830                                  enum dev_state state)
 831 {
 832         int mask = (state == STATE_RADIO_IRQ_OFF);
 833         u32 reg;
 834
 835         /*
 836          * When interrupts are being enabled, the interrupt registers
 837          * should clear the register to assure a clean state.
 838          */
 839         if (state == STATE_RADIO_IRQ_ON) {
 840                 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
 841                 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
 842         }
 843
 844         /*
 845          * Only toggle the interrupts bits we are going to use.
 846          * Non-checked interrupt bits are disabled by default.
 847          */
 848         rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
 849         rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
 850         rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
 851         rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
 852         rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
 853         rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
 854         rt2x00pci_register_write(rt2x00dev, CSR8, reg);
 855 }
 856
 857 static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
 858 {
 859         /*
 860          * Initialize all registers.
 861          */
 862         if (rt2400pci_init_rings(rt2x00dev) ||
 863             rt2400pci_init_registers(rt2x00dev) ||
 864             rt2400pci_init_bbp(rt2x00dev)) {
 865                 ERROR(rt2x00dev, "Register initialization failed.\n");
 866                 return -EIO;
 867         }
 868
 869         /*
 870          * Enable interrupts.
 871          */
 872         rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
 873
 874         /*
 875          * Enable LED
 876          */
 877         rt2400pci_enable_led(rt2x00dev);
 878
 879         return 0;
 880 }
 881
 882 static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
 883 {
 884         u32 reg;
 885
 886         /*
 887          * Disable LED
 888          */
 889         rt2400pci_disable_led(rt2x00dev);
 890
 891         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
 892
 893         /*
 894          * Disable synchronisation.
 895          */
 896         rt2x00pci_register_write(rt2x00dev, CSR14, 0);
 897
 898         /*
 899          * Cancel RX and TX.
 900          */
 901         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
 902         rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
 903         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
 904
 905         /*
 906          * Disable interrupts.
 907          */
 908         rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
 909 }
 910
 911 static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
 912                                enum dev_state state)
 913 {
 914         u32 reg;
 915         unsigned int i;
 916         char put_to_sleep;
 917         char bbp_state;
 918         char rf_state;
 919
 920         put_to_sleep = (state != STATE_AWAKE);
 921
 922         rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
 923         rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
 924         rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
 925         rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
 926         rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
 927         rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
 928
 929         /*
 930          * Device is not guaranteed to be in the requested state yet.
 931          * We must wait until the register indicates that the
 932          * device has entered the correct state.
 933          */
 934         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 935                 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
 936                 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
 937                 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
 938                 if (bbp_state == state && rf_state == state)
 939                         return 0;
 940                 msleep(10);
 941         }
 942
 943         NOTICE(rt2x00dev, "Device failed to enter state %d, "
 944                "current device state: bbp %d and rf %d.\n",
 945                state, bbp_state, rf_state);
 946
 947         return -EBUSY;
 948 }
 949
 950 static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
 951                                       enum dev_state state)
 952 {
 953         int retval = 0;
 954
 955         switch (state) {
 956         case STATE_RADIO_ON:
 957                 retval = rt2400pci_enable_radio(rt2x00dev);
 958                 break;
 959         case STATE_RADIO_OFF:
 960                 rt2400pci_disable_radio(rt2x00dev);
 961                 break;
 962         case STATE_RADIO_RX_ON:
 963         case STATE_RADIO_RX_OFF:
 964                 rt2400pci_toggle_rx(rt2x00dev, state);
 965                 break;
 966         case STATE_DEEP_SLEEP:
 967         case STATE_SLEEP:
 968         case STATE_STANDBY:
 969         case STATE_AWAKE:
 970                 retval = rt2400pci_set_state(rt2x00dev, state);
 971                 break;
 972         default:
 973                 retval = -ENOTSUPP;
 974                 break;
 975         }
 976
 977         return retval;
 978 }
 979
 980 /*
 981  * TX descriptor initialization
 982  */
 983 static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
 984                                     struct sk_buff *skb,
 985                                     struct txdata_entry_desc *desc,
 986                                     struct ieee80211_tx_control *control)
 987 {
 988         struct skb_desc *skbdesc = get_skb_desc(skb);
 989         __le32 *txd = skbdesc->desc;
 990         u32 word;
 991
 992         /*
 993          * Start writing the descriptor words.
 994          */
 995         rt2x00_desc_read(txd, 2, &word);
 996         rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, skbdesc->data_len);
 997         rt2x00_desc_write(txd, 2, word);
 998
 999         rt2x00_desc_read(txd, 3, &word);
1000         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, desc->signal);
1001         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
1002         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
1003         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, desc->service);
1004         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
1005         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
1006         rt2x00_desc_write(txd, 3, word);
1007
1008         rt2x00_desc_read(txd, 4, &word);
1009         rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, desc->length_low);
1010         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
1011         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
1012         rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, desc->length_high);
1013         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
1014         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
1015         rt2x00_desc_write(txd, 4, word);
1016
1017         rt2x00_desc_read(txd, 0, &word);
1018         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1019         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1020         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1021                            test_bit(ENTRY_TXD_MORE_FRAG, &desc->flags));
1022         rt2x00_set_field32(&word, TXD_W0_ACK,
1023                            test_bit(ENTRY_TXD_ACK, &desc->flags));
1024         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1025                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc->flags));
1026         rt2x00_set_field32(&word, TXD_W0_RTS,
1027                            test_bit(ENTRY_TXD_RTS_FRAME, &desc->flags));
1028         rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs);
1029         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1030                            !!(control->flags &
1031                               IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1032         rt2x00_desc_write(txd, 0, word);
1033 }
1034
1035 /*
1036  * TX data initialization
1037  */
1038 static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1039                                     unsigned int queue)
1040 {
1041         u32 reg;
1042
1043         if (queue == IEEE80211_TX_QUEUE_BEACON) {
1044                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1045                 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1046                         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1047                         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1048                 }
1049                 return;
1050         }
1051
1052         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1053         rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO,
1054                            (queue == IEEE80211_TX_QUEUE_DATA0));
1055         rt2x00_set_field32(&reg, TXCSR0_KICK_TX,
1056                            (queue == IEEE80211_TX_QUEUE_DATA1));
1057         rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM,
1058                            (queue == IEEE80211_TX_QUEUE_AFTER_BEACON));
1059         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1060 }
1061
1062 /*
1063  * RX control handlers
1064  */
1065 static void rt2400pci_fill_rxdone(struct data_entry *entry,
1066                                   struct rxdata_entry_desc *desc)
1067 {
1068         __le32 *rxd = entry->priv;
1069         u32 word0;
1070         u32 word2;
1071
1072         rt2x00_desc_read(rxd, 0, &word0);
1073         rt2x00_desc_read(rxd, 2, &word2);
1074
1075         desc->flags = 0;
1076         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1077                 desc->flags |= RX_FLAG_FAILED_FCS_CRC;
1078         if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1079                 desc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1080
1081         /*
1082          * Obtain the status about this packet.
1083          */
1084         desc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1085         desc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1086             entry->ring->rt2x00dev->rssi_offset;
1087         desc->ofdm = 0;
1088         desc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1089         desc->my_bss = !!rt2x00_get_field32(word0, RXD_W0_MY_BSS);
1090 }
1091
1092 /*
1093  * Interrupt functions.
1094  */
1095 static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev, const int queue)
1096 {
1097         struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
1098         struct data_entry *entry;
1099         __le32 *txd;
1100         u32 word;
1101         int tx_status;
1102         int retry;
1103
1104         while (!rt2x00_ring_empty(ring)) {
1105                 entry = rt2x00_get_data_entry_done(ring);
1106                 txd = entry->priv;
1107                 rt2x00_desc_read(txd, 0, &word);
1108
1109                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1110                     !rt2x00_get_field32(word, TXD_W0_VALID))
1111                         break;
1112
1113                 /*
1114                  * Obtain the status about this packet.
1115                  */
1116                 tx_status = rt2x00_get_field32(word, TXD_W0_RESULT);
1117                 retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1118
1119                 rt2x00pci_txdone(rt2x00dev, entry, tx_status, retry);
1120         }
1121 }
1122
1123 static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1124 {
1125         struct rt2x00_dev *rt2x00dev = dev_instance;
1126         u32 reg;
1127
1128         /*
1129          * Get the interrupt sources & saved to local variable.
1130          * Write register value back to clear pending interrupts.
1131          */
1132         rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1133         rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1134
1135         if (!reg)
1136                 return IRQ_NONE;
1137
1138         if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1139                 return IRQ_HANDLED;
1140
1141         /*
1142          * Handle interrupts, walk through all bits
1143          * and run the tasks, the bits are checked in order of
1144          * priority.
1145          */
1146
1147         /*
1148          * 1 - Beacon timer expired interrupt.
1149          */
1150         if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1151                 rt2x00lib_beacondone(rt2x00dev);
1152
1153         /*
1154          * 2 - Rx ring done interrupt.
1155          */
1156         if (rt2x00_get_field32(reg, CSR7_RXDONE))
1157                 rt2x00pci_rxdone(rt2x00dev);
1158
1159         /*
1160          * 3 - Atim ring transmit done interrupt.
1161          */
1162         if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1163                 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
1164
1165         /*
1166          * 4 - Priority ring transmit done interrupt.
1167          */
1168         if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1169                 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
1170
1171         /*
1172          * 5 - Tx ring transmit done interrupt.
1173          */
1174         if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1175                 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
1176
1177         return IRQ_HANDLED;
1178 }
1179
1180 /*
1181  * Device probe functions.
1182  */
1183 static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1184 {
1185         struct eeprom_93cx6 eeprom;
1186         u32 reg;
1187         u16 word;
1188         u8 *mac;
1189
1190         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1191
1192         eeprom.data = rt2x00dev;
1193         eeprom.register_read = rt2400pci_eepromregister_read;
1194         eeprom.register_write = rt2400pci_eepromregister_write;
1195         eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1196             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1197         eeprom.reg_data_in = 0;
1198         eeprom.reg_data_out = 0;
1199         eeprom.reg_data_clock = 0;
1200         eeprom.reg_chip_select = 0;
1201
1202         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1203                                EEPROM_SIZE / sizeof(u16));
1204
1205         /*
1206          * Start validation of the data that has been read.
1207          */
1208         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1209         if (!is_valid_ether_addr(mac)) {
1210                 DECLARE_MAC_BUF(macbuf);
1211
1212                 random_ether_addr(mac);
1213                 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
1214         }
1215
1216         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1217         if (word == 0xffff) {
1218                 ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
1219                 return -EINVAL;
1220         }
1221
1222         return 0;
1223 }
1224
1225 static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1226 {
1227         u32 reg;
1228         u16 value;
1229         u16 eeprom;
1230
1231         /*
1232          * Read EEPROM word for configuration.
1233          */
1234         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1235
1236         /*
1237          * Identify RF chipset.
1238          */
1239         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1240         rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1241         rt2x00_set_chip(rt2x00dev, RT2460, value, reg);
1242
1243         if (!rt2x00_rf(&rt2x00dev->chip, RF2420) &&
1244             !rt2x00_rf(&rt2x00dev->chip, RF2421)) {
1245                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1246                 return -ENODEV;
1247         }
1248
1249         /*
1250          * Identify default antenna configuration.
1251          */
1252         rt2x00dev->default_ant.tx =
1253             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1254         rt2x00dev->default_ant.rx =
1255             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1256
1257         /*
1258          * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
1259          * I am not 100% sure about this, but the legacy drivers do not
1260          * indicate antenna swapping in software is required when
1261          * diversity is enabled.
1262          */
1263         if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
1264                 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
1265         if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
1266                 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
1267
1268         /*
1269          * Store led mode, for correct led behaviour.
1270          */
1271         rt2x00dev->led_mode =
1272             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1273
1274         /*
1275          * Detect if this device has an hardware controlled radio.
1276          */
1277 #ifdef CONFIG_RT2400PCI_RFKILL
1278         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1279                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1280 #endif /* CONFIG_RT2400PCI_RFKILL */
1281
1282         /*
1283          * Check if the BBP tuning should be enabled.
1284          */
1285         if (!rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1286                 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1287
1288         return 0;
1289 }
1290
1291 /*
1292  * RF value list for RF2420 & RF2421
1293  * Supports: 2.4 GHz
1294  */
1295 static const struct rf_channel rf_vals_bg[] = {
1296         { 1,  0x00022058, 0x000c1fda, 0x00000101, 0 },
1297         { 2,  0x00022058, 0x000c1fee, 0x00000101, 0 },
1298         { 3,  0x00022058, 0x000c2002, 0x00000101, 0 },
1299         { 4,  0x00022058, 0x000c2016, 0x00000101, 0 },
1300         { 5,  0x00022058, 0x000c202a, 0x00000101, 0 },
1301         { 6,  0x00022058, 0x000c203e, 0x00000101, 0 },
1302         { 7,  0x00022058, 0x000c2052, 0x00000101, 0 },
1303         { 8,  0x00022058, 0x000c2066, 0x00000101, 0 },
1304         { 9,  0x00022058, 0x000c207a, 0x00000101, 0 },
1305         { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1306         { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1307         { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1308         { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1309         { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1310 };
1311
1312 static void rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1313 {
1314         struct hw_mode_spec *spec = &rt2x00dev->spec;
1315         u8 *txpower;
1316         unsigned int i;
1317
1318         /*
1319          * Initialize all hw fields.
1320          */
1321         rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
1322         rt2x00dev->hw->extra_tx_headroom = 0;
1323         rt2x00dev->hw->max_signal = MAX_SIGNAL;
1324         rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1325         rt2x00dev->hw->queues = 2;
1326
1327         SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
1328         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1329                                 rt2x00_eeprom_addr(rt2x00dev,
1330                                                    EEPROM_MAC_ADDR_0));
1331
1332         /*
1333          * Convert tx_power array in eeprom.
1334          */
1335         txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1336         for (i = 0; i < 14; i++)
1337                 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1338
1339         /*
1340          * Initialize hw_mode information.
1341          */
1342         spec->num_modes = 1;
1343         spec->num_rates = 4;
1344         spec->tx_power_a = NULL;
1345         spec->tx_power_bg = txpower;
1346         spec->tx_power_default = DEFAULT_TXPOWER;
1347
1348         spec->num_channels = ARRAY_SIZE(rf_vals_bg);
1349         spec->channels = rf_vals_bg;
1350 }
1351
1352 static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1353 {
1354         int retval;
1355
1356         /*
1357          * Allocate eeprom data.
1358          */
1359         retval = rt2400pci_validate_eeprom(rt2x00dev);
1360         if (retval)
1361                 return retval;
1362
1363         retval = rt2400pci_init_eeprom(rt2x00dev);
1364         if (retval)
1365                 return retval;
1366
1367         /*
1368          * Initialize hw specifications.
1369          */
1370         rt2400pci_probe_hw_mode(rt2x00dev);
1371
1372         /*
1373          * This device requires the beacon ring
1374          */
1375         __set_bit(DRIVER_REQUIRE_BEACON_RING, &rt2x00dev->flags);
1376
1377         /*
1378          * Set the rssi offset.
1379          */
1380         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1381
1382         return 0;
1383 }
1384
1385 /*
1386  * IEEE80211 stack callback functions.
1387  */
1388 static void rt2400pci_configure_filter(struct ieee80211_hw *hw,
1389                                        unsigned int changed_flags,
1390                                        unsigned int *total_flags,
1391                                        int mc_count,
1392                                        struct dev_addr_list *mc_list)
1393 {
1394         struct rt2x00_dev *rt2x00dev = hw->priv;
1395         u32 reg;
1396
1397         /*
1398          * Mask off any flags we are going to ignore from
1399          * the total_flags field.
1400          */
1401         *total_flags &=
1402             FIF_ALLMULTI |
1403             FIF_FCSFAIL |
1404             FIF_PLCPFAIL |
1405             FIF_CONTROL |
1406             FIF_OTHER_BSS |
1407             FIF_PROMISC_IN_BSS;
1408
1409         /*
1410          * Apply some rules to the filters:
1411          * - Some filters imply different filters to be set.
1412          * - Some things we can't filter out at all.
1413          */
1414         *total_flags |= FIF_ALLMULTI;
1415         if (*total_flags & FIF_OTHER_BSS ||
1416             *total_flags & FIF_PROMISC_IN_BSS)
1417                 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
1418
1419         /*
1420          * Check if there is any work left for us.
1421          */
1422         if (rt2x00dev->packet_filter == *total_flags)
1423                 return;
1424         rt2x00dev->packet_filter = *total_flags;
1425
1426         /*
1427          * Start configuration steps.
1428          * Note that the version error will always be dropped
1429          * since there is no filter for it at this time.
1430          */
1431         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1432         rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
1433                            !(*total_flags & FIF_FCSFAIL));
1434         rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
1435                            !(*total_flags & FIF_PLCPFAIL));
1436         rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
1437                            !(*total_flags & FIF_CONTROL));
1438         rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
1439                            !(*total_flags & FIF_PROMISC_IN_BSS));
1440         rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
1441                            !(*total_flags & FIF_PROMISC_IN_BSS));
1442         rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
1443         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1444 }
1445
1446 static int rt2400pci_set_retry_limit(struct ieee80211_hw *hw,
1447                                      u32 short_retry, u32 long_retry)
1448 {
1449         struct rt2x00_dev *rt2x00dev = hw->priv;
1450         u32 reg;
1451
1452         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
1453         rt2x00_set_field32(&reg, CSR11_LONG_RETRY, long_retry);
1454         rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, short_retry);
1455         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1456
1457         return 0;
1458 }
1459
1460 static int rt2400pci_conf_tx(struct ieee80211_hw *hw,
1461                              int queue,
1462                              const struct ieee80211_tx_queue_params *params)
1463 {
1464         struct rt2x00_dev *rt2x00dev = hw->priv;
1465
1466         /*
1467          * We don't support variating cw_min and cw_max variables
1468          * per queue. So by default we only configure the TX queue,
1469          * and ignore all other configurations.
1470          */
1471         if (queue != IEEE80211_TX_QUEUE_DATA0)
1472                 return -EINVAL;
1473
1474         if (rt2x00mac_conf_tx(hw, queue, params))
1475                 return -EINVAL;
1476
1477         /*
1478          * Write configuration to register.
1479          */
1480         rt2400pci_config_cw(rt2x00dev, &rt2x00dev->tx->tx_params);
1481
1482         return 0;
1483 }
1484
1485 static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
1486 {
1487         struct rt2x00_dev *rt2x00dev = hw->priv;
1488         u64 tsf;
1489         u32 reg;
1490
1491         rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1492         tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1493         rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1494         tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1495
1496         return tsf;
1497 }
1498
1499 static void rt2400pci_reset_tsf(struct ieee80211_hw *hw)
1500 {
1501         struct rt2x00_dev *rt2x00dev = hw->priv;
1502
1503         rt2x00pci_register_write(rt2x00dev, CSR16, 0);
1504         rt2x00pci_register_write(rt2x00dev, CSR17, 0);
1505 }
1506
1507 static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1508 {
1509         struct rt2x00_dev *rt2x00dev = hw->priv;
1510         u32 reg;
1511
1512         rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1513         return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1514 }
1515
1516 static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1517         .tx                     = rt2x00mac_tx,
1518         .start                  = rt2x00mac_start,
1519         .stop                   = rt2x00mac_stop,
1520         .add_interface          = rt2x00mac_add_interface,
1521         .remove_interface       = rt2x00mac_remove_interface,
1522         .config                 = rt2x00mac_config,
1523         .config_interface       = rt2x00mac_config_interface,
1524         .configure_filter       = rt2400pci_configure_filter,
1525         .get_stats              = rt2x00mac_get_stats,
1526         .set_retry_limit        = rt2400pci_set_retry_limit,
1527         .bss_info_changed       = rt2x00mac_bss_info_changed,
1528         .conf_tx                = rt2400pci_conf_tx,
1529         .get_tx_stats           = rt2x00mac_get_tx_stats,
1530         .get_tsf                = rt2400pci_get_tsf,
1531         .reset_tsf              = rt2400pci_reset_tsf,
1532         .beacon_update          = rt2x00pci_beacon_update,
1533         .tx_last_beacon         = rt2400pci_tx_last_beacon,
1534 };
1535
1536 static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1537         .irq_handler            = rt2400pci_interrupt,
1538         .probe_hw               = rt2400pci_probe_hw,
1539         .initialize             = rt2x00pci_initialize,
1540         .uninitialize           = rt2x00pci_uninitialize,
1541         .init_rxentry           = rt2400pci_init_rxentry,
1542         .init_txentry           = rt2400pci_init_txentry,
1543         .set_device_state       = rt2400pci_set_device_state,
1544         .rfkill_poll            = rt2400pci_rfkill_poll,
1545         .link_stats             = rt2400pci_link_stats,
1546         .reset_tuner            = rt2400pci_reset_tuner,
1547         .link_tuner             = rt2400pci_link_tuner,
1548         .write_tx_desc          = rt2400pci_write_tx_desc,
1549         .write_tx_data          = rt2x00pci_write_tx_data,
1550         .kick_tx_queue          = rt2400pci_kick_tx_queue,
1551         .fill_rxdone            = rt2400pci_fill_rxdone,
1552         .config_mac_addr        = rt2400pci_config_mac_addr,
1553         .config_bssid           = rt2400pci_config_bssid,
1554         .config_type            = rt2400pci_config_type,
1555         .config_preamble        = rt2400pci_config_preamble,
1556         .config                 = rt2400pci_config,
1557 };
1558
1559 static const struct rt2x00_ops rt2400pci_ops = {
1560         .name           = KBUILD_MODNAME,
1561         .rxd_size       = RXD_DESC_SIZE,
1562         .txd_size       = TXD_DESC_SIZE,
1563         .eeprom_size    = EEPROM_SIZE,
1564         .rf_size        = RF_SIZE,
1565         .lib            = &rt2400pci_rt2x00_ops,
1566         .hw             = &rt2400pci_mac80211_ops,
1567 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1568         .debugfs        = &rt2400pci_rt2x00debug,
1569 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1570 };
1571
1572 /*
1573  * RT2400pci module information.
1574  */
1575 static struct pci_device_id rt2400pci_device_table[] = {
1576         { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) },
1577         { 0, }
1578 };
1579
1580 MODULE_AUTHOR(DRV_PROJECT);
1581 MODULE_VERSION(DRV_VERSION);
1582 MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1583 MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1584 MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1585 MODULE_LICENSE("GPL");
1586
1587 static struct pci_driver rt2400pci_driver = {
1588         .name           = KBUILD_MODNAME,
1589         .id_table       = rt2400pci_device_table,
1590         .probe          = rt2x00pci_probe,
1591         .remove         = __devexit_p(rt2x00pci_remove),
1592         .suspend        = rt2x00pci_suspend,
1593         .resume         = rt2x00pci_resume,
1594 };
1595
1596 static int __init rt2400pci_init(void)
1597 {
1598         return pci_register_driver(&rt2400pci_driver);
1599 }
1600
1601 static void __exit rt2400pci_exit(void)
1602 {
1603         pci_unregister_driver(&rt2400pci_driver);
1604 }
1605
1606 module_init(rt2400pci_init);
1607 module_exit(rt2400pci_exit);