drivers/net/wireless/rt2x00/rt2400pci.c

   1 /*
   2         Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt2400pci
  23         Abstract: rt2400pci device specific routines.
  24         Supported chipsets: RT2460.
  25  */
  26
  27 /*
  28  * Set enviroment defines for rt2x00.h
  29  */
  30 #define DRV_NAME "rt2400pci"
  31
  32 #include <linux/delay.h>
  33 #include <linux/etherdevice.h>
  34 #include <linux/init.h>
  35 #include <linux/kernel.h>
  36 #include <linux/module.h>
  37 #include <linux/pci.h>
  38 #include <linux/eeprom_93cx6.h>
  39
  40 #include "rt2x00.h"
  41 #include "rt2x00pci.h"
  42 #include "rt2400pci.h"
  43
  44 /*
  45  * Register access.
  46  * All access to the CSR registers will go through the methods
  47  * rt2x00pci_register_read and rt2x00pci_register_write.
  48  * BBP and RF register require indirect register access,
  49  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  50  * These indirect registers work with busy bits,
  51  * and we will try maximal REGISTER_BUSY_COUNT times to access
  52  * the register while taking a REGISTER_BUSY_DELAY us delay
  53  * between each attampt. When the busy bit is still set at that time,
  54  * the access attempt is considered to have failed,
  55  * and we will print an error.
  56  */
  57 static u32 rt2400pci_bbp_check(const struct rt2x00_dev *rt2x00dev)
  58 {
  59         u32 reg;
  60         unsigned int i;
  61
  62         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  63                 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
  64                 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
  65                         break;
  66                 udelay(REGISTER_BUSY_DELAY);
  67         }
  68
  69         return reg;
  70 }
  71
  72 static void rt2400pci_bbp_write(const struct rt2x00_dev *rt2x00dev,
  73                                 const unsigned int word, const u8 value)
  74 {
  75         u32 reg;
  76
  77         /*
  78          * Wait until the BBP becomes ready.
  79          */
  80         reg = rt2400pci_bbp_check(rt2x00dev);
  81         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
  82                 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
  83                 return;
  84         }
  85
  86         /*
  87          * Write the data into the BBP.
  88          */
  89         reg = 0;
  90         rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
  91         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
  92         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
  93         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
  94
  95         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
  96 }
  97
  98 static void rt2400pci_bbp_read(const struct rt2x00_dev *rt2x00dev,
  99                                const unsigned int word, u8 *value)
 100 {
 101         u32 reg;
 102
 103         /*
 104          * Wait until the BBP becomes ready.
 105          */
 106         reg = rt2400pci_bbp_check(rt2x00dev);
 107         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
 108                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
 109                 return;
 110         }
 111
 112         /*
 113          * Write the request into the BBP.
 114          */
 115         reg = 0;
 116         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
 117         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
 118         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
 119
 120         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
 121
 122         /*
 123          * Wait until the BBP becomes ready.
 124          */
 125         reg = rt2400pci_bbp_check(rt2x00dev);
 126         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
 127                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
 128                 *value = 0xff;
 129                 return;
 130         }
 131
 132         *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
 133 }
 134
 135 static void rt2400pci_rf_write(const struct rt2x00_dev *rt2x00dev,
 136                                const unsigned int word, const u32 value)
 137 {
 138         u32 reg;
 139         unsigned int i;
 140
 141         if (!word)
 142                 return;
 143
 144         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 145                 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
 146                 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
 147                         goto rf_write;
 148                 udelay(REGISTER_BUSY_DELAY);
 149         }
 150
 151         ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
 152         return;
 153
 154 rf_write:
 155         reg = 0;
 156         rt2x00_set_field32(&reg, RFCSR_VALUE, value);
 157         rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
 158         rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
 159         rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
 160
 161         rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
 162         rt2x00_rf_write(rt2x00dev, word, value);
 163 }
 164
 165 static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 166 {
 167         struct rt2x00_dev *rt2x00dev = eeprom->data;
 168         u32 reg;
 169
 170         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
 171
 172         eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
 173         eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
 174         eeprom->reg_data_clock =
 175             !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
 176         eeprom->reg_chip_select =
 177             !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
 178 }
 179
 180 static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 181 {
 182         struct rt2x00_dev *rt2x00dev = eeprom->data;
 183         u32 reg = 0;
 184
 185         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
 186         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
 187         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
 188                            !!eeprom->reg_data_clock);
 189         rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
 190                            !!eeprom->reg_chip_select);
 191
 192         rt2x00pci_register_write(rt2x00dev, CSR21, reg);
 193 }
 194
 195 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 196 #define CSR_OFFSET(__word)      ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
 197
 198 static void rt2400pci_read_csr(const struct rt2x00_dev *rt2x00dev,
 199                                const unsigned int word, u32 *data)
 200 {
 201         rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
 202 }
 203
 204 static void rt2400pci_write_csr(const struct rt2x00_dev *rt2x00dev,
 205                                 const unsigned int word, u32 data)
 206 {
 207         rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
 208 }
 209
 210 static const struct rt2x00debug rt2400pci_rt2x00debug = {
 211         .owner  = THIS_MODULE,
 212         .csr    = {
 213                 .read           = rt2400pci_read_csr,
 214                 .write          = rt2400pci_write_csr,
 215                 .word_size      = sizeof(u32),
 216                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 217         },
 218         .eeprom = {
 219                 .read           = rt2x00_eeprom_read,
 220                 .write          = rt2x00_eeprom_write,
 221                 .word_size      = sizeof(u16),
 222                 .word_count     = EEPROM_SIZE / sizeof(u16),
 223         },
 224         .bbp    = {
 225                 .read           = rt2400pci_bbp_read,
 226                 .write          = rt2400pci_bbp_write,
 227                 .word_size      = sizeof(u8),
 228                 .word_count     = BBP_SIZE / sizeof(u8),
 229         },
 230         .rf     = {
 231                 .read           = rt2x00_rf_read,
 232                 .write          = rt2400pci_rf_write,
 233                 .word_size      = sizeof(u32),
 234                 .word_count     = RF_SIZE / sizeof(u32),
 235         },
 236 };
 237 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 238
 239 #ifdef CONFIG_RT2400PCI_RFKILL
 240 static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 241 {
 242         u32 reg;
 243
 244         rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
 245         return rt2x00_get_field32(reg, GPIOCSR_BIT0);
 246 }
 247 #else
 248 #define rt2400pci_rfkill_poll   NULL
 249 #endif /* CONFIG_RT2400PCI_RFKILL */
 250
 251 /*
 252  * Configuration handlers.
 253  */
 254 static void rt2400pci_config_mac_addr(struct rt2x00_dev *rt2x00dev,
 255                                       __le32 *mac)
 256 {
 257         rt2x00pci_register_multiwrite(rt2x00dev, CSR3, mac,
 258                                       (2 * sizeof(__le32)));
 259 }
 260
 261 static void rt2400pci_config_bssid(struct rt2x00_dev *rt2x00dev,
 262                                    __le32 *bssid)
 263 {
 264         rt2x00pci_register_multiwrite(rt2x00dev, CSR5, bssid,
 265                                       (2 * sizeof(__le32)));
 266 }
 267
 268 static void rt2400pci_config_type(struct rt2x00_dev *rt2x00dev, int type)
 269 {
 270         struct interface *intf = &rt2x00dev->interface;
 271         u32 reg;
 272
 273         rt2x00pci_register_write(rt2x00dev, CSR14, 0);
 274
 275         /*
 276          * Enable beacon config
 277          */
 278         rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
 279         rt2x00_set_field32(&reg, BCNCSR1_PRELOAD,
 280                            PREAMBLE + get_duration(IEEE80211_HEADER, 2));
 281         rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
 282
 283         /*
 284          * Enable synchronisation.
 285          */
 286         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
 287         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
 288         rt2x00_set_field32(&reg, CSR14_TBCN, 1);
 289         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
 290         if (is_interface_type(intf, IEEE80211_IF_TYPE_IBSS) ||
 291             is_interface_type(intf, IEEE80211_IF_TYPE_AP))
 292                 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 2);
 293         else if (is_interface_type(intf, IEEE80211_IF_TYPE_STA))
 294                 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 1);
 295         else
 296                 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
 297         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
 298 }
 299
 300 static void rt2400pci_config_rate(struct rt2x00_dev *rt2x00dev, const int rate)
 301 {
 302         struct ieee80211_conf *conf = &rt2x00dev->hw->conf;
 303         u32 reg;
 304         u32 preamble;
 305         u16 value;
 306
 307         if (DEVICE_GET_RATE_FIELD(rate, PREAMBLE))
 308                 preamble = SHORT_PREAMBLE;
 309         else
 310                 preamble = PREAMBLE;
 311
 312         reg = DEVICE_GET_RATE_FIELD(rate, RATEMASK) & DEV_BASIC_RATEMASK;
 313         rt2x00pci_register_write(rt2x00dev, ARCSR1, reg);
 314
 315         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
 316         value = ((conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME) ?
 317                  SHORT_DIFS : DIFS) +
 318             PLCP + preamble + get_duration(ACK_SIZE, 10);
 319         rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, value);
 320         value = SIFS + PLCP + preamble + get_duration(ACK_SIZE, 10);
 321         rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, value);
 322         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
 323
 324         preamble = DEVICE_GET_RATE_FIELD(rate, PREAMBLE) ? 0x08 : 0x00;
 325
 326         rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
 327         rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00 | preamble);
 328         rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
 329         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
 330         rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
 331
 332         rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
 333         rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble);
 334         rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
 335         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
 336         rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
 337
 338         rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
 339         rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble);
 340         rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
 341         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
 342         rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
 343
 344         rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
 345         rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble);
 346         rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
 347         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
 348         rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
 349 }
 350
 351 static void rt2400pci_config_phymode(struct rt2x00_dev *rt2x00dev,
 352                                      const int phymode)
 353 {
 354         struct ieee80211_hw_mode *mode;
 355         struct ieee80211_rate *rate;
 356
 357         rt2x00dev->curr_hwmode = HWMODE_B;
 358
 359         mode = &rt2x00dev->hwmodes[rt2x00dev->curr_hwmode];
 360         rate = &mode->rates[mode->num_rates - 1];
 361
 362         rt2400pci_config_rate(rt2x00dev, rate->val2);
 363 }
 364
 365 static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
 366                                      const int index, const int channel)
 367 {
 368         struct rf_channel reg;
 369
 370         /*
 371          * Fill rf_reg structure.
 372          */
 373         memcpy(&reg, &rt2x00dev->spec.channels[index], sizeof(reg));
 374
 375         /*
 376          * Switch on tuning bits.
 377          */
 378         rt2x00_set_field32(&reg.rf1, RF1_TUNER, 1);
 379         rt2x00_set_field32(&reg.rf3, RF3_TUNER, 1);
 380
 381         rt2400pci_rf_write(rt2x00dev, 1, reg.rf1);
 382         rt2400pci_rf_write(rt2x00dev, 2, reg.rf2);
 383         rt2400pci_rf_write(rt2x00dev, 3, reg.rf3);
 384
 385         /*
 386          * RF2420 chipset don't need any additional actions.
 387          */
 388         if (rt2x00_rf(&rt2x00dev->chip, RF2420))
 389                 return;
 390
 391         /*
 392          * For the RT2421 chipsets we need to write an invalid
 393          * reference clock rate to activate auto_tune.
 394          * After that we set the value back to the correct channel.
 395          */
 396         rt2400pci_rf_write(rt2x00dev, 1, reg.rf1);
 397         rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
 398         rt2400pci_rf_write(rt2x00dev, 3, reg.rf3);
 399
 400         msleep(1);
 401
 402         rt2400pci_rf_write(rt2x00dev, 1, reg.rf1);
 403         rt2400pci_rf_write(rt2x00dev, 2, reg.rf2);
 404         rt2400pci_rf_write(rt2x00dev, 3, reg.rf3);
 405
 406         msleep(1);
 407
 408         /*
 409          * Switch off tuning bits.
 410          */
 411         rt2x00_set_field32(&reg.rf1, RF1_TUNER, 0);
 412         rt2x00_set_field32(&reg.rf3, RF3_TUNER, 0);
 413
 414         rt2400pci_rf_write(rt2x00dev, 1, reg.rf1);
 415         rt2400pci_rf_write(rt2x00dev, 3, reg.rf3);
 416
 417         /*
 418          * Clear false CRC during channel switch.
 419          */
 420         rt2x00pci_register_read(rt2x00dev, CNT0, &reg.rf1);
 421 }
 422
 423 static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
 424 {
 425         rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
 426 }
 427
 428 static void rt2400pci_config_antenna(struct rt2x00_dev *rt2x00dev,
 429                                      int antenna_tx, int antenna_rx)
 430 {
 431         u8 r1;
 432         u8 r4;
 433
 434         rt2400pci_bbp_read(rt2x00dev, 4, &r4);
 435         rt2400pci_bbp_read(rt2x00dev, 1, &r1);
 436
 437         /*
 438          * Configure the TX antenna.
 439          */
 440         switch (antenna_tx) {
 441         case ANTENNA_SW_DIVERSITY:
 442         case ANTENNA_HW_DIVERSITY:
 443                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
 444                 break;
 445         case ANTENNA_A:
 446                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
 447                 break;
 448         case ANTENNA_B:
 449                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
 450                 break;
 451         }
 452
 453         /*
 454          * Configure the RX antenna.
 455          */
 456         switch (antenna_rx) {
 457         case ANTENNA_SW_DIVERSITY:
 458         case ANTENNA_HW_DIVERSITY:
 459                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
 460                 break;
 461         case ANTENNA_A:
 462                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
 463                 break;
 464         case ANTENNA_B:
 465                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
 466                 break;
 467         }
 468
 469         rt2400pci_bbp_write(rt2x00dev, 4, r4);
 470         rt2400pci_bbp_write(rt2x00dev, 1, r1);
 471 }
 472
 473 static void rt2400pci_config_duration(struct rt2x00_dev *rt2x00dev,
 474                                       int short_slot_time, int beacon_int)
 475 {
 476         u32 reg;
 477
 478         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 479         rt2x00_set_field32(&reg, CSR11_SLOT_TIME,
 480                            short_slot_time ? SHORT_SLOT_TIME : SLOT_TIME);
 481         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 482
 483         rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
 484         rt2x00_set_field32(&reg, CSR18_SIFS, SIFS);
 485         rt2x00_set_field32(&reg, CSR18_PIFS,
 486                            short_slot_time ? SHORT_PIFS : PIFS);
 487         rt2x00pci_register_write(rt2x00dev, CSR18, reg);
 488
 489         rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
 490         rt2x00_set_field32(&reg, CSR19_DIFS,
 491                            short_slot_time ? SHORT_DIFS : DIFS);
 492         rt2x00_set_field32(&reg, CSR19_EIFS, EIFS);
 493         rt2x00pci_register_write(rt2x00dev, CSR19, reg);
 494
 495         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
 496         rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
 497         rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
 498         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
 499
 500         rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
 501         rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL, beacon_int * 16);
 502         rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION, beacon_int * 16);
 503         rt2x00pci_register_write(rt2x00dev, CSR12, reg);
 504 }
 505
 506 static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
 507                              const unsigned int flags,
 508                              struct ieee80211_conf *conf)
 509 {
 510         int short_slot_time = conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME;
 511
 512         if (flags & CONFIG_UPDATE_PHYMODE)
 513                 rt2400pci_config_phymode(rt2x00dev, conf->phymode);
 514         if (flags & CONFIG_UPDATE_CHANNEL)
 515                 rt2400pci_config_channel(rt2x00dev, conf->channel_val,
 516                                          conf->channel);
 517         if (flags & CONFIG_UPDATE_TXPOWER)
 518                 rt2400pci_config_txpower(rt2x00dev, conf->power_level);
 519         if (flags & CONFIG_UPDATE_ANTENNA)
 520                 rt2400pci_config_antenna(rt2x00dev, conf->antenna_sel_tx,
 521                                          conf->antenna_sel_rx);
 522         if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
 523                 rt2400pci_config_duration(rt2x00dev, short_slot_time,
 524                                           conf->beacon_int);
 525 }
 526
 527 static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
 528                                 struct ieee80211_tx_queue_params *params)
 529 {
 530         u32 reg;
 531
 532         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 533         rt2x00_set_field32(&reg, CSR11_CWMIN, params->cw_min);
 534         rt2x00_set_field32(&reg, CSR11_CWMAX, params->cw_max);
 535         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 536 }
 537
 538 /*
 539  * LED functions.
 540  */
 541 static void rt2400pci_enable_led(struct rt2x00_dev *rt2x00dev)
 542 {
 543         u32 reg;
 544
 545         rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
 546
 547         rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, 70);
 548         rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, 30);
 549
 550         if (rt2x00dev->led_mode == LED_MODE_TXRX_ACTIVITY) {
 551                 rt2x00_set_field32(&reg, LEDCSR_LINK, 1);
 552                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 0);
 553         } else if (rt2x00dev->led_mode == LED_MODE_ASUS) {
 554                 rt2x00_set_field32(&reg, LEDCSR_LINK, 0);
 555                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 1);
 556         } else {
 557                 rt2x00_set_field32(&reg, LEDCSR_LINK, 1);
 558                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 1);
 559         }
 560
 561         rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
 562 }
 563
 564 static void rt2400pci_disable_led(struct rt2x00_dev *rt2x00dev)
 565 {
 566         u32 reg;
 567
 568         rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
 569         rt2x00_set_field32(&reg, LEDCSR_LINK, 0);
 570         rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 0);
 571         rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
 572 }
 573
 574 /*
 575  * Link tuning
 576  */
 577 static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev)
 578 {
 579         u32 reg;
 580         u8 bbp;
 581
 582         /*
 583          * Update FCS error count from register.
 584          */
 585         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 586         rt2x00dev->link.rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
 587
 588         /*
 589          * Update False CCA count from register.
 590          */
 591         rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
 592         rt2x00dev->link.false_cca = bbp;
 593 }
 594
 595 static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
 596 {
 597         rt2400pci_bbp_write(rt2x00dev, 13, 0x08);
 598         rt2x00dev->link.vgc_level = 0x08;
 599 }
 600
 601 static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev)
 602 {
 603         u8 reg;
 604
 605         /*
 606          * The link tuner should not run longer then 60 seconds,
 607          * and should run once every 2 seconds.
 608          */
 609         if (rt2x00dev->link.count > 60 || !(rt2x00dev->link.count & 1))
 610                 return;
 611
 612         /*
 613          * Base r13 link tuning on the false cca count.
 614          */
 615         rt2400pci_bbp_read(rt2x00dev, 13, &reg);
 616
 617         if (rt2x00dev->link.false_cca > 512 && reg < 0x20) {
 618                 rt2400pci_bbp_write(rt2x00dev, 13, ++reg);
 619                 rt2x00dev->link.vgc_level = reg;
 620         } else if (rt2x00dev->link.false_cca < 100 && reg > 0x08) {
 621                 rt2400pci_bbp_write(rt2x00dev, 13, --reg);
 622                 rt2x00dev->link.vgc_level = reg;
 623         }
 624 }
 625
 626 /*
 627  * Initialization functions.
 628  */
 629 static void rt2400pci_init_rxring(struct rt2x00_dev *rt2x00dev)
 630 {
 631         struct data_ring *ring = rt2x00dev->rx;
 632         struct data_desc *rxd;
 633         unsigned int i;
 634         u32 word;
 635
 636         memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
 637
 638         for (i = 0; i < ring->stats.limit; i++) {
 639                 rxd = ring->entry[i].priv;
 640
 641                 rt2x00_desc_read(rxd, 2, &word);
 642                 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH,
 643                                    ring->data_size);
 644                 rt2x00_desc_write(rxd, 2, word);
 645
 646                 rt2x00_desc_read(rxd, 1, &word);
 647                 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS,
 648                                    ring->entry[i].data_dma);
 649                 rt2x00_desc_write(rxd, 1, word);
 650
 651                 rt2x00_desc_read(rxd, 0, &word);
 652                 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
 653                 rt2x00_desc_write(rxd, 0, word);
 654         }
 655
 656         rt2x00_ring_index_clear(rt2x00dev->rx);
 657 }
 658
 659 static void rt2400pci_init_txring(struct rt2x00_dev *rt2x00dev, const int queue)
 660 {
 661         struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
 662         struct data_desc *txd;
 663         unsigned int i;
 664         u32 word;
 665
 666         memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
 667
 668         for (i = 0; i < ring->stats.limit; i++) {
 669                 txd = ring->entry[i].priv;
 670
 671                 rt2x00_desc_read(txd, 1, &word);
 672                 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS,
 673                                    ring->entry[i].data_dma);
 674                 rt2x00_desc_write(txd, 1, word);
 675
 676                 rt2x00_desc_read(txd, 2, &word);
 677                 rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH,
 678                                    ring->data_size);
 679                 rt2x00_desc_write(txd, 2, word);
 680
 681                 rt2x00_desc_read(txd, 0, &word);
 682                 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
 683                 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
 684                 rt2x00_desc_write(txd, 0, word);
 685         }
 686
 687         rt2x00_ring_index_clear(ring);
 688 }
 689
 690 static int rt2400pci_init_rings(struct rt2x00_dev *rt2x00dev)
 691 {
 692         u32 reg;
 693
 694         /*
 695          * Initialize rings.
 696          */
 697         rt2400pci_init_rxring(rt2x00dev);
 698         rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
 699         rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
 700         rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
 701         rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
 702
 703         /*
 704          * Initialize registers.
 705          */
 706         rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
 707         rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE,
 708                            rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].desc_size);
 709         rt2x00_set_field32(&reg, TXCSR2_NUM_TXD,
 710                            rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].stats.limit);
 711         rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM,
 712                            rt2x00dev->bcn[1].stats.limit);
 713         rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO,
 714                            rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].stats.limit);
 715         rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
 716
 717         rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
 718         rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
 719                            rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].data_dma);
 720         rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
 721
 722         rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
 723         rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
 724                            rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].data_dma);
 725         rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
 726
 727         rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
 728         rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
 729                            rt2x00dev->bcn[1].data_dma);
 730         rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
 731
 732         rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
 733         rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
 734                            rt2x00dev->bcn[0].data_dma);
 735         rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
 736
 737         rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
 738         rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
 739         rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->stats.limit);
 740         rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
 741
 742         rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
 743         rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
 744                            rt2x00dev->rx->data_dma);
 745         rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
 746
 747         return 0;
 748 }
 749
 750 static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
 751 {
 752         u32 reg;
 753
 754         rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
 755         rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
 756         rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20);
 757         rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
 758
 759         rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
 760         rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
 761         rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
 762         rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
 763         rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
 764
 765         rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
 766         rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
 767                            (rt2x00dev->rx->data_size / 128));
 768         rt2x00pci_register_write(rt2x00dev, CSR9, reg);
 769
 770         rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
 771
 772         rt2x00pci_register_read(rt2x00dev, ARCSR0, &reg);
 773         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
 774         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
 775         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
 776         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
 777         rt2x00pci_register_write(rt2x00dev, ARCSR0, reg);
 778
 779         rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
 780         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
 781         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
 782         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
 783         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
 784         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
 785         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
 786         rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
 787
 788         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
 789
 790         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
 791                 return -EBUSY;
 792
 793         rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
 794         rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
 795
 796         rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
 797         rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
 798         rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
 799
 800         rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
 801         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
 802         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
 803         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
 804         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
 805         rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
 806
 807         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 808         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
 809         rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
 810         rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
 811         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 812
 813         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 814         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
 815         rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
 816         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 817
 818         /*
 819          * We must clear the FCS and FIFO error count.
 820          * These registers are cleared on read,
 821          * so we may pass a useless variable to store the value.
 822          */
 823         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 824         rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
 825
 826         return 0;
 827 }
 828
 829 static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
 830 {
 831         unsigned int i;
 832         u16 eeprom;
 833         u8 reg_id;
 834         u8 value;
 835
 836         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 837                 rt2400pci_bbp_read(rt2x00dev, 0, &value);
 838                 if ((value != 0xff) && (value != 0x00))
 839                         goto continue_csr_init;
 840                 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
 841                 udelay(REGISTER_BUSY_DELAY);
 842         }
 843
 844         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
 845         return -EACCES;
 846
 847 continue_csr_init:
 848         rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
 849         rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
 850         rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
 851         rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
 852         rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
 853         rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
 854         rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
 855         rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
 856         rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
 857         rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
 858         rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
 859         rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
 860         rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
 861         rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
 862
 863         DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
 864         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
 865                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
 866
 867                 if (eeprom != 0xffff && eeprom != 0x0000) {
 868                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
 869                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
 870                         DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
 871                               reg_id, value);
 872                         rt2400pci_bbp_write(rt2x00dev, reg_id, value);
 873                 }
 874         }
 875         DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
 876
 877         return 0;
 878 }
 879
 880 /*
 881  * Device state switch handlers.
 882  */
 883 static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
 884                                 enum dev_state state)
 885 {
 886         u32 reg;
 887
 888         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
 889         rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
 890                            state == STATE_RADIO_RX_OFF);
 891         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
 892 }
 893
 894 static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
 895                                  enum dev_state state)
 896 {
 897         int mask = (state == STATE_RADIO_IRQ_OFF);
 898         u32 reg;
 899
 900         /*
 901          * When interrupts are being enabled, the interrupt registers
 902          * should clear the register to assure a clean state.
 903          */
 904         if (state == STATE_RADIO_IRQ_ON) {
 905                 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
 906                 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
 907         }
 908
 909         /*
 910          * Only toggle the interrupts bits we are going to use.
 911          * Non-checked interrupt bits are disabled by default.
 912          */
 913         rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
 914         rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
 915         rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
 916         rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
 917         rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
 918         rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
 919         rt2x00pci_register_write(rt2x00dev, CSR8, reg);
 920 }
 921
 922 static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
 923 {
 924         /*
 925          * Initialize all registers.
 926          */
 927         if (rt2400pci_init_rings(rt2x00dev) ||
 928             rt2400pci_init_registers(rt2x00dev) ||
 929             rt2400pci_init_bbp(rt2x00dev)) {
 930                 ERROR(rt2x00dev, "Register initialization failed.\n");
 931                 return -EIO;
 932         }
 933
 934         /*
 935          * Enable interrupts.
 936          */
 937         rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
 938
 939         /*
 940          * Enable LED
 941          */
 942         rt2400pci_enable_led(rt2x00dev);
 943
 944         return 0;
 945 }
 946
 947 static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
 948 {
 949         u32 reg;
 950
 951         /*
 952          * Disable LED
 953          */
 954         rt2400pci_disable_led(rt2x00dev);
 955
 956         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
 957
 958         /*
 959          * Disable synchronisation.
 960          */
 961         rt2x00pci_register_write(rt2x00dev, CSR14, 0);
 962
 963         /*
 964          * Cancel RX and TX.
 965          */
 966         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
 967         rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
 968         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
 969
 970         /*
 971          * Disable interrupts.
 972          */
 973         rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
 974 }
 975
 976 static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
 977                                enum dev_state state)
 978 {
 979         u32 reg;
 980         unsigned int i;
 981         char put_to_sleep;
 982         char bbp_state;
 983         char rf_state;
 984
 985         put_to_sleep = (state != STATE_AWAKE);
 986
 987         rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
 988         rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
 989         rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
 990         rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
 991         rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
 992         rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
 993
 994         /*
 995          * Device is not guaranteed to be in the requested state yet.
 996          * We must wait until the register indicates that the
 997          * device has entered the correct state.
 998          */
 999         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1000                 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1001                 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
1002                 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
1003                 if (bbp_state == state && rf_state == state)
1004                         return 0;
1005                 msleep(10);
1006         }
1007
1008         NOTICE(rt2x00dev, "Device failed to enter state %d, "
1009                "current device state: bbp %d and rf %d.\n",
1010                state, bbp_state, rf_state);
1011
1012         return -EBUSY;
1013 }
1014
1015 static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1016                                       enum dev_state state)
1017 {
1018         int retval = 0;
1019
1020         switch (state) {
1021         case STATE_RADIO_ON:
1022                 retval = rt2400pci_enable_radio(rt2x00dev);
1023                 break;
1024         case STATE_RADIO_OFF:
1025                 rt2400pci_disable_radio(rt2x00dev);
1026                 break;
1027         case STATE_RADIO_RX_ON:
1028         case STATE_RADIO_RX_OFF:
1029                 rt2400pci_toggle_rx(rt2x00dev, state);
1030                 break;
1031         case STATE_DEEP_SLEEP:
1032         case STATE_SLEEP:
1033         case STATE_STANDBY:
1034         case STATE_AWAKE:
1035                 retval = rt2400pci_set_state(rt2x00dev, state);
1036                 break;
1037         default:
1038                 retval = -ENOTSUPP;
1039                 break;
1040         }
1041
1042         return retval;
1043 }
1044
1045 /*
1046  * TX descriptor initialization
1047  */
1048 static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1049                                     struct data_desc *txd,
1050                                     struct txdata_entry_desc *desc,
1051                                     struct ieee80211_hdr *ieee80211hdr,
1052                                     unsigned int length,
1053                                     struct ieee80211_tx_control *control)
1054 {
1055         u32 word;
1056         u32 signal = 0;
1057         u32 service = 0;
1058         u32 length_high = 0;
1059         u32 length_low = 0;
1060
1061         /*
1062          * The PLCP values should be treated as if they
1063          * were BBP values.
1064          */
1065         rt2x00_set_field32(&signal, BBPCSR_VALUE, desc->signal);
1066         rt2x00_set_field32(&signal, BBPCSR_REGNUM, 5);
1067         rt2x00_set_field32(&signal, BBPCSR_BUSY, 1);
1068
1069         rt2x00_set_field32(&service, BBPCSR_VALUE, desc->service);
1070         rt2x00_set_field32(&service, BBPCSR_REGNUM, 6);
1071         rt2x00_set_field32(&service, BBPCSR_BUSY, 1);
1072
1073         rt2x00_set_field32(&length_high, BBPCSR_VALUE, desc->length_high);
1074         rt2x00_set_field32(&length_high, BBPCSR_REGNUM, 7);
1075         rt2x00_set_field32(&length_high, BBPCSR_BUSY, 1);
1076
1077         rt2x00_set_field32(&length_low, BBPCSR_VALUE, desc->length_low);
1078         rt2x00_set_field32(&length_low, BBPCSR_REGNUM, 8);
1079         rt2x00_set_field32(&length_low, BBPCSR_BUSY, 1);
1080
1081         /*
1082          * Start writing the descriptor words.
1083          */
1084         rt2x00_desc_read(txd, 2, &word);
1085         rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, length);
1086         rt2x00_desc_write(txd, 2, word);
1087
1088         rt2x00_desc_read(txd, 3, &word);
1089         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, signal);
1090         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, service);
1091         rt2x00_desc_write(txd, 3, word);
1092
1093         rt2x00_desc_read(txd, 4, &word);
1094         rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, length_low);
1095         rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, length_high);
1096         rt2x00_desc_write(txd, 4, word);
1097
1098         rt2x00_desc_read(txd, 0, &word);
1099         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1100         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1101         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1102                            test_bit(ENTRY_TXD_MORE_FRAG, &desc->flags));
1103         rt2x00_set_field32(&word, TXD_W0_ACK,
1104                            !(control->flags & IEEE80211_TXCTL_NO_ACK));
1105         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1106                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc->flags));
1107         rt2x00_set_field32(&word, TXD_W0_RTS,
1108                            test_bit(ENTRY_TXD_RTS_FRAME, &desc->flags));
1109         rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs);
1110         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1111                            !!(control->flags &
1112                               IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1113         rt2x00_desc_write(txd, 0, word);
1114 }
1115
1116 /*
1117  * TX data initialization
1118  */
1119 static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1120                                     unsigned int queue)
1121 {
1122         u32 reg;
1123
1124         if (queue == IEEE80211_TX_QUEUE_BEACON) {
1125                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1126                 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1127                         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1128                         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1129                 }
1130                 return;
1131         }
1132
1133         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1134         if (queue == IEEE80211_TX_QUEUE_DATA0)
1135                 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, 1);
1136         else if (queue == IEEE80211_TX_QUEUE_DATA1)
1137                 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, 1);
1138         else if (queue == IEEE80211_TX_QUEUE_AFTER_BEACON)
1139                 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, 1);
1140         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1141 }
1142
1143 /*
1144  * RX control handlers
1145  */
1146 static void rt2400pci_fill_rxdone(struct data_entry *entry,
1147                                   struct rxdata_entry_desc *desc)
1148 {
1149         struct data_desc *rxd = entry->priv;
1150         u32 word0;
1151         u32 word2;
1152
1153         rt2x00_desc_read(rxd, 0, &word0);
1154         rt2x00_desc_read(rxd, 2, &word2);
1155
1156         desc->flags = 0;
1157         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1158                 desc->flags |= RX_FLAG_FAILED_FCS_CRC;
1159         if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1160                 desc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1161
1162         /*
1163          * Obtain the status about this packet.
1164          */
1165         desc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1166         desc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1167             entry->ring->rt2x00dev->rssi_offset;
1168         desc->ofdm = 0;
1169         desc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1170 }
1171
1172 /*
1173  * Interrupt functions.
1174  */
1175 static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev, const int queue)
1176 {
1177         struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
1178         struct data_entry *entry;
1179         struct data_desc *txd;
1180         u32 word;
1181         int tx_status;
1182         int retry;
1183
1184         while (!rt2x00_ring_empty(ring)) {
1185                 entry = rt2x00_get_data_entry_done(ring);
1186                 txd = entry->priv;
1187                 rt2x00_desc_read(txd, 0, &word);
1188
1189                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1190                     !rt2x00_get_field32(word, TXD_W0_VALID))
1191                         break;
1192
1193                 /*
1194                  * Obtain the status about this packet.
1195                  */
1196                 tx_status = rt2x00_get_field32(word, TXD_W0_RESULT);
1197                 retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1198
1199                 rt2x00lib_txdone(entry, tx_status, retry);
1200
1201                 /*
1202                  * Make this entry available for reuse.
1203                  */
1204                 entry->flags = 0;
1205                 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1206                 rt2x00_desc_write(txd, 0, word);
1207                 rt2x00_ring_index_done_inc(ring);
1208         }
1209
1210         /*
1211          * If the data ring was full before the txdone handler
1212          * we must make sure the packet queue in the mac80211 stack
1213          * is reenabled when the txdone handler has finished.
1214          */
1215         entry = ring->entry;
1216         if (!rt2x00_ring_full(ring))
1217                 ieee80211_wake_queue(rt2x00dev->hw,
1218                                      entry->tx_status.control.queue);
1219 }
1220
1221 static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1222 {
1223         struct rt2x00_dev *rt2x00dev = dev_instance;
1224         u32 reg;
1225
1226         /*
1227          * Get the interrupt sources & saved to local variable.
1228          * Write register value back to clear pending interrupts.
1229          */
1230         rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1231         rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1232
1233         if (!reg)
1234                 return IRQ_NONE;
1235
1236         if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1237                 return IRQ_HANDLED;
1238
1239         /*
1240          * Handle interrupts, walk through all bits
1241          * and run the tasks, the bits are checked in order of
1242          * priority.
1243          */
1244
1245         /*
1246          * 1 - Beacon timer expired interrupt.
1247          */
1248         if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1249                 rt2x00lib_beacondone(rt2x00dev);
1250
1251         /*
1252          * 2 - Rx ring done interrupt.
1253          */
1254         if (rt2x00_get_field32(reg, CSR7_RXDONE))
1255                 rt2x00pci_rxdone(rt2x00dev);
1256
1257         /*
1258          * 3 - Atim ring transmit done interrupt.
1259          */
1260         if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1261                 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
1262
1263         /*
1264          * 4 - Priority ring transmit done interrupt.
1265          */
1266         if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1267                 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
1268
1269         /*
1270          * 5 - Tx ring transmit done interrupt.
1271          */
1272         if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1273                 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
1274
1275         return IRQ_HANDLED;
1276 }
1277
1278 /*
1279  * Device probe functions.
1280  */
1281 static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1282 {
1283         struct eeprom_93cx6 eeprom;
1284         u32 reg;
1285         u16 word;
1286         u8 *mac;
1287
1288         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1289
1290         eeprom.data = rt2x00dev;
1291         eeprom.register_read = rt2400pci_eepromregister_read;
1292         eeprom.register_write = rt2400pci_eepromregister_write;
1293         eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1294             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1295         eeprom.reg_data_in = 0;
1296         eeprom.reg_data_out = 0;
1297         eeprom.reg_data_clock = 0;
1298         eeprom.reg_chip_select = 0;
1299
1300         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1301                                EEPROM_SIZE / sizeof(u16));
1302
1303         /*
1304          * Start validation of the data that has been read.
1305          */
1306         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1307         if (!is_valid_ether_addr(mac)) {
1308                 DECLARE_MAC_BUF(macbuf);
1309
1310                 random_ether_addr(mac);
1311                 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
1312         }
1313
1314         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1315         if (word == 0xffff) {
1316                 ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
1317                 return -EINVAL;
1318         }
1319
1320         return 0;
1321 }
1322
1323 static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1324 {
1325         u32 reg;
1326         u16 value;
1327         u16 eeprom;
1328
1329         /*
1330          * Read EEPROM word for configuration.
1331          */
1332         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1333
1334         /*
1335          * Identify RF chipset.
1336          */
1337         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1338         rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1339         rt2x00_set_chip(rt2x00dev, RT2460, value, reg);
1340
1341         if (!rt2x00_rf(&rt2x00dev->chip, RF2420) &&
1342             !rt2x00_rf(&rt2x00dev->chip, RF2421)) {
1343                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1344                 return -ENODEV;
1345         }
1346
1347         /*
1348          * Identify default antenna configuration.
1349          */
1350         rt2x00dev->hw->conf.antenna_sel_tx =
1351             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1352         rt2x00dev->hw->conf.antenna_sel_rx =
1353             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1354
1355         /*
1356          * Store led mode, for correct led behaviour.
1357          */
1358         rt2x00dev->led_mode =
1359             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1360
1361         /*
1362          * Detect if this device has an hardware controlled radio.
1363          */
1364 #ifdef CONFIG_RT2400PCI_RFKILL
1365         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1366                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1367 #endif /* CONFIG_RT2400PCI_RFKILL */
1368
1369         /*
1370          * Check if the BBP tuning should be enabled.
1371          */
1372         if (!rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1373                 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1374
1375         return 0;
1376 }
1377
1378 /*
1379  * RF value list for RF2420 & RF2421
1380  * Supports: 2.4 GHz
1381  */
1382 static const struct rf_channel rf_vals_bg[] = {
1383         { 1,  0x00022058, 0x000c1fda, 0x00000101, 0 },
1384         { 2,  0x00022058, 0x000c1fee, 0x00000101, 0 },
1385         { 3,  0x00022058, 0x000c2002, 0x00000101, 0 },
1386         { 4,  0x00022058, 0x000c2016, 0x00000101, 0 },
1387         { 5,  0x00022058, 0x000c202a, 0x00000101, 0 },
1388         { 6,  0x00022058, 0x000c203e, 0x00000101, 0 },
1389         { 7,  0x00022058, 0x000c2052, 0x00000101, 0 },
1390         { 8,  0x00022058, 0x000c2066, 0x00000101, 0 },
1391         { 9,  0x00022058, 0x000c207a, 0x00000101, 0 },
1392         { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1393         { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1394         { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1395         { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1396         { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1397 };
1398
1399 static void rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1400 {
1401         struct hw_mode_spec *spec = &rt2x00dev->spec;
1402         u8 *txpower;
1403         unsigned int i;
1404
1405         /*
1406          * Initialize all hw fields.
1407          */
1408         rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
1409         rt2x00dev->hw->extra_tx_headroom = 0;
1410         rt2x00dev->hw->max_signal = MAX_SIGNAL;
1411         rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1412         rt2x00dev->hw->queues = 2;
1413
1414         SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
1415         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1416                                 rt2x00_eeprom_addr(rt2x00dev,
1417                                                    EEPROM_MAC_ADDR_0));
1418
1419         /*
1420          * Convert tx_power array in eeprom.
1421          */
1422         txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1423         for (i = 0; i < 14; i++)
1424                 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1425
1426         /*
1427          * Initialize hw_mode information.
1428          */
1429         spec->num_modes = 1;
1430         spec->num_rates = 4;
1431         spec->tx_power_a = NULL;
1432         spec->tx_power_bg = txpower;
1433         spec->tx_power_default = DEFAULT_TXPOWER;
1434
1435         spec->num_channels = ARRAY_SIZE(rf_vals_bg);
1436         spec->channels = rf_vals_bg;
1437 }
1438
1439 static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1440 {
1441         int retval;
1442
1443         /*
1444          * Allocate eeprom data.
1445          */
1446         retval = rt2400pci_validate_eeprom(rt2x00dev);
1447         if (retval)
1448                 return retval;
1449
1450         retval = rt2400pci_init_eeprom(rt2x00dev);
1451         if (retval)
1452                 return retval;
1453
1454         /*
1455          * Initialize hw specifications.
1456          */
1457         rt2400pci_probe_hw_mode(rt2x00dev);
1458
1459         /*
1460          * This device requires the beacon ring
1461          */
1462         __set_bit(DRIVER_REQUIRE_BEACON_RING, &rt2x00dev->flags);
1463
1464         /*
1465          * Set the rssi offset.
1466          */
1467         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1468
1469         return 0;
1470 }
1471
1472 /*
1473  * IEEE80211 stack callback functions.
1474  */
1475 static void rt2400pci_configure_filter(struct ieee80211_hw *hw,
1476                                        unsigned int changed_flags,
1477                                        unsigned int *total_flags,
1478                                        int mc_count,
1479                                        struct dev_addr_list *mc_list)
1480 {
1481         struct rt2x00_dev *rt2x00dev = hw->priv;
1482         struct interface *intf = &rt2x00dev->interface;
1483         u32 reg;
1484
1485         /*
1486          * Mask off any flags we are going to ignore from
1487          * the total_flags field.
1488          */
1489         *total_flags &=
1490             FIF_ALLMULTI |
1491             FIF_FCSFAIL |
1492             FIF_PLCPFAIL |
1493             FIF_CONTROL |
1494             FIF_OTHER_BSS |
1495             FIF_PROMISC_IN_BSS;
1496
1497         /*
1498          * Apply some rules to the filters:
1499          * - Some filters imply different filters to be set.
1500          * - Some things we can't filter out at all.
1501          * - Some filters are set based on interface type.
1502          */
1503         *total_flags |= FIF_ALLMULTI;
1504         if (*total_flags & FIF_OTHER_BSS ||
1505             *total_flags & FIF_PROMISC_IN_BSS)
1506                 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
1507         if (is_interface_type(intf, IEEE80211_IF_TYPE_AP))
1508                 *total_flags |= FIF_PROMISC_IN_BSS;
1509
1510         /*
1511          * Check if there is any work left for us.
1512          */
1513         if (intf->filter == *total_flags)
1514                 return;
1515         intf->filter = *total_flags;
1516
1517         /*
1518          * Start configuration steps.
1519          * Note that the version error will always be dropped
1520          * since there is no filter for it at this time.
1521          */
1522         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1523         rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
1524                            !(*total_flags & FIF_FCSFAIL));
1525         rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
1526                            !(*total_flags & FIF_PLCPFAIL));
1527         rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
1528                            !(*total_flags & FIF_CONTROL));
1529         rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
1530                            !(*total_flags & FIF_PROMISC_IN_BSS));
1531         rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
1532                            !(*total_flags & FIF_PROMISC_IN_BSS));
1533         rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
1534         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1535 }
1536
1537 static int rt2400pci_set_retry_limit(struct ieee80211_hw *hw,
1538                                      u32 short_retry, u32 long_retry)
1539 {
1540         struct rt2x00_dev *rt2x00dev = hw->priv;
1541         u32 reg;
1542
1543         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
1544         rt2x00_set_field32(&reg, CSR11_LONG_RETRY, long_retry);
1545         rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, short_retry);
1546         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1547
1548         return 0;
1549 }
1550
1551 static int rt2400pci_conf_tx(struct ieee80211_hw *hw,
1552                              int queue,
1553                              const struct ieee80211_tx_queue_params *params)
1554 {
1555         struct rt2x00_dev *rt2x00dev = hw->priv;
1556
1557         /*
1558          * We don't support variating cw_min and cw_max variables
1559          * per queue. So by default we only configure the TX queue,
1560          * and ignore all other configurations.
1561          */
1562         if (queue != IEEE80211_TX_QUEUE_DATA0)
1563                 return -EINVAL;
1564
1565         if (rt2x00mac_conf_tx(hw, queue, params))
1566                 return -EINVAL;
1567
1568         /*
1569          * Write configuration to register.
1570          */
1571         rt2400pci_config_cw(rt2x00dev, &rt2x00dev->tx->tx_params);
1572
1573         return 0;
1574 }
1575
1576 static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
1577 {
1578         struct rt2x00_dev *rt2x00dev = hw->priv;
1579         u64 tsf;
1580         u32 reg;
1581
1582         rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1583         tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1584         rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1585         tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1586
1587         return tsf;
1588 }
1589
1590 static void rt2400pci_reset_tsf(struct ieee80211_hw *hw)
1591 {
1592         struct rt2x00_dev *rt2x00dev = hw->priv;
1593
1594         rt2x00pci_register_write(rt2x00dev, CSR16, 0);
1595         rt2x00pci_register_write(rt2x00dev, CSR17, 0);
1596 }
1597
1598 static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1599 {
1600         struct rt2x00_dev *rt2x00dev = hw->priv;
1601         u32 reg;
1602
1603         rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1604         return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1605 }
1606
1607 static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1608         .tx                     = rt2x00mac_tx,
1609         .start                  = rt2x00mac_start,
1610         .stop                   = rt2x00mac_stop,
1611         .add_interface          = rt2x00mac_add_interface,
1612         .remove_interface       = rt2x00mac_remove_interface,
1613         .config                 = rt2x00mac_config,
1614         .config_interface       = rt2x00mac_config_interface,
1615         .configure_filter       = rt2400pci_configure_filter,
1616         .get_stats              = rt2x00mac_get_stats,
1617         .set_retry_limit        = rt2400pci_set_retry_limit,
1618         .conf_tx                = rt2400pci_conf_tx,
1619         .get_tx_stats           = rt2x00mac_get_tx_stats,
1620         .get_tsf                = rt2400pci_get_tsf,
1621         .reset_tsf              = rt2400pci_reset_tsf,
1622         .beacon_update          = rt2x00pci_beacon_update,
1623         .tx_last_beacon         = rt2400pci_tx_last_beacon,
1624 };
1625
1626 static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1627         .irq_handler            = rt2400pci_interrupt,
1628         .probe_hw               = rt2400pci_probe_hw,
1629         .initialize             = rt2x00pci_initialize,
1630         .uninitialize           = rt2x00pci_uninitialize,
1631         .set_device_state       = rt2400pci_set_device_state,
1632         .rfkill_poll            = rt2400pci_rfkill_poll,
1633         .link_stats             = rt2400pci_link_stats,
1634         .reset_tuner            = rt2400pci_reset_tuner,
1635         .link_tuner             = rt2400pci_link_tuner,
1636         .write_tx_desc          = rt2400pci_write_tx_desc,
1637         .write_tx_data          = rt2x00pci_write_tx_data,
1638         .kick_tx_queue          = rt2400pci_kick_tx_queue,
1639         .fill_rxdone            = rt2400pci_fill_rxdone,
1640         .config_mac_addr        = rt2400pci_config_mac_addr,
1641         .config_bssid           = rt2400pci_config_bssid,
1642         .config_type            = rt2400pci_config_type,
1643         .config                 = rt2400pci_config,
1644 };
1645
1646 static const struct rt2x00_ops rt2400pci_ops = {
1647         .name           = DRV_NAME,
1648         .rxd_size       = RXD_DESC_SIZE,
1649         .txd_size       = TXD_DESC_SIZE,
1650         .eeprom_size    = EEPROM_SIZE,
1651         .rf_size        = RF_SIZE,
1652         .lib            = &rt2400pci_rt2x00_ops,
1653         .hw             = &rt2400pci_mac80211_ops,
1654 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1655         .debugfs        = &rt2400pci_rt2x00debug,
1656 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1657 };
1658
1659 /*
1660  * RT2400pci module information.
1661  */
1662 static struct pci_device_id rt2400pci_device_table[] = {
1663         { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) },
1664         { 0, }
1665 };
1666
1667 MODULE_AUTHOR(DRV_PROJECT);
1668 MODULE_VERSION(DRV_VERSION);
1669 MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1670 MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1671 MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1672 MODULE_LICENSE("GPL");
1673
1674 static struct pci_driver rt2400pci_driver = {
1675         .name           = DRV_NAME,
1676         .id_table       = rt2400pci_device_table,
1677         .probe          = rt2x00pci_probe,
1678         .remove         = __devexit_p(rt2x00pci_remove),
1679         .suspend        = rt2x00pci_suspend,
1680         .resume         = rt2x00pci_resume,
1681 };
1682
1683 static int __init rt2400pci_init(void)
1684 {
1685         return pci_register_driver(&rt2400pci_driver);
1686 }
1687
1688 static void __exit rt2400pci_exit(void)
1689 {
1690         pci_unregister_driver(&rt2400pci_driver);
1691 }
1692
1693 module_init(rt2400pci_init);
1694 module_exit(rt2400pci_exit);