drivers/net/wireless/rt2x00/rt2400pci.c

   1 /*
   2         Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt2400pci
  23         Abstract: rt2400pci device specific routines.
  24         Supported chipsets: RT2460.
  25  */
  26
  27 #include <linux/delay.h>
  28 #include <linux/etherdevice.h>
  29 #include <linux/init.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/pci.h>
  33 #include <linux/eeprom_93cx6.h>
  34
  35 #include "rt2x00.h"
  36 #include "rt2x00pci.h"
  37 #include "rt2400pci.h"
  38
  39 /*
  40  * Register access.
  41  * All access to the CSR registers will go through the methods
  42  * rt2x00pci_register_read and rt2x00pci_register_write.
  43  * BBP and RF register require indirect register access,
  44  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  45  * These indirect registers work with busy bits,
  46  * and we will try maximal REGISTER_BUSY_COUNT times to access
  47  * the register while taking a REGISTER_BUSY_DELAY us delay
  48  * between each attampt. When the busy bit is still set at that time,
  49  * the access attempt is considered to have failed,
  50  * and we will print an error.
  51  */
  52 static u32 rt2400pci_bbp_check(struct rt2x00_dev *rt2x00dev)
  53 {
  54         u32 reg;
  55         unsigned int i;
  56
  57         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  58                 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
  59                 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
  60                         break;
  61                 udelay(REGISTER_BUSY_DELAY);
  62         }
  63
  64         return reg;
  65 }
  66
  67 static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
  68                                 const unsigned int word, const u8 value)
  69 {
  70         u32 reg;
  71
  72         /*
  73          * Wait until the BBP becomes ready.
  74          */
  75         reg = rt2400pci_bbp_check(rt2x00dev);
  76         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
  77                 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
  78                 return;
  79         }
  80
  81         /*
  82          * Write the data into the BBP.
  83          */
  84         reg = 0;
  85         rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
  86         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
  87         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
  88         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
  89
  90         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
  91 }
  92
  93 static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
  94                                const unsigned int word, u8 *value)
  95 {
  96         u32 reg;
  97
  98         /*
  99          * Wait until the BBP becomes ready.
 100          */
 101         reg = rt2400pci_bbp_check(rt2x00dev);
 102         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
 103                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
 104                 return;
 105         }
 106
 107         /*
 108          * Write the request into the BBP.
 109          */
 110         reg = 0;
 111         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
 112         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
 113         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
 114
 115         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
 116
 117         /*
 118          * Wait until the BBP becomes ready.
 119          */
 120         reg = rt2400pci_bbp_check(rt2x00dev);
 121         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
 122                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
 123                 *value = 0xff;
 124                 return;
 125         }
 126
 127         *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
 128 }
 129
 130 static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
 131                                const unsigned int word, const u32 value)
 132 {
 133         u32 reg;
 134         unsigned int i;
 135
 136         if (!word)
 137                 return;
 138
 139         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 140                 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
 141                 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
 142                         goto rf_write;
 143                 udelay(REGISTER_BUSY_DELAY);
 144         }
 145
 146         ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
 147         return;
 148
 149 rf_write:
 150         reg = 0;
 151         rt2x00_set_field32(&reg, RFCSR_VALUE, value);
 152         rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
 153         rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
 154         rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
 155
 156         rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
 157         rt2x00_rf_write(rt2x00dev, word, value);
 158 }
 159
 160 static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 161 {
 162         struct rt2x00_dev *rt2x00dev = eeprom->data;
 163         u32 reg;
 164
 165         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
 166
 167         eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
 168         eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
 169         eeprom->reg_data_clock =
 170             !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
 171         eeprom->reg_chip_select =
 172             !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
 173 }
 174
 175 static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 176 {
 177         struct rt2x00_dev *rt2x00dev = eeprom->data;
 178         u32 reg = 0;
 179
 180         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
 181         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
 182         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
 183                            !!eeprom->reg_data_clock);
 184         rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
 185                            !!eeprom->reg_chip_select);
 186
 187         rt2x00pci_register_write(rt2x00dev, CSR21, reg);
 188 }
 189
 190 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 191 #define CSR_OFFSET(__word)      ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
 192
 193 static void rt2400pci_read_csr(struct rt2x00_dev *rt2x00dev,
 194                                const unsigned int word, u32 *data)
 195 {
 196         rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
 197 }
 198
 199 static void rt2400pci_write_csr(struct rt2x00_dev *rt2x00dev,
 200                                 const unsigned int word, u32 data)
 201 {
 202         rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
 203 }
 204
 205 static const struct rt2x00debug rt2400pci_rt2x00debug = {
 206         .owner  = THIS_MODULE,
 207         .csr    = {
 208                 .read           = rt2400pci_read_csr,
 209                 .write          = rt2400pci_write_csr,
 210                 .word_size      = sizeof(u32),
 211                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 212         },
 213         .eeprom = {
 214                 .read           = rt2x00_eeprom_read,
 215                 .write          = rt2x00_eeprom_write,
 216                 .word_size      = sizeof(u16),
 217                 .word_count     = EEPROM_SIZE / sizeof(u16),
 218         },
 219         .bbp    = {
 220                 .read           = rt2400pci_bbp_read,
 221                 .write          = rt2400pci_bbp_write,
 222                 .word_size      = sizeof(u8),
 223                 .word_count     = BBP_SIZE / sizeof(u8),
 224         },
 225         .rf     = {
 226                 .read           = rt2x00_rf_read,
 227                 .write          = rt2400pci_rf_write,
 228                 .word_size      = sizeof(u32),
 229                 .word_count     = RF_SIZE / sizeof(u32),
 230         },
 231 };
 232 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 233
 234 #ifdef CONFIG_RT2400PCI_RFKILL
 235 static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 236 {
 237         u32 reg;
 238
 239         rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
 240         return rt2x00_get_field32(reg, GPIOCSR_BIT0);
 241 }
 242 #else
 243 #define rt2400pci_rfkill_poll   NULL
 244 #endif /* CONFIG_RT2400PCI_RFKILL */
 245
 246 #ifdef CONFIG_RT2400PCI_LEDS
 247 static void rt2400pci_led_brightness(struct led_classdev *led_cdev,
 248                                      enum led_brightness brightness)
 249 {
 250         struct rt2x00_led *led =
 251             container_of(led_cdev, struct rt2x00_led, led_dev);
 252         unsigned int enabled = brightness != LED_OFF;
 253         unsigned int activity =
 254             led->rt2x00dev->led_flags & LED_SUPPORT_ACTIVITY;
 255         u32 reg;
 256
 257         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
 258
 259         if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC) {
 260                 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
 261                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled && activity);
 262         }
 263
 264         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
 265 }
 266 #else
 267 #define rt2400pci_led_brightness        NULL
 268 #endif /* CONFIG_RT2400PCI_LEDS */
 269
 270 /*
 271  * Configuration handlers.
 272  */
 273 static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
 274                                   struct rt2x00_intf *intf,
 275                                   struct rt2x00intf_conf *conf,
 276                                   const unsigned int flags)
 277 {
 278         unsigned int bcn_preload;
 279         u32 reg;
 280
 281         if (flags & CONFIG_UPDATE_TYPE) {
 282                 /*
 283                  * Enable beacon config
 284                  */
 285                 bcn_preload = PREAMBLE + get_duration(IEEE80211_HEADER, 20);
 286                 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
 287                 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
 288                 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
 289
 290                 /*
 291                  * Enable synchronisation.
 292                  */
 293                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
 294                 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
 295                 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
 296         }
 297
 298         if (flags & CONFIG_UPDATE_MAC)
 299                 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
 300                                               conf->mac, sizeof(conf->mac));
 301
 302         if (flags & CONFIG_UPDATE_BSSID)
 303                 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
 304                                               conf->bssid, sizeof(conf->bssid));
 305 }
 306
 307 static int rt2400pci_config_preamble(struct rt2x00_dev *rt2x00dev,
 308                                      const int short_preamble,
 309                                      const int ack_timeout,
 310                                      const int ack_consume_time)
 311 {
 312         int preamble_mask;
 313         u32 reg;
 314
 315         /*
 316          * When short preamble is enabled, we should set bit 0x08
 317          */
 318         preamble_mask = short_preamble << 3;
 319
 320         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
 321         rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, ack_timeout);
 322         rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, ack_consume_time);
 323         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
 324
 325         rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
 326         rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00 | preamble_mask);
 327         rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
 328         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
 329         rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
 330
 331         rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
 332         rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
 333         rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
 334         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
 335         rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
 336
 337         rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
 338         rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
 339         rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
 340         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
 341         rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
 342
 343         rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
 344         rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
 345         rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
 346         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
 347         rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
 348
 349         return 0;
 350 }
 351
 352 static void rt2400pci_config_phymode(struct rt2x00_dev *rt2x00dev,
 353                                      const int basic_rate_mask)
 354 {
 355         rt2x00pci_register_write(rt2x00dev, ARCSR1, basic_rate_mask);
 356 }
 357
 358 static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
 359                                      struct rf_channel *rf)
 360 {
 361         /*
 362          * Switch on tuning bits.
 363          */
 364         rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
 365         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
 366
 367         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
 368         rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
 369         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
 370
 371         /*
 372          * RF2420 chipset don't need any additional actions.
 373          */
 374         if (rt2x00_rf(&rt2x00dev->chip, RF2420))
 375                 return;
 376
 377         /*
 378          * For the RT2421 chipsets we need to write an invalid
 379          * reference clock rate to activate auto_tune.
 380          * After that we set the value back to the correct channel.
 381          */
 382         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
 383         rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
 384         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
 385
 386         msleep(1);
 387
 388         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
 389         rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
 390         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
 391
 392         msleep(1);
 393
 394         /*
 395          * Switch off tuning bits.
 396          */
 397         rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
 398         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
 399
 400         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
 401         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
 402
 403         /*
 404          * Clear false CRC during channel switch.
 405          */
 406         rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
 407 }
 408
 409 static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
 410 {
 411         rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
 412 }
 413
 414 static void rt2400pci_config_antenna(struct rt2x00_dev *rt2x00dev,
 415                                      struct antenna_setup *ant)
 416 {
 417         u8 r1;
 418         u8 r4;
 419
 420         rt2400pci_bbp_read(rt2x00dev, 4, &r4);
 421         rt2400pci_bbp_read(rt2x00dev, 1, &r1);
 422
 423         /*
 424          * Configure the TX antenna.
 425          */
 426         switch (ant->tx) {
 427         case ANTENNA_HW_DIVERSITY:
 428                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
 429                 break;
 430         case ANTENNA_A:
 431                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
 432                 break;
 433         case ANTENNA_SW_DIVERSITY:
 434                 /*
 435                  * NOTE: We should never come here because rt2x00lib is
 436                  * supposed to catch this and send us the correct antenna
 437                  * explicitely. However we are nog going to bug about this.
 438                  * Instead, just default to antenna B.
 439                  */
 440         case ANTENNA_B:
 441                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
 442                 break;
 443         }
 444
 445         /*
 446          * Configure the RX antenna.
 447          */
 448         switch (ant->rx) {
 449         case ANTENNA_HW_DIVERSITY:
 450                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
 451                 break;
 452         case ANTENNA_A:
 453                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
 454                 break;
 455         case ANTENNA_SW_DIVERSITY:
 456                 /*
 457                  * NOTE: We should never come here because rt2x00lib is
 458                  * supposed to catch this and send us the correct antenna
 459                  * explicitely. However we are nog going to bug about this.
 460                  * Instead, just default to antenna B.
 461                  */
 462         case ANTENNA_B:
 463                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
 464                 break;
 465         }
 466
 467         rt2400pci_bbp_write(rt2x00dev, 4, r4);
 468         rt2400pci_bbp_write(rt2x00dev, 1, r1);
 469 }
 470
 471 static void rt2400pci_config_duration(struct rt2x00_dev *rt2x00dev,
 472                                       struct rt2x00lib_conf *libconf)
 473 {
 474         u32 reg;
 475
 476         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 477         rt2x00_set_field32(&reg, CSR11_SLOT_TIME, libconf->slot_time);
 478         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 479
 480         rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
 481         rt2x00_set_field32(&reg, CSR18_SIFS, libconf->sifs);
 482         rt2x00_set_field32(&reg, CSR18_PIFS, libconf->pifs);
 483         rt2x00pci_register_write(rt2x00dev, CSR18, reg);
 484
 485         rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
 486         rt2x00_set_field32(&reg, CSR19_DIFS, libconf->difs);
 487         rt2x00_set_field32(&reg, CSR19_EIFS, libconf->eifs);
 488         rt2x00pci_register_write(rt2x00dev, CSR19, reg);
 489
 490         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
 491         rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
 492         rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
 493         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
 494
 495         rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
 496         rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
 497                            libconf->conf->beacon_int * 16);
 498         rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
 499                            libconf->conf->beacon_int * 16);
 500         rt2x00pci_register_write(rt2x00dev, CSR12, reg);
 501 }
 502
 503 static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
 504                              struct rt2x00lib_conf *libconf,
 505                              const unsigned int flags)
 506 {
 507         if (flags & CONFIG_UPDATE_PHYMODE)
 508                 rt2400pci_config_phymode(rt2x00dev, libconf->basic_rates);
 509         if (flags & CONFIG_UPDATE_CHANNEL)
 510                 rt2400pci_config_channel(rt2x00dev, &libconf->rf);
 511         if (flags & CONFIG_UPDATE_TXPOWER)
 512                 rt2400pci_config_txpower(rt2x00dev,
 513                                          libconf->conf->power_level);
 514         if (flags & CONFIG_UPDATE_ANTENNA)
 515                 rt2400pci_config_antenna(rt2x00dev, &libconf->ant);
 516         if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
 517                 rt2400pci_config_duration(rt2x00dev, libconf);
 518 }
 519
 520 static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
 521                                 const int cw_min, const int cw_max)
 522 {
 523         u32 reg;
 524
 525         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 526         rt2x00_set_field32(&reg, CSR11_CWMIN, cw_min);
 527         rt2x00_set_field32(&reg, CSR11_CWMAX, cw_max);
 528         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 529 }
 530
 531 /*
 532  * Link tuning
 533  */
 534 static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
 535                                  struct link_qual *qual)
 536 {
 537         u32 reg;
 538         u8 bbp;
 539
 540         /*
 541          * Update FCS error count from register.
 542          */
 543         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 544         qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
 545
 546         /*
 547          * Update False CCA count from register.
 548          */
 549         rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
 550         qual->false_cca = bbp;
 551 }
 552
 553 static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
 554 {
 555         rt2400pci_bbp_write(rt2x00dev, 13, 0x08);
 556         rt2x00dev->link.vgc_level = 0x08;
 557 }
 558
 559 static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev)
 560 {
 561         u8 reg;
 562
 563         /*
 564          * The link tuner should not run longer then 60 seconds,
 565          * and should run once every 2 seconds.
 566          */
 567         if (rt2x00dev->link.count > 60 || !(rt2x00dev->link.count & 1))
 568                 return;
 569
 570         /*
 571          * Base r13 link tuning on the false cca count.
 572          */
 573         rt2400pci_bbp_read(rt2x00dev, 13, &reg);
 574
 575         if (rt2x00dev->link.qual.false_cca > 512 && reg < 0x20) {
 576                 rt2400pci_bbp_write(rt2x00dev, 13, ++reg);
 577                 rt2x00dev->link.vgc_level = reg;
 578         } else if (rt2x00dev->link.qual.false_cca < 100 && reg > 0x08) {
 579                 rt2400pci_bbp_write(rt2x00dev, 13, --reg);
 580                 rt2x00dev->link.vgc_level = reg;
 581         }
 582 }
 583
 584 /*
 585  * Initialization functions.
 586  */
 587 static void rt2400pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
 588                                    struct queue_entry *entry)
 589 {
 590         struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
 591         u32 word;
 592
 593         rt2x00_desc_read(priv_rx->desc, 2, &word);
 594         rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH,
 595                            entry->queue->data_size);
 596         rt2x00_desc_write(priv_rx->desc, 2, word);
 597
 598         rt2x00_desc_read(priv_rx->desc, 1, &word);
 599         rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, priv_rx->data_dma);
 600         rt2x00_desc_write(priv_rx->desc, 1, word);
 601
 602         rt2x00_desc_read(priv_rx->desc, 0, &word);
 603         rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
 604         rt2x00_desc_write(priv_rx->desc, 0, word);
 605 }
 606
 607 static void rt2400pci_init_txentry(struct rt2x00_dev *rt2x00dev,
 608                                    struct queue_entry *entry)
 609 {
 610         struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data;
 611         u32 word;
 612
 613         rt2x00_desc_read(priv_tx->desc, 1, &word);
 614         rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, priv_tx->data_dma);
 615         rt2x00_desc_write(priv_tx->desc, 1, word);
 616
 617         rt2x00_desc_read(priv_tx->desc, 2, &word);
 618         rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH,
 619                            entry->queue->data_size);
 620         rt2x00_desc_write(priv_tx->desc, 2, word);
 621
 622         rt2x00_desc_read(priv_tx->desc, 0, &word);
 623         rt2x00_set_field32(&word, TXD_W0_VALID, 0);
 624         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
 625         rt2x00_desc_write(priv_tx->desc, 0, word);
 626 }
 627
 628 static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
 629 {
 630         struct queue_entry_priv_pci_rx *priv_rx;
 631         struct queue_entry_priv_pci_tx *priv_tx;
 632         u32 reg;
 633
 634         /*
 635          * Initialize registers.
 636          */
 637         rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
 638         rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
 639         rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
 640         rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
 641         rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
 642         rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
 643
 644         priv_tx = rt2x00dev->tx[1].entries[0].priv_data;
 645         rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
 646         rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
 647                            priv_tx->desc_dma);
 648         rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
 649
 650         priv_tx = rt2x00dev->tx[0].entries[0].priv_data;
 651         rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
 652         rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
 653                            priv_tx->desc_dma);
 654         rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
 655
 656         priv_tx = rt2x00dev->bcn[1].entries[0].priv_data;
 657         rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
 658         rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
 659                            priv_tx->desc_dma);
 660         rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
 661
 662         priv_tx = rt2x00dev->bcn[0].entries[0].priv_data;
 663         rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
 664         rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
 665                            priv_tx->desc_dma);
 666         rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
 667
 668         rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
 669         rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
 670         rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
 671         rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
 672
 673         priv_rx = rt2x00dev->rx->entries[0].priv_data;
 674         rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
 675         rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER, priv_tx->desc_dma);
 676         rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
 677
 678         return 0;
 679 }
 680
 681 static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
 682 {
 683         u32 reg;
 684
 685         rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
 686         rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
 687         rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20);
 688         rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
 689
 690         rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
 691         rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
 692         rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
 693         rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
 694         rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
 695
 696         rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
 697         rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
 698                            (rt2x00dev->rx->data_size / 128));
 699         rt2x00pci_register_write(rt2x00dev, CSR9, reg);
 700
 701         rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
 702         rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, 70);
 703         rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, 30);
 704         rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
 705
 706         rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
 707
 708         rt2x00pci_register_read(rt2x00dev, ARCSR0, &reg);
 709         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
 710         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
 711         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
 712         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
 713         rt2x00pci_register_write(rt2x00dev, ARCSR0, reg);
 714
 715         rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
 716         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
 717         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
 718         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
 719         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
 720         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
 721         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
 722         rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
 723
 724         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
 725
 726         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
 727                 return -EBUSY;
 728
 729         rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
 730         rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
 731
 732         rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
 733         rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
 734         rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
 735
 736         rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
 737         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
 738         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
 739         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
 740         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
 741         rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
 742
 743         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 744         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
 745         rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
 746         rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
 747         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 748
 749         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 750         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
 751         rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
 752         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 753
 754         /*
 755          * We must clear the FCS and FIFO error count.
 756          * These registers are cleared on read,
 757          * so we may pass a useless variable to store the value.
 758          */
 759         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 760         rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
 761
 762         return 0;
 763 }
 764
 765 static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
 766 {
 767         unsigned int i;
 768         u16 eeprom;
 769         u8 reg_id;
 770         u8 value;
 771
 772         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 773                 rt2400pci_bbp_read(rt2x00dev, 0, &value);
 774                 if ((value != 0xff) && (value != 0x00))
 775                         goto continue_csr_init;
 776                 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
 777                 udelay(REGISTER_BUSY_DELAY);
 778         }
 779
 780         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
 781         return -EACCES;
 782
 783 continue_csr_init:
 784         rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
 785         rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
 786         rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
 787         rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
 788         rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
 789         rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
 790         rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
 791         rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
 792         rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
 793         rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
 794         rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
 795         rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
 796         rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
 797         rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
 798
 799         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
 800                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
 801
 802                 if (eeprom != 0xffff && eeprom != 0x0000) {
 803                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
 804                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
 805                         rt2400pci_bbp_write(rt2x00dev, reg_id, value);
 806                 }
 807         }
 808
 809         return 0;
 810 }
 811
 812 /*
 813  * Device state switch handlers.
 814  */
 815 static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
 816                                 enum dev_state state)
 817 {
 818         u32 reg;
 819
 820         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
 821         rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
 822                            state == STATE_RADIO_RX_OFF);
 823         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
 824 }
 825
 826 static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
 827                                  enum dev_state state)
 828 {
 829         int mask = (state == STATE_RADIO_IRQ_OFF);
 830         u32 reg;
 831
 832         /*
 833          * When interrupts are being enabled, the interrupt registers
 834          * should clear the register to assure a clean state.
 835          */
 836         if (state == STATE_RADIO_IRQ_ON) {
 837                 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
 838                 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
 839         }
 840
 841         /*
 842          * Only toggle the interrupts bits we are going to use.
 843          * Non-checked interrupt bits are disabled by default.
 844          */
 845         rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
 846         rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
 847         rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
 848         rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
 849         rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
 850         rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
 851         rt2x00pci_register_write(rt2x00dev, CSR8, reg);
 852 }
 853
 854 static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
 855 {
 856         /*
 857          * Initialize all registers.
 858          */
 859         if (rt2400pci_init_queues(rt2x00dev) ||
 860             rt2400pci_init_registers(rt2x00dev) ||
 861             rt2400pci_init_bbp(rt2x00dev)) {
 862                 ERROR(rt2x00dev, "Register initialization failed.\n");
 863                 return -EIO;
 864         }
 865
 866         /*
 867          * Enable interrupts.
 868          */
 869         rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
 870
 871         return 0;
 872 }
 873
 874 static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
 875 {
 876         u32 reg;
 877
 878         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
 879
 880         /*
 881          * Disable synchronisation.
 882          */
 883         rt2x00pci_register_write(rt2x00dev, CSR14, 0);
 884
 885         /*
 886          * Cancel RX and TX.
 887          */
 888         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
 889         rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
 890         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
 891
 892         /*
 893          * Disable interrupts.
 894          */
 895         rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
 896 }
 897
 898 static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
 899                                enum dev_state state)
 900 {
 901         u32 reg;
 902         unsigned int i;
 903         char put_to_sleep;
 904         char bbp_state;
 905         char rf_state;
 906
 907         put_to_sleep = (state != STATE_AWAKE);
 908
 909         rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
 910         rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
 911         rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
 912         rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
 913         rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
 914         rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
 915
 916         /*
 917          * Device is not guaranteed to be in the requested state yet.
 918          * We must wait until the register indicates that the
 919          * device has entered the correct state.
 920          */
 921         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 922                 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
 923                 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
 924                 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
 925                 if (bbp_state == state && rf_state == state)
 926                         return 0;
 927                 msleep(10);
 928         }
 929
 930         NOTICE(rt2x00dev, "Device failed to enter state %d, "
 931                "current device state: bbp %d and rf %d.\n",
 932                state, bbp_state, rf_state);
 933
 934         return -EBUSY;
 935 }
 936
 937 static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
 938                                       enum dev_state state)
 939 {
 940         int retval = 0;
 941
 942         switch (state) {
 943         case STATE_RADIO_ON:
 944                 retval = rt2400pci_enable_radio(rt2x00dev);
 945                 break;
 946         case STATE_RADIO_OFF:
 947                 rt2400pci_disable_radio(rt2x00dev);
 948                 break;
 949         case STATE_RADIO_RX_ON:
 950         case STATE_RADIO_RX_ON_LINK:
 951                 rt2400pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON);
 952                 break;
 953         case STATE_RADIO_RX_OFF:
 954         case STATE_RADIO_RX_OFF_LINK:
 955                 rt2400pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF);
 956                 break;
 957         case STATE_DEEP_SLEEP:
 958         case STATE_SLEEP:
 959         case STATE_STANDBY:
 960         case STATE_AWAKE:
 961                 retval = rt2400pci_set_state(rt2x00dev, state);
 962                 break;
 963         default:
 964                 retval = -ENOTSUPP;
 965                 break;
 966         }
 967
 968         return retval;
 969 }
 970
 971 /*
 972  * TX descriptor initialization
 973  */
 974 static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
 975                                     struct sk_buff *skb,
 976                                     struct txentry_desc *txdesc,
 977                                     struct ieee80211_tx_control *control)
 978 {
 979         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
 980         __le32 *txd = skbdesc->desc;
 981         u32 word;
 982
 983         /*
 984          * Start writing the descriptor words.
 985          */
 986         rt2x00_desc_read(txd, 2, &word);
 987         rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, skbdesc->data_len);
 988         rt2x00_desc_write(txd, 2, word);
 989
 990         rt2x00_desc_read(txd, 3, &word);
 991         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
 992         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
 993         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
 994         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
 995         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
 996         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
 997         rt2x00_desc_write(txd, 3, word);
 998
 999         rt2x00_desc_read(txd, 4, &word);
1000         rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, txdesc->length_low);
1001         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
1002         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
1003         rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, txdesc->length_high);
1004         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
1005         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
1006         rt2x00_desc_write(txd, 4, word);
1007
1008         rt2x00_desc_read(txd, 0, &word);
1009         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1010         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1011         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1012                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1013         rt2x00_set_field32(&word, TXD_W0_ACK,
1014                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1015         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1016                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1017         rt2x00_set_field32(&word, TXD_W0_RTS,
1018                            test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1019         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1020         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1021                            !!(control->flags &
1022                               IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1023         rt2x00_desc_write(txd, 0, word);
1024 }
1025
1026 /*
1027  * TX data initialization
1028  */
1029 static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1030                                     const unsigned int queue)
1031 {
1032         u32 reg;
1033
1034         if (queue == RT2X00_BCN_QUEUE_BEACON) {
1035                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1036                 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1037                         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1038                         rt2x00_set_field32(&reg, CSR14_TBCN, 1);
1039                         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1040                         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1041                 }
1042                 return;
1043         }
1044
1045         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1046         rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO,
1047                            (queue == IEEE80211_TX_QUEUE_DATA0));
1048         rt2x00_set_field32(&reg, TXCSR0_KICK_TX,
1049                            (queue == IEEE80211_TX_QUEUE_DATA1));
1050         rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM,
1051                            (queue == RT2X00_BCN_QUEUE_ATIM));
1052         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1053 }
1054
1055 /*
1056  * RX control handlers
1057  */
1058 static void rt2400pci_fill_rxdone(struct queue_entry *entry,
1059                                   struct rxdone_entry_desc *rxdesc)
1060 {
1061         struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
1062         u32 word0;
1063         u32 word2;
1064
1065         rt2x00_desc_read(priv_rx->desc, 0, &word0);
1066         rt2x00_desc_read(priv_rx->desc, 2, &word2);
1067
1068         rxdesc->flags = 0;
1069         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1070                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1071         if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1072                 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1073
1074         /*
1075          * Obtain the status about this packet.
1076          */
1077         rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1078         rxdesc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1079             entry->queue->rt2x00dev->rssi_offset;
1080         rxdesc->ofdm = 0;
1081         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1082         rxdesc->my_bss = !!rt2x00_get_field32(word0, RXD_W0_MY_BSS);
1083 }
1084
1085 /*
1086  * Interrupt functions.
1087  */
1088 static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
1089                              const enum ieee80211_tx_queue queue_idx)
1090 {
1091         struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1092         struct queue_entry_priv_pci_tx *priv_tx;
1093         struct queue_entry *entry;
1094         struct txdone_entry_desc txdesc;
1095         u32 word;
1096
1097         while (!rt2x00queue_empty(queue)) {
1098                 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1099                 priv_tx = entry->priv_data;
1100                 rt2x00_desc_read(priv_tx->desc, 0, &word);
1101
1102                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1103                     !rt2x00_get_field32(word, TXD_W0_VALID))
1104                         break;
1105
1106                 /*
1107                  * Obtain the status about this packet.
1108                  */
1109                 txdesc.status = rt2x00_get_field32(word, TXD_W0_RESULT);
1110                 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1111
1112                 rt2x00pci_txdone(rt2x00dev, entry, &txdesc);
1113         }
1114 }
1115
1116 static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1117 {
1118         struct rt2x00_dev *rt2x00dev = dev_instance;
1119         u32 reg;
1120
1121         /*
1122          * Get the interrupt sources & saved to local variable.
1123          * Write register value back to clear pending interrupts.
1124          */
1125         rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1126         rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1127
1128         if (!reg)
1129                 return IRQ_NONE;
1130
1131         if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1132                 return IRQ_HANDLED;
1133
1134         /*
1135          * Handle interrupts, walk through all bits
1136          * and run the tasks, the bits are checked in order of
1137          * priority.
1138          */
1139
1140         /*
1141          * 1 - Beacon timer expired interrupt.
1142          */
1143         if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1144                 rt2x00lib_beacondone(rt2x00dev);
1145
1146         /*
1147          * 2 - Rx ring done interrupt.
1148          */
1149         if (rt2x00_get_field32(reg, CSR7_RXDONE))
1150                 rt2x00pci_rxdone(rt2x00dev);
1151
1152         /*
1153          * 3 - Atim ring transmit done interrupt.
1154          */
1155         if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1156                 rt2400pci_txdone(rt2x00dev, RT2X00_BCN_QUEUE_ATIM);
1157
1158         /*
1159          * 4 - Priority ring transmit done interrupt.
1160          */
1161         if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1162                 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
1163
1164         /*
1165          * 5 - Tx ring transmit done interrupt.
1166          */
1167         if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1168                 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
1169
1170         return IRQ_HANDLED;
1171 }
1172
1173 /*
1174  * Device probe functions.
1175  */
1176 static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1177 {
1178         struct eeprom_93cx6 eeprom;
1179         u32 reg;
1180         u16 word;
1181         u8 *mac;
1182
1183         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1184
1185         eeprom.data = rt2x00dev;
1186         eeprom.register_read = rt2400pci_eepromregister_read;
1187         eeprom.register_write = rt2400pci_eepromregister_write;
1188         eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1189             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1190         eeprom.reg_data_in = 0;
1191         eeprom.reg_data_out = 0;
1192         eeprom.reg_data_clock = 0;
1193         eeprom.reg_chip_select = 0;
1194
1195         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1196                                EEPROM_SIZE / sizeof(u16));
1197
1198         /*
1199          * Start validation of the data that has been read.
1200          */
1201         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1202         if (!is_valid_ether_addr(mac)) {
1203                 DECLARE_MAC_BUF(macbuf);
1204
1205                 random_ether_addr(mac);
1206                 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
1207         }
1208
1209         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1210         if (word == 0xffff) {
1211                 ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
1212                 return -EINVAL;
1213         }
1214
1215         return 0;
1216 }
1217
1218 static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1219 {
1220         u32 reg;
1221         u16 value;
1222         u16 eeprom;
1223
1224         /*
1225          * Read EEPROM word for configuration.
1226          */
1227         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1228
1229         /*
1230          * Identify RF chipset.
1231          */
1232         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1233         rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1234         rt2x00_set_chip(rt2x00dev, RT2460, value, reg);
1235
1236         if (!rt2x00_rf(&rt2x00dev->chip, RF2420) &&
1237             !rt2x00_rf(&rt2x00dev->chip, RF2421)) {
1238                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1239                 return -ENODEV;
1240         }
1241
1242         /*
1243          * Identify default antenna configuration.
1244          */
1245         rt2x00dev->default_ant.tx =
1246             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1247         rt2x00dev->default_ant.rx =
1248             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1249
1250         /*
1251          * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
1252          * I am not 100% sure about this, but the legacy drivers do not
1253          * indicate antenna swapping in software is required when
1254          * diversity is enabled.
1255          */
1256         if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
1257                 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
1258         if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
1259                 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
1260
1261         /*
1262          * Store led mode, for correct led behaviour.
1263          */
1264 #ifdef CONFIG_RT2400PCI_LEDS
1265         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1266
1267         switch (value) {
1268         case LED_MODE_ASUS:
1269         case LED_MODE_ALPHA:
1270         case LED_MODE_DEFAULT:
1271                 rt2x00dev->led_flags = LED_SUPPORT_RADIO;
1272                 break;
1273         case LED_MODE_TXRX_ACTIVITY:
1274                 rt2x00dev->led_flags =
1275                     LED_SUPPORT_RADIO | LED_SUPPORT_ACTIVITY;
1276                 break;
1277         case LED_MODE_SIGNAL_STRENGTH:
1278                 rt2x00dev->led_flags = LED_SUPPORT_RADIO;
1279                 break;
1280         }
1281 #endif /* CONFIG_RT2400PCI_LEDS */
1282
1283         /*
1284          * Detect if this device has an hardware controlled radio.
1285          */
1286 #ifdef CONFIG_RT2400PCI_RFKILL
1287         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1288                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1289 #endif /* CONFIG_RT2400PCI_RFKILL */
1290
1291         /*
1292          * Check if the BBP tuning should be enabled.
1293          */
1294         if (!rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1295                 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1296
1297         return 0;
1298 }
1299
1300 /*
1301  * RF value list for RF2420 & RF2421
1302  * Supports: 2.4 GHz
1303  */
1304 static const struct rf_channel rf_vals_bg[] = {
1305         { 1,  0x00022058, 0x000c1fda, 0x00000101, 0 },
1306         { 2,  0x00022058, 0x000c1fee, 0x00000101, 0 },
1307         { 3,  0x00022058, 0x000c2002, 0x00000101, 0 },
1308         { 4,  0x00022058, 0x000c2016, 0x00000101, 0 },
1309         { 5,  0x00022058, 0x000c202a, 0x00000101, 0 },
1310         { 6,  0x00022058, 0x000c203e, 0x00000101, 0 },
1311         { 7,  0x00022058, 0x000c2052, 0x00000101, 0 },
1312         { 8,  0x00022058, 0x000c2066, 0x00000101, 0 },
1313         { 9,  0x00022058, 0x000c207a, 0x00000101, 0 },
1314         { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1315         { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1316         { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1317         { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1318         { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1319 };
1320
1321 static void rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1322 {
1323         struct hw_mode_spec *spec = &rt2x00dev->spec;
1324         u8 *txpower;
1325         unsigned int i;
1326
1327         /*
1328          * Initialize all hw fields.
1329          */
1330         rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
1331         rt2x00dev->hw->extra_tx_headroom = 0;
1332         rt2x00dev->hw->max_signal = MAX_SIGNAL;
1333         rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1334         rt2x00dev->hw->queues = 2;
1335
1336         SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
1337         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1338                                 rt2x00_eeprom_addr(rt2x00dev,
1339                                                    EEPROM_MAC_ADDR_0));
1340
1341         /*
1342          * Convert tx_power array in eeprom.
1343          */
1344         txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1345         for (i = 0; i < 14; i++)
1346                 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1347
1348         /*
1349          * Initialize hw_mode information.
1350          */
1351         spec->supported_bands = SUPPORT_BAND_2GHZ;
1352         spec->supported_rates = SUPPORT_RATE_CCK;
1353         spec->tx_power_a = NULL;
1354         spec->tx_power_bg = txpower;
1355         spec->tx_power_default = DEFAULT_TXPOWER;
1356
1357         spec->num_channels = ARRAY_SIZE(rf_vals_bg);
1358         spec->channels = rf_vals_bg;
1359 }
1360
1361 static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1362 {
1363         int retval;
1364
1365         /*
1366          * Allocate eeprom data.
1367          */
1368         retval = rt2400pci_validate_eeprom(rt2x00dev);
1369         if (retval)
1370                 return retval;
1371
1372         retval = rt2400pci_init_eeprom(rt2x00dev);
1373         if (retval)
1374                 return retval;
1375
1376         /*
1377          * Initialize hw specifications.
1378          */
1379         rt2400pci_probe_hw_mode(rt2x00dev);
1380
1381         /*
1382          * This device requires the atim queue
1383          */
1384         __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
1385
1386         /*
1387          * Set the rssi offset.
1388          */
1389         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1390
1391         return 0;
1392 }
1393
1394 /*
1395  * IEEE80211 stack callback functions.
1396  */
1397 static void rt2400pci_configure_filter(struct ieee80211_hw *hw,
1398                                        unsigned int changed_flags,
1399                                        unsigned int *total_flags,
1400                                        int mc_count,
1401                                        struct dev_addr_list *mc_list)
1402 {
1403         struct rt2x00_dev *rt2x00dev = hw->priv;
1404         u32 reg;
1405
1406         /*
1407          * Mask off any flags we are going to ignore from
1408          * the total_flags field.
1409          */
1410         *total_flags &=
1411             FIF_ALLMULTI |
1412             FIF_FCSFAIL |
1413             FIF_PLCPFAIL |
1414             FIF_CONTROL |
1415             FIF_OTHER_BSS |
1416             FIF_PROMISC_IN_BSS;
1417
1418         /*
1419          * Apply some rules to the filters:
1420          * - Some filters imply different filters to be set.
1421          * - Some things we can't filter out at all.
1422          */
1423         *total_flags |= FIF_ALLMULTI;
1424         if (*total_flags & FIF_OTHER_BSS ||
1425             *total_flags & FIF_PROMISC_IN_BSS)
1426                 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
1427
1428         /*
1429          * Check if there is any work left for us.
1430          */
1431         if (rt2x00dev->packet_filter == *total_flags)
1432                 return;
1433         rt2x00dev->packet_filter = *total_flags;
1434
1435         /*
1436          * Start configuration steps.
1437          * Note that the version error will always be dropped
1438          * since there is no filter for it at this time.
1439          */
1440         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1441         rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
1442                            !(*total_flags & FIF_FCSFAIL));
1443         rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
1444                            !(*total_flags & FIF_PLCPFAIL));
1445         rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
1446                            !(*total_flags & FIF_CONTROL));
1447         rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
1448                            !(*total_flags & FIF_PROMISC_IN_BSS));
1449         rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
1450                            !(*total_flags & FIF_PROMISC_IN_BSS));
1451         rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
1452         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1453 }
1454
1455 static int rt2400pci_set_retry_limit(struct ieee80211_hw *hw,
1456                                      u32 short_retry, u32 long_retry)
1457 {
1458         struct rt2x00_dev *rt2x00dev = hw->priv;
1459         u32 reg;
1460
1461         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
1462         rt2x00_set_field32(&reg, CSR11_LONG_RETRY, long_retry);
1463         rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, short_retry);
1464         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1465
1466         return 0;
1467 }
1468
1469 static int rt2400pci_conf_tx(struct ieee80211_hw *hw,
1470                              int queue,
1471                              const struct ieee80211_tx_queue_params *params)
1472 {
1473         struct rt2x00_dev *rt2x00dev = hw->priv;
1474
1475         /*
1476          * We don't support variating cw_min and cw_max variables
1477          * per queue. So by default we only configure the TX queue,
1478          * and ignore all other configurations.
1479          */
1480         if (queue != IEEE80211_TX_QUEUE_DATA0)
1481                 return -EINVAL;
1482
1483         if (rt2x00mac_conf_tx(hw, queue, params))
1484                 return -EINVAL;
1485
1486         /*
1487          * Write configuration to register.
1488          */
1489         rt2400pci_config_cw(rt2x00dev,
1490                             rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max);
1491
1492         return 0;
1493 }
1494
1495 static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
1496 {
1497         struct rt2x00_dev *rt2x00dev = hw->priv;
1498         u64 tsf;
1499         u32 reg;
1500
1501         rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1502         tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1503         rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1504         tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1505
1506         return tsf;
1507 }
1508
1509 static int rt2400pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
1510                                    struct ieee80211_tx_control *control)
1511 {
1512         struct rt2x00_dev *rt2x00dev = hw->priv;
1513         struct rt2x00_intf *intf = vif_to_intf(control->vif);
1514         struct queue_entry_priv_pci_tx *priv_tx;
1515         struct skb_frame_desc *skbdesc;
1516         u32 reg;
1517
1518         if (unlikely(!intf->beacon))
1519                 return -ENOBUFS;
1520         priv_tx = intf->beacon->priv_data;
1521
1522         /*
1523          * Fill in skb descriptor
1524          */
1525         skbdesc = get_skb_frame_desc(skb);
1526         memset(skbdesc, 0, sizeof(*skbdesc));
1527         skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED;
1528         skbdesc->data = skb->data;
1529         skbdesc->data_len = skb->len;
1530         skbdesc->desc = priv_tx->desc;
1531         skbdesc->desc_len = intf->beacon->queue->desc_size;
1532         skbdesc->entry = intf->beacon;
1533
1534         /*
1535          * Disable beaconing while we are reloading the beacon data,
1536          * otherwise we might be sending out invalid data.
1537          */
1538         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1539         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
1540         rt2x00_set_field32(&reg, CSR14_TBCN, 0);
1541         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1542         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1543
1544         /*
1545          * mac80211 doesn't provide the control->queue variable
1546          * for beacons. Set our own queue identification so
1547          * it can be used during descriptor initialization.
1548          */
1549         control->queue = RT2X00_BCN_QUEUE_BEACON;
1550         rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
1551
1552         /*
1553          * Enable beacon generation.
1554          * Write entire beacon with descriptor to register,
1555          * and kick the beacon generator.
1556          */
1557         memcpy(priv_tx->data, skb->data, skb->len);
1558         rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, control->queue);
1559
1560         return 0;
1561 }
1562
1563 static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1564 {
1565         struct rt2x00_dev *rt2x00dev = hw->priv;
1566         u32 reg;
1567
1568         rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1569         return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1570 }
1571
1572 static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1573         .tx                     = rt2x00mac_tx,
1574         .start                  = rt2x00mac_start,
1575         .stop                   = rt2x00mac_stop,
1576         .add_interface          = rt2x00mac_add_interface,
1577         .remove_interface       = rt2x00mac_remove_interface,
1578         .config                 = rt2x00mac_config,
1579         .config_interface       = rt2x00mac_config_interface,
1580         .configure_filter       = rt2400pci_configure_filter,
1581         .get_stats              = rt2x00mac_get_stats,
1582         .set_retry_limit        = rt2400pci_set_retry_limit,
1583         .bss_info_changed       = rt2x00mac_bss_info_changed,
1584         .conf_tx                = rt2400pci_conf_tx,
1585         .get_tx_stats           = rt2x00mac_get_tx_stats,
1586         .get_tsf                = rt2400pci_get_tsf,
1587         .beacon_update          = rt2400pci_beacon_update,
1588         .tx_last_beacon         = rt2400pci_tx_last_beacon,
1589 };
1590
1591 static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1592         .irq_handler            = rt2400pci_interrupt,
1593         .probe_hw               = rt2400pci_probe_hw,
1594         .initialize             = rt2x00pci_initialize,
1595         .uninitialize           = rt2x00pci_uninitialize,
1596         .init_rxentry           = rt2400pci_init_rxentry,
1597         .init_txentry           = rt2400pci_init_txentry,
1598         .set_device_state       = rt2400pci_set_device_state,
1599         .rfkill_poll            = rt2400pci_rfkill_poll,
1600         .link_stats             = rt2400pci_link_stats,
1601         .reset_tuner            = rt2400pci_reset_tuner,
1602         .link_tuner             = rt2400pci_link_tuner,
1603         .led_brightness         = rt2400pci_led_brightness,
1604         .write_tx_desc          = rt2400pci_write_tx_desc,
1605         .write_tx_data          = rt2x00pci_write_tx_data,
1606         .kick_tx_queue          = rt2400pci_kick_tx_queue,
1607         .fill_rxdone            = rt2400pci_fill_rxdone,
1608         .config_intf            = rt2400pci_config_intf,
1609         .config_preamble        = rt2400pci_config_preamble,
1610         .config                 = rt2400pci_config,
1611 };
1612
1613 static const struct data_queue_desc rt2400pci_queue_rx = {
1614         .entry_num              = RX_ENTRIES,
1615         .data_size              = DATA_FRAME_SIZE,
1616         .desc_size              = RXD_DESC_SIZE,
1617         .priv_size              = sizeof(struct queue_entry_priv_pci_rx),
1618 };
1619
1620 static const struct data_queue_desc rt2400pci_queue_tx = {
1621         .entry_num              = TX_ENTRIES,
1622         .data_size              = DATA_FRAME_SIZE,
1623         .desc_size              = TXD_DESC_SIZE,
1624         .priv_size              = sizeof(struct queue_entry_priv_pci_tx),
1625 };
1626
1627 static const struct data_queue_desc rt2400pci_queue_bcn = {
1628         .entry_num              = BEACON_ENTRIES,
1629         .data_size              = MGMT_FRAME_SIZE,
1630         .desc_size              = TXD_DESC_SIZE,
1631         .priv_size              = sizeof(struct queue_entry_priv_pci_tx),
1632 };
1633
1634 static const struct data_queue_desc rt2400pci_queue_atim = {
1635         .entry_num              = ATIM_ENTRIES,
1636         .data_size              = DATA_FRAME_SIZE,
1637         .desc_size              = TXD_DESC_SIZE,
1638         .priv_size              = sizeof(struct queue_entry_priv_pci_tx),
1639 };
1640
1641 static const struct rt2x00_ops rt2400pci_ops = {
1642         .name           = KBUILD_MODNAME,
1643         .max_sta_intf   = 1,
1644         .max_ap_intf    = 1,
1645         .eeprom_size    = EEPROM_SIZE,
1646         .rf_size        = RF_SIZE,
1647         .rx             = &rt2400pci_queue_rx,
1648         .tx             = &rt2400pci_queue_tx,
1649         .bcn            = &rt2400pci_queue_bcn,
1650         .atim           = &rt2400pci_queue_atim,
1651         .lib            = &rt2400pci_rt2x00_ops,
1652         .hw             = &rt2400pci_mac80211_ops,
1653 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1654         .debugfs        = &rt2400pci_rt2x00debug,
1655 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1656 };
1657
1658 /*
1659  * RT2400pci module information.
1660  */
1661 static struct pci_device_id rt2400pci_device_table[] = {
1662         { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) },
1663         { 0, }
1664 };
1665
1666 MODULE_AUTHOR(DRV_PROJECT);
1667 MODULE_VERSION(DRV_VERSION);
1668 MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1669 MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1670 MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1671 MODULE_LICENSE("GPL");
1672
1673 static struct pci_driver rt2400pci_driver = {
1674         .name           = KBUILD_MODNAME,
1675         .id_table       = rt2400pci_device_table,
1676         .probe          = rt2x00pci_probe,
1677         .remove         = __devexit_p(rt2x00pci_remove),
1678         .suspend        = rt2x00pci_suspend,
1679         .resume         = rt2x00pci_resume,
1680 };
1681
1682 static int __init rt2400pci_init(void)
1683 {
1684         return pci_register_driver(&rt2400pci_driver);
1685 }
1686
1687 static void __exit rt2400pci_exit(void)
1688 {
1689         pci_unregister_driver(&rt2400pci_driver);
1690 }
1691
1692 module_init(rt2400pci_init);
1693 module_exit(rt2400pci_exit);