2 * drivers/net/wireless/mwl8k.c
3 * Driver for Marvell TOPDOG 802.11 Wireless cards
5 * Copyright (C) 2008-2009 Marvell Semiconductor Inc.
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/sched.h>
16 #include <linux/spinlock.h>
17 #include <linux/list.h>
18 #include <linux/pci.h>
19 #include <linux/delay.h>
20 #include <linux/completion.h>
21 #include <linux/etherdevice.h>
22 #include <net/mac80211.h>
23 #include <linux/moduleparam.h>
24 #include <linux/firmware.h>
25 #include <linux/workqueue.h>
27 #define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
28 #define MWL8K_NAME KBUILD_MODNAME
29 #define MWL8K_VERSION "0.10"
31 /* Register definitions */
32 #define MWL8K_HIU_GEN_PTR 0x00000c10
33 #define MWL8K_MODE_STA 0x0000005a
34 #define MWL8K_MODE_AP 0x000000a5
35 #define MWL8K_HIU_INT_CODE 0x00000c14
36 #define MWL8K_FWSTA_READY 0xf0f1f2f4
37 #define MWL8K_FWAP_READY 0xf1f2f4a5
38 #define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
39 #define MWL8K_HIU_SCRATCH 0x00000c40
41 /* Host->device communications */
42 #define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
43 #define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
44 #define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
45 #define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
46 #define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
47 #define MWL8K_H2A_INT_DUMMY (1 << 20)
48 #define MWL8K_H2A_INT_RESET (1 << 15)
49 #define MWL8K_H2A_INT_DOORBELL (1 << 1)
50 #define MWL8K_H2A_INT_PPA_READY (1 << 0)
52 /* Device->host communications */
53 #define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
54 #define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
55 #define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
56 #define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
57 #define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
58 #define MWL8K_A2H_INT_DUMMY (1 << 20)
59 #define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
60 #define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
61 #define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
62 #define MWL8K_A2H_INT_RADIO_ON (1 << 6)
63 #define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
64 #define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
65 #define MWL8K_A2H_INT_OPC_DONE (1 << 2)
66 #define MWL8K_A2H_INT_RX_READY (1 << 1)
67 #define MWL8K_A2H_INT_TX_DONE (1 << 0)
69 #define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
70 MWL8K_A2H_INT_CHNL_SWITCHED | \
71 MWL8K_A2H_INT_QUEUE_EMPTY | \
72 MWL8K_A2H_INT_RADAR_DETECT | \
73 MWL8K_A2H_INT_RADIO_ON | \
74 MWL8K_A2H_INT_RADIO_OFF | \
75 MWL8K_A2H_INT_MAC_EVENT | \
76 MWL8K_A2H_INT_OPC_DONE | \
77 MWL8K_A2H_INT_RX_READY | \
78 MWL8K_A2H_INT_TX_DONE)
80 #define MWL8K_RX_QUEUES 1
81 #define MWL8K_TX_QUEUES 4
85 void (*rxd_init)(void *rxd, dma_addr_t next_dma_addr);
86 void (*rxd_refill)(void *rxd, dma_addr_t addr, int len);
87 int (*rxd_process)(void *rxd, struct ieee80211_rx_status *status,
91 struct mwl8k_device_info {
95 struct rxd_ops *rxd_ops;
99 struct mwl8k_rx_queue {
102 /* hw receives here */
105 /* refill descs here */
112 DECLARE_PCI_UNMAP_ADDR(dma)
116 struct mwl8k_tx_queue {
117 /* hw transmits here */
120 /* sw appends here */
123 struct ieee80211_tx_queue_stats stats;
124 struct mwl8k_tx_desc *txd;
126 struct sk_buff **skb;
132 struct ieee80211_hw *hw;
134 struct pci_dev *pdev;
136 struct mwl8k_device_info *device_info;
138 struct rxd_ops *rxd_ops;
140 /* firmware files and meta data */
141 struct firmware *fw_helper;
142 struct firmware *fw_ucode;
144 /* firmware access */
145 struct mutex fw_mutex;
146 struct task_struct *fw_mutex_owner;
148 struct completion *hostcmd_wait;
150 /* lock held over TX and TX reap */
153 /* TX quiesce completion, protected by fw_mutex and tx_lock */
154 struct completion *tx_wait;
156 struct ieee80211_vif *vif;
158 struct ieee80211_channel *current_channel;
160 /* power management status cookie from firmware */
162 dma_addr_t cookie_dma;
169 * Running count of TX packets in flight, to avoid
170 * iterating over the transmit rings each time.
174 struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
175 struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES];
178 struct ieee80211_supported_band band;
179 struct ieee80211_channel channels[14];
180 struct ieee80211_rate rates[14];
183 bool radio_short_preamble;
184 bool sniffer_enabled;
187 /* XXX need to convert this to handle multiple interfaces */
189 u8 capture_bssid[ETH_ALEN];
190 struct sk_buff *beacon_skb;
193 * This FJ worker has to be global as it is scheduled from the
194 * RX handler. At this point we don't know which interface it
195 * belongs to until the list of bssids waiting to complete join
198 struct work_struct finalize_join_worker;
200 /* Tasklet to reclaim TX descriptors and buffers after tx */
201 struct tasklet_struct tx_reclaim_task;
204 /* Per interface specific private data */
206 /* backpointer to parent config block */
207 struct mwl8k_priv *priv;
209 /* BSS config of AP or IBSS from mac80211*/
210 struct ieee80211_bss_conf bss_info;
212 /* BSSID of AP or IBSS */
214 u8 mac_addr[ETH_ALEN];
216 /* Index into station database. Returned by UPDATE_STADB. */
219 /* Non AMPDU sequence number assigned by driver */
223 #define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
225 static const struct ieee80211_channel mwl8k_channels[] = {
226 { .center_freq = 2412, .hw_value = 1, },
227 { .center_freq = 2417, .hw_value = 2, },
228 { .center_freq = 2422, .hw_value = 3, },
229 { .center_freq = 2427, .hw_value = 4, },
230 { .center_freq = 2432, .hw_value = 5, },
231 { .center_freq = 2437, .hw_value = 6, },
232 { .center_freq = 2442, .hw_value = 7, },
233 { .center_freq = 2447, .hw_value = 8, },
234 { .center_freq = 2452, .hw_value = 9, },
235 { .center_freq = 2457, .hw_value = 10, },
236 { .center_freq = 2462, .hw_value = 11, },
237 { .center_freq = 2467, .hw_value = 12, },
238 { .center_freq = 2472, .hw_value = 13, },
239 { .center_freq = 2484, .hw_value = 14, },
242 static const struct ieee80211_rate mwl8k_rates[] = {
243 { .bitrate = 10, .hw_value = 2, },
244 { .bitrate = 20, .hw_value = 4, },
245 { .bitrate = 55, .hw_value = 11, },
246 { .bitrate = 110, .hw_value = 22, },
247 { .bitrate = 220, .hw_value = 44, },
248 { .bitrate = 60, .hw_value = 12, },
249 { .bitrate = 90, .hw_value = 18, },
250 { .bitrate = 120, .hw_value = 24, },
251 { .bitrate = 180, .hw_value = 36, },
252 { .bitrate = 240, .hw_value = 48, },
253 { .bitrate = 360, .hw_value = 72, },
254 { .bitrate = 480, .hw_value = 96, },
255 { .bitrate = 540, .hw_value = 108, },
256 { .bitrate = 720, .hw_value = 144, },
259 static const u8 mwl8k_rateids[12] = {
260 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108,
263 /* Set or get info from Firmware */
264 #define MWL8K_CMD_SET 0x0001
265 #define MWL8K_CMD_GET 0x0000
267 /* Firmware command codes */
268 #define MWL8K_CMD_CODE_DNLD 0x0001
269 #define MWL8K_CMD_GET_HW_SPEC 0x0003
270 #define MWL8K_CMD_SET_HW_SPEC 0x0004
271 #define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
272 #define MWL8K_CMD_GET_STAT 0x0014
273 #define MWL8K_CMD_RADIO_CONTROL 0x001c
274 #define MWL8K_CMD_RF_TX_POWER 0x001e
275 #define MWL8K_CMD_RF_ANTENNA 0x0020
276 #define MWL8K_CMD_SET_PRE_SCAN 0x0107
277 #define MWL8K_CMD_SET_POST_SCAN 0x0108
278 #define MWL8K_CMD_SET_RF_CHANNEL 0x010a
279 #define MWL8K_CMD_SET_AID 0x010d
280 #define MWL8K_CMD_SET_RATE 0x0110
281 #define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
282 #define MWL8K_CMD_RTS_THRESHOLD 0x0113
283 #define MWL8K_CMD_SET_SLOT 0x0114
284 #define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
285 #define MWL8K_CMD_SET_WMM_MODE 0x0123
286 #define MWL8K_CMD_MIMO_CONFIG 0x0125
287 #define MWL8K_CMD_USE_FIXED_RATE 0x0126
288 #define MWL8K_CMD_ENABLE_SNIFFER 0x0150
289 #define MWL8K_CMD_SET_MAC_ADDR 0x0202
290 #define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
291 #define MWL8K_CMD_UPDATE_STADB 0x1123
293 static const char *mwl8k_cmd_name(u16 cmd, char *buf, int bufsize)
295 #define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
296 snprintf(buf, bufsize, "%s", #x);\
299 switch (cmd & ~0x8000) {
300 MWL8K_CMDNAME(CODE_DNLD);
301 MWL8K_CMDNAME(GET_HW_SPEC);
302 MWL8K_CMDNAME(SET_HW_SPEC);
303 MWL8K_CMDNAME(MAC_MULTICAST_ADR);
304 MWL8K_CMDNAME(GET_STAT);
305 MWL8K_CMDNAME(RADIO_CONTROL);
306 MWL8K_CMDNAME(RF_TX_POWER);
307 MWL8K_CMDNAME(RF_ANTENNA);
308 MWL8K_CMDNAME(SET_PRE_SCAN);
309 MWL8K_CMDNAME(SET_POST_SCAN);
310 MWL8K_CMDNAME(SET_RF_CHANNEL);
311 MWL8K_CMDNAME(SET_AID);
312 MWL8K_CMDNAME(SET_RATE);
313 MWL8K_CMDNAME(SET_FINALIZE_JOIN);
314 MWL8K_CMDNAME(RTS_THRESHOLD);
315 MWL8K_CMDNAME(SET_SLOT);
316 MWL8K_CMDNAME(SET_EDCA_PARAMS);
317 MWL8K_CMDNAME(SET_WMM_MODE);
318 MWL8K_CMDNAME(MIMO_CONFIG);
319 MWL8K_CMDNAME(USE_FIXED_RATE);
320 MWL8K_CMDNAME(ENABLE_SNIFFER);
321 MWL8K_CMDNAME(SET_MAC_ADDR);
322 MWL8K_CMDNAME(SET_RATEADAPT_MODE);
323 MWL8K_CMDNAME(UPDATE_STADB);
325 snprintf(buf, bufsize, "0x%x", cmd);
332 /* Hardware and firmware reset */
333 static void mwl8k_hw_reset(struct mwl8k_priv *priv)
335 iowrite32(MWL8K_H2A_INT_RESET,
336 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
337 iowrite32(MWL8K_H2A_INT_RESET,
338 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
342 /* Release fw image */
343 static void mwl8k_release_fw(struct firmware **fw)
347 release_firmware(*fw);
351 static void mwl8k_release_firmware(struct mwl8k_priv *priv)
353 mwl8k_release_fw(&priv->fw_ucode);
354 mwl8k_release_fw(&priv->fw_helper);
357 /* Request fw image */
358 static int mwl8k_request_fw(struct mwl8k_priv *priv,
359 const char *fname, struct firmware **fw)
361 /* release current image */
363 mwl8k_release_fw(fw);
365 return request_firmware((const struct firmware **)fw,
366 fname, &priv->pdev->dev);
369 static int mwl8k_request_firmware(struct mwl8k_priv *priv)
371 struct mwl8k_device_info *di = priv->device_info;
374 if (di->helper_image != NULL) {
375 rc = mwl8k_request_fw(priv, di->helper_image, &priv->fw_helper);
377 printk(KERN_ERR "%s: Error requesting helper "
378 "firmware file %s\n", pci_name(priv->pdev),
384 rc = mwl8k_request_fw(priv, di->fw_image, &priv->fw_ucode);
386 printk(KERN_ERR "%s: Error requesting firmware file %s\n",
387 pci_name(priv->pdev), di->fw_image);
388 mwl8k_release_fw(&priv->fw_helper);
395 MODULE_FIRMWARE("mwl8k/helper_8687.fw");
396 MODULE_FIRMWARE("mwl8k/fmimage_8687.fw");
398 struct mwl8k_cmd_pkt {
404 } __attribute__((packed));
410 mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
412 void __iomem *regs = priv->regs;
416 dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
417 if (pci_dma_mapping_error(priv->pdev, dma_addr))
420 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
421 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
422 iowrite32(MWL8K_H2A_INT_DOORBELL,
423 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
424 iowrite32(MWL8K_H2A_INT_DUMMY,
425 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
431 int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
432 if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
433 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
441 pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
443 return loops ? 0 : -ETIMEDOUT;
446 static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
447 const u8 *data, size_t length)
449 struct mwl8k_cmd_pkt *cmd;
453 cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
457 cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
463 int block_size = length > 256 ? 256 : length;
465 memcpy(cmd->payload, data + done, block_size);
466 cmd->length = cpu_to_le16(block_size);
468 rc = mwl8k_send_fw_load_cmd(priv, cmd,
469 sizeof(*cmd) + block_size);
474 length -= block_size;
479 rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
487 static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
488 const u8 *data, size_t length)
490 unsigned char *buffer;
491 int may_continue, rc = 0;
492 u32 done, prev_block_size;
494 buffer = kmalloc(1024, GFP_KERNEL);
501 while (may_continue > 0) {
504 block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
505 if (block_size & 1) {
509 done += prev_block_size;
510 length -= prev_block_size;
513 if (block_size > 1024 || block_size > length) {
523 if (block_size == 0) {
530 prev_block_size = block_size;
531 memcpy(buffer, data + done, block_size);
533 rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
538 if (!rc && length != 0)
546 static int mwl8k_load_firmware(struct ieee80211_hw *hw)
548 struct mwl8k_priv *priv = hw->priv;
549 struct firmware *fw = priv->fw_ucode;
550 struct mwl8k_device_info *di = priv->device_info;
554 if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) {
555 struct firmware *helper = priv->fw_helper;
557 if (helper == NULL) {
558 printk(KERN_ERR "%s: helper image needed but none "
559 "given\n", pci_name(priv->pdev));
563 rc = mwl8k_load_fw_image(priv, helper->data, helper->size);
565 printk(KERN_ERR "%s: unable to load firmware "
566 "helper image\n", pci_name(priv->pdev));
571 rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
573 rc = mwl8k_load_fw_image(priv, fw->data, fw->size);
577 printk(KERN_ERR "%s: unable to load firmware image\n",
578 pci_name(priv->pdev));
582 if (di->modes & BIT(NL80211_IFTYPE_AP))
583 iowrite32(MWL8K_MODE_AP, priv->regs + MWL8K_HIU_GEN_PTR);
585 iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
591 ready_code = ioread32(priv->regs + MWL8K_HIU_INT_CODE);
592 if (ready_code == MWL8K_FWAP_READY) {
595 } else if (ready_code == MWL8K_FWSTA_READY) {
604 return loops ? 0 : -ETIMEDOUT;
609 * Defines shared between transmission and reception.
611 /* HT control fields for firmware */
616 } __attribute__((packed));
618 /* Firmware Station database operations */
619 #define MWL8K_STA_DB_ADD_ENTRY 0
620 #define MWL8K_STA_DB_MODIFY_ENTRY 1
621 #define MWL8K_STA_DB_DEL_ENTRY 2
622 #define MWL8K_STA_DB_FLUSH 3
624 /* Peer Entry flags - used to define the type of the peer node */
625 #define MWL8K_PEER_TYPE_ACCESSPOINT 2
627 struct peer_capability_info {
628 /* Peer type - AP vs. STA. */
631 /* Basic 802.11 capabilities from assoc resp. */
634 /* Set if peer supports 802.11n high throughput (HT). */
637 /* Valid if HT is supported. */
639 __u8 extended_ht_caps;
640 struct ewc_ht_info ewc_info;
642 /* Legacy rate table. Intersection of our rates and peer rates. */
643 __u8 legacy_rates[12];
645 /* HT rate table. Intersection of our rates and peer rates. */
649 /* If set, interoperability mode, no proprietary extensions. */
653 __le16 amsdu_enabled;
654 } __attribute__((packed));
656 /* DMA header used by firmware and hardware. */
657 struct mwl8k_dma_data {
659 struct ieee80211_hdr wh;
661 } __attribute__((packed));
663 /* Routines to add/remove DMA header from skb. */
664 static inline void mwl8k_remove_dma_header(struct sk_buff *skb, __le16 qos)
666 struct mwl8k_dma_data *tr;
669 tr = (struct mwl8k_dma_data *)skb->data;
670 hdrlen = ieee80211_hdrlen(tr->wh.frame_control);
672 if (hdrlen != sizeof(tr->wh)) {
673 if (ieee80211_is_data_qos(tr->wh.frame_control)) {
674 memmove(tr->data - hdrlen, &tr->wh, hdrlen - 2);
675 *((__le16 *)(tr->data - 2)) = qos;
677 memmove(tr->data - hdrlen, &tr->wh, hdrlen);
681 if (hdrlen != sizeof(*tr))
682 skb_pull(skb, sizeof(*tr) - hdrlen);
685 static inline void mwl8k_add_dma_header(struct sk_buff *skb)
687 struct ieee80211_hdr *wh;
689 struct mwl8k_dma_data *tr;
692 * Add a firmware DMA header; the firmware requires that we
693 * present a 2-byte payload length followed by a 4-address
694 * header (without QoS field), followed (optionally) by any
695 * WEP/ExtIV header (but only filled in for CCMP).
697 wh = (struct ieee80211_hdr *)skb->data;
699 hdrlen = ieee80211_hdrlen(wh->frame_control);
700 if (hdrlen != sizeof(*tr))
701 skb_push(skb, sizeof(*tr) - hdrlen);
703 if (ieee80211_is_data_qos(wh->frame_control))
706 tr = (struct mwl8k_dma_data *)skb->data;
708 memmove(&tr->wh, wh, hdrlen);
709 if (hdrlen != sizeof(tr->wh))
710 memset(((void *)&tr->wh) + hdrlen, 0, sizeof(tr->wh) - hdrlen);
713 * Firmware length is the length of the fully formed "802.11
714 * payload". That is, everything except for the 802.11 header.
715 * This includes all crypto material including the MIC.
717 tr->fwlen = cpu_to_le16(skb->len - sizeof(*tr));
722 * Packet reception for 88w8366.
724 struct mwl8k_rxd_8366 {
728 __le32 pkt_phys_addr;
729 __le32 next_rxd_phys_addr;
733 __le32 hw_noise_floor_info;
740 } __attribute__((packed));
742 #define MWL8K_8366_RATE_INFO_MCS_FORMAT 0x80
743 #define MWL8K_8366_RATE_INFO_40MHZ 0x40
744 #define MWL8K_8366_RATE_INFO_RATEID(x) ((x) & 0x3f)
746 #define MWL8K_8366_RX_CTRL_OWNED_BY_HOST 0x80
748 static void mwl8k_rxd_8366_init(void *_rxd, dma_addr_t next_dma_addr)
750 struct mwl8k_rxd_8366 *rxd = _rxd;
752 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
753 rxd->rx_ctrl = MWL8K_8366_RX_CTRL_OWNED_BY_HOST;
756 static void mwl8k_rxd_8366_refill(void *_rxd, dma_addr_t addr, int len)
758 struct mwl8k_rxd_8366 *rxd = _rxd;
760 rxd->pkt_len = cpu_to_le16(len);
761 rxd->pkt_phys_addr = cpu_to_le32(addr);
767 mwl8k_rxd_8366_process(void *_rxd, struct ieee80211_rx_status *status,
770 struct mwl8k_rxd_8366 *rxd = _rxd;
772 if (!(rxd->rx_ctrl & MWL8K_8366_RX_CTRL_OWNED_BY_HOST))
776 memset(status, 0, sizeof(*status));
778 status->signal = -rxd->rssi;
779 status->noise = -rxd->noise_floor;
781 if (rxd->rate & MWL8K_8366_RATE_INFO_MCS_FORMAT) {
782 status->flag |= RX_FLAG_HT;
783 if (rxd->rate & MWL8K_8366_RATE_INFO_40MHZ)
784 status->flag |= RX_FLAG_40MHZ;
785 status->rate_idx = MWL8K_8366_RATE_INFO_RATEID(rxd->rate);
789 for (i = 0; i < ARRAY_SIZE(mwl8k_rates); i++) {
790 if (mwl8k_rates[i].hw_value == rxd->rate) {
791 status->rate_idx = i;
797 status->band = IEEE80211_BAND_2GHZ;
798 status->freq = ieee80211_channel_to_frequency(rxd->channel);
800 *qos = rxd->qos_control;
802 return le16_to_cpu(rxd->pkt_len);
805 static struct rxd_ops rxd_8366_ops = {
806 .rxd_size = sizeof(struct mwl8k_rxd_8366),
807 .rxd_init = mwl8k_rxd_8366_init,
808 .rxd_refill = mwl8k_rxd_8366_refill,
809 .rxd_process = mwl8k_rxd_8366_process,
813 * Packet reception for 88w8687.
815 struct mwl8k_rxd_8687 {
819 __le32 pkt_phys_addr;
820 __le32 next_rxd_phys_addr;
830 } __attribute__((packed));
832 #define MWL8K_8687_RATE_INFO_SHORTPRE 0x8000
833 #define MWL8K_8687_RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3)
834 #define MWL8K_8687_RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f)
835 #define MWL8K_8687_RATE_INFO_40MHZ 0x0004
836 #define MWL8K_8687_RATE_INFO_SHORTGI 0x0002
837 #define MWL8K_8687_RATE_INFO_MCS_FORMAT 0x0001
839 #define MWL8K_8687_RX_CTRL_OWNED_BY_HOST 0x02
841 static void mwl8k_rxd_8687_init(void *_rxd, dma_addr_t next_dma_addr)
843 struct mwl8k_rxd_8687 *rxd = _rxd;
845 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
846 rxd->rx_ctrl = MWL8K_8687_RX_CTRL_OWNED_BY_HOST;
849 static void mwl8k_rxd_8687_refill(void *_rxd, dma_addr_t addr, int len)
851 struct mwl8k_rxd_8687 *rxd = _rxd;
853 rxd->pkt_len = cpu_to_le16(len);
854 rxd->pkt_phys_addr = cpu_to_le32(addr);
860 mwl8k_rxd_8687_process(void *_rxd, struct ieee80211_rx_status *status,
863 struct mwl8k_rxd_8687 *rxd = _rxd;
866 if (!(rxd->rx_ctrl & MWL8K_8687_RX_CTRL_OWNED_BY_HOST))
870 rate_info = le16_to_cpu(rxd->rate_info);
872 memset(status, 0, sizeof(*status));
874 status->signal = -rxd->rssi;
875 status->noise = -rxd->noise_level;
876 status->antenna = MWL8K_8687_RATE_INFO_ANTSELECT(rate_info);
877 status->rate_idx = MWL8K_8687_RATE_INFO_RATEID(rate_info);
879 if (rate_info & MWL8K_8687_RATE_INFO_SHORTPRE)
880 status->flag |= RX_FLAG_SHORTPRE;
881 if (rate_info & MWL8K_8687_RATE_INFO_40MHZ)
882 status->flag |= RX_FLAG_40MHZ;
883 if (rate_info & MWL8K_8687_RATE_INFO_SHORTGI)
884 status->flag |= RX_FLAG_SHORT_GI;
885 if (rate_info & MWL8K_8687_RATE_INFO_MCS_FORMAT)
886 status->flag |= RX_FLAG_HT;
888 status->band = IEEE80211_BAND_2GHZ;
889 status->freq = ieee80211_channel_to_frequency(rxd->channel);
891 *qos = rxd->qos_control;
893 return le16_to_cpu(rxd->pkt_len);
896 static struct rxd_ops rxd_8687_ops = {
897 .rxd_size = sizeof(struct mwl8k_rxd_8687),
898 .rxd_init = mwl8k_rxd_8687_init,
899 .rxd_refill = mwl8k_rxd_8687_refill,
900 .rxd_process = mwl8k_rxd_8687_process,
904 #define MWL8K_RX_DESCS 256
905 #define MWL8K_RX_MAXSZ 3800
907 static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
909 struct mwl8k_priv *priv = hw->priv;
910 struct mwl8k_rx_queue *rxq = priv->rxq + index;
918 size = MWL8K_RX_DESCS * priv->rxd_ops->rxd_size;
920 rxq->rxd = pci_alloc_consistent(priv->pdev, size, &rxq->rxd_dma);
921 if (rxq->rxd == NULL) {
922 printk(KERN_ERR "%s: failed to alloc RX descriptors\n",
923 wiphy_name(hw->wiphy));
926 memset(rxq->rxd, 0, size);
928 rxq->buf = kmalloc(MWL8K_RX_DESCS * sizeof(*rxq->buf), GFP_KERNEL);
929 if (rxq->buf == NULL) {
930 printk(KERN_ERR "%s: failed to alloc RX skbuff list\n",
931 wiphy_name(hw->wiphy));
932 pci_free_consistent(priv->pdev, size, rxq->rxd, rxq->rxd_dma);
935 memset(rxq->buf, 0, MWL8K_RX_DESCS * sizeof(*rxq->buf));
937 for (i = 0; i < MWL8K_RX_DESCS; i++) {
941 dma_addr_t next_dma_addr;
943 desc_size = priv->rxd_ops->rxd_size;
944 rxd = rxq->rxd + (i * priv->rxd_ops->rxd_size);
947 if (nexti == MWL8K_RX_DESCS)
949 next_dma_addr = rxq->rxd_dma + (nexti * desc_size);
951 priv->rxd_ops->rxd_init(rxd, next_dma_addr);
957 static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
959 struct mwl8k_priv *priv = hw->priv;
960 struct mwl8k_rx_queue *rxq = priv->rxq + index;
964 while (rxq->rxd_count < MWL8K_RX_DESCS && limit--) {
970 skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
974 addr = pci_map_single(priv->pdev, skb->data,
975 MWL8K_RX_MAXSZ, DMA_FROM_DEVICE);
979 if (rxq->tail == MWL8K_RX_DESCS)
981 rxq->buf[rx].skb = skb;
982 pci_unmap_addr_set(&rxq->buf[rx], dma, addr);
984 rxd = rxq->rxd + (rx * priv->rxd_ops->rxd_size);
985 priv->rxd_ops->rxd_refill(rxd, addr, MWL8K_RX_MAXSZ);
993 /* Must be called only when the card's reception is completely halted */
994 static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
996 struct mwl8k_priv *priv = hw->priv;
997 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1000 for (i = 0; i < MWL8K_RX_DESCS; i++) {
1001 if (rxq->buf[i].skb != NULL) {
1002 pci_unmap_single(priv->pdev,
1003 pci_unmap_addr(&rxq->buf[i], dma),
1004 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
1005 pci_unmap_addr_set(&rxq->buf[i], dma, 0);
1007 kfree_skb(rxq->buf[i].skb);
1008 rxq->buf[i].skb = NULL;
1015 pci_free_consistent(priv->pdev,
1016 MWL8K_RX_DESCS * priv->rxd_ops->rxd_size,
1017 rxq->rxd, rxq->rxd_dma);
1023 * Scan a list of BSSIDs to process for finalize join.
1024 * Allows for extension to process multiple BSSIDs.
1027 mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
1029 return priv->capture_beacon &&
1030 ieee80211_is_beacon(wh->frame_control) &&
1031 !compare_ether_addr(wh->addr3, priv->capture_bssid);
1034 static inline void mwl8k_save_beacon(struct ieee80211_hw *hw,
1035 struct sk_buff *skb)
1037 struct mwl8k_priv *priv = hw->priv;
1039 priv->capture_beacon = false;
1040 memset(priv->capture_bssid, 0, ETH_ALEN);
1043 * Use GFP_ATOMIC as rxq_process is called from
1044 * the primary interrupt handler, memory allocation call
1047 priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
1048 if (priv->beacon_skb != NULL)
1049 ieee80211_queue_work(hw, &priv->finalize_join_worker);
1052 static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
1054 struct mwl8k_priv *priv = hw->priv;
1055 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1059 while (rxq->rxd_count && limit--) {
1060 struct sk_buff *skb;
1063 struct ieee80211_rx_status status;
1066 skb = rxq->buf[rxq->head].skb;
1070 rxd = rxq->rxd + (rxq->head * priv->rxd_ops->rxd_size);
1072 pkt_len = priv->rxd_ops->rxd_process(rxd, &status, &qos);
1076 rxq->buf[rxq->head].skb = NULL;
1078 pci_unmap_single(priv->pdev,
1079 pci_unmap_addr(&rxq->buf[rxq->head], dma),
1080 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
1081 pci_unmap_addr_set(&rxq->buf[rxq->head], dma, 0);
1084 if (rxq->head == MWL8K_RX_DESCS)
1089 skb_put(skb, pkt_len);
1090 mwl8k_remove_dma_header(skb, qos);
1093 * Check for a pending join operation. Save a
1094 * copy of the beacon and schedule a tasklet to
1095 * send a FINALIZE_JOIN command to the firmware.
1097 if (mwl8k_capture_bssid(priv, (void *)skb->data))
1098 mwl8k_save_beacon(hw, skb);
1100 memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
1101 ieee80211_rx_irqsafe(hw, skb);
1111 * Packet transmission.
1114 #define MWL8K_TXD_STATUS_OK 0x00000001
1115 #define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
1116 #define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
1117 #define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
1118 #define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
1120 #define MWL8K_QOS_QLEN_UNSPEC 0xff00
1121 #define MWL8K_QOS_ACK_POLICY_MASK 0x0060
1122 #define MWL8K_QOS_ACK_POLICY_NORMAL 0x0000
1123 #define MWL8K_QOS_ACK_POLICY_BLOCKACK 0x0060
1124 #define MWL8K_QOS_EOSP 0x0010
1126 struct mwl8k_tx_desc {
1131 __le32 pkt_phys_addr;
1133 __u8 dest_MAC_addr[ETH_ALEN];
1134 __le32 next_txd_phys_addr;
1139 } __attribute__((packed));
1141 #define MWL8K_TX_DESCS 128
1143 static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
1145 struct mwl8k_priv *priv = hw->priv;
1146 struct mwl8k_tx_queue *txq = priv->txq + index;
1150 memset(&txq->stats, 0, sizeof(struct ieee80211_tx_queue_stats));
1151 txq->stats.limit = MWL8K_TX_DESCS;
1155 size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
1157 txq->txd = pci_alloc_consistent(priv->pdev, size, &txq->txd_dma);
1158 if (txq->txd == NULL) {
1159 printk(KERN_ERR "%s: failed to alloc TX descriptors\n",
1160 wiphy_name(hw->wiphy));
1163 memset(txq->txd, 0, size);
1165 txq->skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->skb), GFP_KERNEL);
1166 if (txq->skb == NULL) {
1167 printk(KERN_ERR "%s: failed to alloc TX skbuff list\n",
1168 wiphy_name(hw->wiphy));
1169 pci_free_consistent(priv->pdev, size, txq->txd, txq->txd_dma);
1172 memset(txq->skb, 0, MWL8K_TX_DESCS * sizeof(*txq->skb));
1174 for (i = 0; i < MWL8K_TX_DESCS; i++) {
1175 struct mwl8k_tx_desc *tx_desc;
1178 tx_desc = txq->txd + i;
1179 nexti = (i + 1) % MWL8K_TX_DESCS;
1181 tx_desc->status = 0;
1182 tx_desc->next_txd_phys_addr =
1183 cpu_to_le32(txq->txd_dma + nexti * sizeof(*tx_desc));
1189 static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
1191 iowrite32(MWL8K_H2A_INT_PPA_READY,
1192 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1193 iowrite32(MWL8K_H2A_INT_DUMMY,
1194 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1195 ioread32(priv->regs + MWL8K_HIU_INT_CODE);
1198 static void mwl8k_dump_tx_rings(struct ieee80211_hw *hw)
1200 struct mwl8k_priv *priv = hw->priv;
1203 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
1204 struct mwl8k_tx_queue *txq = priv->txq + i;
1210 for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
1211 struct mwl8k_tx_desc *tx_desc = txq->txd + desc;
1214 status = le32_to_cpu(tx_desc->status);
1215 if (status & MWL8K_TXD_STATUS_FW_OWNED)
1220 if (tx_desc->pkt_len == 0)
1224 printk(KERN_ERR "%s: txq[%d] len=%d head=%d tail=%d "
1225 "fw_owned=%d drv_owned=%d unused=%d\n",
1226 wiphy_name(hw->wiphy), i,
1227 txq->stats.len, txq->head, txq->tail,
1228 fw_owned, drv_owned, unused);
1233 * Must be called with priv->fw_mutex held and tx queues stopped.
1235 #define MWL8K_TX_WAIT_TIMEOUT_MS 1000
1237 static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw)
1239 struct mwl8k_priv *priv = hw->priv;
1240 DECLARE_COMPLETION_ONSTACK(tx_wait);
1247 * The TX queues are stopped at this point, so this test
1248 * doesn't need to take ->tx_lock.
1250 if (!priv->pending_tx_pkts)
1256 spin_lock_bh(&priv->tx_lock);
1257 priv->tx_wait = &tx_wait;
1260 unsigned long timeout;
1262 oldcount = priv->pending_tx_pkts;
1264 spin_unlock_bh(&priv->tx_lock);
1265 timeout = wait_for_completion_timeout(&tx_wait,
1266 msecs_to_jiffies(MWL8K_TX_WAIT_TIMEOUT_MS));
1267 spin_lock_bh(&priv->tx_lock);
1270 WARN_ON(priv->pending_tx_pkts);
1272 printk(KERN_NOTICE "%s: tx rings drained\n",
1273 wiphy_name(hw->wiphy));
1278 if (priv->pending_tx_pkts < oldcount) {
1279 printk(KERN_NOTICE "%s: timeout waiting for tx "
1280 "rings to drain (%d -> %d pkts), retrying\n",
1281 wiphy_name(hw->wiphy), oldcount,
1282 priv->pending_tx_pkts);
1287 priv->tx_wait = NULL;
1289 printk(KERN_ERR "%s: tx rings stuck for %d ms\n",
1290 wiphy_name(hw->wiphy), MWL8K_TX_WAIT_TIMEOUT_MS);
1291 mwl8k_dump_tx_rings(hw);
1295 spin_unlock_bh(&priv->tx_lock);
1300 #define MWL8K_TXD_SUCCESS(status) \
1301 ((status) & (MWL8K_TXD_STATUS_OK | \
1302 MWL8K_TXD_STATUS_OK_RETRY | \
1303 MWL8K_TXD_STATUS_OK_MORE_RETRY))
1305 static void mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int force)
1307 struct mwl8k_priv *priv = hw->priv;
1308 struct mwl8k_tx_queue *txq = priv->txq + index;
1311 while (txq->stats.len > 0) {
1313 struct mwl8k_tx_desc *tx_desc;
1316 struct sk_buff *skb;
1317 struct ieee80211_tx_info *info;
1321 tx_desc = txq->txd + tx;
1323 status = le32_to_cpu(tx_desc->status);
1325 if (status & MWL8K_TXD_STATUS_FW_OWNED) {
1329 ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
1332 txq->head = (tx + 1) % MWL8K_TX_DESCS;
1333 BUG_ON(txq->stats.len == 0);
1335 priv->pending_tx_pkts--;
1337 addr = le32_to_cpu(tx_desc->pkt_phys_addr);
1338 size = le16_to_cpu(tx_desc->pkt_len);
1340 txq->skb[tx] = NULL;
1342 BUG_ON(skb == NULL);
1343 pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
1345 mwl8k_remove_dma_header(skb, tx_desc->qos_control);
1347 /* Mark descriptor as unused */
1348 tx_desc->pkt_phys_addr = 0;
1349 tx_desc->pkt_len = 0;
1351 info = IEEE80211_SKB_CB(skb);
1352 ieee80211_tx_info_clear_status(info);
1353 if (MWL8K_TXD_SUCCESS(status))
1354 info->flags |= IEEE80211_TX_STAT_ACK;
1356 ieee80211_tx_status_irqsafe(hw, skb);
1361 if (wake && priv->radio_on && !mutex_is_locked(&priv->fw_mutex))
1362 ieee80211_wake_queue(hw, index);
1365 /* must be called only when the card's transmit is completely halted */
1366 static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
1368 struct mwl8k_priv *priv = hw->priv;
1369 struct mwl8k_tx_queue *txq = priv->txq + index;
1371 mwl8k_txq_reclaim(hw, index, 1);
1376 pci_free_consistent(priv->pdev,
1377 MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
1378 txq->txd, txq->txd_dma);
1383 mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb)
1385 struct mwl8k_priv *priv = hw->priv;
1386 struct ieee80211_tx_info *tx_info;
1387 struct mwl8k_vif *mwl8k_vif;
1388 struct ieee80211_hdr *wh;
1389 struct mwl8k_tx_queue *txq;
1390 struct mwl8k_tx_desc *tx;
1396 wh = (struct ieee80211_hdr *)skb->data;
1397 if (ieee80211_is_data_qos(wh->frame_control))
1398 qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
1402 mwl8k_add_dma_header(skb);
1403 wh = &((struct mwl8k_dma_data *)skb->data)->wh;
1405 tx_info = IEEE80211_SKB_CB(skb);
1406 mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
1408 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1409 u16 seqno = mwl8k_vif->seqno;
1411 wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1412 wh->seq_ctrl |= cpu_to_le16(seqno << 4);
1413 mwl8k_vif->seqno = seqno++ % 4096;
1416 /* Setup firmware control bit fields for each frame type. */
1419 if (ieee80211_is_mgmt(wh->frame_control) ||
1420 ieee80211_is_ctl(wh->frame_control)) {
1422 qos |= MWL8K_QOS_QLEN_UNSPEC | MWL8K_QOS_EOSP;
1423 } else if (ieee80211_is_data(wh->frame_control)) {
1425 if (is_multicast_ether_addr(wh->addr1))
1426 txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX;
1428 qos &= ~MWL8K_QOS_ACK_POLICY_MASK;
1429 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
1430 qos |= MWL8K_QOS_ACK_POLICY_BLOCKACK;
1432 qos |= MWL8K_QOS_ACK_POLICY_NORMAL;
1435 dma = pci_map_single(priv->pdev, skb->data,
1436 skb->len, PCI_DMA_TODEVICE);
1438 if (pci_dma_mapping_error(priv->pdev, dma)) {
1439 printk(KERN_DEBUG "%s: failed to dma map skb, "
1440 "dropping TX frame.\n", wiphy_name(hw->wiphy));
1442 return NETDEV_TX_OK;
1445 spin_lock_bh(&priv->tx_lock);
1447 txq = priv->txq + index;
1449 BUG_ON(txq->skb[txq->tail] != NULL);
1450 txq->skb[txq->tail] = skb;
1452 tx = txq->txd + txq->tail;
1453 tx->data_rate = txdatarate;
1454 tx->tx_priority = index;
1455 tx->qos_control = cpu_to_le16(qos);
1456 tx->pkt_phys_addr = cpu_to_le32(dma);
1457 tx->pkt_len = cpu_to_le16(skb->len);
1459 tx->peer_id = mwl8k_vif->peer_id;
1461 tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus);
1465 priv->pending_tx_pkts++;
1468 if (txq->tail == MWL8K_TX_DESCS)
1471 if (txq->head == txq->tail)
1472 ieee80211_stop_queue(hw, index);
1474 mwl8k_tx_start(priv);
1476 spin_unlock_bh(&priv->tx_lock);
1478 return NETDEV_TX_OK;
1485 * We have the following requirements for issuing firmware commands:
1486 * - Some commands require that the packet transmit path is idle when
1487 * the command is issued. (For simplicity, we'll just quiesce the
1488 * transmit path for every command.)
1489 * - There are certain sequences of commands that need to be issued to
1490 * the hardware sequentially, with no other intervening commands.
1492 * This leads to an implementation of a "firmware lock" as a mutex that
1493 * can be taken recursively, and which is taken by both the low-level
1494 * command submission function (mwl8k_post_cmd) as well as any users of
1495 * that function that require issuing of an atomic sequence of commands,
1496 * and quiesces the transmit path whenever it's taken.
1498 static int mwl8k_fw_lock(struct ieee80211_hw *hw)
1500 struct mwl8k_priv *priv = hw->priv;
1502 if (priv->fw_mutex_owner != current) {
1505 mutex_lock(&priv->fw_mutex);
1506 ieee80211_stop_queues(hw);
1508 rc = mwl8k_tx_wait_empty(hw);
1510 ieee80211_wake_queues(hw);
1511 mutex_unlock(&priv->fw_mutex);
1516 priv->fw_mutex_owner = current;
1519 priv->fw_mutex_depth++;
1524 static void mwl8k_fw_unlock(struct ieee80211_hw *hw)
1526 struct mwl8k_priv *priv = hw->priv;
1528 if (!--priv->fw_mutex_depth) {
1529 ieee80211_wake_queues(hw);
1530 priv->fw_mutex_owner = NULL;
1531 mutex_unlock(&priv->fw_mutex);
1537 * Command processing.
1540 /* Timeout firmware commands after 10s */
1541 #define MWL8K_CMD_TIMEOUT_MS 10000
1543 static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
1545 DECLARE_COMPLETION_ONSTACK(cmd_wait);
1546 struct mwl8k_priv *priv = hw->priv;
1547 void __iomem *regs = priv->regs;
1548 dma_addr_t dma_addr;
1549 unsigned int dma_size;
1551 unsigned long timeout = 0;
1554 cmd->result = 0xffff;
1555 dma_size = le16_to_cpu(cmd->length);
1556 dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
1557 PCI_DMA_BIDIRECTIONAL);
1558 if (pci_dma_mapping_error(priv->pdev, dma_addr))
1561 rc = mwl8k_fw_lock(hw);
1563 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1564 PCI_DMA_BIDIRECTIONAL);
1568 priv->hostcmd_wait = &cmd_wait;
1569 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
1570 iowrite32(MWL8K_H2A_INT_DOORBELL,
1571 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1572 iowrite32(MWL8K_H2A_INT_DUMMY,
1573 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1575 timeout = wait_for_completion_timeout(&cmd_wait,
1576 msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS));
1578 priv->hostcmd_wait = NULL;
1580 mwl8k_fw_unlock(hw);
1582 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1583 PCI_DMA_BIDIRECTIONAL);
1586 printk(KERN_ERR "%s: Command %s timeout after %u ms\n",
1587 wiphy_name(hw->wiphy),
1588 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1589 MWL8K_CMD_TIMEOUT_MS);
1594 ms = MWL8K_CMD_TIMEOUT_MS - jiffies_to_msecs(timeout);
1596 rc = cmd->result ? -EINVAL : 0;
1598 printk(KERN_ERR "%s: Command %s error 0x%x\n",
1599 wiphy_name(hw->wiphy),
1600 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1601 le16_to_cpu(cmd->result));
1603 printk(KERN_NOTICE "%s: Command %s took %d ms\n",
1604 wiphy_name(hw->wiphy),
1605 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1613 * CMD_GET_HW_SPEC (STA version).
1615 struct mwl8k_cmd_get_hw_spec_sta {
1616 struct mwl8k_cmd_pkt header;
1618 __u8 host_interface;
1620 __u8 perm_addr[ETH_ALEN];
1625 __u8 mcs_bitmap[16];
1626 __le32 rx_queue_ptr;
1627 __le32 num_tx_queues;
1628 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1630 __le32 num_tx_desc_per_queue;
1632 } __attribute__((packed));
1634 static int mwl8k_cmd_get_hw_spec_sta(struct ieee80211_hw *hw)
1636 struct mwl8k_priv *priv = hw->priv;
1637 struct mwl8k_cmd_get_hw_spec_sta *cmd;
1641 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1645 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1646 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1648 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1649 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1650 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
1651 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
1652 for (i = 0; i < MWL8K_TX_QUEUES; i++)
1653 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
1654 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
1655 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
1657 rc = mwl8k_post_cmd(hw, &cmd->header);
1660 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1661 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
1662 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
1663 priv->hw_rev = cmd->hw_rev;
1671 * CMD_GET_HW_SPEC (AP version).
1673 struct mwl8k_cmd_get_hw_spec_ap {
1674 struct mwl8k_cmd_pkt header;
1676 __u8 host_interface;
1679 __u8 perm_addr[ETH_ALEN];
1690 } __attribute__((packed));
1692 static int mwl8k_cmd_get_hw_spec_ap(struct ieee80211_hw *hw)
1694 struct mwl8k_priv *priv = hw->priv;
1695 struct mwl8k_cmd_get_hw_spec_ap *cmd;
1698 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1702 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1703 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1705 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1706 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1708 rc = mwl8k_post_cmd(hw, &cmd->header);
1713 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1714 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
1715 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
1716 priv->hw_rev = cmd->hw_rev;
1718 off = le32_to_cpu(cmd->wcbbase0) & 0xffff;
1719 iowrite32(cpu_to_le32(priv->txq[0].txd_dma), priv->sram + off);
1721 off = le32_to_cpu(cmd->rxwrptr) & 0xffff;
1722 iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
1724 off = le32_to_cpu(cmd->rxrdptr) & 0xffff;
1725 iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
1727 off = le32_to_cpu(cmd->wcbbase1) & 0xffff;
1728 iowrite32(cpu_to_le32(priv->txq[1].txd_dma), priv->sram + off);
1730 off = le32_to_cpu(cmd->wcbbase2) & 0xffff;
1731 iowrite32(cpu_to_le32(priv->txq[2].txd_dma), priv->sram + off);
1733 off = le32_to_cpu(cmd->wcbbase3) & 0xffff;
1734 iowrite32(cpu_to_le32(priv->txq[3].txd_dma), priv->sram + off);
1744 struct mwl8k_cmd_set_hw_spec {
1745 struct mwl8k_cmd_pkt header;
1747 __u8 host_interface;
1749 __u8 perm_addr[ETH_ALEN];
1754 __le32 rx_queue_ptr;
1755 __le32 num_tx_queues;
1756 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1758 __le32 num_tx_desc_per_queue;
1760 } __attribute__((packed));
1762 #define MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT 0x00000080
1764 static int mwl8k_cmd_set_hw_spec(struct ieee80211_hw *hw)
1766 struct mwl8k_priv *priv = hw->priv;
1767 struct mwl8k_cmd_set_hw_spec *cmd;
1771 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1775 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_HW_SPEC);
1776 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1778 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1779 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
1780 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
1781 for (i = 0; i < MWL8K_TX_QUEUES; i++)
1782 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
1783 cmd->flags = cpu_to_le32(MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT);
1784 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
1785 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
1787 rc = mwl8k_post_cmd(hw, &cmd->header);
1794 * CMD_MAC_MULTICAST_ADR.
1796 struct mwl8k_cmd_mac_multicast_adr {
1797 struct mwl8k_cmd_pkt header;
1800 __u8 addr[0][ETH_ALEN];
1803 #define MWL8K_ENABLE_RX_DIRECTED 0x0001
1804 #define MWL8K_ENABLE_RX_MULTICAST 0x0002
1805 #define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004
1806 #define MWL8K_ENABLE_RX_BROADCAST 0x0008
1808 static struct mwl8k_cmd_pkt *
1809 __mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti,
1810 int mc_count, struct dev_addr_list *mclist)
1812 struct mwl8k_priv *priv = hw->priv;
1813 struct mwl8k_cmd_mac_multicast_adr *cmd;
1816 if (allmulti || mc_count > priv->num_mcaddrs) {
1821 size = sizeof(*cmd) + mc_count * ETH_ALEN;
1823 cmd = kzalloc(size, GFP_ATOMIC);
1827 cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
1828 cmd->header.length = cpu_to_le16(size);
1829 cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED |
1830 MWL8K_ENABLE_RX_BROADCAST);
1833 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST);
1834 } else if (mc_count) {
1837 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
1838 cmd->numaddr = cpu_to_le16(mc_count);
1839 for (i = 0; i < mc_count && mclist; i++) {
1840 if (mclist->da_addrlen != ETH_ALEN) {
1844 memcpy(cmd->addr[i], mclist->da_addr, ETH_ALEN);
1845 mclist = mclist->next;
1849 return &cmd->header;
1855 struct mwl8k_cmd_get_stat {
1856 struct mwl8k_cmd_pkt header;
1858 } __attribute__((packed));
1860 #define MWL8K_STAT_ACK_FAILURE 9
1861 #define MWL8K_STAT_RTS_FAILURE 12
1862 #define MWL8K_STAT_FCS_ERROR 24
1863 #define MWL8K_STAT_RTS_SUCCESS 11
1865 static int mwl8k_cmd_get_stat(struct ieee80211_hw *hw,
1866 struct ieee80211_low_level_stats *stats)
1868 struct mwl8k_cmd_get_stat *cmd;
1871 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1875 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
1876 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1878 rc = mwl8k_post_cmd(hw, &cmd->header);
1880 stats->dot11ACKFailureCount =
1881 le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]);
1882 stats->dot11RTSFailureCount =
1883 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]);
1884 stats->dot11FCSErrorCount =
1885 le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]);
1886 stats->dot11RTSSuccessCount =
1887 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]);
1895 * CMD_RADIO_CONTROL.
1897 struct mwl8k_cmd_radio_control {
1898 struct mwl8k_cmd_pkt header;
1902 } __attribute__((packed));
1905 mwl8k_cmd_radio_control(struct ieee80211_hw *hw, bool enable, bool force)
1907 struct mwl8k_priv *priv = hw->priv;
1908 struct mwl8k_cmd_radio_control *cmd;
1911 if (enable == priv->radio_on && !force)
1914 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1918 cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL);
1919 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1920 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1921 cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1);
1922 cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000);
1924 rc = mwl8k_post_cmd(hw, &cmd->header);
1928 priv->radio_on = enable;
1933 static int mwl8k_cmd_radio_disable(struct ieee80211_hw *hw)
1935 return mwl8k_cmd_radio_control(hw, 0, 0);
1938 static int mwl8k_cmd_radio_enable(struct ieee80211_hw *hw)
1940 return mwl8k_cmd_radio_control(hw, 1, 0);
1944 mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
1946 struct mwl8k_priv *priv = hw->priv;
1948 priv->radio_short_preamble = short_preamble;
1950 return mwl8k_cmd_radio_control(hw, 1, 1);
1956 #define MWL8K_TX_POWER_LEVEL_TOTAL 8
1958 struct mwl8k_cmd_rf_tx_power {
1959 struct mwl8k_cmd_pkt header;
1961 __le16 support_level;
1962 __le16 current_level;
1964 __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
1965 } __attribute__((packed));
1967 static int mwl8k_cmd_rf_tx_power(struct ieee80211_hw *hw, int dBm)
1969 struct mwl8k_cmd_rf_tx_power *cmd;
1972 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1976 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER);
1977 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1978 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1979 cmd->support_level = cpu_to_le16(dBm);
1981 rc = mwl8k_post_cmd(hw, &cmd->header);
1990 struct mwl8k_cmd_rf_antenna {
1991 struct mwl8k_cmd_pkt header;
1994 } __attribute__((packed));
1996 #define MWL8K_RF_ANTENNA_RX 1
1997 #define MWL8K_RF_ANTENNA_TX 2
2000 mwl8k_cmd_rf_antenna(struct ieee80211_hw *hw, int antenna, int mask)
2002 struct mwl8k_cmd_rf_antenna *cmd;
2005 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2009 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_ANTENNA);
2010 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2011 cmd->antenna = cpu_to_le16(antenna);
2012 cmd->mode = cpu_to_le16(mask);
2014 rc = mwl8k_post_cmd(hw, &cmd->header);
2023 struct mwl8k_cmd_set_pre_scan {
2024 struct mwl8k_cmd_pkt header;
2025 } __attribute__((packed));
2027 static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw)
2029 struct mwl8k_cmd_set_pre_scan *cmd;
2032 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2036 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN);
2037 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2039 rc = mwl8k_post_cmd(hw, &cmd->header);
2046 * CMD_SET_POST_SCAN.
2048 struct mwl8k_cmd_set_post_scan {
2049 struct mwl8k_cmd_pkt header;
2051 __u8 bssid[ETH_ALEN];
2052 } __attribute__((packed));
2055 mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, __u8 *mac)
2057 struct mwl8k_cmd_set_post_scan *cmd;
2060 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2064 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN);
2065 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2067 memcpy(cmd->bssid, mac, ETH_ALEN);
2069 rc = mwl8k_post_cmd(hw, &cmd->header);
2076 * CMD_SET_RF_CHANNEL.
2078 struct mwl8k_cmd_set_rf_channel {
2079 struct mwl8k_cmd_pkt header;
2081 __u8 current_channel;
2082 __le32 channel_flags;
2083 } __attribute__((packed));
2085 static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw,
2086 struct ieee80211_channel *channel)
2088 struct mwl8k_cmd_set_rf_channel *cmd;
2091 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2095 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL);
2096 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2097 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2098 cmd->current_channel = channel->hw_value;
2099 if (channel->band == IEEE80211_BAND_2GHZ)
2100 cmd->channel_flags = cpu_to_le32(0x00000081);
2102 cmd->channel_flags = cpu_to_le32(0x00000000);
2104 rc = mwl8k_post_cmd(hw, &cmd->header);
2113 #define MWL8K_FRAME_PROT_DISABLED 0x00
2114 #define MWL8K_FRAME_PROT_11G 0x07
2115 #define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
2116 #define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
2118 struct mwl8k_cmd_update_set_aid {
2119 struct mwl8k_cmd_pkt header;
2122 /* AP's MAC address (BSSID) */
2123 __u8 bssid[ETH_ALEN];
2124 __le16 protection_mode;
2125 __u8 supp_rates[14];
2126 } __attribute__((packed));
2129 mwl8k_cmd_set_aid(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
2131 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2132 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2133 struct mwl8k_cmd_update_set_aid *cmd;
2137 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2141 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID);
2142 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2143 cmd->aid = cpu_to_le16(info->aid);
2145 memcpy(cmd->bssid, mv_vif->bssid, ETH_ALEN);
2147 if (info->use_cts_prot) {
2148 prot_mode = MWL8K_FRAME_PROT_11G;
2150 switch (info->ht_operation_mode &
2151 IEEE80211_HT_OP_MODE_PROTECTION) {
2152 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
2153 prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY;
2155 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
2156 prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL;
2159 prot_mode = MWL8K_FRAME_PROT_DISABLED;
2163 cmd->protection_mode = cpu_to_le16(prot_mode);
2165 memcpy(cmd->supp_rates, mwl8k_rateids, sizeof(mwl8k_rateids));
2167 rc = mwl8k_post_cmd(hw, &cmd->header);
2176 struct mwl8k_cmd_set_rate {
2177 struct mwl8k_cmd_pkt header;
2178 __u8 legacy_rates[14];
2180 /* Bitmap for supported MCS codes. */
2183 } __attribute__((packed));
2186 mwl8k_cmd_set_rate(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
2188 struct mwl8k_cmd_set_rate *cmd;
2191 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2195 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE);
2196 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2197 memcpy(cmd->legacy_rates, mwl8k_rateids, sizeof(mwl8k_rateids));
2199 rc = mwl8k_post_cmd(hw, &cmd->header);
2206 * CMD_FINALIZE_JOIN.
2208 #define MWL8K_FJ_BEACON_MAXLEN 128
2210 struct mwl8k_cmd_finalize_join {
2211 struct mwl8k_cmd_pkt header;
2212 __le32 sleep_interval; /* Number of beacon periods to sleep */
2213 __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN];
2214 } __attribute__((packed));
2216 static int mwl8k_cmd_finalize_join(struct ieee80211_hw *hw, void *frame,
2217 int framelen, int dtim)
2219 struct mwl8k_cmd_finalize_join *cmd;
2220 struct ieee80211_mgmt *payload = frame;
2224 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2228 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN);
2229 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2230 cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1);
2232 payload_len = framelen - ieee80211_hdrlen(payload->frame_control);
2233 if (payload_len < 0)
2235 else if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2236 payload_len = MWL8K_FJ_BEACON_MAXLEN;
2238 memcpy(cmd->beacon_data, &payload->u.beacon, payload_len);
2240 rc = mwl8k_post_cmd(hw, &cmd->header);
2247 * CMD_SET_RTS_THRESHOLD.
2249 struct mwl8k_cmd_set_rts_threshold {
2250 struct mwl8k_cmd_pkt header;
2253 } __attribute__((packed));
2255 static int mwl8k_cmd_set_rts_threshold(struct ieee80211_hw *hw,
2256 u16 action, u16 threshold)
2258 struct mwl8k_cmd_set_rts_threshold *cmd;
2261 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2265 cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD);
2266 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2267 cmd->action = cpu_to_le16(action);
2268 cmd->threshold = cpu_to_le16(threshold);
2270 rc = mwl8k_post_cmd(hw, &cmd->header);
2279 struct mwl8k_cmd_set_slot {
2280 struct mwl8k_cmd_pkt header;
2283 } __attribute__((packed));
2285 static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time)
2287 struct mwl8k_cmd_set_slot *cmd;
2290 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2294 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT);
2295 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2296 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2297 cmd->short_slot = short_slot_time;
2299 rc = mwl8k_post_cmd(hw, &cmd->header);
2306 * CMD_SET_EDCA_PARAMS.
2308 struct mwl8k_cmd_set_edca_params {
2309 struct mwl8k_cmd_pkt header;
2311 /* See MWL8K_SET_EDCA_XXX below */
2314 /* TX opportunity in units of 32 us */
2319 /* Log exponent of max contention period: 0...15 */
2322 /* Log exponent of min contention period: 0...15 */
2325 /* Adaptive interframe spacing in units of 32us */
2328 /* TX queue to configure */
2332 /* Log exponent of max contention period: 0...15 */
2335 /* Log exponent of min contention period: 0...15 */
2338 /* Adaptive interframe spacing in units of 32us */
2341 /* TX queue to configure */
2345 } __attribute__((packed));
2347 #define MWL8K_SET_EDCA_CW 0x01
2348 #define MWL8K_SET_EDCA_TXOP 0x02
2349 #define MWL8K_SET_EDCA_AIFS 0x04
2351 #define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \
2352 MWL8K_SET_EDCA_TXOP | \
2353 MWL8K_SET_EDCA_AIFS)
2356 mwl8k_cmd_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
2357 __u16 cw_min, __u16 cw_max,
2358 __u8 aifs, __u16 txop)
2360 struct mwl8k_priv *priv = hw->priv;
2361 struct mwl8k_cmd_set_edca_params *cmd;
2364 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2369 * Queues 0 (BE) and 1 (BK) are swapped in hardware for
2372 qnum ^= !(qnum >> 1);
2374 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
2375 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2376 cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
2377 cmd->txop = cpu_to_le16(txop);
2379 cmd->ap.log_cw_max = cpu_to_le32(ilog2(cw_max + 1));
2380 cmd->ap.log_cw_min = cpu_to_le32(ilog2(cw_min + 1));
2381 cmd->ap.aifs = aifs;
2384 cmd->sta.log_cw_max = (u8)ilog2(cw_max + 1);
2385 cmd->sta.log_cw_min = (u8)ilog2(cw_min + 1);
2386 cmd->sta.aifs = aifs;
2387 cmd->sta.txq = qnum;
2390 rc = mwl8k_post_cmd(hw, &cmd->header);
2399 struct mwl8k_cmd_set_wmm_mode {
2400 struct mwl8k_cmd_pkt header;
2402 } __attribute__((packed));
2404 static int mwl8k_cmd_set_wmm_mode(struct ieee80211_hw *hw, bool enable)
2406 struct mwl8k_priv *priv = hw->priv;
2407 struct mwl8k_cmd_set_wmm_mode *cmd;
2410 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2414 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE);
2415 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2416 cmd->action = cpu_to_le16(!!enable);
2418 rc = mwl8k_post_cmd(hw, &cmd->header);
2422 priv->wmm_enabled = enable;
2430 struct mwl8k_cmd_mimo_config {
2431 struct mwl8k_cmd_pkt header;
2433 __u8 rx_antenna_map;
2434 __u8 tx_antenna_map;
2435 } __attribute__((packed));
2437 static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx)
2439 struct mwl8k_cmd_mimo_config *cmd;
2442 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2446 cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG);
2447 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2448 cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET);
2449 cmd->rx_antenna_map = rx;
2450 cmd->tx_antenna_map = tx;
2452 rc = mwl8k_post_cmd(hw, &cmd->header);
2459 * CMD_USE_FIXED_RATE.
2461 #define MWL8K_RATE_TABLE_SIZE 8
2462 #define MWL8K_UCAST_RATE 0
2463 #define MWL8K_USE_AUTO_RATE 0x0002
2465 struct mwl8k_rate_entry {
2466 /* Set to 1 if HT rate, 0 if legacy. */
2469 /* Set to 1 to use retry_count field. */
2470 __le32 enable_retry;
2472 /* Specified legacy rate or MCS. */
2475 /* Number of allowed retries. */
2477 } __attribute__((packed));
2479 struct mwl8k_rate_table {
2480 /* 1 to allow specified rate and below */
2481 __le32 allow_rate_drop;
2483 struct mwl8k_rate_entry rate_entry[MWL8K_RATE_TABLE_SIZE];
2484 } __attribute__((packed));
2486 struct mwl8k_cmd_use_fixed_rate {
2487 struct mwl8k_cmd_pkt header;
2489 struct mwl8k_rate_table rate_table;
2491 /* Unicast, Broadcast or Multicast */
2495 } __attribute__((packed));
2497 static int mwl8k_cmd_use_fixed_rate(struct ieee80211_hw *hw,
2498 u32 action, u32 rate_type, struct mwl8k_rate_table *rate_table)
2500 struct mwl8k_cmd_use_fixed_rate *cmd;
2504 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2508 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
2509 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2511 cmd->action = cpu_to_le32(action);
2512 cmd->rate_type = cpu_to_le32(rate_type);
2514 if (rate_table != NULL) {
2516 * Copy over each field manually so that endian
2517 * conversion can be done.
2519 cmd->rate_table.allow_rate_drop =
2520 cpu_to_le32(rate_table->allow_rate_drop);
2521 cmd->rate_table.num_rates =
2522 cpu_to_le32(rate_table->num_rates);
2524 for (count = 0; count < rate_table->num_rates; count++) {
2525 struct mwl8k_rate_entry *dst =
2526 &cmd->rate_table.rate_entry[count];
2527 struct mwl8k_rate_entry *src =
2528 &rate_table->rate_entry[count];
2530 dst->is_ht_rate = cpu_to_le32(src->is_ht_rate);
2531 dst->enable_retry = cpu_to_le32(src->enable_retry);
2532 dst->rate = cpu_to_le32(src->rate);
2533 dst->retry_count = cpu_to_le32(src->retry_count);
2537 rc = mwl8k_post_cmd(hw, &cmd->header);
2544 * CMD_ENABLE_SNIFFER.
2546 struct mwl8k_cmd_enable_sniffer {
2547 struct mwl8k_cmd_pkt header;
2549 } __attribute__((packed));
2551 static int mwl8k_cmd_enable_sniffer(struct ieee80211_hw *hw, bool enable)
2553 struct mwl8k_cmd_enable_sniffer *cmd;
2556 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2560 cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER);
2561 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2562 cmd->action = cpu_to_le32(!!enable);
2564 rc = mwl8k_post_cmd(hw, &cmd->header);
2573 struct mwl8k_cmd_set_mac_addr {
2574 struct mwl8k_cmd_pkt header;
2578 __u8 mac_addr[ETH_ALEN];
2580 __u8 mac_addr[ETH_ALEN];
2582 } __attribute__((packed));
2584 static int mwl8k_cmd_set_mac_addr(struct ieee80211_hw *hw, u8 *mac)
2586 struct mwl8k_priv *priv = hw->priv;
2587 struct mwl8k_cmd_set_mac_addr *cmd;
2590 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2594 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR);
2595 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2597 cmd->mbss.mac_type = 0;
2598 memcpy(cmd->mbss.mac_addr, mac, ETH_ALEN);
2600 memcpy(cmd->mac_addr, mac, ETH_ALEN);
2603 rc = mwl8k_post_cmd(hw, &cmd->header);
2610 * CMD_SET_RATEADAPT_MODE.
2612 struct mwl8k_cmd_set_rate_adapt_mode {
2613 struct mwl8k_cmd_pkt header;
2616 } __attribute__((packed));
2618 static int mwl8k_cmd_set_rateadapt_mode(struct ieee80211_hw *hw, __u16 mode)
2620 struct mwl8k_cmd_set_rate_adapt_mode *cmd;
2623 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2627 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE);
2628 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2629 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2630 cmd->mode = cpu_to_le16(mode);
2632 rc = mwl8k_post_cmd(hw, &cmd->header);
2641 struct mwl8k_cmd_update_stadb {
2642 struct mwl8k_cmd_pkt header;
2644 /* See STADB_ACTION_TYPE */
2647 /* Peer MAC address */
2648 __u8 peer_addr[ETH_ALEN];
2652 /* Peer info - valid during add/update. */
2653 struct peer_capability_info peer_info;
2654 } __attribute__((packed));
2656 static int mwl8k_cmd_update_stadb(struct ieee80211_hw *hw,
2657 struct ieee80211_vif *vif, __u32 action)
2659 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2660 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2661 struct mwl8k_cmd_update_stadb *cmd;
2662 struct peer_capability_info *peer_info;
2665 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2669 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
2670 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2672 cmd->action = cpu_to_le32(action);
2673 peer_info = &cmd->peer_info;
2674 memcpy(cmd->peer_addr, mv_vif->bssid, ETH_ALEN);
2677 case MWL8K_STA_DB_ADD_ENTRY:
2678 case MWL8K_STA_DB_MODIFY_ENTRY:
2679 /* Build peer_info block */
2680 peer_info->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT;
2681 peer_info->basic_caps = cpu_to_le16(info->assoc_capability);
2682 memcpy(peer_info->legacy_rates, mwl8k_rateids,
2683 sizeof(mwl8k_rateids));
2684 peer_info->interop = 1;
2685 peer_info->amsdu_enabled = 0;
2687 rc = mwl8k_post_cmd(hw, &cmd->header);
2689 mv_vif->peer_id = peer_info->station_id;
2693 case MWL8K_STA_DB_DEL_ENTRY:
2694 case MWL8K_STA_DB_FLUSH:
2696 rc = mwl8k_post_cmd(hw, &cmd->header);
2698 mv_vif->peer_id = 0;
2708 * Interrupt handling.
2710 static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
2712 struct ieee80211_hw *hw = dev_id;
2713 struct mwl8k_priv *priv = hw->priv;
2716 status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2717 iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2722 if (status & MWL8K_A2H_INT_TX_DONE)
2723 tasklet_schedule(&priv->tx_reclaim_task);
2725 if (status & MWL8K_A2H_INT_RX_READY) {
2726 while (rxq_process(hw, 0, 1))
2727 rxq_refill(hw, 0, 1);
2730 if (status & MWL8K_A2H_INT_OPC_DONE) {
2731 if (priv->hostcmd_wait != NULL)
2732 complete(priv->hostcmd_wait);
2735 if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
2736 if (!mutex_is_locked(&priv->fw_mutex) &&
2737 priv->radio_on && priv->pending_tx_pkts)
2738 mwl8k_tx_start(priv);
2746 * Core driver operations.
2748 static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2750 struct mwl8k_priv *priv = hw->priv;
2751 int index = skb_get_queue_mapping(skb);
2754 if (priv->current_channel == NULL) {
2755 printk(KERN_DEBUG "%s: dropped TX frame since radio "
2756 "disabled\n", wiphy_name(hw->wiphy));
2758 return NETDEV_TX_OK;
2761 rc = mwl8k_txq_xmit(hw, index, skb);
2766 static int mwl8k_start(struct ieee80211_hw *hw)
2768 struct mwl8k_priv *priv = hw->priv;
2771 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
2772 IRQF_SHARED, MWL8K_NAME, hw);
2774 printk(KERN_ERR "%s: failed to register IRQ handler\n",
2775 wiphy_name(hw->wiphy));
2779 /* Enable tx reclaim tasklet */
2780 tasklet_enable(&priv->tx_reclaim_task);
2782 /* Enable interrupts */
2783 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2785 rc = mwl8k_fw_lock(hw);
2787 rc = mwl8k_cmd_radio_enable(hw);
2791 rc = mwl8k_cmd_enable_sniffer(hw, 0);
2794 rc = mwl8k_cmd_set_pre_scan(hw);
2797 rc = mwl8k_cmd_set_post_scan(hw,
2798 "\x00\x00\x00\x00\x00\x00");
2802 rc = mwl8k_cmd_set_rateadapt_mode(hw, 0);
2805 rc = mwl8k_cmd_set_wmm_mode(hw, 0);
2807 mwl8k_fw_unlock(hw);
2811 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2812 free_irq(priv->pdev->irq, hw);
2813 tasklet_disable(&priv->tx_reclaim_task);
2819 static void mwl8k_stop(struct ieee80211_hw *hw)
2821 struct mwl8k_priv *priv = hw->priv;
2824 mwl8k_cmd_radio_disable(hw);
2826 ieee80211_stop_queues(hw);
2828 /* Disable interrupts */
2829 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2830 free_irq(priv->pdev->irq, hw);
2832 /* Stop finalize join worker */
2833 cancel_work_sync(&priv->finalize_join_worker);
2834 if (priv->beacon_skb != NULL)
2835 dev_kfree_skb(priv->beacon_skb);
2837 /* Stop tx reclaim tasklet */
2838 tasklet_disable(&priv->tx_reclaim_task);
2840 /* Return all skbs to mac80211 */
2841 for (i = 0; i < MWL8K_TX_QUEUES; i++)
2842 mwl8k_txq_reclaim(hw, i, 1);
2845 static int mwl8k_add_interface(struct ieee80211_hw *hw,
2846 struct ieee80211_if_init_conf *conf)
2848 struct mwl8k_priv *priv = hw->priv;
2849 struct mwl8k_vif *mwl8k_vif;
2852 * We only support one active interface at a time.
2854 if (priv->vif != NULL)
2858 * We only support managed interfaces for now.
2860 if (conf->type != NL80211_IFTYPE_STATION)
2864 * Reject interface creation if sniffer mode is active, as
2865 * STA operation is mutually exclusive with hardware sniffer
2868 if (priv->sniffer_enabled) {
2869 printk(KERN_INFO "%s: unable to create STA "
2870 "interface due to sniffer mode being enabled\n",
2871 wiphy_name(hw->wiphy));
2875 /* Clean out driver private area */
2876 mwl8k_vif = MWL8K_VIF(conf->vif);
2877 memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
2879 /* Set and save the mac address */
2880 mwl8k_cmd_set_mac_addr(hw, conf->mac_addr);
2881 memcpy(mwl8k_vif->mac_addr, conf->mac_addr, ETH_ALEN);
2883 /* Back pointer to parent config block */
2884 mwl8k_vif->priv = priv;
2886 /* Set Initial sequence number to zero */
2887 mwl8k_vif->seqno = 0;
2889 priv->vif = conf->vif;
2890 priv->current_channel = NULL;
2895 static void mwl8k_remove_interface(struct ieee80211_hw *hw,
2896 struct ieee80211_if_init_conf *conf)
2898 struct mwl8k_priv *priv = hw->priv;
2900 if (priv->vif == NULL)
2903 mwl8k_cmd_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
2908 static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
2910 struct ieee80211_conf *conf = &hw->conf;
2911 struct mwl8k_priv *priv = hw->priv;
2914 if (conf->flags & IEEE80211_CONF_IDLE) {
2915 mwl8k_cmd_radio_disable(hw);
2916 priv->current_channel = NULL;
2920 rc = mwl8k_fw_lock(hw);
2924 rc = mwl8k_cmd_radio_enable(hw);
2928 rc = mwl8k_cmd_set_rf_channel(hw, conf->channel);
2932 priv->current_channel = conf->channel;
2934 if (conf->power_level > 18)
2935 conf->power_level = 18;
2936 rc = mwl8k_cmd_rf_tx_power(hw, conf->power_level);
2941 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_RX, 0x7);
2943 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_TX, 0x7);
2945 rc = mwl8k_cmd_mimo_config(hw, 0x7, 0x7);
2949 mwl8k_fw_unlock(hw);
2954 static void mwl8k_bss_info_changed(struct ieee80211_hw *hw,
2955 struct ieee80211_vif *vif,
2956 struct ieee80211_bss_conf *info,
2959 struct mwl8k_priv *priv = hw->priv;
2960 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
2963 if ((changed & BSS_CHANGED_ASSOC) == 0)
2966 priv->capture_beacon = false;
2968 rc = mwl8k_fw_lock(hw);
2973 memcpy(&mwl8k_vif->bss_info, info,
2974 sizeof(struct ieee80211_bss_conf));
2976 memcpy(mwl8k_vif->bssid, info->bssid, ETH_ALEN);
2979 rc = mwl8k_cmd_set_rate(hw, vif);
2983 /* Turn on rate adaptation */
2984 rc = mwl8k_cmd_use_fixed_rate(hw, MWL8K_USE_AUTO_RATE,
2985 MWL8K_UCAST_RATE, NULL);
2989 /* Set radio preamble */
2990 rc = mwl8k_set_radio_preamble(hw, info->use_short_preamble);
2995 rc = mwl8k_cmd_set_slot(hw, info->use_short_slot);
2999 /* Update peer rate info */
3000 rc = mwl8k_cmd_update_stadb(hw, vif,
3001 MWL8K_STA_DB_MODIFY_ENTRY);
3006 rc = mwl8k_cmd_set_aid(hw, vif);
3011 * Finalize the join. Tell rx handler to process
3012 * next beacon from our BSSID.
3014 memcpy(priv->capture_bssid, mwl8k_vif->bssid, ETH_ALEN);
3015 priv->capture_beacon = true;
3017 rc = mwl8k_cmd_update_stadb(hw, vif, MWL8K_STA_DB_DEL_ENTRY);
3018 memset(&mwl8k_vif->bss_info, 0,
3019 sizeof(struct ieee80211_bss_conf));
3020 memset(mwl8k_vif->bssid, 0, ETH_ALEN);
3024 mwl8k_fw_unlock(hw);
3027 static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw,
3028 int mc_count, struct dev_addr_list *mclist)
3030 struct mwl8k_cmd_pkt *cmd;
3033 * Synthesize and return a command packet that programs the
3034 * hardware multicast address filter. At this point we don't
3035 * know whether FIF_ALLMULTI is being requested, but if it is,
3036 * we'll end up throwing this packet away and creating a new
3037 * one in mwl8k_configure_filter().
3039 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_count, mclist);
3041 return (unsigned long)cmd;
3045 mwl8k_configure_filter_sniffer(struct ieee80211_hw *hw,
3046 unsigned int changed_flags,
3047 unsigned int *total_flags)
3049 struct mwl8k_priv *priv = hw->priv;
3052 * Hardware sniffer mode is mutually exclusive with STA
3053 * operation, so refuse to enable sniffer mode if a STA
3054 * interface is active.
3056 if (priv->vif != NULL) {
3057 if (net_ratelimit())
3058 printk(KERN_INFO "%s: not enabling sniffer "
3059 "mode because STA interface is active\n",
3060 wiphy_name(hw->wiphy));
3064 if (!priv->sniffer_enabled) {
3065 if (mwl8k_cmd_enable_sniffer(hw, 1))
3067 priv->sniffer_enabled = true;
3070 *total_flags &= FIF_PROMISC_IN_BSS | FIF_ALLMULTI |
3071 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL |
3077 static void mwl8k_configure_filter(struct ieee80211_hw *hw,
3078 unsigned int changed_flags,
3079 unsigned int *total_flags,
3082 struct mwl8k_priv *priv = hw->priv;
3083 struct mwl8k_cmd_pkt *cmd = (void *)(unsigned long)multicast;
3086 * AP firmware doesn't allow fine-grained control over
3087 * the receive filter.
3090 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
3096 * Enable hardware sniffer mode if FIF_CONTROL or
3097 * FIF_OTHER_BSS is requested.
3099 if (*total_flags & (FIF_CONTROL | FIF_OTHER_BSS) &&
3100 mwl8k_configure_filter_sniffer(hw, changed_flags, total_flags)) {
3105 /* Clear unsupported feature flags */
3106 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
3108 if (mwl8k_fw_lock(hw))
3111 if (priv->sniffer_enabled) {
3112 mwl8k_cmd_enable_sniffer(hw, 0);
3113 priv->sniffer_enabled = false;
3116 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
3117 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
3119 * Disable the BSS filter.
3121 mwl8k_cmd_set_pre_scan(hw);
3126 * Enable the BSS filter.
3128 * If there is an active STA interface, use that
3129 * interface's BSSID, otherwise use a dummy one
3130 * (where the OUI part needs to be nonzero for
3131 * the BSSID to be accepted by POST_SCAN).
3133 bssid = "\x01\x00\x00\x00\x00\x00";
3134 if (priv->vif != NULL)
3135 bssid = MWL8K_VIF(priv->vif)->bssid;
3137 mwl8k_cmd_set_post_scan(hw, bssid);
3142 * If FIF_ALLMULTI is being requested, throw away the command
3143 * packet that ->prepare_multicast() built and replace it with
3144 * a command packet that enables reception of all multicast
3147 if (*total_flags & FIF_ALLMULTI) {
3149 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, 0, NULL);
3153 mwl8k_post_cmd(hw, cmd);
3157 mwl8k_fw_unlock(hw);
3160 static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
3162 return mwl8k_cmd_set_rts_threshold(hw, MWL8K_CMD_SET, value);
3165 static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue,
3166 const struct ieee80211_tx_queue_params *params)
3168 struct mwl8k_priv *priv = hw->priv;
3171 rc = mwl8k_fw_lock(hw);
3173 if (!priv->wmm_enabled)
3174 rc = mwl8k_cmd_set_wmm_mode(hw, 1);
3177 rc = mwl8k_cmd_set_edca_params(hw, queue,
3183 mwl8k_fw_unlock(hw);
3189 static int mwl8k_get_tx_stats(struct ieee80211_hw *hw,
3190 struct ieee80211_tx_queue_stats *stats)
3192 struct mwl8k_priv *priv = hw->priv;
3193 struct mwl8k_tx_queue *txq;
3196 spin_lock_bh(&priv->tx_lock);
3197 for (index = 0; index < MWL8K_TX_QUEUES; index++) {
3198 txq = priv->txq + index;
3199 memcpy(&stats[index], &txq->stats,
3200 sizeof(struct ieee80211_tx_queue_stats));
3202 spin_unlock_bh(&priv->tx_lock);
3207 static int mwl8k_get_stats(struct ieee80211_hw *hw,
3208 struct ieee80211_low_level_stats *stats)
3210 return mwl8k_cmd_get_stat(hw, stats);
3213 static const struct ieee80211_ops mwl8k_ops = {
3215 .start = mwl8k_start,
3217 .add_interface = mwl8k_add_interface,
3218 .remove_interface = mwl8k_remove_interface,
3219 .config = mwl8k_config,
3220 .bss_info_changed = mwl8k_bss_info_changed,
3221 .prepare_multicast = mwl8k_prepare_multicast,
3222 .configure_filter = mwl8k_configure_filter,
3223 .set_rts_threshold = mwl8k_set_rts_threshold,
3224 .conf_tx = mwl8k_conf_tx,
3225 .get_tx_stats = mwl8k_get_tx_stats,
3226 .get_stats = mwl8k_get_stats,
3229 static void mwl8k_tx_reclaim_handler(unsigned long data)
3232 struct ieee80211_hw *hw = (struct ieee80211_hw *) data;
3233 struct mwl8k_priv *priv = hw->priv;
3235 spin_lock_bh(&priv->tx_lock);
3236 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3237 mwl8k_txq_reclaim(hw, i, 0);
3239 if (priv->tx_wait != NULL && !priv->pending_tx_pkts) {
3240 complete(priv->tx_wait);
3241 priv->tx_wait = NULL;
3243 spin_unlock_bh(&priv->tx_lock);
3246 static void mwl8k_finalize_join_worker(struct work_struct *work)
3248 struct mwl8k_priv *priv =
3249 container_of(work, struct mwl8k_priv, finalize_join_worker);
3250 struct sk_buff *skb = priv->beacon_skb;
3251 u8 dtim = MWL8K_VIF(priv->vif)->bss_info.dtim_period;
3253 mwl8k_cmd_finalize_join(priv->hw, skb->data, skb->len, dtim);
3256 priv->beacon_skb = NULL;
3264 static struct mwl8k_device_info mwl8k_info_tbl[] __devinitdata = {
3266 .part_name = "88w8687",
3267 .helper_image = "mwl8k/helper_8687.fw",
3268 .fw_image = "mwl8k/fmimage_8687.fw",
3269 .rxd_ops = &rxd_8687_ops,
3270 .modes = BIT(NL80211_IFTYPE_STATION),
3273 .part_name = "88w8366",
3274 .helper_image = "mwl8k/helper_8366.fw",
3275 .fw_image = "mwl8k/fmimage_8366.fw",
3276 .rxd_ops = &rxd_8366_ops,
3281 static DEFINE_PCI_DEVICE_TABLE(mwl8k_pci_id_table) = {
3282 { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = MWL8687, },
3283 { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = MWL8687, },
3284 { PCI_VDEVICE(MARVELL, 0x2a40), .driver_data = MWL8366, },
3287 MODULE_DEVICE_TABLE(pci, mwl8k_pci_id_table);
3289 static int __devinit mwl8k_probe(struct pci_dev *pdev,
3290 const struct pci_device_id *id)
3292 static int printed_version = 0;
3293 struct ieee80211_hw *hw;
3294 struct mwl8k_priv *priv;
3298 if (!printed_version) {
3299 printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION);
3300 printed_version = 1;
3303 rc = pci_enable_device(pdev);
3305 printk(KERN_ERR "%s: Cannot enable new PCI device\n",
3310 rc = pci_request_regions(pdev, MWL8K_NAME);
3312 printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
3314 goto err_disable_device;
3317 pci_set_master(pdev);
3319 hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
3321 printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
3329 priv->device_info = &mwl8k_info_tbl[id->driver_data];
3330 priv->rxd_ops = priv->device_info->rxd_ops;
3331 priv->sniffer_enabled = false;
3332 priv->wmm_enabled = false;
3333 priv->pending_tx_pkts = 0;
3335 SET_IEEE80211_DEV(hw, &pdev->dev);
3336 pci_set_drvdata(pdev, hw);
3338 priv->sram = pci_iomap(pdev, 0, 0x10000);
3339 if (priv->sram == NULL) {
3340 printk(KERN_ERR "%s: Cannot map device SRAM\n",
3341 wiphy_name(hw->wiphy));
3346 * If BAR0 is a 32 bit BAR, the register BAR will be BAR1.
3347 * If BAR0 is a 64 bit BAR, the register BAR will be BAR2.
3349 priv->regs = pci_iomap(pdev, 1, 0x10000);
3350 if (priv->regs == NULL) {
3351 priv->regs = pci_iomap(pdev, 2, 0x10000);
3352 if (priv->regs == NULL) {
3353 printk(KERN_ERR "%s: Cannot map device registers\n",
3354 wiphy_name(hw->wiphy));
3359 memcpy(priv->channels, mwl8k_channels, sizeof(mwl8k_channels));
3360 priv->band.band = IEEE80211_BAND_2GHZ;
3361 priv->band.channels = priv->channels;
3362 priv->band.n_channels = ARRAY_SIZE(mwl8k_channels);
3363 priv->band.bitrates = priv->rates;
3364 priv->band.n_bitrates = ARRAY_SIZE(mwl8k_rates);
3365 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
3367 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(mwl8k_rates));
3368 memcpy(priv->rates, mwl8k_rates, sizeof(mwl8k_rates));
3371 * Extra headroom is the size of the required DMA header
3372 * minus the size of the smallest 802.11 frame (CTS frame).
3374 hw->extra_tx_headroom =
3375 sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
3377 hw->channel_change_time = 10;
3379 hw->queues = MWL8K_TX_QUEUES;
3381 hw->wiphy->interface_modes = priv->device_info->modes;
3383 /* Set rssi and noise values to dBm */
3384 hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_NOISE_DBM;
3385 hw->vif_data_size = sizeof(struct mwl8k_vif);
3388 /* Set default radio state and preamble */
3390 priv->radio_short_preamble = 0;
3392 /* Finalize join worker */
3393 INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
3395 /* TX reclaim tasklet */
3396 tasklet_init(&priv->tx_reclaim_task,
3397 mwl8k_tx_reclaim_handler, (unsigned long)hw);
3398 tasklet_disable(&priv->tx_reclaim_task);
3400 /* Power management cookie */
3401 priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
3402 if (priv->cookie == NULL)
3405 rc = mwl8k_rxq_init(hw, 0);
3408 rxq_refill(hw, 0, INT_MAX);
3410 mutex_init(&priv->fw_mutex);
3411 priv->fw_mutex_owner = NULL;
3412 priv->fw_mutex_depth = 0;
3413 priv->hostcmd_wait = NULL;
3415 spin_lock_init(&priv->tx_lock);
3417 priv->tx_wait = NULL;
3419 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
3420 rc = mwl8k_txq_init(hw, i);
3422 goto err_free_queues;
3425 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
3426 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3427 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
3428 iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
3430 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
3431 IRQF_SHARED, MWL8K_NAME, hw);
3433 printk(KERN_ERR "%s: failed to register IRQ handler\n",
3434 wiphy_name(hw->wiphy));
3435 goto err_free_queues;
3438 /* Reset firmware and hardware */
3439 mwl8k_hw_reset(priv);
3441 /* Ask userland hotplug daemon for the device firmware */
3442 rc = mwl8k_request_firmware(priv);
3444 printk(KERN_ERR "%s: Firmware files not found\n",
3445 wiphy_name(hw->wiphy));
3449 /* Load firmware into hardware */
3450 rc = mwl8k_load_firmware(hw);
3452 printk(KERN_ERR "%s: Cannot start firmware\n",
3453 wiphy_name(hw->wiphy));
3454 goto err_stop_firmware;
3457 /* Reclaim memory once firmware is successfully loaded */
3458 mwl8k_release_firmware(priv);
3461 * Temporarily enable interrupts. Initial firmware host
3462 * commands use interrupts and avoids polling. Disable
3463 * interrupts when done.
3465 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3467 /* Get config data, mac addrs etc */
3469 rc = mwl8k_cmd_get_hw_spec_ap(hw);
3471 rc = mwl8k_cmd_set_hw_spec(hw);
3473 rc = mwl8k_cmd_get_hw_spec_sta(hw);
3476 printk(KERN_ERR "%s: Cannot initialise firmware\n",
3477 wiphy_name(hw->wiphy));
3478 goto err_stop_firmware;
3481 /* Turn radio off */
3482 rc = mwl8k_cmd_radio_disable(hw);
3484 printk(KERN_ERR "%s: Cannot disable\n", wiphy_name(hw->wiphy));
3485 goto err_stop_firmware;
3488 /* Clear MAC address */
3489 rc = mwl8k_cmd_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
3491 printk(KERN_ERR "%s: Cannot clear MAC address\n",
3492 wiphy_name(hw->wiphy));
3493 goto err_stop_firmware;
3496 /* Disable interrupts */
3497 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3498 free_irq(priv->pdev->irq, hw);
3500 rc = ieee80211_register_hw(hw);
3502 printk(KERN_ERR "%s: Cannot register device\n",
3503 wiphy_name(hw->wiphy));
3504 goto err_stop_firmware;
3507 printk(KERN_INFO "%s: %s v%d, %pM, %s firmware %u.%u.%u.%u\n",
3508 wiphy_name(hw->wiphy), priv->device_info->part_name,
3509 priv->hw_rev, hw->wiphy->perm_addr,
3510 priv->ap_fw ? "AP" : "STA",
3511 (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff,
3512 (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff);
3517 mwl8k_hw_reset(priv);
3518 mwl8k_release_firmware(priv);
3521 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3522 free_irq(priv->pdev->irq, hw);
3525 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3526 mwl8k_txq_deinit(hw, i);
3527 mwl8k_rxq_deinit(hw, 0);
3530 if (priv->cookie != NULL)
3531 pci_free_consistent(priv->pdev, 4,
3532 priv->cookie, priv->cookie_dma);
3534 if (priv->regs != NULL)
3535 pci_iounmap(pdev, priv->regs);
3537 if (priv->sram != NULL)
3538 pci_iounmap(pdev, priv->sram);
3540 pci_set_drvdata(pdev, NULL);
3541 ieee80211_free_hw(hw);
3544 pci_release_regions(pdev);
3547 pci_disable_device(pdev);
3552 static void __devexit mwl8k_shutdown(struct pci_dev *pdev)
3554 printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__);
3557 static void __devexit mwl8k_remove(struct pci_dev *pdev)
3559 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
3560 struct mwl8k_priv *priv;
3567 ieee80211_stop_queues(hw);
3569 ieee80211_unregister_hw(hw);
3571 /* Remove tx reclaim tasklet */
3572 tasklet_kill(&priv->tx_reclaim_task);
3575 mwl8k_hw_reset(priv);
3577 /* Return all skbs to mac80211 */
3578 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3579 mwl8k_txq_reclaim(hw, i, 1);
3581 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3582 mwl8k_txq_deinit(hw, i);
3584 mwl8k_rxq_deinit(hw, 0);
3586 pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma);
3588 pci_iounmap(pdev, priv->regs);
3589 pci_iounmap(pdev, priv->sram);
3590 pci_set_drvdata(pdev, NULL);
3591 ieee80211_free_hw(hw);
3592 pci_release_regions(pdev);
3593 pci_disable_device(pdev);
3596 static struct pci_driver mwl8k_driver = {
3598 .id_table = mwl8k_pci_id_table,
3599 .probe = mwl8k_probe,
3600 .remove = __devexit_p(mwl8k_remove),
3601 .shutdown = __devexit_p(mwl8k_shutdown),
3604 static int __init mwl8k_init(void)
3606 return pci_register_driver(&mwl8k_driver);
3609 static void __exit mwl8k_exit(void)
3611 pci_unregister_driver(&mwl8k_driver);
3614 module_init(mwl8k_init);
3615 module_exit(mwl8k_exit);
3617 MODULE_DESCRIPTION(MWL8K_DESC);
3618 MODULE_VERSION(MWL8K_VERSION);
3619 MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
3620 MODULE_LICENSE("GPL");