1 /******************************************************************************
3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
30 #include <linux/etherdevice.h>
31 #include <linux/sched.h>
32 #include <net/mac80211.h>
33 #include "iwl-eeprom.h"
38 #include "iwl-helpers.h"
40 static const u16 default_tid_to_tx_fifo[] = {
60 static inline int iwl_alloc_dma_ptr(struct iwl_priv *priv,
61 struct iwl_dma_ptr *ptr, size_t size)
63 ptr->addr = pci_alloc_consistent(priv->pci_dev, size, &ptr->dma);
70 static inline void iwl_free_dma_ptr(struct iwl_priv *priv,
71 struct iwl_dma_ptr *ptr)
73 if (unlikely(!ptr->addr))
76 pci_free_consistent(priv->pci_dev, ptr->size, ptr->addr, ptr->dma);
77 memset(ptr, 0, sizeof(*ptr));
81 * iwl_txq_update_write_ptr - Send new write index to hardware
83 void iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq)
86 int txq_id = txq->q.id;
88 if (txq->need_update == 0)
91 /* if we're trying to save power */
92 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
93 /* wake up nic if it's powered down ...
94 * uCode will wake up, and interrupt us again, so next
95 * time we'll skip this part. */
96 reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
98 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
99 IWL_DEBUG_INFO(priv, "Tx queue %d requesting wakeup, GP1 = 0x%x\n",
101 iwl_set_bit(priv, CSR_GP_CNTRL,
102 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
106 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
107 txq->q.write_ptr | (txq_id << 8));
109 /* else not in power-save mode, uCode will never sleep when we're
110 * trying to tx (during RFKILL, we're not trying to tx). */
112 iwl_write32(priv, HBUS_TARG_WRPTR,
113 txq->q.write_ptr | (txq_id << 8));
115 txq->need_update = 0;
117 EXPORT_SYMBOL(iwl_txq_update_write_ptr);
121 * iwl_tx_queue_free - Deallocate DMA queue.
122 * @txq: Transmit queue to deallocate.
124 * Empty queue by removing and destroying all BD's.
126 * 0-fill, but do not free "txq" descriptor structure.
128 void iwl_tx_queue_free(struct iwl_priv *priv, int txq_id)
130 struct iwl_tx_queue *txq = &priv->txq[txq_id];
131 struct iwl_queue *q = &txq->q;
132 struct pci_dev *dev = priv->pci_dev;
138 /* first, empty all BD's */
139 for (; q->write_ptr != q->read_ptr;
140 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
141 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
143 /* De-alloc array of command/tx buffers */
144 for (i = 0; i < TFD_TX_CMD_SLOTS; i++)
147 /* De-alloc circular buffer of TFDs */
149 pci_free_consistent(dev, priv->hw_params.tfd_size *
150 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
152 /* De-alloc array of per-TFD driver data */
156 /* deallocate arrays */
162 /* 0-fill queue descriptor structure */
163 memset(txq, 0, sizeof(*txq));
165 EXPORT_SYMBOL(iwl_tx_queue_free);
168 * iwl_cmd_queue_free - Deallocate DMA queue.
169 * @txq: Transmit queue to deallocate.
171 * Empty queue by removing and destroying all BD's.
173 * 0-fill, but do not free "txq" descriptor structure.
175 void iwl_cmd_queue_free(struct iwl_priv *priv)
177 struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
178 struct iwl_queue *q = &txq->q;
179 struct pci_dev *dev = priv->pci_dev;
185 /* De-alloc array of command/tx buffers */
186 for (i = 0; i <= TFD_CMD_SLOTS; i++)
189 /* De-alloc circular buffer of TFDs */
191 pci_free_consistent(dev, priv->hw_params.tfd_size *
192 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
194 /* deallocate arrays */
200 /* 0-fill queue descriptor structure */
201 memset(txq, 0, sizeof(*txq));
203 EXPORT_SYMBOL(iwl_cmd_queue_free);
205 /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
208 * Theory of operation
210 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
211 * of buffer descriptors, each of which points to one or more data buffers for
212 * the device to read from or fill. Driver and device exchange status of each
213 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
214 * entries in each circular buffer, to protect against confusing empty and full
217 * The device reads or writes the data in the queues via the device's several
218 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
220 * For Tx queue, there are low mark and high mark limits. If, after queuing
221 * the packet for Tx, free space become < low mark, Tx queue stopped. When
222 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
225 * See more detailed info in iwl-4965-hw.h.
226 ***************************************************/
228 int iwl_queue_space(const struct iwl_queue *q)
230 int s = q->read_ptr - q->write_ptr;
232 if (q->read_ptr > q->write_ptr)
237 /* keep some reserve to not confuse empty and full situations */
243 EXPORT_SYMBOL(iwl_queue_space);
247 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
249 static int iwl_queue_init(struct iwl_priv *priv, struct iwl_queue *q,
250 int count, int slots_num, u32 id)
253 q->n_window = slots_num;
256 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
257 * and iwl_queue_dec_wrap are broken. */
258 BUG_ON(!is_power_of_2(count));
260 /* slots_num must be power-of-two size, otherwise
261 * get_cmd_index is broken. */
262 BUG_ON(!is_power_of_2(slots_num));
264 q->low_mark = q->n_window / 4;
268 q->high_mark = q->n_window / 8;
269 if (q->high_mark < 2)
272 q->write_ptr = q->read_ptr = 0;
278 * iwl_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
280 static int iwl_tx_queue_alloc(struct iwl_priv *priv,
281 struct iwl_tx_queue *txq, u32 id)
283 struct pci_dev *dev = priv->pci_dev;
284 size_t tfd_sz = priv->hw_params.tfd_size * TFD_QUEUE_SIZE_MAX;
286 /* Driver private data, only for Tx (not command) queues,
287 * not shared with device. */
288 if (id != IWL_CMD_QUEUE_NUM) {
289 txq->txb = kmalloc(sizeof(txq->txb[0]) *
290 TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
292 IWL_ERR(priv, "kmalloc for auxiliary BD "
293 "structures failed\n");
300 /* Circular buffer of transmit frame descriptors (TFDs),
301 * shared with device */
302 txq->tfds = pci_alloc_consistent(dev, tfd_sz, &txq->q.dma_addr);
305 IWL_ERR(priv, "pci_alloc_consistent(%zd) failed\n", tfd_sz);
320 * iwl_tx_queue_init - Allocate and initialize one tx/cmd queue
322 int iwl_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq,
323 int slots_num, u32 txq_id)
327 int actual_slots = slots_num;
330 * Alloc buffer array for commands (Tx or other types of commands).
331 * For the command queue (#4), allocate command space + one big
332 * command for scan, since scan command is very huge; the system will
333 * not have two scans at the same time, so only one is needed.
334 * For normal Tx queues (all other queues), no super-size command
337 if (txq_id == IWL_CMD_QUEUE_NUM)
340 txq->meta = kzalloc(sizeof(struct iwl_cmd_meta) * actual_slots,
342 txq->cmd = kzalloc(sizeof(struct iwl_device_cmd *) * actual_slots,
345 if (!txq->meta || !txq->cmd)
346 goto out_free_arrays;
348 len = sizeof(struct iwl_device_cmd);
349 for (i = 0; i < actual_slots; i++) {
350 /* only happens for cmd queue */
352 len += IWL_MAX_SCAN_SIZE;
354 txq->cmd[i] = kmalloc(len, GFP_KERNEL);
359 /* Alloc driver data array and TFD circular buffer */
360 ret = iwl_tx_queue_alloc(priv, txq, txq_id);
364 txq->need_update = 0;
367 * Aggregation TX queues will get their ID when aggregation begins;
368 * they overwrite the setting done here. The command FIFO doesn't
369 * need an swq_id so don't set one to catch errors, all others can
370 * be set up to the identity mapping.
372 if (txq_id != IWL_CMD_QUEUE_NUM)
373 txq->swq_id = txq_id;
375 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
376 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
377 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
379 /* Initialize queue's high/low-water marks, and head/tail indexes */
380 iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
382 /* Tell device where to find queue */
383 priv->cfg->ops->lib->txq_init(priv, txq);
387 for (i = 0; i < actual_slots; i++)
395 EXPORT_SYMBOL(iwl_tx_queue_init);
398 * iwl_hw_txq_ctx_free - Free TXQ Context
400 * Destroy all TX DMA queues and structures
402 void iwl_hw_txq_ctx_free(struct iwl_priv *priv)
408 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num;
410 if (txq_id == IWL_CMD_QUEUE_NUM)
411 iwl_cmd_queue_free(priv);
413 iwl_tx_queue_free(priv, txq_id);
415 iwl_free_dma_ptr(priv, &priv->kw);
417 iwl_free_dma_ptr(priv, &priv->scd_bc_tbls);
419 /* free tx queue structure */
420 iwl_free_txq_mem(priv);
422 EXPORT_SYMBOL(iwl_hw_txq_ctx_free);
425 * iwl_txq_ctx_reset - Reset TX queue context
426 * Destroys all DMA structures and initialize them again
431 int iwl_txq_ctx_reset(struct iwl_priv *priv)
434 int txq_id, slots_num;
437 /* Free all tx/cmd queues and keep-warm buffer */
438 iwl_hw_txq_ctx_free(priv);
440 ret = iwl_alloc_dma_ptr(priv, &priv->scd_bc_tbls,
441 priv->hw_params.scd_bc_tbls_size);
443 IWL_ERR(priv, "Scheduler BC Table allocation failed\n");
446 /* Alloc keep-warm buffer */
447 ret = iwl_alloc_dma_ptr(priv, &priv->kw, IWL_KW_SIZE);
449 IWL_ERR(priv, "Keep Warm allocation failed\n");
453 /* allocate tx queue structure */
454 ret = iwl_alloc_txq_mem(priv);
458 spin_lock_irqsave(&priv->lock, flags);
460 /* Turn off all Tx DMA fifos */
461 priv->cfg->ops->lib->txq_set_sched(priv, 0);
463 /* Tell NIC where to find the "keep warm" buffer */
464 iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG, priv->kw.dma >> 4);
466 spin_unlock_irqrestore(&priv->lock, flags);
468 /* Alloc and init all Tx queues, including the command queue (#4) */
469 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
470 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
471 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
472 ret = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
475 IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
483 iwl_hw_txq_ctx_free(priv);
484 iwl_free_dma_ptr(priv, &priv->kw);
486 iwl_free_dma_ptr(priv, &priv->scd_bc_tbls);
492 * iwl_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory
494 void iwl_txq_ctx_stop(struct iwl_priv *priv)
499 /* Turn off all Tx DMA fifos */
500 spin_lock_irqsave(&priv->lock, flags);
502 priv->cfg->ops->lib->txq_set_sched(priv, 0);
504 /* Stop each Tx DMA channel, and wait for it to be idle */
505 for (ch = 0; ch < priv->hw_params.dma_chnl_num; ch++) {
506 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
507 iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS_REG,
508 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
511 spin_unlock_irqrestore(&priv->lock, flags);
513 /* Deallocate memory for all Tx queues */
514 iwl_hw_txq_ctx_free(priv);
516 EXPORT_SYMBOL(iwl_txq_ctx_stop);
519 * handle build REPLY_TX command notification.
521 static void iwl_tx_cmd_build_basic(struct iwl_priv *priv,
522 struct iwl_tx_cmd *tx_cmd,
523 struct ieee80211_tx_info *info,
524 struct ieee80211_hdr *hdr,
527 __le16 fc = hdr->frame_control;
528 __le32 tx_flags = tx_cmd->tx_flags;
530 tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
531 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
532 tx_flags |= TX_CMD_FLG_ACK_MSK;
533 if (ieee80211_is_mgmt(fc))
534 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
535 if (ieee80211_is_probe_resp(fc) &&
536 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
537 tx_flags |= TX_CMD_FLG_TSF_MSK;
539 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
540 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
543 if (ieee80211_is_back_req(fc))
544 tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK;
547 tx_cmd->sta_id = std_id;
548 if (ieee80211_has_morefrags(fc))
549 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
551 if (ieee80211_is_data_qos(fc)) {
552 u8 *qc = ieee80211_get_qos_ctl(hdr);
553 tx_cmd->tid_tspec = qc[0] & 0xf;
554 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
556 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
559 priv->cfg->ops->utils->rts_tx_cmd_flag(info, &tx_flags);
561 if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
562 tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
564 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
565 if (ieee80211_is_mgmt(fc)) {
566 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
567 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
569 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
571 tx_cmd->timeout.pm_frame_timeout = 0;
574 tx_cmd->driver_txop = 0;
575 tx_cmd->tx_flags = tx_flags;
576 tx_cmd->next_frame_len = 0;
579 #define RTS_HCCA_RETRY_LIMIT 3
580 #define RTS_DFAULT_RETRY_LIMIT 60
582 static void iwl_tx_cmd_build_rate(struct iwl_priv *priv,
583 struct iwl_tx_cmd *tx_cmd,
584 struct ieee80211_tx_info *info,
585 __le16 fc, int is_hcca)
593 /* Set retry limit on DATA packets and Probe Responses*/
594 if (ieee80211_is_probe_resp(fc))
595 data_retry_limit = 3;
597 data_retry_limit = IWL_DEFAULT_TX_RETRY;
598 tx_cmd->data_retry_limit = data_retry_limit;
600 /* Set retry limit on RTS packets */
601 rts_retry_limit = (is_hcca) ? RTS_HCCA_RETRY_LIMIT :
602 RTS_DFAULT_RETRY_LIMIT;
603 if (data_retry_limit < rts_retry_limit)
604 rts_retry_limit = data_retry_limit;
605 tx_cmd->rts_retry_limit = rts_retry_limit;
607 /* DATA packets will use the uCode station table for rate/antenna
609 if (ieee80211_is_data(fc)) {
610 tx_cmd->initial_rate_index = 0;
611 tx_cmd->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
616 * If the current TX rate stored in mac80211 has the MCS bit set, it's
617 * not really a TX rate. Thus, we use the lowest supported rate for
618 * this band. Also use the lowest supported rate if the stored rate
621 rate_idx = info->control.rates[0].idx;
622 if (info->control.rates[0].flags & IEEE80211_TX_RC_MCS ||
623 (rate_idx < 0) || (rate_idx > IWL_RATE_COUNT_LEGACY))
624 rate_idx = rate_lowest_index(&priv->bands[info->band],
626 /* For 5 GHZ band, remap mac80211 rate indices into driver indices */
627 if (info->band == IEEE80211_BAND_5GHZ)
628 rate_idx += IWL_FIRST_OFDM_RATE;
629 /* Get PLCP rate for tx_cmd->rate_n_flags */
630 rate_plcp = iwl_rates[rate_idx].plcp;
631 /* Zero out flags for this packet */
634 /* Set CCK flag as needed */
635 if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE))
636 rate_flags |= RATE_MCS_CCK_MSK;
638 /* Set up RTS and CTS flags for certain packets */
639 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
640 case cpu_to_le16(IEEE80211_STYPE_AUTH):
641 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
642 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
643 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
644 if (tx_cmd->tx_flags & TX_CMD_FLG_RTS_MSK) {
645 tx_cmd->tx_flags &= ~TX_CMD_FLG_RTS_MSK;
646 tx_cmd->tx_flags |= TX_CMD_FLG_CTS_MSK;
653 /* Set up antennas */
654 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant);
655 rate_flags |= iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
657 /* Set the rate in the TX cmd */
658 tx_cmd->rate_n_flags = iwl_hw_set_rate_n_flags(rate_plcp, rate_flags);
661 static void iwl_tx_cmd_build_hwcrypto(struct iwl_priv *priv,
662 struct ieee80211_tx_info *info,
663 struct iwl_tx_cmd *tx_cmd,
664 struct sk_buff *skb_frag,
667 struct ieee80211_key_conf *keyconf = info->control.hw_key;
669 switch (keyconf->alg) {
671 tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
672 memcpy(tx_cmd->key, keyconf->key, keyconf->keylen);
673 if (info->flags & IEEE80211_TX_CTL_AMPDU)
674 tx_cmd->tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK;
675 IWL_DEBUG_TX(priv, "tx_cmd with AES hwcrypto\n");
679 tx_cmd->sec_ctl = TX_CMD_SEC_TKIP;
680 ieee80211_get_tkip_key(keyconf, skb_frag,
681 IEEE80211_TKIP_P2_KEY, tx_cmd->key);
682 IWL_DEBUG_TX(priv, "tx_cmd with tkip hwcrypto\n");
686 tx_cmd->sec_ctl |= (TX_CMD_SEC_WEP |
687 (keyconf->keyidx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT);
689 if (keyconf->keylen == WEP_KEY_LEN_128)
690 tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
692 memcpy(&tx_cmd->key[3], keyconf->key, keyconf->keylen);
694 IWL_DEBUG_TX(priv, "Configuring packet for WEP encryption "
695 "with key %d\n", keyconf->keyidx);
699 IWL_ERR(priv, "Unknown encode alg %d\n", keyconf->alg);
705 * start REPLY_TX command process
707 int iwl_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
709 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
710 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
711 struct ieee80211_sta *sta = info->control.sta;
712 struct iwl_station_priv *sta_priv = NULL;
713 struct iwl_tx_queue *txq;
715 struct iwl_device_cmd *out_cmd;
716 struct iwl_cmd_meta *out_meta;
717 struct iwl_tx_cmd *tx_cmd;
719 dma_addr_t phys_addr;
720 dma_addr_t txcmd_phys;
721 dma_addr_t scratch_phys;
722 u16 len, len_org, firstlen, secondlen;
727 u8 wait_write_ptr = 0;
732 spin_lock_irqsave(&priv->lock, flags);
733 if (iwl_is_rfkill(priv)) {
734 IWL_DEBUG_DROP(priv, "Dropping - RF KILL\n");
738 fc = hdr->frame_control;
740 #ifdef CONFIG_IWLWIFI_DEBUG
741 if (ieee80211_is_auth(fc))
742 IWL_DEBUG_TX(priv, "Sending AUTH frame\n");
743 else if (ieee80211_is_assoc_req(fc))
744 IWL_DEBUG_TX(priv, "Sending ASSOC frame\n");
745 else if (ieee80211_is_reassoc_req(fc))
746 IWL_DEBUG_TX(priv, "Sending REASSOC frame\n");
749 /* drop all non-injected data frame if we are not associated */
750 if (ieee80211_is_data(fc) &&
751 !(info->flags & IEEE80211_TX_CTL_INJECTED) &&
752 (!iwl_is_associated(priv) ||
753 ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id) ||
754 !priv->assoc_station_added)) {
755 IWL_DEBUG_DROP(priv, "Dropping - !iwl_is_associated\n");
759 hdr_len = ieee80211_hdrlen(fc);
761 /* Find (or create) index into station table for destination station */
762 if (info->flags & IEEE80211_TX_CTL_INJECTED)
763 sta_id = priv->hw_params.bcast_sta_id;
765 sta_id = iwl_get_sta_id(priv, hdr);
766 if (sta_id == IWL_INVALID_STATION) {
767 IWL_DEBUG_DROP(priv, "Dropping - INVALID STATION: %pM\n",
772 IWL_DEBUG_TX(priv, "station Id %d\n", sta_id);
775 sta_priv = (void *)sta->drv_priv;
777 if (sta_priv && sta_id != priv->hw_params.bcast_sta_id &&
779 WARN_ON(!(info->flags & IEEE80211_TX_CTL_PSPOLL_RESPONSE));
781 * This sends an asynchronous command to the device,
782 * but we can rely on it being processed before the
783 * next frame is processed -- and the next frame to
784 * this station is the one that will consume this
786 * For now set the counter to just 1 since we do not
789 iwl_sta_modify_sleep_tx_count(priv, sta_id, 1);
792 txq_id = skb_get_queue_mapping(skb);
793 if (ieee80211_is_data_qos(fc)) {
794 qc = ieee80211_get_qos_ctl(hdr);
795 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
796 if (unlikely(tid >= MAX_TID_COUNT))
798 seq_number = priv->stations[sta_id].tid[tid].seq_number;
799 seq_number &= IEEE80211_SCTL_SEQ;
800 hdr->seq_ctrl = hdr->seq_ctrl &
801 cpu_to_le16(IEEE80211_SCTL_FRAG);
802 hdr->seq_ctrl |= cpu_to_le16(seq_number);
804 /* aggregation is on for this <sta,tid> */
805 if (info->flags & IEEE80211_TX_CTL_AMPDU &&
806 priv->stations[sta_id].tid[tid].agg.state == IWL_AGG_ON) {
807 txq_id = priv->stations[sta_id].tid[tid].agg.txq_id;
811 txq = &priv->txq[txq_id];
812 swq_id = txq->swq_id;
815 if (unlikely(iwl_queue_space(q) < q->high_mark))
818 if (ieee80211_is_data_qos(fc))
819 priv->stations[sta_id].tid[tid].tfds_in_queue++;
821 /* Set up driver data for this TFD */
822 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
823 txq->txb[q->write_ptr].skb[0] = skb;
825 /* Set up first empty entry in queue's array of Tx/cmd buffers */
826 out_cmd = txq->cmd[q->write_ptr];
827 out_meta = &txq->meta[q->write_ptr];
828 tx_cmd = &out_cmd->cmd.tx;
829 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
830 memset(tx_cmd, 0, sizeof(struct iwl_tx_cmd));
833 * Set up the Tx-command (not MAC!) header.
834 * Store the chosen Tx queue and TFD index within the sequence field;
835 * after Tx, uCode's Tx response will return this value so driver can
836 * locate the frame within the tx queue and do post-tx processing.
838 out_cmd->hdr.cmd = REPLY_TX;
839 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
840 INDEX_TO_SEQ(q->write_ptr)));
842 /* Copy MAC header from skb into command buffer */
843 memcpy(tx_cmd->hdr, hdr, hdr_len);
846 /* Total # bytes to be transmitted */
848 tx_cmd->len = cpu_to_le16(len);
850 if (info->control.hw_key)
851 iwl_tx_cmd_build_hwcrypto(priv, info, tx_cmd, skb, sta_id);
853 /* TODO need this for burst mode later on */
854 iwl_tx_cmd_build_basic(priv, tx_cmd, info, hdr, sta_id);
855 iwl_dbg_log_tx_data_frame(priv, len, hdr);
857 /* set is_hcca to 0; it probably will never be implemented */
858 iwl_tx_cmd_build_rate(priv, tx_cmd, info, fc, 0);
860 iwl_update_stats(priv, true, fc, len);
862 * Use the first empty entry in this queue's command buffer array
863 * to contain the Tx command and MAC header concatenated together
864 * (payload data will be in another buffer).
865 * Size of this varies, due to varying MAC header length.
866 * If end is not dword aligned, we'll have 2 extra bytes at the end
867 * of the MAC header (device reads on dword boundaries).
868 * We'll tell device about this padding later.
870 len = sizeof(struct iwl_tx_cmd) +
871 sizeof(struct iwl_cmd_header) + hdr_len;
874 firstlen = len = (len + 3) & ~3;
881 /* Tell NIC about any 2-byte padding after MAC header */
883 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
885 /* Physical address of this Tx command's header (not MAC header!),
886 * within command buffer array. */
887 txcmd_phys = pci_map_single(priv->pci_dev,
889 PCI_DMA_BIDIRECTIONAL);
890 pci_unmap_addr_set(out_meta, mapping, txcmd_phys);
891 pci_unmap_len_set(out_meta, len, len);
892 /* Add buffer containing Tx command and MAC(!) header to TFD's
894 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
895 txcmd_phys, len, 1, 0);
897 if (!ieee80211_has_morefrags(hdr->frame_control)) {
898 txq->need_update = 1;
900 priv->stations[sta_id].tid[tid].seq_number = seq_number;
903 txq->need_update = 0;
906 /* Set up TFD's 2nd entry to point directly to remainder of skb,
907 * if any (802.11 null frames have no payload). */
908 secondlen = len = skb->len - hdr_len;
910 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
911 len, PCI_DMA_TODEVICE);
912 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
917 scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
918 offsetof(struct iwl_tx_cmd, scratch);
920 len = sizeof(struct iwl_tx_cmd) +
921 sizeof(struct iwl_cmd_header) + hdr_len;
922 /* take back ownership of DMA buffer to enable update */
923 pci_dma_sync_single_for_cpu(priv->pci_dev, txcmd_phys,
924 len, PCI_DMA_BIDIRECTIONAL);
925 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
926 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
928 IWL_DEBUG_TX(priv, "sequence nr = 0X%x \n",
929 le16_to_cpu(out_cmd->hdr.sequence));
930 IWL_DEBUG_TX(priv, "tx_flags = 0X%x \n", le32_to_cpu(tx_cmd->tx_flags));
931 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
932 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
934 /* Set up entry for this TFD in Tx byte-count array */
935 if (info->flags & IEEE80211_TX_CTL_AMPDU)
936 priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq,
937 le16_to_cpu(tx_cmd->len));
939 pci_dma_sync_single_for_device(priv->pci_dev, txcmd_phys,
940 len, PCI_DMA_BIDIRECTIONAL);
942 trace_iwlwifi_dev_tx(priv,
943 &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr],
944 sizeof(struct iwl_tfd),
945 &out_cmd->hdr, firstlen,
946 skb->data + hdr_len, secondlen);
948 /* Tell device the write index *just past* this latest filled TFD */
949 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
950 iwl_txq_update_write_ptr(priv, txq);
951 spin_unlock_irqrestore(&priv->lock, flags);
954 * At this point the frame is "transmitted" successfully
955 * and we will get a TX status notification eventually,
956 * regardless of the value of ret. "ret" only indicates
957 * whether or not we should update the write pointer.
960 /* avoid atomic ops if it isn't an associated client */
961 if (sta_priv && sta_priv->client)
962 atomic_inc(&sta_priv->pending_frames);
964 if ((iwl_queue_space(q) < q->high_mark) && priv->mac80211_registered) {
965 if (wait_write_ptr) {
966 spin_lock_irqsave(&priv->lock, flags);
967 txq->need_update = 1;
968 iwl_txq_update_write_ptr(priv, txq);
969 spin_unlock_irqrestore(&priv->lock, flags);
971 iwl_stop_queue(priv, txq->swq_id);
978 spin_unlock_irqrestore(&priv->lock, flags);
981 EXPORT_SYMBOL(iwl_tx_skb);
983 /*************** HOST COMMAND QUEUE FUNCTIONS *****/
986 * iwl_enqueue_hcmd - enqueue a uCode command
987 * @priv: device private data point
988 * @cmd: a point to the ucode command structure
990 * The function returns < 0 values to indicate the operation is
991 * failed. On success, it turns the index (> 0) of command in the
994 int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
996 struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
997 struct iwl_queue *q = &txq->q;
998 struct iwl_device_cmd *out_cmd;
999 struct iwl_cmd_meta *out_meta;
1000 dma_addr_t phys_addr;
1001 unsigned long flags;
1006 cmd->len = priv->cfg->ops->utils->get_hcmd_size(cmd->id, cmd->len);
1007 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
1009 /* If any of the command structures end up being larger than
1010 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
1011 * we will need to increase the size of the TFD entries */
1012 BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
1013 !(cmd->flags & CMD_SIZE_HUGE));
1015 if (iwl_is_rfkill(priv) || iwl_is_ctkill(priv)) {
1016 IWL_WARN(priv, "Not sending command - %s KILL\n",
1017 iwl_is_rfkill(priv) ? "RF" : "CT");
1021 if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
1022 IWL_ERR(priv, "No space in command queue\n");
1023 if (iwl_within_ct_kill_margin(priv))
1024 iwl_tt_enter_ct_kill(priv);
1026 IWL_ERR(priv, "Restarting adapter due to queue full\n");
1027 queue_work(priv->workqueue, &priv->restart);
1032 spin_lock_irqsave(&priv->hcmd_lock, flags);
1034 idx = get_cmd_index(q, q->write_ptr, cmd->flags & CMD_SIZE_HUGE);
1035 out_cmd = txq->cmd[idx];
1036 out_meta = &txq->meta[idx];
1038 memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
1039 out_meta->flags = cmd->flags;
1040 if (cmd->flags & CMD_WANT_SKB)
1041 out_meta->source = cmd;
1042 if (cmd->flags & CMD_ASYNC)
1043 out_meta->callback = cmd->callback;
1045 out_cmd->hdr.cmd = cmd->id;
1046 memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
1048 /* At this point, the out_cmd now has all of the incoming cmd
1051 out_cmd->hdr.flags = 0;
1052 out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
1053 INDEX_TO_SEQ(q->write_ptr));
1054 if (cmd->flags & CMD_SIZE_HUGE)
1055 out_cmd->hdr.sequence |= SEQ_HUGE_FRAME;
1056 len = sizeof(struct iwl_device_cmd);
1057 len += (idx == TFD_CMD_SLOTS) ? IWL_MAX_SCAN_SIZE : 0;
1060 #ifdef CONFIG_IWLWIFI_DEBUG
1061 switch (out_cmd->hdr.cmd) {
1062 case REPLY_TX_LINK_QUALITY_CMD:
1063 case SENSITIVITY_CMD:
1064 IWL_DEBUG_HC_DUMP(priv, "Sending command %s (#%x), seq: 0x%04X, "
1065 "%d bytes at %d[%d]:%d\n",
1066 get_cmd_string(out_cmd->hdr.cmd),
1068 le16_to_cpu(out_cmd->hdr.sequence), fix_size,
1069 q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
1072 IWL_DEBUG_HC(priv, "Sending command %s (#%x), seq: 0x%04X, "
1073 "%d bytes at %d[%d]:%d\n",
1074 get_cmd_string(out_cmd->hdr.cmd),
1076 le16_to_cpu(out_cmd->hdr.sequence), fix_size,
1077 q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
1080 txq->need_update = 1;
1082 if (priv->cfg->ops->lib->txq_update_byte_cnt_tbl)
1083 /* Set up entry in queue's byte count circular buffer */
1084 priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, 0);
1086 phys_addr = pci_map_single(priv->pci_dev, &out_cmd->hdr,
1087 fix_size, PCI_DMA_BIDIRECTIONAL);
1088 pci_unmap_addr_set(out_meta, mapping, phys_addr);
1089 pci_unmap_len_set(out_meta, len, fix_size);
1091 trace_iwlwifi_dev_hcmd(priv, &out_cmd->hdr, fix_size, cmd->flags);
1093 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
1094 phys_addr, fix_size, 1,
1097 /* Increment and update queue's write index */
1098 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1099 iwl_txq_update_write_ptr(priv, txq);
1101 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
1105 static void iwl_tx_status(struct iwl_priv *priv, struct sk_buff *skb)
1107 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1108 struct ieee80211_sta *sta;
1109 struct iwl_station_priv *sta_priv;
1111 sta = ieee80211_find_sta(priv->vif, hdr->addr1);
1113 sta_priv = (void *)sta->drv_priv;
1114 /* avoid atomic ops if this isn't a client */
1115 if (sta_priv->client &&
1116 atomic_dec_return(&sta_priv->pending_frames) == 0)
1117 ieee80211_sta_block_awake(priv->hw, sta, false);
1120 ieee80211_tx_status_irqsafe(priv->hw, skb);
1123 int iwl_tx_queue_reclaim(struct iwl_priv *priv, int txq_id, int index)
1125 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1126 struct iwl_queue *q = &txq->q;
1127 struct iwl_tx_info *tx_info;
1130 if ((index >= q->n_bd) || (iwl_queue_used(q, index) == 0)) {
1131 IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, "
1132 "is out of range [0-%d] %d %d.\n", txq_id,
1133 index, q->n_bd, q->write_ptr, q->read_ptr);
1137 for (index = iwl_queue_inc_wrap(index, q->n_bd);
1138 q->read_ptr != index;
1139 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1141 tx_info = &txq->txb[txq->q.read_ptr];
1142 iwl_tx_status(priv, tx_info->skb[0]);
1143 tx_info->skb[0] = NULL;
1145 if (priv->cfg->ops->lib->txq_inval_byte_cnt_tbl)
1146 priv->cfg->ops->lib->txq_inval_byte_cnt_tbl(priv, txq);
1148 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
1153 EXPORT_SYMBOL(iwl_tx_queue_reclaim);
1157 * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
1159 * When FW advances 'R' index, all entries between old and new 'R' index
1160 * need to be reclaimed. As result, some free space forms. If there is
1161 * enough free space (> low mark), wake the stack that feeds us.
1163 static void iwl_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id,
1164 int idx, int cmd_idx)
1166 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1167 struct iwl_queue *q = &txq->q;
1170 if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) {
1171 IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, "
1172 "is out of range [0-%d] %d %d.\n", txq_id,
1173 idx, q->n_bd, q->write_ptr, q->read_ptr);
1177 for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
1178 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1181 IWL_ERR(priv, "HCMD skipped: index (%d) %d %d\n", idx,
1182 q->write_ptr, q->read_ptr);
1183 queue_work(priv->workqueue, &priv->restart);
1190 * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
1191 * @rxb: Rx buffer to reclaim
1193 * If an Rx buffer has an async callback associated with it the callback
1194 * will be executed. The attached skb (if present) will only be freed
1195 * if the callback returns 1
1197 void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
1199 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1200 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1201 int txq_id = SEQ_TO_QUEUE(sequence);
1202 int index = SEQ_TO_INDEX(sequence);
1204 bool huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME);
1205 struct iwl_device_cmd *cmd;
1206 struct iwl_cmd_meta *meta;
1208 /* If a Tx command is being handled and it isn't in the actual
1209 * command queue then there a command routing bug has been introduced
1210 * in the queue management code. */
1211 if (WARN(txq_id != IWL_CMD_QUEUE_NUM,
1212 "wrong command queue %d, sequence 0x%X readp=%d writep=%d\n",
1214 priv->txq[IWL_CMD_QUEUE_NUM].q.read_ptr,
1215 priv->txq[IWL_CMD_QUEUE_NUM].q.write_ptr)) {
1216 iwl_print_hex_error(priv, pkt, 32);
1220 cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
1221 cmd = priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
1222 meta = &priv->txq[IWL_CMD_QUEUE_NUM].meta[cmd_index];
1224 pci_unmap_single(priv->pci_dev,
1225 pci_unmap_addr(meta, mapping),
1226 pci_unmap_len(meta, len),
1227 PCI_DMA_BIDIRECTIONAL);
1229 /* Input error checking is done when commands are added to queue. */
1230 if (meta->flags & CMD_WANT_SKB) {
1231 meta->source->reply_page = (unsigned long)rxb_addr(rxb);
1233 } else if (meta->callback)
1234 meta->callback(priv, cmd, pkt);
1236 iwl_hcmd_queue_reclaim(priv, txq_id, index, cmd_index);
1238 if (!(meta->flags & CMD_ASYNC)) {
1239 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1240 wake_up_interruptible(&priv->wait_command_queue);
1243 EXPORT_SYMBOL(iwl_tx_cmd_complete);
1246 * Find first available (lowest unused) Tx Queue, mark it "active".
1247 * Called only when finding queue for aggregation.
1248 * Should never return anything < 7, because they should already
1249 * be in use as EDCA AC (0-3), Command (4), HCCA (5, 6).
1251 static int iwl_txq_ctx_activate_free(struct iwl_priv *priv)
1255 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
1256 if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk))
1261 int iwl_tx_agg_start(struct iwl_priv *priv, const u8 *ra, u16 tid, u16 *ssn)
1267 unsigned long flags;
1268 struct iwl_tid_data *tid_data;
1270 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
1271 tx_fifo = default_tid_to_tx_fifo[tid];
1275 IWL_WARN(priv, "%s on ra = %pM tid = %d\n",
1278 sta_id = iwl_find_station(priv, ra);
1279 if (sta_id == IWL_INVALID_STATION) {
1280 IWL_ERR(priv, "Start AGG on invalid station\n");
1283 if (unlikely(tid >= MAX_TID_COUNT))
1286 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) {
1287 IWL_ERR(priv, "Start AGG when state is not IWL_AGG_OFF !\n");
1291 txq_id = iwl_txq_ctx_activate_free(priv);
1293 IWL_ERR(priv, "No free aggregation queue available\n");
1297 spin_lock_irqsave(&priv->sta_lock, flags);
1298 tid_data = &priv->stations[sta_id].tid[tid];
1299 *ssn = SEQ_TO_SN(tid_data->seq_number);
1300 tid_data->agg.txq_id = txq_id;
1301 priv->txq[txq_id].swq_id = iwl_virtual_agg_queue_num(tx_fifo, txq_id);
1302 spin_unlock_irqrestore(&priv->sta_lock, flags);
1304 ret = priv->cfg->ops->lib->txq_agg_enable(priv, txq_id, tx_fifo,
1309 if (tid_data->tfds_in_queue == 0) {
1310 IWL_DEBUG_HT(priv, "HW queue is empty\n");
1311 tid_data->agg.state = IWL_AGG_ON;
1312 ieee80211_start_tx_ba_cb_irqsafe(priv->vif, ra, tid);
1314 IWL_DEBUG_HT(priv, "HW queue is NOT empty: %d packets in HW queue\n",
1315 tid_data->tfds_in_queue);
1316 tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA;
1320 EXPORT_SYMBOL(iwl_tx_agg_start);
1322 int iwl_tx_agg_stop(struct iwl_priv *priv , const u8 *ra, u16 tid)
1324 int tx_fifo_id, txq_id, sta_id, ssn = -1;
1325 struct iwl_tid_data *tid_data;
1326 int write_ptr, read_ptr;
1327 unsigned long flags;
1330 IWL_ERR(priv, "ra = NULL\n");
1334 if (unlikely(tid >= MAX_TID_COUNT))
1337 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
1338 tx_fifo_id = default_tid_to_tx_fifo[tid];
1342 sta_id = iwl_find_station(priv, ra);
1344 if (sta_id == IWL_INVALID_STATION) {
1345 IWL_ERR(priv, "Invalid station for AGG tid %d\n", tid);
1349 if (priv->stations[sta_id].tid[tid].agg.state ==
1350 IWL_EMPTYING_HW_QUEUE_ADDBA) {
1351 IWL_DEBUG_HT(priv, "AGG stop before setup done\n");
1352 ieee80211_stop_tx_ba_cb_irqsafe(priv->vif, ra, tid);
1353 priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
1357 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_ON)
1358 IWL_WARN(priv, "Stopping AGG while state not ON or starting\n");
1360 tid_data = &priv->stations[sta_id].tid[tid];
1361 ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
1362 txq_id = tid_data->agg.txq_id;
1363 write_ptr = priv->txq[txq_id].q.write_ptr;
1364 read_ptr = priv->txq[txq_id].q.read_ptr;
1366 /* The queue is not empty */
1367 if (write_ptr != read_ptr) {
1368 IWL_DEBUG_HT(priv, "Stopping a non empty AGG HW QUEUE\n");
1369 priv->stations[sta_id].tid[tid].agg.state =
1370 IWL_EMPTYING_HW_QUEUE_DELBA;
1374 IWL_DEBUG_HT(priv, "HW queue is empty\n");
1375 priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
1377 spin_lock_irqsave(&priv->lock, flags);
1379 * the only reason this call can fail is queue number out of range,
1380 * which can happen if uCode is reloaded and all the station
1381 * information are lost. if it is outside the range, there is no need
1382 * to deactivate the uCode queue, just return "success" to allow
1383 * mac80211 to clean up it own data.
1385 priv->cfg->ops->lib->txq_agg_disable(priv, txq_id, ssn,
1387 spin_unlock_irqrestore(&priv->lock, flags);
1389 ieee80211_stop_tx_ba_cb_irqsafe(priv->vif, ra, tid);
1393 EXPORT_SYMBOL(iwl_tx_agg_stop);
1395 int iwl_txq_check_empty(struct iwl_priv *priv, int sta_id, u8 tid, int txq_id)
1397 struct iwl_queue *q = &priv->txq[txq_id].q;
1398 u8 *addr = priv->stations[sta_id].sta.sta.addr;
1399 struct iwl_tid_data *tid_data = &priv->stations[sta_id].tid[tid];
1401 switch (priv->stations[sta_id].tid[tid].agg.state) {
1402 case IWL_EMPTYING_HW_QUEUE_DELBA:
1403 /* We are reclaiming the last packet of the */
1404 /* aggregated HW queue */
1405 if ((txq_id == tid_data->agg.txq_id) &&
1406 (q->read_ptr == q->write_ptr)) {
1407 u16 ssn = SEQ_TO_SN(tid_data->seq_number);
1408 int tx_fifo = default_tid_to_tx_fifo[tid];
1409 IWL_DEBUG_HT(priv, "HW queue empty: continue DELBA flow\n");
1410 priv->cfg->ops->lib->txq_agg_disable(priv, txq_id,
1412 tid_data->agg.state = IWL_AGG_OFF;
1413 ieee80211_stop_tx_ba_cb_irqsafe(priv->vif, addr, tid);
1416 case IWL_EMPTYING_HW_QUEUE_ADDBA:
1417 /* We are reclaiming the last packet of the queue */
1418 if (tid_data->tfds_in_queue == 0) {
1419 IWL_DEBUG_HT(priv, "HW queue empty: continue ADDBA flow\n");
1420 tid_data->agg.state = IWL_AGG_ON;
1421 ieee80211_start_tx_ba_cb_irqsafe(priv->vif, addr, tid);
1427 EXPORT_SYMBOL(iwl_txq_check_empty);
1430 * iwl_tx_status_reply_compressed_ba - Update tx status from block-ack
1432 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
1433 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
1435 static int iwl_tx_status_reply_compressed_ba(struct iwl_priv *priv,
1436 struct iwl_ht_agg *agg,
1437 struct iwl_compressed_ba_resp *ba_resp)
1441 u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
1442 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
1445 struct ieee80211_tx_info *info;
1447 if (unlikely(!agg->wait_for_ba)) {
1448 IWL_ERR(priv, "Received BA when not expected\n");
1452 /* Mark that the expected block-ack response arrived */
1453 agg->wait_for_ba = 0;
1454 IWL_DEBUG_TX_REPLY(priv, "BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
1456 /* Calculate shift to align block-ack bits with our Tx window bits */
1457 sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl >> 4);
1458 if (sh < 0) /* tbw something is wrong with indices */
1461 /* don't use 64-bit values for now */
1462 bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
1464 if (agg->frame_count > (64 - sh)) {
1465 IWL_DEBUG_TX_REPLY(priv, "more frames than bitmap size");
1469 /* check for success or failure according to the
1470 * transmitted bitmap and block-ack bitmap */
1471 bitmap &= agg->bitmap;
1473 /* For each frame attempted in aggregation,
1474 * update driver's record of tx frame's status. */
1475 for (i = 0; i < agg->frame_count ; i++) {
1476 ack = bitmap & (1ULL << i);
1478 IWL_DEBUG_TX_REPLY(priv, "%s ON i=%d idx=%d raw=%d\n",
1479 ack ? "ACK" : "NACK", i, (agg->start_idx + i) & 0xff,
1480 agg->start_idx + i);
1483 info = IEEE80211_SKB_CB(priv->txq[scd_flow].txb[agg->start_idx].skb[0]);
1484 memset(&info->status, 0, sizeof(info->status));
1485 info->flags |= IEEE80211_TX_STAT_ACK;
1486 info->flags |= IEEE80211_TX_STAT_AMPDU;
1487 info->status.ampdu_ack_map = successes;
1488 info->status.ampdu_ack_len = agg->frame_count;
1489 iwl_hwrate_to_tx_control(priv, agg->rate_n_flags, info);
1491 IWL_DEBUG_TX_REPLY(priv, "Bitmap %llx\n", (unsigned long long)bitmap);
1497 * iwl_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
1499 * Handles block-acknowledge notification from device, which reports success
1500 * of frames sent via aggregation.
1502 void iwl_rx_reply_compressed_ba(struct iwl_priv *priv,
1503 struct iwl_rx_mem_buffer *rxb)
1505 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1506 struct iwl_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
1507 struct iwl_tx_queue *txq = NULL;
1508 struct iwl_ht_agg *agg;
1513 /* "flow" corresponds to Tx queue */
1514 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
1516 /* "ssn" is start of block-ack Tx window, corresponds to index
1517 * (in Tx queue's circular buffer) of first TFD/frame in window */
1518 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
1520 if (scd_flow >= priv->hw_params.max_txq_num) {
1522 "BUG_ON scd_flow is bigger than number of queues\n");
1526 txq = &priv->txq[scd_flow];
1527 sta_id = ba_resp->sta_id;
1529 agg = &priv->stations[sta_id].tid[tid].agg;
1531 /* Find index just before block-ack window */
1532 index = iwl_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
1534 /* TODO: Need to get this copy more safely - now good for debug */
1536 IWL_DEBUG_TX_REPLY(priv, "REPLY_COMPRESSED_BA [%d] Received from %pM, "
1539 (u8 *) &ba_resp->sta_addr_lo32,
1541 IWL_DEBUG_TX_REPLY(priv, "TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
1542 "%d, scd_ssn = %d\n",
1545 (unsigned long long)le64_to_cpu(ba_resp->bitmap),
1548 IWL_DEBUG_TX_REPLY(priv, "DAT start_idx = %d, bitmap = 0x%llx \n",
1550 (unsigned long long)agg->bitmap);
1552 /* Update driver's record of ACK vs. not for each frame in window */
1553 iwl_tx_status_reply_compressed_ba(priv, agg, ba_resp);
1555 /* Release all TFDs before the SSN, i.e. all TFDs in front of
1556 * block-ack window (we assume that they've been successfully
1557 * transmitted ... if not, it's too late anyway). */
1558 if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
1559 /* calculate mac80211 ampdu sw queue to wake */
1560 int freed = iwl_tx_queue_reclaim(priv, scd_flow, index);
1561 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1563 if ((iwl_queue_space(&txq->q) > txq->q.low_mark) &&
1564 priv->mac80211_registered &&
1565 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA))
1566 iwl_wake_queue(priv, txq->swq_id);
1568 iwl_txq_check_empty(priv, sta_id, tid, scd_flow);
1571 EXPORT_SYMBOL(iwl_rx_reply_compressed_ba);
1573 #ifdef CONFIG_IWLWIFI_DEBUG
1574 #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
1576 const char *iwl_get_tx_fail_reason(u32 status)
1578 switch (status & TX_STATUS_MSK) {
1579 case TX_STATUS_SUCCESS:
1581 TX_STATUS_ENTRY(SHORT_LIMIT);
1582 TX_STATUS_ENTRY(LONG_LIMIT);
1583 TX_STATUS_ENTRY(FIFO_UNDERRUN);
1584 TX_STATUS_ENTRY(MGMNT_ABORT);
1585 TX_STATUS_ENTRY(NEXT_FRAG);
1586 TX_STATUS_ENTRY(LIFE_EXPIRE);
1587 TX_STATUS_ENTRY(DEST_PS);
1588 TX_STATUS_ENTRY(ABORTED);
1589 TX_STATUS_ENTRY(BT_RETRY);
1590 TX_STATUS_ENTRY(STA_INVALID);
1591 TX_STATUS_ENTRY(FRAG_DROPPED);
1592 TX_STATUS_ENTRY(TID_DISABLE);
1593 TX_STATUS_ENTRY(FRAME_FLUSHED);
1594 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
1595 TX_STATUS_ENTRY(TX_LOCKED);
1596 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
1601 EXPORT_SYMBOL(iwl_get_tx_fail_reason);
1602 #endif /* CONFIG_IWLWIFI_DEBUG */