1 /******************************************************************************
3 * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
30 #include <linux/etherdevice.h>
31 #include <net/mac80211.h>
32 #include "iwl-eeprom.h"
37 #include "iwl-helpers.h"
39 static const u16 default_tid_to_tx_fifo[] = {
59 static inline int iwl_alloc_dma_ptr(struct iwl_priv *priv,
60 struct iwl_dma_ptr *ptr, size_t size)
62 ptr->addr = pci_alloc_consistent(priv->pci_dev, size, &ptr->dma);
69 static inline void iwl_free_dma_ptr(struct iwl_priv *priv,
70 struct iwl_dma_ptr *ptr)
72 if (unlikely(!ptr->addr))
75 pci_free_consistent(priv->pci_dev, ptr->size, ptr->addr, ptr->dma);
76 memset(ptr, 0, sizeof(*ptr));
80 * iwl_txq_update_write_ptr - Send new write index to hardware
82 int iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq)
86 int txq_id = txq->q.id;
88 if (txq->need_update == 0)
91 /* if we're trying to save power */
92 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
93 /* wake up nic if it's powered down ...
94 * uCode will wake up, and interrupt us again, so next
95 * time we'll skip this part. */
96 reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
98 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
99 IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
100 iwl_set_bit(priv, CSR_GP_CNTRL,
101 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
105 /* restore this queue's parameters in nic hardware. */
106 ret = iwl_grab_nic_access(priv);
109 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
110 txq->q.write_ptr | (txq_id << 8));
111 iwl_release_nic_access(priv);
113 /* else not in power-save mode, uCode will never sleep when we're
114 * trying to tx (during RFKILL, we're not trying to tx). */
116 iwl_write32(priv, HBUS_TARG_WRPTR,
117 txq->q.write_ptr | (txq_id << 8));
119 txq->need_update = 0;
123 EXPORT_SYMBOL(iwl_txq_update_write_ptr);
127 * iwl_tx_queue_free - Deallocate DMA queue.
128 * @txq: Transmit queue to deallocate.
130 * Empty queue by removing and destroying all BD's.
132 * 0-fill, but do not free "txq" descriptor structure.
134 static void iwl_tx_queue_free(struct iwl_priv *priv, int txq_id)
136 struct iwl_tx_queue *txq = &priv->txq[txq_id];
137 struct iwl_queue *q = &txq->q;
138 struct pci_dev *dev = priv->pci_dev;
144 /* first, empty all BD's */
145 for (; q->write_ptr != q->read_ptr;
146 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
147 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
149 len = sizeof(struct iwl_cmd) * q->n_window;
151 /* De-alloc array of command/tx buffers */
152 for (i = 0; i < TFD_TX_CMD_SLOTS; i++)
155 /* De-alloc circular buffer of TFDs */
157 pci_free_consistent(dev, sizeof(struct iwl_tfd) *
158 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
160 /* De-alloc array of per-TFD driver data */
164 /* 0-fill queue descriptor structure */
165 memset(txq, 0, sizeof(*txq));
170 * iwl_cmd_queue_free - Deallocate DMA queue.
171 * @txq: Transmit queue to deallocate.
173 * Empty queue by removing and destroying all BD's.
175 * 0-fill, but do not free "txq" descriptor structure.
177 static void iwl_cmd_queue_free(struct iwl_priv *priv)
179 struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
180 struct iwl_queue *q = &txq->q;
181 struct pci_dev *dev = priv->pci_dev;
187 len = sizeof(struct iwl_cmd) * q->n_window;
188 len += IWL_MAX_SCAN_SIZE;
190 /* De-alloc array of command/tx buffers */
191 for (i = 0; i <= TFD_CMD_SLOTS; i++)
194 /* De-alloc circular buffer of TFDs */
196 pci_free_consistent(dev, sizeof(struct iwl_tfd) *
197 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
199 /* 0-fill queue descriptor structure */
200 memset(txq, 0, sizeof(*txq));
202 /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
205 * Theory of operation
207 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
208 * of buffer descriptors, each of which points to one or more data buffers for
209 * the device to read from or fill. Driver and device exchange status of each
210 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
211 * entries in each circular buffer, to protect against confusing empty and full
214 * The device reads or writes the data in the queues via the device's several
215 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
217 * For Tx queue, there are low mark and high mark limits. If, after queuing
218 * the packet for Tx, free space become < low mark, Tx queue stopped. When
219 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
222 * See more detailed info in iwl-4965-hw.h.
223 ***************************************************/
225 int iwl_queue_space(const struct iwl_queue *q)
227 int s = q->read_ptr - q->write_ptr;
229 if (q->read_ptr > q->write_ptr)
234 /* keep some reserve to not confuse empty and full situations */
240 EXPORT_SYMBOL(iwl_queue_space);
244 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
246 static int iwl_queue_init(struct iwl_priv *priv, struct iwl_queue *q,
247 int count, int slots_num, u32 id)
250 q->n_window = slots_num;
253 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
254 * and iwl_queue_dec_wrap are broken. */
255 BUG_ON(!is_power_of_2(count));
257 /* slots_num must be power-of-two size, otherwise
258 * get_cmd_index is broken. */
259 BUG_ON(!is_power_of_2(slots_num));
261 q->low_mark = q->n_window / 4;
265 q->high_mark = q->n_window / 8;
266 if (q->high_mark < 2)
269 q->write_ptr = q->read_ptr = 0;
275 * iwl_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
277 static int iwl_tx_queue_alloc(struct iwl_priv *priv,
278 struct iwl_tx_queue *txq, u32 id)
280 struct pci_dev *dev = priv->pci_dev;
282 /* Driver private data, only for Tx (not command) queues,
283 * not shared with device. */
284 if (id != IWL_CMD_QUEUE_NUM) {
285 txq->txb = kmalloc(sizeof(txq->txb[0]) *
286 TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
288 IWL_ERR(priv, "kmalloc for auxiliary BD "
289 "structures failed\n");
295 /* Circular buffer of transmit frame descriptors (TFDs),
296 * shared with device */
297 txq->tfds = pci_alloc_consistent(dev,
298 sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX,
302 IWL_ERR(priv, "pci_alloc_consistent(%zd) failed\n",
303 sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX);
318 * Tell nic where to find circular buffer of Tx Frame Descriptors for
319 * given Tx queue, and enable the DMA channel used for that queue.
321 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
322 * channels supported in hardware.
324 static int iwl_hw_tx_queue_init(struct iwl_priv *priv,
325 struct iwl_tx_queue *txq)
329 int txq_id = txq->q.id;
331 spin_lock_irqsave(&priv->lock, flags);
332 ret = iwl_grab_nic_access(priv);
334 spin_unlock_irqrestore(&priv->lock, flags);
338 /* Circular buffer (TFD queue in DRAM) physical base address */
339 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
340 txq->q.dma_addr >> 8);
342 iwl_release_nic_access(priv);
343 spin_unlock_irqrestore(&priv->lock, flags);
349 * iwl_tx_queue_init - Allocate and initialize one tx/cmd queue
351 static int iwl_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq,
352 int slots_num, u32 txq_id)
358 * Alloc buffer array for commands (Tx or other types of commands).
359 * For the command queue (#4), allocate command space + one big
360 * command for scan, since scan command is very huge; the system will
361 * not have two scans at the same time, so only one is needed.
362 * For normal Tx queues (all other queues), no super-size command
365 len = sizeof(struct iwl_cmd);
366 for (i = 0; i <= slots_num; i++) {
367 if (i == slots_num) {
368 if (txq_id == IWL_CMD_QUEUE_NUM)
369 len += IWL_MAX_SCAN_SIZE;
374 txq->cmd[i] = kmalloc(len, GFP_KERNEL);
379 /* Alloc driver data array and TFD circular buffer */
380 ret = iwl_tx_queue_alloc(priv, txq, txq_id);
384 txq->need_update = 0;
386 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
387 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
388 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
390 /* Initialize queue's high/low-water marks, and head/tail indexes */
391 iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
393 /* Tell device where to find queue */
394 iwl_hw_tx_queue_init(priv, txq);
398 for (i = 0; i < slots_num; i++) {
403 if (txq_id == IWL_CMD_QUEUE_NUM) {
404 kfree(txq->cmd[slots_num]);
405 txq->cmd[slots_num] = NULL;
410 * iwl_hw_txq_ctx_free - Free TXQ Context
412 * Destroy all TX DMA queues and structures
414 void iwl_hw_txq_ctx_free(struct iwl_priv *priv)
419 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
420 if (txq_id == IWL_CMD_QUEUE_NUM)
421 iwl_cmd_queue_free(priv);
423 iwl_tx_queue_free(priv, txq_id);
425 iwl_free_dma_ptr(priv, &priv->kw);
427 iwl_free_dma_ptr(priv, &priv->scd_bc_tbls);
429 EXPORT_SYMBOL(iwl_hw_txq_ctx_free);
432 * iwl_txq_ctx_reset - Reset TX queue context
433 * Destroys all DMA structures and initialize them again
438 int iwl_txq_ctx_reset(struct iwl_priv *priv)
441 int txq_id, slots_num;
444 /* Free all tx/cmd queues and keep-warm buffer */
445 iwl_hw_txq_ctx_free(priv);
447 ret = iwl_alloc_dma_ptr(priv, &priv->scd_bc_tbls,
448 priv->hw_params.scd_bc_tbls_size);
450 IWL_ERR(priv, "Scheduler BC Table allocation failed\n");
453 /* Alloc keep-warm buffer */
454 ret = iwl_alloc_dma_ptr(priv, &priv->kw, IWL_KW_SIZE);
456 IWL_ERR(priv, "Keep Warm allocation failed\n");
459 spin_lock_irqsave(&priv->lock, flags);
460 ret = iwl_grab_nic_access(priv);
462 spin_unlock_irqrestore(&priv->lock, flags);
466 /* Turn off all Tx DMA fifos */
467 priv->cfg->ops->lib->txq_set_sched(priv, 0);
469 /* Tell NIC where to find the "keep warm" buffer */
470 iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG, priv->kw.dma >> 4);
472 iwl_release_nic_access(priv);
473 spin_unlock_irqrestore(&priv->lock, flags);
475 /* Alloc and init all Tx queues, including the command queue (#4) */
476 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
477 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
478 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
479 ret = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
482 IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
490 iwl_hw_txq_ctx_free(priv);
492 iwl_free_dma_ptr(priv, &priv->kw);
494 iwl_free_dma_ptr(priv, &priv->scd_bc_tbls);
500 * iwl_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory
502 void iwl_txq_ctx_stop(struct iwl_priv *priv)
507 /* Turn off all Tx DMA fifos */
508 spin_lock_irqsave(&priv->lock, flags);
509 if (iwl_grab_nic_access(priv)) {
510 spin_unlock_irqrestore(&priv->lock, flags);
514 priv->cfg->ops->lib->txq_set_sched(priv, 0);
516 /* Stop each Tx DMA channel, and wait for it to be idle */
517 for (ch = 0; ch < priv->hw_params.dma_chnl_num; ch++) {
518 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
519 iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS_REG,
520 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
523 iwl_release_nic_access(priv);
524 spin_unlock_irqrestore(&priv->lock, flags);
526 /* Deallocate memory for all Tx queues */
527 iwl_hw_txq_ctx_free(priv);
529 EXPORT_SYMBOL(iwl_txq_ctx_stop);
532 * handle build REPLY_TX command notification.
534 static void iwl_tx_cmd_build_basic(struct iwl_priv *priv,
535 struct iwl_tx_cmd *tx_cmd,
536 struct ieee80211_tx_info *info,
537 struct ieee80211_hdr *hdr,
540 __le16 fc = hdr->frame_control;
541 __le32 tx_flags = tx_cmd->tx_flags;
543 tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
544 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
545 tx_flags |= TX_CMD_FLG_ACK_MSK;
546 if (ieee80211_is_mgmt(fc))
547 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
548 if (ieee80211_is_probe_resp(fc) &&
549 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
550 tx_flags |= TX_CMD_FLG_TSF_MSK;
552 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
553 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
556 if (ieee80211_is_back_req(fc))
557 tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK;
560 tx_cmd->sta_id = std_id;
561 if (ieee80211_has_morefrags(fc))
562 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
564 if (ieee80211_is_data_qos(fc)) {
565 u8 *qc = ieee80211_get_qos_ctl(hdr);
566 tx_cmd->tid_tspec = qc[0] & 0xf;
567 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
569 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
572 priv->cfg->ops->utils->rts_tx_cmd_flag(info, &tx_flags);
574 if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
575 tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
577 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
578 if (ieee80211_is_mgmt(fc)) {
579 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
580 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
582 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
584 tx_cmd->timeout.pm_frame_timeout = 0;
587 tx_cmd->driver_txop = 0;
588 tx_cmd->tx_flags = tx_flags;
589 tx_cmd->next_frame_len = 0;
592 #define RTS_HCCA_RETRY_LIMIT 3
593 #define RTS_DFAULT_RETRY_LIMIT 60
595 static void iwl_tx_cmd_build_rate(struct iwl_priv *priv,
596 struct iwl_tx_cmd *tx_cmd,
597 struct ieee80211_tx_info *info,
598 __le16 fc, int sta_id,
603 u8 rts_retry_limit = 0;
604 u8 data_retry_limit = 0;
607 rate_idx = min(ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xffff,
610 rate_plcp = iwl_rates[rate_idx].plcp;
612 rts_retry_limit = (is_hcca) ?
613 RTS_HCCA_RETRY_LIMIT : RTS_DFAULT_RETRY_LIMIT;
615 if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE))
616 rate_flags |= RATE_MCS_CCK_MSK;
619 if (ieee80211_is_probe_resp(fc)) {
620 data_retry_limit = 3;
621 if (data_retry_limit < rts_retry_limit)
622 rts_retry_limit = data_retry_limit;
624 data_retry_limit = IWL_DEFAULT_TX_RETRY;
626 if (priv->data_retry_limit != -1)
627 data_retry_limit = priv->data_retry_limit;
630 if (ieee80211_is_data(fc)) {
631 tx_cmd->initial_rate_index = 0;
632 tx_cmd->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
634 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
635 case cpu_to_le16(IEEE80211_STYPE_AUTH):
636 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
637 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
638 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
639 if (tx_cmd->tx_flags & TX_CMD_FLG_RTS_MSK) {
640 tx_cmd->tx_flags &= ~TX_CMD_FLG_RTS_MSK;
641 tx_cmd->tx_flags |= TX_CMD_FLG_CTS_MSK;
648 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant);
649 rate_flags |= iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
652 tx_cmd->rts_retry_limit = rts_retry_limit;
653 tx_cmd->data_retry_limit = data_retry_limit;
654 tx_cmd->rate_n_flags = iwl_hw_set_rate_n_flags(rate_plcp, rate_flags);
657 static void iwl_tx_cmd_build_hwcrypto(struct iwl_priv *priv,
658 struct ieee80211_tx_info *info,
659 struct iwl_tx_cmd *tx_cmd,
660 struct sk_buff *skb_frag,
663 struct ieee80211_key_conf *keyconf = info->control.hw_key;
665 switch (keyconf->alg) {
667 tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
668 memcpy(tx_cmd->key, keyconf->key, keyconf->keylen);
669 if (info->flags & IEEE80211_TX_CTL_AMPDU)
670 tx_cmd->tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK;
671 IWL_DEBUG_TX("tx_cmd with AES hwcrypto\n");
675 tx_cmd->sec_ctl = TX_CMD_SEC_TKIP;
676 ieee80211_get_tkip_key(keyconf, skb_frag,
677 IEEE80211_TKIP_P2_KEY, tx_cmd->key);
678 IWL_DEBUG_TX("tx_cmd with tkip hwcrypto\n");
682 tx_cmd->sec_ctl |= (TX_CMD_SEC_WEP |
683 (keyconf->keyidx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT);
685 if (keyconf->keylen == WEP_KEY_LEN_128)
686 tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
688 memcpy(&tx_cmd->key[3], keyconf->key, keyconf->keylen);
690 IWL_DEBUG_TX("Configuring packet for WEP encryption "
691 "with key %d\n", keyconf->keyidx);
695 IWL_ERR(priv, "Unknown encode alg %d\n", keyconf->alg);
700 static void iwl_update_tx_stats(struct iwl_priv *priv, u16 fc, u16 len)
702 /* 0 - mgmt, 1 - cnt, 2 - data */
703 int idx = (fc & IEEE80211_FCTL_FTYPE) >> 2;
704 priv->tx_stats[idx].cnt++;
705 priv->tx_stats[idx].bytes += len;
709 * start REPLY_TX command process
711 int iwl_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
713 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
714 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
715 struct iwl_tx_queue *txq;
717 struct iwl_cmd *out_cmd;
718 struct iwl_tx_cmd *tx_cmd;
720 dma_addr_t phys_addr;
721 dma_addr_t txcmd_phys;
722 dma_addr_t scratch_phys;
728 u8 wait_write_ptr = 0;
734 spin_lock_irqsave(&priv->lock, flags);
735 if (iwl_is_rfkill(priv)) {
736 IWL_DEBUG_DROP("Dropping - RF KILL\n");
740 if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) ==
742 IWL_ERR(priv, "ERROR: No TX rate available.\n");
746 fc = hdr->frame_control;
748 #ifdef CONFIG_IWLWIFI_DEBUG
749 if (ieee80211_is_auth(fc))
750 IWL_DEBUG_TX("Sending AUTH frame\n");
751 else if (ieee80211_is_assoc_req(fc))
752 IWL_DEBUG_TX("Sending ASSOC frame\n");
753 else if (ieee80211_is_reassoc_req(fc))
754 IWL_DEBUG_TX("Sending REASSOC frame\n");
757 /* drop all data frame if we are not associated */
758 if (ieee80211_is_data(fc) &&
759 (priv->iw_mode != NL80211_IFTYPE_MONITOR ||
760 !(info->flags & IEEE80211_TX_CTL_INJECTED)) && /* packet injection */
761 (!iwl_is_associated(priv) ||
762 ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id) ||
763 !priv->assoc_station_added)) {
764 IWL_DEBUG_DROP("Dropping - !iwl_is_associated\n");
768 spin_unlock_irqrestore(&priv->lock, flags);
770 hdr_len = ieee80211_hdrlen(fc);
772 /* Find (or create) index into station table for destination station */
773 sta_id = iwl_get_sta_id(priv, hdr);
774 if (sta_id == IWL_INVALID_STATION) {
775 IWL_DEBUG_DROP("Dropping - INVALID STATION: %pM\n",
780 IWL_DEBUG_TX("station Id %d\n", sta_id);
782 swq_id = skb_get_queue_mapping(skb);
784 if (ieee80211_is_data_qos(fc)) {
785 qc = ieee80211_get_qos_ctl(hdr);
786 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
787 seq_number = priv->stations[sta_id].tid[tid].seq_number;
788 seq_number &= IEEE80211_SCTL_SEQ;
789 hdr->seq_ctrl = hdr->seq_ctrl &
790 __constant_cpu_to_le16(IEEE80211_SCTL_FRAG);
791 hdr->seq_ctrl |= cpu_to_le16(seq_number);
793 /* aggregation is on for this <sta,tid> */
794 if (info->flags & IEEE80211_TX_CTL_AMPDU)
795 txq_id = priv->stations[sta_id].tid[tid].agg.txq_id;
796 priv->stations[sta_id].tid[tid].tfds_in_queue++;
799 txq = &priv->txq[txq_id];
801 txq->swq_id = swq_id;
803 spin_lock_irqsave(&priv->lock, flags);
805 /* Set up driver data for this TFD */
806 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
807 txq->txb[q->write_ptr].skb[0] = skb;
809 /* Set up first empty entry in queue's array of Tx/cmd buffers */
810 out_cmd = txq->cmd[q->write_ptr];
811 tx_cmd = &out_cmd->cmd.tx;
812 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
813 memset(tx_cmd, 0, sizeof(struct iwl_tx_cmd));
816 * Set up the Tx-command (not MAC!) header.
817 * Store the chosen Tx queue and TFD index within the sequence field;
818 * after Tx, uCode's Tx response will return this value so driver can
819 * locate the frame within the tx queue and do post-tx processing.
821 out_cmd->hdr.cmd = REPLY_TX;
822 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
823 INDEX_TO_SEQ(q->write_ptr)));
825 /* Copy MAC header from skb into command buffer */
826 memcpy(tx_cmd->hdr, hdr, hdr_len);
829 * Use the first empty entry in this queue's command buffer array
830 * to contain the Tx command and MAC header concatenated together
831 * (payload data will be in another buffer).
832 * Size of this varies, due to varying MAC header length.
833 * If end is not dword aligned, we'll have 2 extra bytes at the end
834 * of the MAC header (device reads on dword boundaries).
835 * We'll tell device about this padding later.
837 len = sizeof(struct iwl_tx_cmd) +
838 sizeof(struct iwl_cmd_header) + hdr_len;
841 len = (len + 3) & ~3;
848 /* Physical address of this Tx command's header (not MAC header!),
849 * within command buffer array. */
850 txcmd_phys = pci_map_single(priv->pci_dev,
851 out_cmd, sizeof(struct iwl_cmd),
853 pci_unmap_addr_set(&out_cmd->meta, mapping, txcmd_phys);
854 pci_unmap_len_set(&out_cmd->meta, len, sizeof(struct iwl_cmd));
855 /* Add buffer containing Tx command and MAC(!) header to TFD's
857 txcmd_phys += offsetof(struct iwl_cmd, hdr);
858 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
859 txcmd_phys, len, 1, 0);
861 if (info->control.hw_key)
862 iwl_tx_cmd_build_hwcrypto(priv, info, tx_cmd, skb, sta_id);
864 /* Set up TFD's 2nd entry to point directly to remainder of skb,
865 * if any (802.11 null frames have no payload). */
866 len = skb->len - hdr_len;
868 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
869 len, PCI_DMA_TODEVICE);
870 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
875 /* Tell NIC about any 2-byte padding after MAC header */
877 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
879 /* Total # bytes to be transmitted */
881 tx_cmd->len = cpu_to_le16(len);
882 /* TODO need this for burst mode later on */
883 iwl_tx_cmd_build_basic(priv, tx_cmd, info, hdr, sta_id);
885 /* set is_hcca to 0; it probably will never be implemented */
886 iwl_tx_cmd_build_rate(priv, tx_cmd, info, fc, sta_id, 0);
888 iwl_update_tx_stats(priv, le16_to_cpu(fc), len);
890 scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
891 offsetof(struct iwl_tx_cmd, scratch);
892 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
893 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
895 if (!ieee80211_has_morefrags(hdr->frame_control)) {
896 txq->need_update = 1;
898 priv->stations[sta_id].tid[tid].seq_number = seq_number;
901 txq->need_update = 0;
904 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
906 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
908 /* Set up entry for this TFD in Tx byte-count array */
909 priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, len);
911 /* Tell device the write index *just past* this latest filled TFD */
912 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
913 ret = iwl_txq_update_write_ptr(priv, txq);
914 spin_unlock_irqrestore(&priv->lock, flags);
919 if ((iwl_queue_space(q) < q->high_mark) && priv->mac80211_registered) {
920 if (wait_write_ptr) {
921 spin_lock_irqsave(&priv->lock, flags);
922 txq->need_update = 1;
923 iwl_txq_update_write_ptr(priv, txq);
924 spin_unlock_irqrestore(&priv->lock, flags);
926 ieee80211_stop_queue(priv->hw, txq->swq_id);
933 spin_unlock_irqrestore(&priv->lock, flags);
937 EXPORT_SYMBOL(iwl_tx_skb);
939 /*************** HOST COMMAND QUEUE FUNCTIONS *****/
942 * iwl_enqueue_hcmd - enqueue a uCode command
943 * @priv: device private data point
944 * @cmd: a point to the ucode command structure
946 * The function returns < 0 values to indicate the operation is
947 * failed. On success, it turns the index (> 0) of command in the
950 int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
952 struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
953 struct iwl_queue *q = &txq->q;
954 struct iwl_cmd *out_cmd;
955 dma_addr_t phys_addr;
961 cmd->len = priv->cfg->ops->utils->get_hcmd_size(cmd->id, cmd->len);
962 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
964 /* If any of the command structures end up being larger than
965 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
966 * we will need to increase the size of the TFD entries */
967 BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
968 !(cmd->meta.flags & CMD_SIZE_HUGE));
970 if (iwl_is_rfkill(priv)) {
971 IWL_DEBUG_INFO("Not sending command - RF KILL");
975 if (iwl_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
976 IWL_ERR(priv, "No space for Tx\n");
980 spin_lock_irqsave(&priv->hcmd_lock, flags);
982 idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
983 out_cmd = txq->cmd[idx];
985 out_cmd->hdr.cmd = cmd->id;
986 memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
987 memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
989 /* At this point, the out_cmd now has all of the incoming cmd
992 out_cmd->hdr.flags = 0;
993 out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
994 INDEX_TO_SEQ(q->write_ptr));
995 if (out_cmd->meta.flags & CMD_SIZE_HUGE)
996 out_cmd->hdr.sequence |= SEQ_HUGE_FRAME;
997 len = (idx == TFD_CMD_SLOTS) ?
998 IWL_MAX_SCAN_SIZE : sizeof(struct iwl_cmd);
1000 phys_addr = pci_map_single(priv->pci_dev, out_cmd,
1001 len, PCI_DMA_TODEVICE);
1002 pci_unmap_addr_set(&out_cmd->meta, mapping, phys_addr);
1003 pci_unmap_len_set(&out_cmd->meta, len, len);
1004 phys_addr += offsetof(struct iwl_cmd, hdr);
1006 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
1007 phys_addr, fix_size, 1,
1010 #ifdef CONFIG_IWLWIFI_DEBUG
1011 switch (out_cmd->hdr.cmd) {
1012 case REPLY_TX_LINK_QUALITY_CMD:
1013 case SENSITIVITY_CMD:
1014 IWL_DEBUG_HC_DUMP("Sending command %s (#%x), seq: 0x%04X, "
1015 "%d bytes at %d[%d]:%d\n",
1016 get_cmd_string(out_cmd->hdr.cmd),
1018 le16_to_cpu(out_cmd->hdr.sequence), fix_size,
1019 q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
1022 IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
1023 "%d bytes at %d[%d]:%d\n",
1024 get_cmd_string(out_cmd->hdr.cmd),
1026 le16_to_cpu(out_cmd->hdr.sequence), fix_size,
1027 q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
1030 txq->need_update = 1;
1032 if (priv->cfg->ops->lib->txq_update_byte_cnt_tbl)
1033 /* Set up entry in queue's byte count circular buffer */
1034 priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, 0);
1036 /* Increment and update queue's write index */
1037 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1038 ret = iwl_txq_update_write_ptr(priv, txq);
1040 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
1041 return ret ? ret : idx;
1044 int iwl_tx_queue_reclaim(struct iwl_priv *priv, int txq_id, int index)
1046 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1047 struct iwl_queue *q = &txq->q;
1048 struct iwl_tx_info *tx_info;
1051 if ((index >= q->n_bd) || (iwl_queue_used(q, index) == 0)) {
1052 IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, "
1053 "is out of range [0-%d] %d %d.\n", txq_id,
1054 index, q->n_bd, q->write_ptr, q->read_ptr);
1058 for (index = iwl_queue_inc_wrap(index, q->n_bd);
1059 q->read_ptr != index;
1060 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1062 tx_info = &txq->txb[txq->q.read_ptr];
1063 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
1064 tx_info->skb[0] = NULL;
1066 if (priv->cfg->ops->lib->txq_inval_byte_cnt_tbl)
1067 priv->cfg->ops->lib->txq_inval_byte_cnt_tbl(priv, txq);
1069 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
1074 EXPORT_SYMBOL(iwl_tx_queue_reclaim);
1078 * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
1080 * When FW advances 'R' index, all entries between old and new 'R' index
1081 * need to be reclaimed. As result, some free space forms. If there is
1082 * enough free space (> low mark), wake the stack that feeds us.
1084 static void iwl_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id,
1085 int idx, int cmd_idx)
1087 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1088 struct iwl_queue *q = &txq->q;
1091 if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) {
1092 IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, "
1093 "is out of range [0-%d] %d %d.\n", txq_id,
1094 idx, q->n_bd, q->write_ptr, q->read_ptr);
1098 pci_unmap_single(priv->pci_dev,
1099 pci_unmap_addr(&txq->cmd[cmd_idx]->meta, mapping),
1100 pci_unmap_len(&txq->cmd[cmd_idx]->meta, len),
1103 for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
1104 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1107 IWL_ERR(priv, "HCMD skipped: index (%d) %d %d\n", idx,
1108 q->write_ptr, q->read_ptr);
1109 queue_work(priv->workqueue, &priv->restart);
1116 * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
1117 * @rxb: Rx buffer to reclaim
1119 * If an Rx buffer has an async callback associated with it the callback
1120 * will be executed. The attached skb (if present) will only be freed
1121 * if the callback returns 1
1123 void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
1125 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1126 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1127 int txq_id = SEQ_TO_QUEUE(sequence);
1128 int index = SEQ_TO_INDEX(sequence);
1130 bool huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME);
1131 struct iwl_cmd *cmd;
1133 /* If a Tx command is being handled and it isn't in the actual
1134 * command queue then there a command routing bug has been introduced
1135 * in the queue management code. */
1136 if (WARN(txq_id != IWL_CMD_QUEUE_NUM,
1137 "wrong command queue %d, sequence 0x%X readp=%d writep=%d\n",
1139 priv->txq[IWL_CMD_QUEUE_NUM].q.read_ptr,
1140 priv->txq[IWL_CMD_QUEUE_NUM].q.write_ptr)) {
1141 iwl_print_hex_dump(priv, IWL_DL_INFO , rxb, 32);
1145 cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
1146 cmd = priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
1148 /* Input error checking is done when commands are added to queue. */
1149 if (cmd->meta.flags & CMD_WANT_SKB) {
1150 cmd->meta.source->u.skb = rxb->skb;
1152 } else if (cmd->meta.u.callback &&
1153 !cmd->meta.u.callback(priv, cmd, rxb->skb))
1156 iwl_hcmd_queue_reclaim(priv, txq_id, index, cmd_index);
1158 if (!(cmd->meta.flags & CMD_ASYNC)) {
1159 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1160 wake_up_interruptible(&priv->wait_command_queue);
1163 EXPORT_SYMBOL(iwl_tx_cmd_complete);
1166 * Find first available (lowest unused) Tx Queue, mark it "active".
1167 * Called only when finding queue for aggregation.
1168 * Should never return anything < 7, because they should already
1169 * be in use as EDCA AC (0-3), Command (4), HCCA (5, 6).
1171 static int iwl_txq_ctx_activate_free(struct iwl_priv *priv)
1175 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
1176 if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk))
1181 int iwl_tx_agg_start(struct iwl_priv *priv, const u8 *ra, u16 tid, u16 *ssn)
1187 unsigned long flags;
1188 struct iwl_tid_data *tid_data;
1190 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
1191 tx_fifo = default_tid_to_tx_fifo[tid];
1195 IWL_WARN(priv, "%s on ra = %pM tid = %d\n",
1198 sta_id = iwl_find_station(priv, ra);
1199 if (sta_id == IWL_INVALID_STATION)
1202 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) {
1203 IWL_ERR(priv, "Start AGG when state is not IWL_AGG_OFF !\n");
1207 txq_id = iwl_txq_ctx_activate_free(priv);
1211 spin_lock_irqsave(&priv->sta_lock, flags);
1212 tid_data = &priv->stations[sta_id].tid[tid];
1213 *ssn = SEQ_TO_SN(tid_data->seq_number);
1214 tid_data->agg.txq_id = txq_id;
1215 spin_unlock_irqrestore(&priv->sta_lock, flags);
1217 ret = priv->cfg->ops->lib->txq_agg_enable(priv, txq_id, tx_fifo,
1222 if (tid_data->tfds_in_queue == 0) {
1223 IWL_ERR(priv, "HW queue is empty\n");
1224 tid_data->agg.state = IWL_AGG_ON;
1225 ieee80211_start_tx_ba_cb_irqsafe(priv->hw, ra, tid);
1227 IWL_DEBUG_HT("HW queue is NOT empty: %d packets in HW queue\n",
1228 tid_data->tfds_in_queue);
1229 tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA;
1233 EXPORT_SYMBOL(iwl_tx_agg_start);
1235 int iwl_tx_agg_stop(struct iwl_priv *priv , const u8 *ra, u16 tid)
1237 int tx_fifo_id, txq_id, sta_id, ssn = -1;
1238 struct iwl_tid_data *tid_data;
1239 int ret, write_ptr, read_ptr;
1240 unsigned long flags;
1243 IWL_ERR(priv, "ra = NULL\n");
1247 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
1248 tx_fifo_id = default_tid_to_tx_fifo[tid];
1252 sta_id = iwl_find_station(priv, ra);
1254 if (sta_id == IWL_INVALID_STATION)
1257 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_ON)
1258 IWL_WARN(priv, "Stopping AGG while state not IWL_AGG_ON\n");
1260 tid_data = &priv->stations[sta_id].tid[tid];
1261 ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
1262 txq_id = tid_data->agg.txq_id;
1263 write_ptr = priv->txq[txq_id].q.write_ptr;
1264 read_ptr = priv->txq[txq_id].q.read_ptr;
1266 /* The queue is not empty */
1267 if (write_ptr != read_ptr) {
1268 IWL_DEBUG_HT("Stopping a non empty AGG HW QUEUE\n");
1269 priv->stations[sta_id].tid[tid].agg.state =
1270 IWL_EMPTYING_HW_QUEUE_DELBA;
1274 IWL_DEBUG_HT("HW queue is empty\n");
1275 priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
1277 spin_lock_irqsave(&priv->lock, flags);
1278 ret = priv->cfg->ops->lib->txq_agg_disable(priv, txq_id, ssn,
1280 spin_unlock_irqrestore(&priv->lock, flags);
1285 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, ra, tid);
1289 EXPORT_SYMBOL(iwl_tx_agg_stop);
1291 int iwl_txq_check_empty(struct iwl_priv *priv, int sta_id, u8 tid, int txq_id)
1293 struct iwl_queue *q = &priv->txq[txq_id].q;
1294 u8 *addr = priv->stations[sta_id].sta.sta.addr;
1295 struct iwl_tid_data *tid_data = &priv->stations[sta_id].tid[tid];
1297 switch (priv->stations[sta_id].tid[tid].agg.state) {
1298 case IWL_EMPTYING_HW_QUEUE_DELBA:
1299 /* We are reclaiming the last packet of the */
1300 /* aggregated HW queue */
1301 if ((txq_id == tid_data->agg.txq_id) &&
1302 (q->read_ptr == q->write_ptr)) {
1303 u16 ssn = SEQ_TO_SN(tid_data->seq_number);
1304 int tx_fifo = default_tid_to_tx_fifo[tid];
1305 IWL_DEBUG_HT("HW queue empty: continue DELBA flow\n");
1306 priv->cfg->ops->lib->txq_agg_disable(priv, txq_id,
1308 tid_data->agg.state = IWL_AGG_OFF;
1309 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, addr, tid);
1312 case IWL_EMPTYING_HW_QUEUE_ADDBA:
1313 /* We are reclaiming the last packet of the queue */
1314 if (tid_data->tfds_in_queue == 0) {
1315 IWL_DEBUG_HT("HW queue empty: continue ADDBA flow\n");
1316 tid_data->agg.state = IWL_AGG_ON;
1317 ieee80211_start_tx_ba_cb_irqsafe(priv->hw, addr, tid);
1323 EXPORT_SYMBOL(iwl_txq_check_empty);
1326 * iwl_tx_status_reply_compressed_ba - Update tx status from block-ack
1328 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
1329 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
1331 static int iwl_tx_status_reply_compressed_ba(struct iwl_priv *priv,
1332 struct iwl_ht_agg *agg,
1333 struct iwl_compressed_ba_resp *ba_resp)
1337 u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
1338 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
1341 struct ieee80211_tx_info *info;
1343 if (unlikely(!agg->wait_for_ba)) {
1344 IWL_ERR(priv, "Received BA when not expected\n");
1348 /* Mark that the expected block-ack response arrived */
1349 agg->wait_for_ba = 0;
1350 IWL_DEBUG_TX_REPLY("BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
1352 /* Calculate shift to align block-ack bits with our Tx window bits */
1353 sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl >> 4);
1354 if (sh < 0) /* tbw something is wrong with indices */
1357 /* don't use 64-bit values for now */
1358 bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
1360 if (agg->frame_count > (64 - sh)) {
1361 IWL_DEBUG_TX_REPLY("more frames than bitmap size");
1365 /* check for success or failure according to the
1366 * transmitted bitmap and block-ack bitmap */
1367 bitmap &= agg->bitmap;
1369 /* For each frame attempted in aggregation,
1370 * update driver's record of tx frame's status. */
1371 for (i = 0; i < agg->frame_count ; i++) {
1372 ack = bitmap & (1ULL << i);
1374 IWL_DEBUG_TX_REPLY("%s ON i=%d idx=%d raw=%d\n",
1375 ack ? "ACK" : "NACK", i, (agg->start_idx + i) & 0xff,
1376 agg->start_idx + i);
1379 info = IEEE80211_SKB_CB(priv->txq[scd_flow].txb[agg->start_idx].skb[0]);
1380 memset(&info->status, 0, sizeof(info->status));
1381 info->flags = IEEE80211_TX_STAT_ACK;
1382 info->flags |= IEEE80211_TX_STAT_AMPDU;
1383 info->status.ampdu_ack_map = successes;
1384 info->status.ampdu_ack_len = agg->frame_count;
1385 iwl_hwrate_to_tx_control(priv, agg->rate_n_flags, info);
1387 IWL_DEBUG_TX_REPLY("Bitmap %llx\n", (unsigned long long)bitmap);
1393 * iwl_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
1395 * Handles block-acknowledge notification from device, which reports success
1396 * of frames sent via aggregation.
1398 void iwl_rx_reply_compressed_ba(struct iwl_priv *priv,
1399 struct iwl_rx_mem_buffer *rxb)
1401 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1402 struct iwl_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
1403 struct iwl_tx_queue *txq = NULL;
1404 struct iwl_ht_agg *agg;
1409 /* "flow" corresponds to Tx queue */
1410 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
1412 /* "ssn" is start of block-ack Tx window, corresponds to index
1413 * (in Tx queue's circular buffer) of first TFD/frame in window */
1414 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
1416 if (scd_flow >= priv->hw_params.max_txq_num) {
1418 "BUG_ON scd_flow is bigger than number of queues\n");
1422 txq = &priv->txq[scd_flow];
1423 sta_id = ba_resp->sta_id;
1425 agg = &priv->stations[sta_id].tid[tid].agg;
1427 /* Find index just before block-ack window */
1428 index = iwl_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
1430 /* TODO: Need to get this copy more safely - now good for debug */
1432 IWL_DEBUG_TX_REPLY("REPLY_COMPRESSED_BA [%d] Received from %pM, "
1435 (u8 *) &ba_resp->sta_addr_lo32,
1437 IWL_DEBUG_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
1438 "%d, scd_ssn = %d\n",
1441 (unsigned long long)le64_to_cpu(ba_resp->bitmap),
1444 IWL_DEBUG_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx \n",
1446 (unsigned long long)agg->bitmap);
1448 /* Update driver's record of ACK vs. not for each frame in window */
1449 iwl_tx_status_reply_compressed_ba(priv, agg, ba_resp);
1451 /* Release all TFDs before the SSN, i.e. all TFDs in front of
1452 * block-ack window (we assume that they've been successfully
1453 * transmitted ... if not, it's too late anyway). */
1454 if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
1455 /* calculate mac80211 ampdu sw queue to wake */
1456 int freed = iwl_tx_queue_reclaim(priv, scd_flow, index);
1457 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1459 if ((iwl_queue_space(&txq->q) > txq->q.low_mark) &&
1460 priv->mac80211_registered &&
1461 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA))
1462 ieee80211_wake_queue(priv->hw, txq->swq_id);
1464 iwl_txq_check_empty(priv, sta_id, tid, scd_flow);
1467 EXPORT_SYMBOL(iwl_rx_reply_compressed_ba);
1469 #ifdef CONFIG_IWLWIFI_DEBUG
1470 #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
1472 const char *iwl_get_tx_fail_reason(u32 status)
1474 switch (status & TX_STATUS_MSK) {
1475 case TX_STATUS_SUCCESS:
1477 TX_STATUS_ENTRY(SHORT_LIMIT);
1478 TX_STATUS_ENTRY(LONG_LIMIT);
1479 TX_STATUS_ENTRY(FIFO_UNDERRUN);
1480 TX_STATUS_ENTRY(MGMNT_ABORT);
1481 TX_STATUS_ENTRY(NEXT_FRAG);
1482 TX_STATUS_ENTRY(LIFE_EXPIRE);
1483 TX_STATUS_ENTRY(DEST_PS);
1484 TX_STATUS_ENTRY(ABORTED);
1485 TX_STATUS_ENTRY(BT_RETRY);
1486 TX_STATUS_ENTRY(STA_INVALID);
1487 TX_STATUS_ENTRY(FRAG_DROPPED);
1488 TX_STATUS_ENTRY(TID_DISABLE);
1489 TX_STATUS_ENTRY(FRAME_FLUSHED);
1490 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
1491 TX_STATUS_ENTRY(TX_LOCKED);
1492 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
1497 EXPORT_SYMBOL(iwl_get_tx_fail_reason);
1498 #endif /* CONFIG_IWLWIFI_DEBUG */