drivers/net/wireless/iwlwifi/iwl-trans-tx-pcie.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
   4  *
   5  * Portions of this file are derived from the ipw3945 project, as well
   6  * as portions of the ieee80211 subsystem header files.
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of version 2 of the GNU General Public License as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program; if not, write to the Free Software Foundation, Inc.,
  19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20  *
  21  * The full GNU General Public License is included in this distribution in the
  22  * file called LICENSE.
  23  *
  24  * Contact Information:
  25  *  Intel Linux Wireless <ilw@linux.intel.com>
  26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27  *
  28  *****************************************************************************/
  29 #include <linux/etherdevice.h>
  30 #include <linux/slab.h>
  31 #include <linux/sched.h>
  32 #include <net/mac80211.h>
  33
  34 #include "iwl-agn.h"
  35 #include "iwl-dev.h"
  36 #include "iwl-core.h"
  37 #include "iwl-io.h"
  38 #include "iwl-helpers.h"
  39 #include "iwl-trans-int-pcie.h"
  40
  41 /**
  42  * iwl_trans_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
  43  */
  44 void iwl_trans_txq_update_byte_cnt_tbl(struct iwl_trans *trans,
  45                                            struct iwl_tx_queue *txq,
  46                                            u16 byte_cnt)
  47 {
  48         struct iwlagn_scd_bc_tbl *scd_bc_tbl;
  49         struct iwl_trans_pcie *trans_pcie =
  50                 IWL_TRANS_GET_PCIE_TRANS(trans);
  51         int write_ptr = txq->q.write_ptr;
  52         int txq_id = txq->q.id;
  53         u8 sec_ctl = 0;
  54         u8 sta_id = 0;
  55         u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
  56         __le16 bc_ent;
  57
  58         scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
  59
  60         WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
  61
  62         sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
  63         sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl;
  64
  65         switch (sec_ctl & TX_CMD_SEC_MSK) {
  66         case TX_CMD_SEC_CCM:
  67                 len += CCMP_MIC_LEN;
  68                 break;
  69         case TX_CMD_SEC_TKIP:
  70                 len += TKIP_ICV_LEN;
  71                 break;
  72         case TX_CMD_SEC_WEP:
  73                 len += WEP_IV_LEN + WEP_ICV_LEN;
  74                 break;
  75         }
  76
  77         bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
  78
  79         scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
  80
  81         if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
  82                 scd_bc_tbl[txq_id].
  83                         tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
  84 }
  85
  86 /**
  87  * iwl_txq_update_write_ptr - Send new write index to hardware
  88  */
  89 void iwl_txq_update_write_ptr(struct iwl_trans *trans, struct iwl_tx_queue *txq)
  90 {
  91         u32 reg = 0;
  92         int txq_id = txq->q.id;
  93
  94         if (txq->need_update == 0)
  95                 return;
  96
  97         if (hw_params(trans).shadow_reg_enable) {
  98                 /* shadow register enabled */
  99                 iwl_write32(bus(trans), HBUS_TARG_WRPTR,
 100                             txq->q.write_ptr | (txq_id << 8));
 101         } else {
 102                 /* if we're trying to save power */
 103                 if (test_bit(STATUS_POWER_PMI, &trans->shrd->status)) {
 104                         /* wake up nic if it's powered down ...
 105                          * uCode will wake up, and interrupt us again, so next
 106                          * time we'll skip this part. */
 107                         reg = iwl_read32(bus(trans), CSR_UCODE_DRV_GP1);
 108
 109                         if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
 110                                 IWL_DEBUG_INFO(trans,
 111                                         "Tx queue %d requesting wakeup,"
 112                                         " GP1 = 0x%x\n", txq_id, reg);
 113                                 iwl_set_bit(bus(trans), CSR_GP_CNTRL,
 114                                         CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 115                                 return;
 116                         }
 117
 118                         iwl_write_direct32(bus(trans), HBUS_TARG_WRPTR,
 119                                      txq->q.write_ptr | (txq_id << 8));
 120
 121                 /*
 122                  * else not in power-save mode,
 123                  * uCode will never sleep when we're
 124                  * trying to tx (during RFKILL, we're not trying to tx).
 125                  */
 126                 } else
 127                         iwl_write32(bus(trans), HBUS_TARG_WRPTR,
 128                                     txq->q.write_ptr | (txq_id << 8));
 129         }
 130         txq->need_update = 0;
 131 }
 132
 133 static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
 134 {
 135         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 136
 137         dma_addr_t addr = get_unaligned_le32(&tb->lo);
 138         if (sizeof(dma_addr_t) > sizeof(u32))
 139                 addr |=
 140                 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
 141
 142         return addr;
 143 }
 144
 145 static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
 146 {
 147         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 148
 149         return le16_to_cpu(tb->hi_n_len) >> 4;
 150 }
 151
 152 static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
 153                                   dma_addr_t addr, u16 len)
 154 {
 155         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 156         u16 hi_n_len = len << 4;
 157
 158         put_unaligned_le32(addr, &tb->lo);
 159         if (sizeof(dma_addr_t) > sizeof(u32))
 160                 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
 161
 162         tb->hi_n_len = cpu_to_le16(hi_n_len);
 163
 164         tfd->num_tbs = idx + 1;
 165 }
 166
 167 static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
 168 {
 169         return tfd->num_tbs & 0x1f;
 170 }
 171
 172 static void iwlagn_unmap_tfd(struct iwl_trans *trans, struct iwl_cmd_meta *meta,
 173                      struct iwl_tfd *tfd, enum dma_data_direction dma_dir)
 174 {
 175         int i;
 176         int num_tbs;
 177
 178         /* Sanity check on number of chunks */
 179         num_tbs = iwl_tfd_get_num_tbs(tfd);
 180
 181         if (num_tbs >= IWL_NUM_OF_TBS) {
 182                 IWL_ERR(trans, "Too many chunks: %i\n", num_tbs);
 183                 /* @todo issue fatal error, it is quite serious situation */
 184                 return;
 185         }
 186
 187         /* Unmap tx_cmd */
 188         if (num_tbs)
 189                 dma_unmap_single(bus(trans)->dev,
 190                                 dma_unmap_addr(meta, mapping),
 191                                 dma_unmap_len(meta, len),
 192                                 DMA_BIDIRECTIONAL);
 193
 194         /* Unmap chunks, if any. */
 195         for (i = 1; i < num_tbs; i++)
 196                 dma_unmap_single(bus(trans)->dev, iwl_tfd_tb_get_addr(tfd, i),
 197                                 iwl_tfd_tb_get_len(tfd, i), dma_dir);
 198 }
 199
 200 /**
 201  * iwlagn_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
 202  * @trans - transport private data
 203  * @txq - tx queue
 204  * @index - the index of the TFD to be freed
 205  *
 206  * Does NOT advance any TFD circular buffer read/write indexes
 207  * Does NOT free the TFD itself (which is within circular buffer)
 208  */
 209 void iwlagn_txq_free_tfd(struct iwl_trans *trans, struct iwl_tx_queue *txq,
 210         int index)
 211 {
 212         struct iwl_tfd *tfd_tmp = txq->tfds;
 213
 214         iwlagn_unmap_tfd(trans, &txq->meta[index], &tfd_tmp[index],
 215                          DMA_TO_DEVICE);
 216
 217         /* free SKB */
 218         if (txq->skbs) {
 219                 struct sk_buff *skb;
 220
 221                 skb = txq->skbs[index];
 222
 223                 /* can be called from irqs-disabled context */
 224                 if (skb) {
 225                         dev_kfree_skb_any(skb);
 226                         txq->skbs[index] = NULL;
 227                 }
 228         }
 229 }
 230
 231 int iwlagn_txq_attach_buf_to_tfd(struct iwl_trans *trans,
 232                                  struct iwl_tx_queue *txq,
 233                                  dma_addr_t addr, u16 len,
 234                                  u8 reset)
 235 {
 236         struct iwl_queue *q;
 237         struct iwl_tfd *tfd, *tfd_tmp;
 238         u32 num_tbs;
 239
 240         q = &txq->q;
 241         tfd_tmp = txq->tfds;
 242         tfd = &tfd_tmp[q->write_ptr];
 243
 244         if (reset)
 245                 memset(tfd, 0, sizeof(*tfd));
 246
 247         num_tbs = iwl_tfd_get_num_tbs(tfd);
 248
 249         /* Each TFD can point to a maximum 20 Tx buffers */
 250         if (num_tbs >= IWL_NUM_OF_TBS) {
 251                 IWL_ERR(trans, "Error can not send more than %d chunks\n",
 252                           IWL_NUM_OF_TBS);
 253                 return -EINVAL;
 254         }
 255
 256         if (WARN_ON(addr & ~DMA_BIT_MASK(36)))
 257                 return -EINVAL;
 258
 259         if (unlikely(addr & ~IWL_TX_DMA_MASK))
 260                 IWL_ERR(trans, "Unaligned address = %llx\n",
 261                           (unsigned long long)addr);
 262
 263         iwl_tfd_set_tb(tfd, num_tbs, addr, len);
 264
 265         return 0;
 266 }
 267
 268 /*************** DMA-QUEUE-GENERAL-FUNCTIONS  *****
 269  * DMA services
 270  *
 271  * Theory of operation
 272  *
 273  * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
 274  * of buffer descriptors, each of which points to one or more data buffers for
 275  * the device to read from or fill.  Driver and device exchange status of each
 276  * queue via "read" and "write" pointers.  Driver keeps minimum of 2 empty
 277  * entries in each circular buffer, to protect against confusing empty and full
 278  * queue states.
 279  *
 280  * The device reads or writes the data in the queues via the device's several
 281  * DMA/FIFO channels.  Each queue is mapped to a single DMA channel.
 282  *
 283  * For Tx queue, there are low mark and high mark limits. If, after queuing
 284  * the packet for Tx, free space become < low mark, Tx queue stopped. When
 285  * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
 286  * Tx queue resumed.
 287  *
 288  ***************************************************/
 289
 290 int iwl_queue_space(const struct iwl_queue *q)
 291 {
 292         int s = q->read_ptr - q->write_ptr;
 293
 294         if (q->read_ptr > q->write_ptr)
 295                 s -= q->n_bd;
 296
 297         if (s <= 0)
 298                 s += q->n_window;
 299         /* keep some reserve to not confuse empty and full situations */
 300         s -= 2;
 301         if (s < 0)
 302                 s = 0;
 303         return s;
 304 }
 305
 306 /**
 307  * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
 308  */
 309 int iwl_queue_init(struct iwl_queue *q, int count, int slots_num, u32 id)
 310 {
 311         q->n_bd = count;
 312         q->n_window = slots_num;
 313         q->id = id;
 314
 315         /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
 316          * and iwl_queue_dec_wrap are broken. */
 317         if (WARN_ON(!is_power_of_2(count)))
 318                 return -EINVAL;
 319
 320         /* slots_num must be power-of-two size, otherwise
 321          * get_cmd_index is broken. */
 322         if (WARN_ON(!is_power_of_2(slots_num)))
 323                 return -EINVAL;
 324
 325         q->low_mark = q->n_window / 4;
 326         if (q->low_mark < 4)
 327                 q->low_mark = 4;
 328
 329         q->high_mark = q->n_window / 8;
 330         if (q->high_mark < 2)
 331                 q->high_mark = 2;
 332
 333         q->write_ptr = q->read_ptr = 0;
 334
 335         return 0;
 336 }
 337
 338 static void iwlagn_txq_inval_byte_cnt_tbl(struct iwl_trans *trans,
 339                                           struct iwl_tx_queue *txq)
 340 {
 341         struct iwl_trans_pcie *trans_pcie =
 342                 IWL_TRANS_GET_PCIE_TRANS(trans);
 343         struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
 344         int txq_id = txq->q.id;
 345         int read_ptr = txq->q.read_ptr;
 346         u8 sta_id = 0;
 347         __le16 bc_ent;
 348
 349         WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
 350
 351         if (txq_id != trans->shrd->cmd_queue)
 352                 sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id;
 353
 354         bc_ent = cpu_to_le16(1 | (sta_id << 12));
 355         scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
 356
 357         if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
 358                 scd_bc_tbl[txq_id].
 359                         tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
 360 }
 361
 362 static int iwlagn_tx_queue_set_q2ratid(struct iwl_trans *trans, u16 ra_tid,
 363                                         u16 txq_id)
 364 {
 365         u32 tbl_dw_addr;
 366         u32 tbl_dw;
 367         u16 scd_q2ratid;
 368
 369         struct iwl_trans_pcie *trans_pcie =
 370                 IWL_TRANS_GET_PCIE_TRANS(trans);
 371
 372         scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
 373
 374         tbl_dw_addr = trans_pcie->scd_base_addr +
 375                         SCD_TRANS_TBL_OFFSET_QUEUE(txq_id);
 376
 377         tbl_dw = iwl_read_targ_mem(bus(trans), tbl_dw_addr);
 378
 379         if (txq_id & 0x1)
 380                 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
 381         else
 382                 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
 383
 384         iwl_write_targ_mem(bus(trans), tbl_dw_addr, tbl_dw);
 385
 386         return 0;
 387 }
 388
 389 static void iwlagn_tx_queue_stop_scheduler(struct iwl_trans *trans, u16 txq_id)
 390 {
 391         /* Simply stop the queue, but don't change any configuration;
 392          * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
 393         iwl_write_prph(bus(trans),
 394                 SCD_QUEUE_STATUS_BITS(txq_id),
 395                 (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)|
 396                 (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
 397 }
 398
 399 void iwl_trans_set_wr_ptrs(struct iwl_trans *trans,
 400                                 int txq_id, u32 index)
 401 {
 402         iwl_write_direct32(bus(trans), HBUS_TARG_WRPTR,
 403                         (index & 0xff) | (txq_id << 8));
 404         iwl_write_prph(bus(trans), SCD_QUEUE_RDPTR(txq_id), index);
 405 }
 406
 407 void iwl_trans_tx_queue_set_status(struct iwl_priv *priv,
 408                                         struct iwl_tx_queue *txq,
 409                                         int tx_fifo_id, int scd_retry)
 410 {
 411         int txq_id = txq->q.id;
 412         int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
 413
 414         iwl_write_prph(bus(priv), SCD_QUEUE_STATUS_BITS(txq_id),
 415                         (active << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
 416                         (tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) |
 417                         (1 << SCD_QUEUE_STTS_REG_POS_WSL) |
 418                         SCD_QUEUE_STTS_REG_MSK);
 419
 420         txq->sched_retry = scd_retry;
 421
 422         IWL_DEBUG_INFO(priv, "%s %s Queue %d on FIFO %d\n",
 423                        active ? "Activate" : "Deactivate",
 424                        scd_retry ? "BA" : "AC/CMD", txq_id, tx_fifo_id);
 425 }
 426
 427 static inline int get_fifo_from_tid(struct iwl_trans_pcie *trans_pcie,
 428                                     u8 ctx, u16 tid)
 429 {
 430         const u8 *ac_to_fifo = trans_pcie->ac_to_fifo[ctx];
 431         if (likely(tid < ARRAY_SIZE(tid_to_ac)))
 432                 return ac_to_fifo[tid_to_ac[tid]];
 433
 434         /* no support for TIDs 8-15 yet */
 435         return -EINVAL;
 436 }
 437
 438 void iwl_trans_pcie_txq_agg_setup(struct iwl_priv *priv,
 439                                   enum iwl_rxon_context_id ctx, int sta_id,
 440                                   int tid, int frame_limit)
 441 {
 442         int tx_fifo, txq_id, ssn_idx;
 443         u16 ra_tid;
 444         unsigned long flags;
 445         struct iwl_tid_data *tid_data;
 446
 447         struct iwl_trans *trans = trans(priv);
 448         struct iwl_trans_pcie *trans_pcie =
 449                 IWL_TRANS_GET_PCIE_TRANS(trans);
 450
 451         if (WARN_ON(sta_id == IWL_INVALID_STATION))
 452                 return;
 453         if (WARN_ON(tid >= IWL_MAX_TID_COUNT))
 454                 return;
 455
 456         tx_fifo = get_fifo_from_tid(trans_pcie, ctx, tid);
 457         if (WARN_ON(tx_fifo < 0)) {
 458                 IWL_ERR(trans, "txq_agg_setup, bad fifo: %d\n", tx_fifo);
 459                 return;
 460         }
 461
 462         spin_lock_irqsave(&priv->shrd->sta_lock, flags);
 463         tid_data = &priv->shrd->tid_data[sta_id][tid];
 464         ssn_idx = SEQ_TO_SN(tid_data->seq_number);
 465         txq_id = tid_data->agg.txq_id;
 466         spin_unlock_irqrestore(&priv->shrd->sta_lock, flags);
 467
 468         ra_tid = BUILD_RAxTID(sta_id, tid);
 469
 470         spin_lock_irqsave(&priv->shrd->lock, flags);
 471
 472         /* Stop this Tx queue before configuring it */
 473         iwlagn_tx_queue_stop_scheduler(trans, txq_id);
 474
 475         /* Map receiver-address / traffic-ID to this queue */
 476         iwlagn_tx_queue_set_q2ratid(trans, ra_tid, txq_id);
 477
 478         /* Set this queue as a chain-building queue */
 479         iwl_set_bits_prph(bus(priv), SCD_QUEUECHAIN_SEL, (1<<txq_id));
 480
 481         /* enable aggregations for the queue */
 482         iwl_set_bits_prph(bus(priv), SCD_AGGR_SEL, (1<<txq_id));
 483
 484         /* Place first TFD at index corresponding to start sequence number.
 485          * Assumes that ssn_idx is valid (!= 0xFFF) */
 486         priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
 487         priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
 488         iwl_trans_set_wr_ptrs(trans, txq_id, ssn_idx);
 489
 490         /* Set up Tx window size and frame limit for this queue */
 491         iwl_write_targ_mem(bus(priv), trans_pcie->scd_base_addr +
 492                         SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
 493                         sizeof(u32),
 494                         ((frame_limit <<
 495                         SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
 496                         SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
 497                         ((frame_limit <<
 498                         SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
 499                         SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
 500
 501         iwl_set_bits_prph(bus(priv), SCD_INTERRUPT_MASK, (1 << txq_id));
 502
 503         /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
 504         iwl_trans_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
 505
 506         priv->txq[txq_id].sta_id = sta_id;
 507         priv->txq[txq_id].tid = tid;
 508
 509         spin_unlock_irqrestore(&priv->shrd->lock, flags);
 510 }
 511
 512 int iwl_trans_pcie_txq_agg_disable(struct iwl_priv *priv, u16 txq_id)
 513 {
 514         struct iwl_trans *trans = trans(priv);
 515         if ((IWLAGN_FIRST_AMPDU_QUEUE > txq_id) ||
 516             (IWLAGN_FIRST_AMPDU_QUEUE +
 517                 hw_params(priv).num_ampdu_queues <= txq_id)) {
 518                 IWL_ERR(priv,
 519                         "queue number out of range: %d, must be %d to %d\n",
 520                         txq_id, IWLAGN_FIRST_AMPDU_QUEUE,
 521                         IWLAGN_FIRST_AMPDU_QUEUE +
 522                         hw_params(priv).num_ampdu_queues - 1);
 523                 return -EINVAL;
 524         }
 525
 526         iwlagn_tx_queue_stop_scheduler(trans, txq_id);
 527
 528         iwl_clear_bits_prph(bus(priv), SCD_AGGR_SEL, (1 << txq_id));
 529
 530         priv->txq[txq_id].q.read_ptr = 0;
 531         priv->txq[txq_id].q.write_ptr = 0;
 532         /* supposes that ssn_idx is valid (!= 0xFFF) */
 533         iwl_trans_set_wr_ptrs(trans, txq_id, 0);
 534
 535         iwl_clear_bits_prph(bus(priv), SCD_INTERRUPT_MASK, (1 << txq_id));
 536         iwl_txq_ctx_deactivate(priv, txq_id);
 537         iwl_trans_tx_queue_set_status(priv, &priv->txq[txq_id], 0, 0);
 538
 539         return 0;
 540 }
 541
 542 /*************** HOST COMMAND QUEUE FUNCTIONS   *****/
 543
 544 /**
 545  * iwl_enqueue_hcmd - enqueue a uCode command
 546  * @priv: device private data point
 547  * @cmd: a point to the ucode command structure
 548  *
 549  * The function returns < 0 values to indicate the operation is
 550  * failed. On success, it turns the index (> 0) of command in the
 551  * command queue.
 552  */
 553 static int iwl_enqueue_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
 554 {
 555         struct iwl_tx_queue *txq = &priv(trans)->txq[trans->shrd->cmd_queue];
 556         struct iwl_queue *q = &txq->q;
 557         struct iwl_device_cmd *out_cmd;
 558         struct iwl_cmd_meta *out_meta;
 559         dma_addr_t phys_addr;
 560         unsigned long flags;
 561         u32 idx;
 562         u16 copy_size, cmd_size;
 563         bool is_ct_kill = false;
 564         bool had_nocopy = false;
 565         int i;
 566         u8 *cmd_dest;
 567 #ifdef CONFIG_IWLWIFI_DEVICE_TRACING
 568         const void *trace_bufs[IWL_MAX_CMD_TFDS + 1] = {};
 569         int trace_lens[IWL_MAX_CMD_TFDS + 1] = {};
 570         int trace_idx;
 571 #endif
 572
 573         if (test_bit(STATUS_FW_ERROR, &trans->shrd->status)) {
 574                 IWL_WARN(trans, "fw recovery, no hcmd send\n");
 575                 return -EIO;
 576         }
 577
 578         if ((trans->shrd->ucode_owner == IWL_OWNERSHIP_TM) &&
 579             !(cmd->flags & CMD_ON_DEMAND)) {
 580                 IWL_DEBUG_HC(trans, "tm own the uCode, no regular hcmd send\n");
 581                 return -EIO;
 582         }
 583
 584         copy_size = sizeof(out_cmd->hdr);
 585         cmd_size = sizeof(out_cmd->hdr);
 586
 587         /* need one for the header if the first is NOCOPY */
 588         BUILD_BUG_ON(IWL_MAX_CMD_TFDS > IWL_NUM_OF_TBS - 1);
 589
 590         for (i = 0; i < IWL_MAX_CMD_TFDS; i++) {
 591                 if (!cmd->len[i])
 592                         continue;
 593                 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) {
 594                         had_nocopy = true;
 595                 } else {
 596                         /* NOCOPY must not be followed by normal! */
 597                         if (WARN_ON(had_nocopy))
 598                                 return -EINVAL;
 599                         copy_size += cmd->len[i];
 600                 }
 601                 cmd_size += cmd->len[i];
 602         }
 603
 604         /*
 605          * If any of the command structures end up being larger than
 606          * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically
 607          * allocated into separate TFDs, then we will need to
 608          * increase the size of the buffers.
 609          */
 610         if (WARN_ON(copy_size > TFD_MAX_PAYLOAD_SIZE))
 611                 return -EINVAL;
 612
 613         if (iwl_is_rfkill(trans->shrd) || iwl_is_ctkill(trans->shrd)) {
 614                 IWL_WARN(trans, "Not sending command - %s KILL\n",
 615                          iwl_is_rfkill(trans->shrd) ? "RF" : "CT");
 616                 return -EIO;
 617         }
 618
 619         spin_lock_irqsave(&trans->hcmd_lock, flags);
 620
 621         if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
 622                 spin_unlock_irqrestore(&trans->hcmd_lock, flags);
 623
 624                 IWL_ERR(trans, "No space in command queue\n");
 625                 is_ct_kill = iwl_check_for_ct_kill(priv(trans));
 626                 if (!is_ct_kill) {
 627                         IWL_ERR(trans, "Restarting adapter queue is full\n");
 628                         iwlagn_fw_error(priv(trans), false);
 629                 }
 630                 return -ENOSPC;
 631         }
 632
 633         idx = get_cmd_index(q, q->write_ptr);
 634         out_cmd = txq->cmd[idx];
 635         out_meta = &txq->meta[idx];
 636
 637         memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
 638         if (cmd->flags & CMD_WANT_SKB)
 639                 out_meta->source = cmd;
 640         if (cmd->flags & CMD_ASYNC)
 641                 out_meta->callback = cmd->callback;
 642
 643         /* set up the header */
 644
 645         out_cmd->hdr.cmd = cmd->id;
 646         out_cmd->hdr.flags = 0;
 647         out_cmd->hdr.sequence =
 648                 cpu_to_le16(QUEUE_TO_SEQ(trans->shrd->cmd_queue) |
 649                                          INDEX_TO_SEQ(q->write_ptr));
 650
 651         /* and copy the data that needs to be copied */
 652
 653         cmd_dest = &out_cmd->cmd.payload[0];
 654         for (i = 0; i < IWL_MAX_CMD_TFDS; i++) {
 655                 if (!cmd->len[i])
 656                         continue;
 657                 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY)
 658                         break;
 659                 memcpy(cmd_dest, cmd->data[i], cmd->len[i]);
 660                 cmd_dest += cmd->len[i];
 661         }
 662
 663         IWL_DEBUG_HC(trans, "Sending command %s (#%x), seq: 0x%04X, "
 664                         "%d bytes at %d[%d]:%d\n",
 665                         get_cmd_string(out_cmd->hdr.cmd),
 666                         out_cmd->hdr.cmd,
 667                         le16_to_cpu(out_cmd->hdr.sequence), cmd_size,
 668                         q->write_ptr, idx, trans->shrd->cmd_queue);
 669
 670         phys_addr = dma_map_single(bus(trans)->dev, &out_cmd->hdr, copy_size,
 671                                 DMA_BIDIRECTIONAL);
 672         if (unlikely(dma_mapping_error(bus(trans)->dev, phys_addr))) {
 673                 idx = -ENOMEM;
 674                 goto out;
 675         }
 676
 677         dma_unmap_addr_set(out_meta, mapping, phys_addr);
 678         dma_unmap_len_set(out_meta, len, copy_size);
 679
 680         iwlagn_txq_attach_buf_to_tfd(trans, txq,
 681                                         phys_addr, copy_size, 1);
 682 #ifdef CONFIG_IWLWIFI_DEVICE_TRACING
 683         trace_bufs[0] = &out_cmd->hdr;
 684         trace_lens[0] = copy_size;
 685         trace_idx = 1;
 686 #endif
 687
 688         for (i = 0; i < IWL_MAX_CMD_TFDS; i++) {
 689                 if (!cmd->len[i])
 690                         continue;
 691                 if (!(cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY))
 692                         continue;
 693                 phys_addr = dma_map_single(bus(trans)->dev,
 694                                            (void *)cmd->data[i],
 695                                            cmd->len[i], DMA_BIDIRECTIONAL);
 696                 if (dma_mapping_error(bus(trans)->dev, phys_addr)) {
 697                         iwlagn_unmap_tfd(trans, out_meta,
 698                                          &txq->tfds[q->write_ptr],
 699                                          DMA_BIDIRECTIONAL);
 700                         idx = -ENOMEM;
 701                         goto out;
 702                 }
 703
 704                 iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr,
 705                                              cmd->len[i], 0);
 706 #ifdef CONFIG_IWLWIFI_DEVICE_TRACING
 707                 trace_bufs[trace_idx] = cmd->data[i];
 708                 trace_lens[trace_idx] = cmd->len[i];
 709                 trace_idx++;
 710 #endif
 711         }
 712
 713         out_meta->flags = cmd->flags;
 714
 715         txq->need_update = 1;
 716
 717         /* check that tracing gets all possible blocks */
 718         BUILD_BUG_ON(IWL_MAX_CMD_TFDS + 1 != 3);
 719 #ifdef CONFIG_IWLWIFI_DEVICE_TRACING
 720         trace_iwlwifi_dev_hcmd(priv(trans), cmd->flags,
 721                                trace_bufs[0], trace_lens[0],
 722                                trace_bufs[1], trace_lens[1],
 723                                trace_bufs[2], trace_lens[2]);
 724 #endif
 725
 726         /* Increment and update queue's write index */
 727         q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
 728         iwl_txq_update_write_ptr(trans, txq);
 729
 730  out:
 731         spin_unlock_irqrestore(&trans->hcmd_lock, flags);
 732         return idx;
 733 }
 734
 735 /**
 736  * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
 737  *
 738  * When FW advances 'R' index, all entries between old and new 'R' index
 739  * need to be reclaimed. As result, some free space forms.  If there is
 740  * enough free space (> low mark), wake the stack that feeds us.
 741  */
 742 static void iwl_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id, int idx)
 743 {
 744         struct iwl_tx_queue *txq = &priv->txq[txq_id];
 745         struct iwl_queue *q = &txq->q;
 746         int nfreed = 0;
 747
 748         if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) {
 749                 IWL_ERR(priv, "%s: Read index for DMA queue txq id (%d), "
 750                           "index %d is out of range [0-%d] %d %d.\n", __func__,
 751                           txq_id, idx, q->n_bd, q->write_ptr, q->read_ptr);
 752                 return;
 753         }
 754
 755         for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
 756              q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
 757
 758                 if (nfreed++ > 0) {
 759                         IWL_ERR(priv, "HCMD skipped: index (%d) %d %d\n", idx,
 760                                         q->write_ptr, q->read_ptr);
 761                         iwlagn_fw_error(priv, false);
 762                 }
 763
 764         }
 765 }
 766
 767 /**
 768  * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
 769  * @rxb: Rx buffer to reclaim
 770  *
 771  * If an Rx buffer has an async callback associated with it the callback
 772  * will be executed.  The attached skb (if present) will only be freed
 773  * if the callback returns 1
 774  */
 775 void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
 776 {
 777         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 778         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
 779         int txq_id = SEQ_TO_QUEUE(sequence);
 780         int index = SEQ_TO_INDEX(sequence);
 781         int cmd_index;
 782         struct iwl_device_cmd *cmd;
 783         struct iwl_cmd_meta *meta;
 784         struct iwl_trans *trans = trans(priv);
 785         struct iwl_tx_queue *txq = &priv->txq[trans->shrd->cmd_queue];
 786         unsigned long flags;
 787
 788         /* If a Tx command is being handled and it isn't in the actual
 789          * command queue then there a command routing bug has been introduced
 790          * in the queue management code. */
 791         if (WARN(txq_id != trans->shrd->cmd_queue,
 792                  "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
 793                   txq_id, trans->shrd->cmd_queue, sequence,
 794                   priv->txq[trans->shrd->cmd_queue].q.read_ptr,
 795                   priv->txq[trans->shrd->cmd_queue].q.write_ptr)) {
 796                 iwl_print_hex_error(priv, pkt, 32);
 797                 return;
 798         }
 799
 800         cmd_index = get_cmd_index(&txq->q, index);
 801         cmd = txq->cmd[cmd_index];
 802         meta = &txq->meta[cmd_index];
 803
 804         iwlagn_unmap_tfd(trans, meta, &txq->tfds[index],
 805                          DMA_BIDIRECTIONAL);
 806
 807         /* Input error checking is done when commands are added to queue. */
 808         if (meta->flags & CMD_WANT_SKB) {
 809                 meta->source->reply_page = (unsigned long)rxb_addr(rxb);
 810                 rxb->page = NULL;
 811         } else if (meta->callback)
 812                 meta->callback(priv, cmd, pkt);
 813
 814         spin_lock_irqsave(&trans->hcmd_lock, flags);
 815
 816         iwl_hcmd_queue_reclaim(priv, txq_id, index);
 817
 818         if (!(meta->flags & CMD_ASYNC)) {
 819                 clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status);
 820                 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
 821                                get_cmd_string(cmd->hdr.cmd));
 822                 wake_up_interruptible(&priv->wait_command_queue);
 823         }
 824
 825         meta->flags = 0;
 826
 827         spin_unlock_irqrestore(&trans->hcmd_lock, flags);
 828 }
 829
 830 const char *get_cmd_string(u8 cmd)
 831 {
 832         switch (cmd) {
 833                 IWL_CMD(REPLY_ALIVE);
 834                 IWL_CMD(REPLY_ERROR);
 835                 IWL_CMD(REPLY_RXON);
 836                 IWL_CMD(REPLY_RXON_ASSOC);
 837                 IWL_CMD(REPLY_QOS_PARAM);
 838                 IWL_CMD(REPLY_RXON_TIMING);
 839                 IWL_CMD(REPLY_ADD_STA);
 840                 IWL_CMD(REPLY_REMOVE_STA);
 841                 IWL_CMD(REPLY_REMOVE_ALL_STA);
 842                 IWL_CMD(REPLY_TXFIFO_FLUSH);
 843                 IWL_CMD(REPLY_WEPKEY);
 844                 IWL_CMD(REPLY_TX);
 845                 IWL_CMD(REPLY_LEDS_CMD);
 846                 IWL_CMD(REPLY_TX_LINK_QUALITY_CMD);
 847                 IWL_CMD(COEX_PRIORITY_TABLE_CMD);
 848                 IWL_CMD(COEX_MEDIUM_NOTIFICATION);
 849                 IWL_CMD(COEX_EVENT_CMD);
 850                 IWL_CMD(REPLY_QUIET_CMD);
 851                 IWL_CMD(REPLY_CHANNEL_SWITCH);
 852                 IWL_CMD(CHANNEL_SWITCH_NOTIFICATION);
 853                 IWL_CMD(REPLY_SPECTRUM_MEASUREMENT_CMD);
 854                 IWL_CMD(SPECTRUM_MEASURE_NOTIFICATION);
 855                 IWL_CMD(POWER_TABLE_CMD);
 856                 IWL_CMD(PM_SLEEP_NOTIFICATION);
 857                 IWL_CMD(PM_DEBUG_STATISTIC_NOTIFIC);
 858                 IWL_CMD(REPLY_SCAN_CMD);
 859                 IWL_CMD(REPLY_SCAN_ABORT_CMD);
 860                 IWL_CMD(SCAN_START_NOTIFICATION);
 861                 IWL_CMD(SCAN_RESULTS_NOTIFICATION);
 862                 IWL_CMD(SCAN_COMPLETE_NOTIFICATION);
 863                 IWL_CMD(BEACON_NOTIFICATION);
 864                 IWL_CMD(REPLY_TX_BEACON);
 865                 IWL_CMD(WHO_IS_AWAKE_NOTIFICATION);
 866                 IWL_CMD(QUIET_NOTIFICATION);
 867                 IWL_CMD(REPLY_TX_PWR_TABLE_CMD);
 868                 IWL_CMD(MEASURE_ABORT_NOTIFICATION);
 869                 IWL_CMD(REPLY_BT_CONFIG);
 870                 IWL_CMD(REPLY_STATISTICS_CMD);
 871                 IWL_CMD(STATISTICS_NOTIFICATION);
 872                 IWL_CMD(REPLY_CARD_STATE_CMD);
 873                 IWL_CMD(CARD_STATE_NOTIFICATION);
 874                 IWL_CMD(MISSED_BEACONS_NOTIFICATION);
 875                 IWL_CMD(REPLY_CT_KILL_CONFIG_CMD);
 876                 IWL_CMD(SENSITIVITY_CMD);
 877                 IWL_CMD(REPLY_PHY_CALIBRATION_CMD);
 878                 IWL_CMD(REPLY_RX_PHY_CMD);
 879                 IWL_CMD(REPLY_RX_MPDU_CMD);
 880                 IWL_CMD(REPLY_RX);
 881                 IWL_CMD(REPLY_COMPRESSED_BA);
 882                 IWL_CMD(CALIBRATION_CFG_CMD);
 883                 IWL_CMD(CALIBRATION_RES_NOTIFICATION);
 884                 IWL_CMD(CALIBRATION_COMPLETE_NOTIFICATION);
 885                 IWL_CMD(REPLY_TX_POWER_DBM_CMD);
 886                 IWL_CMD(TEMPERATURE_NOTIFICATION);
 887                 IWL_CMD(TX_ANT_CONFIGURATION_CMD);
 888                 IWL_CMD(REPLY_BT_COEX_PROFILE_NOTIF);
 889                 IWL_CMD(REPLY_BT_COEX_PRIO_TABLE);
 890                 IWL_CMD(REPLY_BT_COEX_PROT_ENV);
 891                 IWL_CMD(REPLY_WIPAN_PARAMS);
 892                 IWL_CMD(REPLY_WIPAN_RXON);
 893                 IWL_CMD(REPLY_WIPAN_RXON_TIMING);
 894                 IWL_CMD(REPLY_WIPAN_RXON_ASSOC);
 895                 IWL_CMD(REPLY_WIPAN_QOS_PARAM);
 896                 IWL_CMD(REPLY_WIPAN_WEPKEY);
 897                 IWL_CMD(REPLY_WIPAN_P2P_CHANNEL_SWITCH);
 898                 IWL_CMD(REPLY_WIPAN_NOA_NOTIFICATION);
 899                 IWL_CMD(REPLY_WIPAN_DEACTIVATION_COMPLETE);
 900                 IWL_CMD(REPLY_WOWLAN_PATTERNS);
 901                 IWL_CMD(REPLY_WOWLAN_WAKEUP_FILTER);
 902                 IWL_CMD(REPLY_WOWLAN_TSC_RSC_PARAMS);
 903                 IWL_CMD(REPLY_WOWLAN_TKIP_PARAMS);
 904                 IWL_CMD(REPLY_WOWLAN_KEK_KCK_MATERIAL);
 905                 IWL_CMD(REPLY_WOWLAN_GET_STATUS);
 906         default:
 907                 return "UNKNOWN";
 908
 909         }
 910 }
 911
 912 #define HOST_COMPLETE_TIMEOUT (2 * HZ)
 913
 914 static void iwl_generic_cmd_callback(struct iwl_priv *priv,
 915                                      struct iwl_device_cmd *cmd,
 916                                      struct iwl_rx_packet *pkt)
 917 {
 918         if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) {
 919                 IWL_ERR(priv, "Bad return from %s (0x%08X)\n",
 920                         get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags);
 921                 return;
 922         }
 923
 924 #ifdef CONFIG_IWLWIFI_DEBUG
 925         switch (cmd->hdr.cmd) {
 926         case REPLY_TX_LINK_QUALITY_CMD:
 927         case SENSITIVITY_CMD:
 928                 IWL_DEBUG_HC_DUMP(priv, "back from %s (0x%08X)\n",
 929                                 get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags);
 930                 break;
 931         default:
 932                 IWL_DEBUG_HC(priv, "back from %s (0x%08X)\n",
 933                                 get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags);
 934         }
 935 #endif
 936 }
 937
 938 static int iwl_send_cmd_async(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
 939 {
 940         int ret;
 941
 942         /* An asynchronous command can not expect an SKB to be set. */
 943         if (WARN_ON(cmd->flags & CMD_WANT_SKB))
 944                 return -EINVAL;
 945
 946         /* Assign a generic callback if one is not provided */
 947         if (!cmd->callback)
 948                 cmd->callback = iwl_generic_cmd_callback;
 949
 950         if (test_bit(STATUS_EXIT_PENDING, &trans->shrd->status))
 951                 return -EBUSY;
 952
 953         ret = iwl_enqueue_hcmd(trans, cmd);
 954         if (ret < 0) {
 955                 IWL_ERR(trans, "Error sending %s: enqueue_hcmd failed: %d\n",
 956                           get_cmd_string(cmd->id), ret);
 957                 return ret;
 958         }
 959         return 0;
 960 }
 961
 962 static int iwl_send_cmd_sync(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
 963 {
 964         int cmd_idx;
 965         int ret;
 966
 967         lockdep_assert_held(&trans->shrd->mutex);
 968
 969          /* A synchronous command can not have a callback set. */
 970         if (WARN_ON(cmd->callback))
 971                 return -EINVAL;
 972
 973         IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n",
 974                         get_cmd_string(cmd->id));
 975
 976         set_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status);
 977         IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n",
 978                         get_cmd_string(cmd->id));
 979
 980         cmd_idx = iwl_enqueue_hcmd(trans, cmd);
 981         if (cmd_idx < 0) {
 982                 ret = cmd_idx;
 983                 clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status);
 984                 IWL_ERR(trans, "Error sending %s: enqueue_hcmd failed: %d\n",
 985                           get_cmd_string(cmd->id), ret);
 986                 return ret;
 987         }
 988
 989         ret = wait_event_interruptible_timeout(priv(trans)->wait_command_queue,
 990                         !test_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status),
 991                         HOST_COMPLETE_TIMEOUT);
 992         if (!ret) {
 993                 if (test_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status)) {
 994                         IWL_ERR(trans,
 995                                 "Error sending %s: time out after %dms.\n",
 996                                 get_cmd_string(cmd->id),
 997                                 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
 998
 999                         clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status);
1000                         IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command"
1001                                  "%s\n", get_cmd_string(cmd->id));
1002                         ret = -ETIMEDOUT;
1003                         goto cancel;
1004                 }
1005         }
1006
1007         if (test_bit(STATUS_RF_KILL_HW, &trans->shrd->status)) {
1008                 IWL_ERR(trans, "Command %s aborted: RF KILL Switch\n",
1009                                get_cmd_string(cmd->id));
1010                 ret = -ECANCELED;
1011                 goto fail;
1012         }
1013         if (test_bit(STATUS_FW_ERROR, &trans->shrd->status)) {
1014                 IWL_ERR(trans, "Command %s failed: FW Error\n",
1015                                get_cmd_string(cmd->id));
1016                 ret = -EIO;
1017                 goto fail;
1018         }
1019         if ((cmd->flags & CMD_WANT_SKB) && !cmd->reply_page) {
1020                 IWL_ERR(trans, "Error: Response NULL in '%s'\n",
1021                           get_cmd_string(cmd->id));
1022                 ret = -EIO;
1023                 goto cancel;
1024         }
1025
1026         return 0;
1027
1028 cancel:
1029         if (cmd->flags & CMD_WANT_SKB) {
1030                 /*
1031                  * Cancel the CMD_WANT_SKB flag for the cmd in the
1032                  * TX cmd queue. Otherwise in case the cmd comes
1033                  * in later, it will possibly set an invalid
1034                  * address (cmd->meta.source).
1035                  */
1036                 priv(trans)->txq[trans->shrd->cmd_queue].meta[cmd_idx].flags &=
1037                                                         ~CMD_WANT_SKB;
1038         }
1039 fail:
1040         if (cmd->reply_page) {
1041                 iwl_free_pages(trans->shrd, cmd->reply_page);
1042                 cmd->reply_page = 0;
1043         }
1044
1045         return ret;
1046 }
1047
1048 int iwl_trans_pcie_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
1049 {
1050         if (cmd->flags & CMD_ASYNC)
1051                 return iwl_send_cmd_async(trans, cmd);
1052
1053         return iwl_send_cmd_sync(trans, cmd);
1054 }
1055
1056 int iwl_trans_pcie_send_cmd_pdu(struct iwl_trans *trans, u8 id, u32 flags,
1057                 u16 len, const void *data)
1058 {
1059         struct iwl_host_cmd cmd = {
1060                 .id = id,
1061                 .len = { len, },
1062                 .data = { data, },
1063                 .flags = flags,
1064         };
1065
1066         return iwl_trans_pcie_send_cmd(trans, &cmd);
1067 }
1068
1069 /* Frees buffers until index _not_ inclusive */
1070 void iwl_tx_queue_reclaim(struct iwl_trans *trans, int txq_id, int index,
1071                             struct sk_buff_head *skbs)
1072 {
1073         struct iwl_tx_queue *txq = &priv(trans)->txq[txq_id];
1074         struct iwl_queue *q = &txq->q;
1075         int last_to_free;
1076
1077         /*Since we free until index _not_ inclusive, the one before index is
1078          * the last we will free. This one must be used */
1079         last_to_free = iwl_queue_dec_wrap(index, q->n_bd);
1080
1081         if ((index >= q->n_bd) ||
1082            (iwl_queue_used(q, last_to_free) == 0)) {
1083                 IWL_ERR(trans, "%s: Read index for DMA queue txq id (%d), "
1084                           "last_to_free %d is out of range [0-%d] %d %d.\n",
1085                           __func__, txq_id, last_to_free, q->n_bd,
1086                           q->write_ptr, q->read_ptr);
1087                 return;
1088         }
1089
1090         IWL_DEBUG_TX_REPLY(trans, "reclaim: [%d, %d, %d]\n", txq_id,
1091                            q->read_ptr, index);
1092
1093         if (WARN_ON(!skb_queue_empty(skbs)))
1094                 return;
1095
1096         for (;
1097              q->read_ptr != index;
1098              q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1099
1100                 if (WARN_ON_ONCE(txq->skbs[txq->q.read_ptr] == NULL))
1101                         continue;
1102
1103                 __skb_queue_tail(skbs, txq->skbs[txq->q.read_ptr]);
1104
1105                 txq->skbs[txq->q.read_ptr] = NULL;
1106
1107                 iwlagn_txq_inval_byte_cnt_tbl(trans, txq);
1108
1109                 iwlagn_txq_free_tfd(trans, txq, txq->q.read_ptr);
1110         }
1111 }