1 /******************************************************************************
3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
29 #include <linux/etherdevice.h>
30 #include <linux/slab.h>
31 #include <linux/sched.h>
33 /* TODO: remove include to iwl-dev.h */
35 #include "iwl-debug.h"
39 #include "iwl-agn-hw.h"
40 #include "iwl-helpers.h"
41 #include "iwl-trans-int-pcie.h"
43 #define IWL_TX_CRC_SIZE 4
44 #define IWL_TX_DELIMITER_SIZE 4
47 * iwl_trans_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
49 void iwl_trans_txq_update_byte_cnt_tbl(struct iwl_trans *trans,
50 struct iwl_tx_queue *txq,
53 struct iwlagn_scd_bc_tbl *scd_bc_tbl;
54 struct iwl_trans_pcie *trans_pcie =
55 IWL_TRANS_GET_PCIE_TRANS(trans);
56 int write_ptr = txq->q.write_ptr;
57 int txq_id = txq->q.id;
60 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
63 scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
65 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
67 sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
68 sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl;
70 switch (sec_ctl & TX_CMD_SEC_MSK) {
78 len += WEP_IV_LEN + WEP_ICV_LEN;
82 bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
84 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
86 if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
88 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
92 * iwl_txq_update_write_ptr - Send new write index to hardware
94 void iwl_txq_update_write_ptr(struct iwl_trans *trans, struct iwl_tx_queue *txq)
97 int txq_id = txq->q.id;
99 if (txq->need_update == 0)
102 if (hw_params(trans).shadow_reg_enable) {
103 /* shadow register enabled */
104 iwl_write32(bus(trans), HBUS_TARG_WRPTR,
105 txq->q.write_ptr | (txq_id << 8));
107 /* if we're trying to save power */
108 if (test_bit(STATUS_POWER_PMI, &trans->shrd->status)) {
109 /* wake up nic if it's powered down ...
110 * uCode will wake up, and interrupt us again, so next
111 * time we'll skip this part. */
112 reg = iwl_read32(bus(trans), CSR_UCODE_DRV_GP1);
114 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
115 IWL_DEBUG_INFO(trans,
116 "Tx queue %d requesting wakeup,"
117 " GP1 = 0x%x\n", txq_id, reg);
118 iwl_set_bit(bus(trans), CSR_GP_CNTRL,
119 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
123 iwl_write_direct32(bus(trans), HBUS_TARG_WRPTR,
124 txq->q.write_ptr | (txq_id << 8));
127 * else not in power-save mode,
128 * uCode will never sleep when we're
129 * trying to tx (during RFKILL, we're not trying to tx).
132 iwl_write32(bus(trans), HBUS_TARG_WRPTR,
133 txq->q.write_ptr | (txq_id << 8));
135 txq->need_update = 0;
138 static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
140 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
142 dma_addr_t addr = get_unaligned_le32(&tb->lo);
143 if (sizeof(dma_addr_t) > sizeof(u32))
145 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
150 static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
152 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
154 return le16_to_cpu(tb->hi_n_len) >> 4;
157 static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
158 dma_addr_t addr, u16 len)
160 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
161 u16 hi_n_len = len << 4;
163 put_unaligned_le32(addr, &tb->lo);
164 if (sizeof(dma_addr_t) > sizeof(u32))
165 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
167 tb->hi_n_len = cpu_to_le16(hi_n_len);
169 tfd->num_tbs = idx + 1;
172 static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
174 return tfd->num_tbs & 0x1f;
177 static void iwlagn_unmap_tfd(struct iwl_trans *trans, struct iwl_cmd_meta *meta,
178 struct iwl_tfd *tfd, enum dma_data_direction dma_dir)
183 /* Sanity check on number of chunks */
184 num_tbs = iwl_tfd_get_num_tbs(tfd);
186 if (num_tbs >= IWL_NUM_OF_TBS) {
187 IWL_ERR(trans, "Too many chunks: %i\n", num_tbs);
188 /* @todo issue fatal error, it is quite serious situation */
194 dma_unmap_single(bus(trans)->dev,
195 dma_unmap_addr(meta, mapping),
196 dma_unmap_len(meta, len),
199 /* Unmap chunks, if any. */
200 for (i = 1; i < num_tbs; i++)
201 dma_unmap_single(bus(trans)->dev, iwl_tfd_tb_get_addr(tfd, i),
202 iwl_tfd_tb_get_len(tfd, i), dma_dir);
206 * iwlagn_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
207 * @trans - transport private data
209 * @index - the index of the TFD to be freed
211 * Does NOT advance any TFD circular buffer read/write indexes
212 * Does NOT free the TFD itself (which is within circular buffer)
214 void iwlagn_txq_free_tfd(struct iwl_trans *trans, struct iwl_tx_queue *txq,
217 struct iwl_tfd *tfd_tmp = txq->tfds;
219 iwlagn_unmap_tfd(trans, &txq->meta[index], &tfd_tmp[index],
226 skb = txq->skbs[index];
228 /* can be called from irqs-disabled context */
230 dev_kfree_skb_any(skb);
231 txq->skbs[index] = NULL;
236 int iwlagn_txq_attach_buf_to_tfd(struct iwl_trans *trans,
237 struct iwl_tx_queue *txq,
238 dma_addr_t addr, u16 len,
242 struct iwl_tfd *tfd, *tfd_tmp;
247 tfd = &tfd_tmp[q->write_ptr];
250 memset(tfd, 0, sizeof(*tfd));
252 num_tbs = iwl_tfd_get_num_tbs(tfd);
254 /* Each TFD can point to a maximum 20 Tx buffers */
255 if (num_tbs >= IWL_NUM_OF_TBS) {
256 IWL_ERR(trans, "Error can not send more than %d chunks\n",
261 if (WARN_ON(addr & ~DMA_BIT_MASK(36)))
264 if (unlikely(addr & ~IWL_TX_DMA_MASK))
265 IWL_ERR(trans, "Unaligned address = %llx\n",
266 (unsigned long long)addr);
268 iwl_tfd_set_tb(tfd, num_tbs, addr, len);
273 /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
276 * Theory of operation
278 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
279 * of buffer descriptors, each of which points to one or more data buffers for
280 * the device to read from or fill. Driver and device exchange status of each
281 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
282 * entries in each circular buffer, to protect against confusing empty and full
285 * The device reads or writes the data in the queues via the device's several
286 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
288 * For Tx queue, there are low mark and high mark limits. If, after queuing
289 * the packet for Tx, free space become < low mark, Tx queue stopped. When
290 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
293 ***************************************************/
295 int iwl_queue_space(const struct iwl_queue *q)
297 int s = q->read_ptr - q->write_ptr;
299 if (q->read_ptr > q->write_ptr)
304 /* keep some reserve to not confuse empty and full situations */
312 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
314 int iwl_queue_init(struct iwl_queue *q, int count, int slots_num, u32 id)
317 q->n_window = slots_num;
320 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
321 * and iwl_queue_dec_wrap are broken. */
322 if (WARN_ON(!is_power_of_2(count)))
325 /* slots_num must be power-of-two size, otherwise
326 * get_cmd_index is broken. */
327 if (WARN_ON(!is_power_of_2(slots_num)))
330 q->low_mark = q->n_window / 4;
334 q->high_mark = q->n_window / 8;
335 if (q->high_mark < 2)
338 q->write_ptr = q->read_ptr = 0;
343 static void iwlagn_txq_inval_byte_cnt_tbl(struct iwl_trans *trans,
344 struct iwl_tx_queue *txq)
346 struct iwl_trans_pcie *trans_pcie =
347 IWL_TRANS_GET_PCIE_TRANS(trans);
348 struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
349 int txq_id = txq->q.id;
350 int read_ptr = txq->q.read_ptr;
354 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
356 if (txq_id != trans->shrd->cmd_queue)
357 sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id;
359 bc_ent = cpu_to_le16(1 | (sta_id << 12));
360 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
362 if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
364 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
367 static int iwlagn_tx_queue_set_q2ratid(struct iwl_trans *trans, u16 ra_tid,
374 struct iwl_trans_pcie *trans_pcie =
375 IWL_TRANS_GET_PCIE_TRANS(trans);
377 scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
379 tbl_dw_addr = trans_pcie->scd_base_addr +
380 SCD_TRANS_TBL_OFFSET_QUEUE(txq_id);
382 tbl_dw = iwl_read_targ_mem(bus(trans), tbl_dw_addr);
385 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
387 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
389 iwl_write_targ_mem(bus(trans), tbl_dw_addr, tbl_dw);
394 static void iwlagn_tx_queue_stop_scheduler(struct iwl_trans *trans, u16 txq_id)
396 /* Simply stop the queue, but don't change any configuration;
397 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
398 iwl_write_prph(bus(trans),
399 SCD_QUEUE_STATUS_BITS(txq_id),
400 (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)|
401 (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
404 void iwl_trans_set_wr_ptrs(struct iwl_trans *trans,
405 int txq_id, u32 index)
407 iwl_write_direct32(bus(trans), HBUS_TARG_WRPTR,
408 (index & 0xff) | (txq_id << 8));
409 iwl_write_prph(bus(trans), SCD_QUEUE_RDPTR(txq_id), index);
412 void iwl_trans_tx_queue_set_status(struct iwl_trans *trans,
413 struct iwl_tx_queue *txq,
414 int tx_fifo_id, int scd_retry)
416 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
417 int txq_id = txq->q.id;
419 test_bit(txq_id, &trans_pcie->txq_ctx_active_msk) ? 1 : 0;
421 iwl_write_prph(bus(trans), SCD_QUEUE_STATUS_BITS(txq_id),
422 (active << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
423 (tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) |
424 (1 << SCD_QUEUE_STTS_REG_POS_WSL) |
425 SCD_QUEUE_STTS_REG_MSK);
427 txq->sched_retry = scd_retry;
429 IWL_DEBUG_INFO(trans, "%s %s Queue %d on FIFO %d\n",
430 active ? "Activate" : "Deactivate",
431 scd_retry ? "BA" : "AC/CMD", txq_id, tx_fifo_id);
434 static inline int get_fifo_from_tid(struct iwl_trans_pcie *trans_pcie,
437 const u8 *ac_to_fifo = trans_pcie->ac_to_fifo[ctx];
438 if (likely(tid < ARRAY_SIZE(tid_to_ac)))
439 return ac_to_fifo[tid_to_ac[tid]];
441 /* no support for TIDs 8-15 yet */
445 void iwl_trans_pcie_tx_agg_setup(struct iwl_trans *trans,
446 enum iwl_rxon_context_id ctx, int sta_id,
447 int tid, int frame_limit)
449 int tx_fifo, txq_id, ssn_idx;
452 struct iwl_tid_data *tid_data;
454 struct iwl_trans_pcie *trans_pcie =
455 IWL_TRANS_GET_PCIE_TRANS(trans);
457 if (WARN_ON(sta_id == IWL_INVALID_STATION))
459 if (WARN_ON(tid >= IWL_MAX_TID_COUNT))
462 tx_fifo = get_fifo_from_tid(trans_pcie, ctx, tid);
463 if (WARN_ON(tx_fifo < 0)) {
464 IWL_ERR(trans, "txq_agg_setup, bad fifo: %d\n", tx_fifo);
468 spin_lock_irqsave(&trans->shrd->sta_lock, flags);
469 tid_data = &trans->shrd->tid_data[sta_id][tid];
470 ssn_idx = SEQ_TO_SN(tid_data->seq_number);
471 txq_id = tid_data->agg.txq_id;
472 spin_unlock_irqrestore(&trans->shrd->sta_lock, flags);
474 ra_tid = BUILD_RAxTID(sta_id, tid);
476 spin_lock_irqsave(&trans->shrd->lock, flags);
478 /* Stop this Tx queue before configuring it */
479 iwlagn_tx_queue_stop_scheduler(trans, txq_id);
481 /* Map receiver-address / traffic-ID to this queue */
482 iwlagn_tx_queue_set_q2ratid(trans, ra_tid, txq_id);
484 /* Set this queue as a chain-building queue */
485 iwl_set_bits_prph(bus(trans), SCD_QUEUECHAIN_SEL, (1<<txq_id));
487 /* enable aggregations for the queue */
488 iwl_set_bits_prph(bus(trans), SCD_AGGR_SEL, (1<<txq_id));
490 /* Place first TFD at index corresponding to start sequence number.
491 * Assumes that ssn_idx is valid (!= 0xFFF) */
492 trans_pcie->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
493 trans_pcie->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
494 iwl_trans_set_wr_ptrs(trans, txq_id, ssn_idx);
496 /* Set up Tx window size and frame limit for this queue */
497 iwl_write_targ_mem(bus(trans), trans_pcie->scd_base_addr +
498 SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
501 SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
502 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
504 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
505 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
507 iwl_set_bits_prph(bus(trans), SCD_INTERRUPT_MASK, (1 << txq_id));
509 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
510 iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[txq_id],
513 trans_pcie->txq[txq_id].sta_id = sta_id;
514 trans_pcie->txq[txq_id].tid = tid;
516 spin_unlock_irqrestore(&trans->shrd->lock, flags);
520 * Find first available (lowest unused) Tx Queue, mark it "active".
521 * Called only when finding queue for aggregation.
522 * Should never return anything < 7, because they should already
523 * be in use as EDCA AC (0-3), Command (4), reserved (5, 6)
525 static int iwlagn_txq_ctx_activate_free(struct iwl_trans *trans)
527 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
530 for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++)
531 if (!test_and_set_bit(txq_id,
532 &trans_pcie->txq_ctx_active_msk))
537 int iwl_trans_pcie_tx_agg_alloc(struct iwl_trans *trans,
538 enum iwl_rxon_context_id ctx, int sta_id,
541 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
542 struct iwl_tid_data *tid_data;
546 txq_id = iwlagn_txq_ctx_activate_free(trans);
548 IWL_ERR(trans, "No free aggregation queue available\n");
552 spin_lock_irqsave(&trans->shrd->sta_lock, flags);
553 tid_data = &trans->shrd->tid_data[sta_id][tid];
554 *ssn = SEQ_TO_SN(tid_data->seq_number);
555 tid_data->agg.txq_id = txq_id;
556 iwl_set_swq_id(&trans_pcie->txq[txq_id], get_ac_from_tid(tid), txq_id);
558 tid_data = &trans->shrd->tid_data[sta_id][tid];
559 if (tid_data->tfds_in_queue == 0) {
560 IWL_DEBUG_HT(trans, "HW queue is empty\n");
561 tid_data->agg.state = IWL_AGG_ON;
562 iwl_start_tx_ba_trans_ready(priv(trans), ctx, sta_id, tid);
564 IWL_DEBUG_HT(trans, "HW queue is NOT empty: %d packets in HW"
565 "queue\n", tid_data->tfds_in_queue);
566 tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA;
568 spin_unlock_irqrestore(&trans->shrd->sta_lock, flags);
573 void iwl_trans_pcie_txq_agg_disable(struct iwl_trans *trans, int txq_id)
575 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
576 iwlagn_tx_queue_stop_scheduler(trans, txq_id);
578 iwl_clear_bits_prph(bus(trans), SCD_AGGR_SEL, (1 << txq_id));
580 trans_pcie->txq[txq_id].q.read_ptr = 0;
581 trans_pcie->txq[txq_id].q.write_ptr = 0;
582 /* supposes that ssn_idx is valid (!= 0xFFF) */
583 iwl_trans_set_wr_ptrs(trans, txq_id, 0);
585 iwl_clear_bits_prph(bus(trans), SCD_INTERRUPT_MASK, (1 << txq_id));
586 iwl_txq_ctx_deactivate(trans_pcie, txq_id);
587 iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[txq_id], 0, 0);
590 int iwl_trans_pcie_tx_agg_disable(struct iwl_trans *trans,
591 enum iwl_rxon_context_id ctx, int sta_id,
594 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
596 int read_ptr, write_ptr;
597 struct iwl_tid_data *tid_data;
600 spin_lock_irqsave(&trans->shrd->sta_lock, flags);
602 tid_data = &trans->shrd->tid_data[sta_id][tid];
603 txq_id = tid_data->agg.txq_id;
605 if ((IWLAGN_FIRST_AMPDU_QUEUE > txq_id) ||
606 (IWLAGN_FIRST_AMPDU_QUEUE +
607 hw_params(trans).num_ampdu_queues <= txq_id)) {
609 "queue number out of range: %d, must be %d to %d\n",
610 txq_id, IWLAGN_FIRST_AMPDU_QUEUE,
611 IWLAGN_FIRST_AMPDU_QUEUE +
612 hw_params(trans).num_ampdu_queues - 1);
613 spin_unlock_irqrestore(&trans->shrd->sta_lock, flags);
617 switch (trans->shrd->tid_data[sta_id][tid].agg.state) {
618 case IWL_EMPTYING_HW_QUEUE_ADDBA:
620 * This can happen if the peer stops aggregation
621 * again before we've had a chance to drain the
622 * queue we selected previously, i.e. before the
623 * session was really started completely.
625 IWL_DEBUG_HT(trans, "AGG stop before setup done\n");
630 IWL_WARN(trans, "Stopping AGG while state not ON"
634 write_ptr = trans_pcie->txq[txq_id].q.write_ptr;
635 read_ptr = trans_pcie->txq[txq_id].q.read_ptr;
637 /* The queue is not empty */
638 if (write_ptr != read_ptr) {
639 IWL_DEBUG_HT(trans, "Stopping a non empty AGG HW QUEUE\n");
640 trans->shrd->tid_data[sta_id][tid].agg.state =
641 IWL_EMPTYING_HW_QUEUE_DELBA;
642 spin_unlock_irqrestore(&trans->shrd->sta_lock, flags);
646 IWL_DEBUG_HT(trans, "HW queue is empty\n");
648 trans->shrd->tid_data[sta_id][tid].agg.state = IWL_AGG_OFF;
650 /* do not restore/save irqs */
651 spin_unlock(&trans->shrd->sta_lock);
652 spin_lock(&trans->shrd->lock);
654 iwl_trans_pcie_txq_agg_disable(trans, txq_id);
656 spin_unlock_irqrestore(&trans->shrd->lock, flags);
658 iwl_stop_tx_ba_trans_ready(priv(trans), ctx, sta_id, tid);
663 /*************** HOST COMMAND QUEUE FUNCTIONS *****/
666 * iwl_enqueue_hcmd - enqueue a uCode command
667 * @priv: device private data point
668 * @cmd: a point to the ucode command structure
670 * The function returns < 0 values to indicate the operation is
671 * failed. On success, it turns the index (> 0) of command in the
674 static int iwl_enqueue_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
676 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
677 struct iwl_tx_queue *txq = &trans_pcie->txq[trans->shrd->cmd_queue];
678 struct iwl_queue *q = &txq->q;
679 struct iwl_device_cmd *out_cmd;
680 struct iwl_cmd_meta *out_meta;
681 dma_addr_t phys_addr;
684 u16 copy_size, cmd_size;
685 bool is_ct_kill = false;
686 bool had_nocopy = false;
689 #ifdef CONFIG_IWLWIFI_DEVICE_TRACING
690 const void *trace_bufs[IWL_MAX_CMD_TFDS + 1] = {};
691 int trace_lens[IWL_MAX_CMD_TFDS + 1] = {};
695 if (test_bit(STATUS_FW_ERROR, &trans->shrd->status)) {
696 IWL_WARN(trans, "fw recovery, no hcmd send\n");
700 if ((trans->shrd->ucode_owner == IWL_OWNERSHIP_TM) &&
701 !(cmd->flags & CMD_ON_DEMAND)) {
702 IWL_DEBUG_HC(trans, "tm own the uCode, no regular hcmd send\n");
706 copy_size = sizeof(out_cmd->hdr);
707 cmd_size = sizeof(out_cmd->hdr);
709 /* need one for the header if the first is NOCOPY */
710 BUILD_BUG_ON(IWL_MAX_CMD_TFDS > IWL_NUM_OF_TBS - 1);
712 for (i = 0; i < IWL_MAX_CMD_TFDS; i++) {
715 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) {
718 /* NOCOPY must not be followed by normal! */
719 if (WARN_ON(had_nocopy))
721 copy_size += cmd->len[i];
723 cmd_size += cmd->len[i];
727 * If any of the command structures end up being larger than
728 * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically
729 * allocated into separate TFDs, then we will need to
730 * increase the size of the buffers.
732 if (WARN_ON(copy_size > TFD_MAX_PAYLOAD_SIZE))
735 if (iwl_is_rfkill(trans->shrd) || iwl_is_ctkill(trans->shrd)) {
736 IWL_WARN(trans, "Not sending command - %s KILL\n",
737 iwl_is_rfkill(trans->shrd) ? "RF" : "CT");
741 spin_lock_irqsave(&trans->hcmd_lock, flags);
743 if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
744 spin_unlock_irqrestore(&trans->hcmd_lock, flags);
746 IWL_ERR(trans, "No space in command queue\n");
747 is_ct_kill = iwl_check_for_ct_kill(priv(trans));
749 IWL_ERR(trans, "Restarting adapter queue is full\n");
750 iwlagn_fw_error(priv(trans), false);
755 idx = get_cmd_index(q, q->write_ptr);
756 out_cmd = txq->cmd[idx];
757 out_meta = &txq->meta[idx];
759 memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
760 if (cmd->flags & CMD_WANT_SKB)
761 out_meta->source = cmd;
762 if (cmd->flags & CMD_ASYNC)
763 out_meta->callback = cmd->callback;
765 /* set up the header */
767 out_cmd->hdr.cmd = cmd->id;
768 out_cmd->hdr.flags = 0;
769 out_cmd->hdr.sequence =
770 cpu_to_le16(QUEUE_TO_SEQ(trans->shrd->cmd_queue) |
771 INDEX_TO_SEQ(q->write_ptr));
773 /* and copy the data that needs to be copied */
775 cmd_dest = &out_cmd->cmd.payload[0];
776 for (i = 0; i < IWL_MAX_CMD_TFDS; i++) {
779 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY)
781 memcpy(cmd_dest, cmd->data[i], cmd->len[i]);
782 cmd_dest += cmd->len[i];
785 IWL_DEBUG_HC(trans, "Sending command %s (#%x), seq: 0x%04X, "
786 "%d bytes at %d[%d]:%d\n",
787 get_cmd_string(out_cmd->hdr.cmd),
789 le16_to_cpu(out_cmd->hdr.sequence), cmd_size,
790 q->write_ptr, idx, trans->shrd->cmd_queue);
792 phys_addr = dma_map_single(bus(trans)->dev, &out_cmd->hdr, copy_size,
794 if (unlikely(dma_mapping_error(bus(trans)->dev, phys_addr))) {
799 dma_unmap_addr_set(out_meta, mapping, phys_addr);
800 dma_unmap_len_set(out_meta, len, copy_size);
802 iwlagn_txq_attach_buf_to_tfd(trans, txq,
803 phys_addr, copy_size, 1);
804 #ifdef CONFIG_IWLWIFI_DEVICE_TRACING
805 trace_bufs[0] = &out_cmd->hdr;
806 trace_lens[0] = copy_size;
810 for (i = 0; i < IWL_MAX_CMD_TFDS; i++) {
813 if (!(cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY))
815 phys_addr = dma_map_single(bus(trans)->dev,
816 (void *)cmd->data[i],
817 cmd->len[i], DMA_BIDIRECTIONAL);
818 if (dma_mapping_error(bus(trans)->dev, phys_addr)) {
819 iwlagn_unmap_tfd(trans, out_meta,
820 &txq->tfds[q->write_ptr],
826 iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr,
828 #ifdef CONFIG_IWLWIFI_DEVICE_TRACING
829 trace_bufs[trace_idx] = cmd->data[i];
830 trace_lens[trace_idx] = cmd->len[i];
835 out_meta->flags = cmd->flags;
837 txq->need_update = 1;
839 /* check that tracing gets all possible blocks */
840 BUILD_BUG_ON(IWL_MAX_CMD_TFDS + 1 != 3);
841 #ifdef CONFIG_IWLWIFI_DEVICE_TRACING
842 trace_iwlwifi_dev_hcmd(priv(trans), cmd->flags,
843 trace_bufs[0], trace_lens[0],
844 trace_bufs[1], trace_lens[1],
845 trace_bufs[2], trace_lens[2]);
848 /* Increment and update queue's write index */
849 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
850 iwl_txq_update_write_ptr(trans, txq);
853 spin_unlock_irqrestore(&trans->hcmd_lock, flags);
858 * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
860 * When FW advances 'R' index, all entries between old and new 'R' index
861 * need to be reclaimed. As result, some free space forms. If there is
862 * enough free space (> low mark), wake the stack that feeds us.
864 static void iwl_hcmd_queue_reclaim(struct iwl_trans *trans, int txq_id,
867 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
868 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
869 struct iwl_queue *q = &txq->q;
872 if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) {
873 IWL_ERR(trans, "%s: Read index for DMA queue txq id (%d), "
874 "index %d is out of range [0-%d] %d %d.\n", __func__,
875 txq_id, idx, q->n_bd, q->write_ptr, q->read_ptr);
879 for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
880 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
883 IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n", idx,
884 q->write_ptr, q->read_ptr);
885 iwlagn_fw_error(priv(trans), false);
892 * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
893 * @rxb: Rx buffer to reclaim
895 * If an Rx buffer has an async callback associated with it the callback
896 * will be executed. The attached skb (if present) will only be freed
897 * if the callback returns 1
899 void iwl_tx_cmd_complete(struct iwl_trans *trans, struct iwl_rx_mem_buffer *rxb)
901 struct iwl_rx_packet *pkt = rxb_addr(rxb);
902 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
903 int txq_id = SEQ_TO_QUEUE(sequence);
904 int index = SEQ_TO_INDEX(sequence);
906 struct iwl_device_cmd *cmd;
907 struct iwl_cmd_meta *meta;
908 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
909 struct iwl_tx_queue *txq = &trans_pcie->txq[trans->shrd->cmd_queue];
912 /* If a Tx command is being handled and it isn't in the actual
913 * command queue then there a command routing bug has been introduced
914 * in the queue management code. */
915 if (WARN(txq_id != trans->shrd->cmd_queue,
916 "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
917 txq_id, trans->shrd->cmd_queue, sequence,
918 trans_pcie->txq[trans->shrd->cmd_queue].q.read_ptr,
919 trans_pcie->txq[trans->shrd->cmd_queue].q.write_ptr)) {
920 iwl_print_hex_error(trans, pkt, 32);
924 cmd_index = get_cmd_index(&txq->q, index);
925 cmd = txq->cmd[cmd_index];
926 meta = &txq->meta[cmd_index];
928 iwlagn_unmap_tfd(trans, meta, &txq->tfds[index],
931 /* Input error checking is done when commands are added to queue. */
932 if (meta->flags & CMD_WANT_SKB) {
933 meta->source->reply_page = (unsigned long)rxb_addr(rxb);
935 } else if (meta->callback)
936 meta->callback(trans->shrd, cmd, pkt);
938 spin_lock_irqsave(&trans->hcmd_lock, flags);
940 iwl_hcmd_queue_reclaim(trans, txq_id, index);
942 if (!(meta->flags & CMD_ASYNC)) {
943 clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status);
944 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
945 get_cmd_string(cmd->hdr.cmd));
946 wake_up_interruptible(&trans->shrd->wait_command_queue);
951 spin_unlock_irqrestore(&trans->hcmd_lock, flags);
954 #define HOST_COMPLETE_TIMEOUT (2 * HZ)
956 static void iwl_generic_cmd_callback(struct iwl_shared *shrd,
957 struct iwl_device_cmd *cmd,
958 struct iwl_rx_packet *pkt)
960 if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) {
961 IWL_ERR(shrd->trans, "Bad return from %s (0x%08X)\n",
962 get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags);
966 #ifdef CONFIG_IWLWIFI_DEBUG
967 switch (cmd->hdr.cmd) {
968 case REPLY_TX_LINK_QUALITY_CMD:
969 case SENSITIVITY_CMD:
970 IWL_DEBUG_HC_DUMP(shrd->trans, "back from %s (0x%08X)\n",
971 get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags);
974 IWL_DEBUG_HC(shrd->trans, "back from %s (0x%08X)\n",
975 get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags);
980 static int iwl_send_cmd_async(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
984 /* An asynchronous command can not expect an SKB to be set. */
985 if (WARN_ON(cmd->flags & CMD_WANT_SKB))
988 /* Assign a generic callback if one is not provided */
990 cmd->callback = iwl_generic_cmd_callback;
992 if (test_bit(STATUS_EXIT_PENDING, &trans->shrd->status))
995 ret = iwl_enqueue_hcmd(trans, cmd);
997 IWL_ERR(trans, "Error sending %s: enqueue_hcmd failed: %d\n",
998 get_cmd_string(cmd->id), ret);
1004 static int iwl_send_cmd_sync(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
1006 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1010 lockdep_assert_held(&trans->shrd->mutex);
1012 /* A synchronous command can not have a callback set. */
1013 if (WARN_ON(cmd->callback))
1016 IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n",
1017 get_cmd_string(cmd->id));
1019 set_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status);
1020 IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n",
1021 get_cmd_string(cmd->id));
1023 cmd_idx = iwl_enqueue_hcmd(trans, cmd);
1026 clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status);
1027 IWL_ERR(trans, "Error sending %s: enqueue_hcmd failed: %d\n",
1028 get_cmd_string(cmd->id), ret);
1032 ret = wait_event_interruptible_timeout(trans->shrd->wait_command_queue,
1033 !test_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status),
1034 HOST_COMPLETE_TIMEOUT);
1036 if (test_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status)) {
1038 "Error sending %s: time out after %dms.\n",
1039 get_cmd_string(cmd->id),
1040 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
1042 clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status);
1043 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command"
1044 "%s\n", get_cmd_string(cmd->id));
1050 if (test_bit(STATUS_RF_KILL_HW, &trans->shrd->status)) {
1051 IWL_ERR(trans, "Command %s aborted: RF KILL Switch\n",
1052 get_cmd_string(cmd->id));
1056 if (test_bit(STATUS_FW_ERROR, &trans->shrd->status)) {
1057 IWL_ERR(trans, "Command %s failed: FW Error\n",
1058 get_cmd_string(cmd->id));
1062 if ((cmd->flags & CMD_WANT_SKB) && !cmd->reply_page) {
1063 IWL_ERR(trans, "Error: Response NULL in '%s'\n",
1064 get_cmd_string(cmd->id));
1072 if (cmd->flags & CMD_WANT_SKB) {
1074 * Cancel the CMD_WANT_SKB flag for the cmd in the
1075 * TX cmd queue. Otherwise in case the cmd comes
1076 * in later, it will possibly set an invalid
1077 * address (cmd->meta.source).
1079 trans_pcie->txq[trans->shrd->cmd_queue].meta[cmd_idx].flags &=
1083 if (cmd->reply_page) {
1084 iwl_free_pages(trans->shrd, cmd->reply_page);
1085 cmd->reply_page = 0;
1091 int iwl_trans_pcie_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
1093 if (cmd->flags & CMD_ASYNC)
1094 return iwl_send_cmd_async(trans, cmd);
1096 return iwl_send_cmd_sync(trans, cmd);
1099 int iwl_trans_pcie_send_cmd_pdu(struct iwl_trans *trans, u8 id, u32 flags,
1100 u16 len, const void *data)
1102 struct iwl_host_cmd cmd = {
1109 return iwl_trans_pcie_send_cmd(trans, &cmd);
1112 /* Frees buffers until index _not_ inclusive */
1113 int iwl_tx_queue_reclaim(struct iwl_trans *trans, int txq_id, int index,
1114 struct sk_buff_head *skbs)
1116 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1117 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
1118 struct iwl_queue *q = &txq->q;
1122 /*Since we free until index _not_ inclusive, the one before index is
1123 * the last we will free. This one must be used */
1124 last_to_free = iwl_queue_dec_wrap(index, q->n_bd);
1126 if ((index >= q->n_bd) ||
1127 (iwl_queue_used(q, last_to_free) == 0)) {
1128 IWL_ERR(trans, "%s: Read index for DMA queue txq id (%d), "
1129 "last_to_free %d is out of range [0-%d] %d %d.\n",
1130 __func__, txq_id, last_to_free, q->n_bd,
1131 q->write_ptr, q->read_ptr);
1135 IWL_DEBUG_TX_REPLY(trans, "reclaim: [%d, %d, %d]\n", txq_id,
1136 q->read_ptr, index);
1138 if (WARN_ON(!skb_queue_empty(skbs)))
1142 q->read_ptr != index;
1143 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1145 if (WARN_ON_ONCE(txq->skbs[txq->q.read_ptr] == NULL))
1148 __skb_queue_tail(skbs, txq->skbs[txq->q.read_ptr]);
1150 txq->skbs[txq->q.read_ptr] = NULL;
1152 iwlagn_txq_inval_byte_cnt_tbl(trans, txq);
1154 iwlagn_txq_free_tfd(trans, txq, txq->q.read_ptr);