drivers/net/wireless/iwlwifi/iwl-trans-rx-pcie.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
   4  *
   5  * Portions of this file are derived from the ipw3945 project, as well
   6  * as portions of the ieee80211 subsystem header files.
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of version 2 of the GNU General Public License as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program; if not, write to the Free Software Foundation, Inc.,
  19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20  *
  21  * The full GNU General Public License is included in this distribution in the
  22  * file called LICENSE.
  23  *
  24  * Contact Information:
  25  *  Intel Linux Wireless <ilw@linux.intel.com>
  26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27  *
  28  *****************************************************************************/
  29 #include <linux/sched.h>
  30 #include <linux/wait.h>
  31 #include <linux/gfp.h>
  32
  33 #include "iwl-dev.h"
  34 #include "iwl-agn.h"
  35 #include "iwl-core.h"
  36 #include "iwl-io.h"
  37 #include "iwl-helpers.h"
  38 #include "iwl-trans-int-pcie.h"
  39
  40 /******************************************************************************
  41  *
  42  * RX path functions
  43  *
  44  ******************************************************************************/
  45
  46 /*
  47  * Rx theory of operation
  48  *
  49  * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
  50  * each of which point to Receive Buffers to be filled by the NIC.  These get
  51  * used not only for Rx frames, but for any command response or notification
  52  * from the NIC.  The driver and NIC manage the Rx buffers by means
  53  * of indexes into the circular buffer.
  54  *
  55  * Rx Queue Indexes
  56  * The host/firmware share two index registers for managing the Rx buffers.
  57  *
  58  * The READ index maps to the first position that the firmware may be writing
  59  * to -- the driver can read up to (but not including) this position and get
  60  * good data.
  61  * The READ index is managed by the firmware once the card is enabled.
  62  *
  63  * The WRITE index maps to the last position the driver has read from -- the
  64  * position preceding WRITE is the last slot the firmware can place a packet.
  65  *
  66  * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  67  * WRITE = READ.
  68  *
  69  * During initialization, the host sets up the READ queue position to the first
  70  * INDEX position, and WRITE to the last (READ - 1 wrapped)
  71  *
  72  * When the firmware places a packet in a buffer, it will advance the READ index
  73  * and fire the RX interrupt.  The driver can then query the READ index and
  74  * process as many packets as possible, moving the WRITE index forward as it
  75  * resets the Rx queue buffers with new memory.
  76  *
  77  * The management in the driver is as follows:
  78  * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free.  When
  79  *   iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  80  *   to replenish the iwl->rxq->rx_free.
  81  * + In iwl_rx_replenish (scheduled) if 'processed' != 'read' then the
  82  *   iwl->rxq is replenished and the READ INDEX is updated (updating the
  83  *   'processed' and 'read' driver indexes as well)
  84  * + A received packet is processed and handed to the kernel network stack,
  85  *   detached from the iwl->rxq.  The driver 'processed' index is updated.
  86  * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
  87  *   list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
  88  *   INDEX is not incremented and iwl->status(RX_STALLED) is set.  If there
  89  *   were enough free buffers and RX_STALLED is set it is cleared.
  90  *
  91  *
  92  * Driver sequence:
  93  *
  94  * iwl_rx_queue_alloc()   Allocates rx_free
  95  * iwl_rx_replenish()     Replenishes rx_free list from rx_used, and calls
  96  *                            iwl_rx_queue_restock
  97  * iwl_rx_queue_restock() Moves available buffers from rx_free into Rx
  98  *                            queue, updates firmware pointers, and updates
  99  *                            the WRITE index.  If insufficient rx_free buffers
 100  *                            are available, schedules iwl_rx_replenish
 101  *
 102  * -- enable interrupts --
 103  * ISR - iwl_rx()         Detach iwl_rx_mem_buffers from pool up to the
 104  *                            READ INDEX, detaching the SKB from the pool.
 105  *                            Moves the packet buffer from queue to rx_used.
 106  *                            Calls iwl_rx_queue_restock to refill any empty
 107  *                            slots.
 108  * ...
 109  *
 110  */
 111
 112 /**
 113  * iwl_rx_queue_space - Return number of free slots available in queue.
 114  */
 115 static int iwl_rx_queue_space(const struct iwl_rx_queue *q)
 116 {
 117         int s = q->read - q->write;
 118         if (s <= 0)
 119                 s += RX_QUEUE_SIZE;
 120         /* keep some buffer to not confuse full and empty queue */
 121         s -= 2;
 122         if (s < 0)
 123                 s = 0;
 124         return s;
 125 }
 126
 127 /**
 128  * iwl_rx_queue_update_write_ptr - Update the write pointer for the RX queue
 129  */
 130 void iwl_rx_queue_update_write_ptr(struct iwl_trans *trans,
 131                         struct iwl_rx_queue *q)
 132 {
 133         struct iwl_priv *priv = priv(trans);
 134         unsigned long flags;
 135         u32 reg;
 136
 137         spin_lock_irqsave(&q->lock, flags);
 138
 139         if (q->need_update == 0)
 140                 goto exit_unlock;
 141
 142         if (priv->cfg->base_params->shadow_reg_enable) {
 143                 /* shadow register enabled */
 144                 /* Device expects a multiple of 8 */
 145                 q->write_actual = (q->write & ~0x7);
 146                 iwl_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write_actual);
 147         } else {
 148                 /* If power-saving is in use, make sure device is awake */
 149                 if (test_bit(STATUS_POWER_PMI, &trans->shrd->status)) {
 150                         reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
 151
 152                         if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
 153                                 IWL_DEBUG_INFO(trans,
 154                                         "Rx queue requesting wakeup,"
 155                                         " GP1 = 0x%x\n", reg);
 156                                 iwl_set_bit(priv, CSR_GP_CNTRL,
 157                                         CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 158                                 goto exit_unlock;
 159                         }
 160
 161                         q->write_actual = (q->write & ~0x7);
 162                         iwl_write_direct32(priv, FH_RSCSR_CHNL0_WPTR,
 163                                         q->write_actual);
 164
 165                 /* Else device is assumed to be awake */
 166                 } else {
 167                         /* Device expects a multiple of 8 */
 168                         q->write_actual = (q->write & ~0x7);
 169                         iwl_write_direct32(priv, FH_RSCSR_CHNL0_WPTR,
 170                                 q->write_actual);
 171                 }
 172         }
 173         q->need_update = 0;
 174
 175  exit_unlock:
 176         spin_unlock_irqrestore(&q->lock, flags);
 177 }
 178
 179 /**
 180  * iwlagn_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
 181  */
 182 static inline __le32 iwlagn_dma_addr2rbd_ptr(dma_addr_t dma_addr)
 183 {
 184         return cpu_to_le32((u32)(dma_addr >> 8));
 185 }
 186
 187 /**
 188  * iwlagn_rx_queue_restock - refill RX queue from pre-allocated pool
 189  *
 190  * If there are slots in the RX queue that need to be restocked,
 191  * and we have free pre-allocated buffers, fill the ranks as much
 192  * as we can, pulling from rx_free.
 193  *
 194  * This moves the 'write' index forward to catch up with 'processed', and
 195  * also updates the memory address in the firmware to reference the new
 196  * target buffer.
 197  */
 198 static void iwlagn_rx_queue_restock(struct iwl_trans *trans)
 199 {
 200         struct iwl_trans_pcie *trans_pcie =
 201                 IWL_TRANS_GET_PCIE_TRANS(trans);
 202
 203         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 204         struct list_head *element;
 205         struct iwl_rx_mem_buffer *rxb;
 206         unsigned long flags;
 207
 208         spin_lock_irqsave(&rxq->lock, flags);
 209         while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
 210                 /* The overwritten rxb must be a used one */
 211                 rxb = rxq->queue[rxq->write];
 212                 BUG_ON(rxb && rxb->page);
 213
 214                 /* Get next free Rx buffer, remove from free list */
 215                 element = rxq->rx_free.next;
 216                 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
 217                 list_del(element);
 218
 219                 /* Point to Rx buffer via next RBD in circular buffer */
 220                 rxq->bd[rxq->write] = iwlagn_dma_addr2rbd_ptr(rxb->page_dma);
 221                 rxq->queue[rxq->write] = rxb;
 222                 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
 223                 rxq->free_count--;
 224         }
 225         spin_unlock_irqrestore(&rxq->lock, flags);
 226         /* If the pre-allocated buffer pool is dropping low, schedule to
 227          * refill it */
 228         if (rxq->free_count <= RX_LOW_WATERMARK)
 229                 queue_work(trans->shrd->workqueue, &trans_pcie->rx_replenish);
 230
 231
 232         /* If we've added more space for the firmware to place data, tell it.
 233          * Increment device's write pointer in multiples of 8. */
 234         if (rxq->write_actual != (rxq->write & ~0x7)) {
 235                 spin_lock_irqsave(&rxq->lock, flags);
 236                 rxq->need_update = 1;
 237                 spin_unlock_irqrestore(&rxq->lock, flags);
 238                 iwl_rx_queue_update_write_ptr(trans, rxq);
 239         }
 240 }
 241
 242 /**
 243  * iwlagn_rx_replenish - Move all used packet from rx_used to rx_free
 244  *
 245  * When moving to rx_free an SKB is allocated for the slot.
 246  *
 247  * Also restock the Rx queue via iwl_rx_queue_restock.
 248  * This is called as a scheduled work item (except for during initialization)
 249  */
 250 static void iwlagn_rx_allocate(struct iwl_trans *trans, gfp_t priority)
 251 {
 252         struct iwl_trans_pcie *trans_pcie =
 253                 IWL_TRANS_GET_PCIE_TRANS(trans);
 254
 255         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 256         struct list_head *element;
 257         struct iwl_rx_mem_buffer *rxb;
 258         struct page *page;
 259         unsigned long flags;
 260         gfp_t gfp_mask = priority;
 261
 262         while (1) {
 263                 spin_lock_irqsave(&rxq->lock, flags);
 264                 if (list_empty(&rxq->rx_used)) {
 265                         spin_unlock_irqrestore(&rxq->lock, flags);
 266                         return;
 267                 }
 268                 spin_unlock_irqrestore(&rxq->lock, flags);
 269
 270                 if (rxq->free_count > RX_LOW_WATERMARK)
 271                         gfp_mask |= __GFP_NOWARN;
 272
 273                 if (hw_params(trans).rx_page_order > 0)
 274                         gfp_mask |= __GFP_COMP;
 275
 276                 /* Alloc a new receive buffer */
 277                 page = alloc_pages(gfp_mask,
 278                                   hw_params(trans).rx_page_order);
 279                 if (!page) {
 280                         if (net_ratelimit())
 281                                 IWL_DEBUG_INFO(trans, "alloc_pages failed, "
 282                                            "order: %d\n",
 283                                            hw_params(trans).rx_page_order);
 284
 285                         if ((rxq->free_count <= RX_LOW_WATERMARK) &&
 286                             net_ratelimit())
 287                                 IWL_CRIT(trans, "Failed to alloc_pages with %s."
 288                                          "Only %u free buffers remaining.\n",
 289                                          priority == GFP_ATOMIC ?
 290                                          "GFP_ATOMIC" : "GFP_KERNEL",
 291                                          rxq->free_count);
 292                         /* We don't reschedule replenish work here -- we will
 293                          * call the restock method and if it still needs
 294                          * more buffers it will schedule replenish */
 295                         return;
 296                 }
 297
 298                 spin_lock_irqsave(&rxq->lock, flags);
 299
 300                 if (list_empty(&rxq->rx_used)) {
 301                         spin_unlock_irqrestore(&rxq->lock, flags);
 302                         __free_pages(page, hw_params(trans).rx_page_order);
 303                         return;
 304                 }
 305                 element = rxq->rx_used.next;
 306                 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
 307                 list_del(element);
 308
 309                 spin_unlock_irqrestore(&rxq->lock, flags);
 310
 311                 BUG_ON(rxb->page);
 312                 rxb->page = page;
 313                 /* Get physical address of the RB */
 314                 rxb->page_dma = dma_map_page(bus(trans)->dev, page, 0,
 315                                 PAGE_SIZE << hw_params(trans).rx_page_order,
 316                                 DMA_FROM_DEVICE);
 317                 /* dma address must be no more than 36 bits */
 318                 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
 319                 /* and also 256 byte aligned! */
 320                 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
 321
 322                 spin_lock_irqsave(&rxq->lock, flags);
 323
 324                 list_add_tail(&rxb->list, &rxq->rx_free);
 325                 rxq->free_count++;
 326
 327                 spin_unlock_irqrestore(&rxq->lock, flags);
 328         }
 329 }
 330
 331 void iwlagn_rx_replenish(struct iwl_trans *trans)
 332 {
 333         unsigned long flags;
 334
 335         iwlagn_rx_allocate(trans, GFP_KERNEL);
 336
 337         spin_lock_irqsave(&trans->shrd->lock, flags);
 338         iwlagn_rx_queue_restock(trans);
 339         spin_unlock_irqrestore(&trans->shrd->lock, flags);
 340 }
 341
 342 static void iwlagn_rx_replenish_now(struct iwl_trans *trans)
 343 {
 344         iwlagn_rx_allocate(trans, GFP_ATOMIC);
 345
 346         iwlagn_rx_queue_restock(trans);
 347 }
 348
 349 void iwl_bg_rx_replenish(struct work_struct *data)
 350 {
 351         struct iwl_trans_pcie *trans_pcie =
 352             container_of(data, struct iwl_trans_pcie, rx_replenish);
 353         struct iwl_trans *trans = trans_pcie->trans;
 354
 355         if (test_bit(STATUS_EXIT_PENDING, &trans->shrd->status))
 356                 return;
 357
 358         mutex_lock(&trans->shrd->mutex);
 359         iwlagn_rx_replenish(trans);
 360         mutex_unlock(&trans->shrd->mutex);
 361 }
 362
 363 /**
 364  * iwl_rx_handle - Main entry function for receiving responses from uCode
 365  *
 366  * Uses the priv->rx_handlers callback function array to invoke
 367  * the appropriate handlers, including command responses,
 368  * frame-received notifications, and other notifications.
 369  */
 370 static void iwl_rx_handle(struct iwl_trans *trans)
 371 {
 372         struct iwl_rx_mem_buffer *rxb;
 373         struct iwl_rx_packet *pkt;
 374         struct iwl_trans_pcie *trans_pcie =
 375                 IWL_TRANS_GET_PCIE_TRANS(trans);
 376         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 377         u32 r, i;
 378         int reclaim;
 379         unsigned long flags;
 380         u8 fill_rx = 0;
 381         u32 count = 8;
 382         int total_empty;
 383
 384         /* uCode's read index (stored in shared DRAM) indicates the last Rx
 385          * buffer that the driver may process (last buffer filled by ucode). */
 386         r = le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF;
 387         i = rxq->read;
 388
 389         /* Rx interrupt, but nothing sent from uCode */
 390         if (i == r)
 391                 IWL_DEBUG_RX(trans, "r = %d, i = %d\n", r, i);
 392
 393         /* calculate total frames need to be restock after handling RX */
 394         total_empty = r - rxq->write_actual;
 395         if (total_empty < 0)
 396                 total_empty += RX_QUEUE_SIZE;
 397
 398         if (total_empty > (RX_QUEUE_SIZE / 2))
 399                 fill_rx = 1;
 400
 401         while (i != r) {
 402                 int len;
 403
 404                 rxb = rxq->queue[i];
 405
 406                 /* If an RXB doesn't have a Rx queue slot associated with it,
 407                  * then a bug has been introduced in the queue refilling
 408                  * routines -- catch it here */
 409                 if (WARN_ON(rxb == NULL)) {
 410                         i = (i + 1) & RX_QUEUE_MASK;
 411                         continue;
 412                 }
 413
 414                 rxq->queue[i] = NULL;
 415
 416                 dma_unmap_page(bus(trans)->dev, rxb->page_dma,
 417                                PAGE_SIZE << hw_params(trans).rx_page_order,
 418                                DMA_FROM_DEVICE);
 419                 pkt = rxb_addr(rxb);
 420
 421                 IWL_DEBUG_RX(trans, "r = %d, i = %d, %s, 0x%02x\n", r,
 422                         i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
 423
 424                 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
 425                 len += sizeof(u32); /* account for status word */
 426                 trace_iwlwifi_dev_rx(priv(trans), pkt, len);
 427
 428                 /* Reclaim a command buffer only if this packet is a response
 429                  *   to a (driver-originated) command.
 430                  * If the packet (e.g. Rx frame) originated from uCode,
 431                  *   there is no command buffer to reclaim.
 432                  * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
 433                  *   but apparently a few don't get set; catch them here. */
 434                 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
 435                         (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
 436                         (pkt->hdr.cmd != REPLY_RX) &&
 437                         (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
 438                         (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
 439                         (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
 440                         (pkt->hdr.cmd != REPLY_TX);
 441
 442                 iwl_rx_dispatch(priv(trans), rxb);
 443
 444                 /*
 445                  * XXX: After here, we should always check rxb->page
 446                  * against NULL before touching it or its virtual
 447                  * memory (pkt). Because some rx_handler might have
 448                  * already taken or freed the pages.
 449                  */
 450
 451                 if (reclaim) {
 452                         /* Invoke any callbacks, transfer the buffer to caller,
 453                          * and fire off the (possibly) blocking
 454                          * iwl_trans_send_cmd()
 455                          * as we reclaim the driver command queue */
 456                         if (rxb->page)
 457                                 iwl_tx_cmd_complete(priv(trans), rxb);
 458                         else
 459                                 IWL_WARN(trans, "Claim null rxb?\n");
 460                 }
 461
 462                 /* Reuse the page if possible. For notification packets and
 463                  * SKBs that fail to Rx correctly, add them back into the
 464                  * rx_free list for reuse later. */
 465                 spin_lock_irqsave(&rxq->lock, flags);
 466                 if (rxb->page != NULL) {
 467                         rxb->page_dma = dma_map_page(bus(trans)->dev, rxb->page,
 468                                 0, PAGE_SIZE <<
 469                                     hw_params(trans).rx_page_order,
 470                                 DMA_FROM_DEVICE);
 471                         list_add_tail(&rxb->list, &rxq->rx_free);
 472                         rxq->free_count++;
 473                 } else
 474                         list_add_tail(&rxb->list, &rxq->rx_used);
 475
 476                 spin_unlock_irqrestore(&rxq->lock, flags);
 477
 478                 i = (i + 1) & RX_QUEUE_MASK;
 479                 /* If there are a lot of unused frames,
 480                  * restock the Rx queue so ucode wont assert. */
 481                 if (fill_rx) {
 482                         count++;
 483                         if (count >= 8) {
 484                                 rxq->read = i;
 485                                 iwlagn_rx_replenish_now(trans);
 486                                 count = 0;
 487                         }
 488                 }
 489         }
 490
 491         /* Backtrack one entry */
 492         rxq->read = i;
 493         if (fill_rx)
 494                 iwlagn_rx_replenish_now(trans);
 495         else
 496                 iwlagn_rx_queue_restock(trans);
 497 }
 498
 499 /* tasklet for iwlagn interrupt */
 500 void iwl_irq_tasklet(struct iwl_trans *trans)
 501 {
 502         u32 inta = 0;
 503         u32 handled = 0;
 504         unsigned long flags;
 505         u32 i;
 506 #ifdef CONFIG_IWLWIFI_DEBUG
 507         u32 inta_mask;
 508 #endif
 509
 510         struct iwl_trans_pcie *trans_pcie =
 511                 IWL_TRANS_GET_PCIE_TRANS(trans);
 512
 513         spin_lock_irqsave(&trans->shrd->lock, flags);
 514
 515         /* Ack/clear/reset pending uCode interrupts.
 516          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
 517          */
 518         /* There is a hardware bug in the interrupt mask function that some
 519          * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
 520          * they are disabled in the CSR_INT_MASK register. Furthermore the
 521          * ICT interrupt handling mechanism has another bug that might cause
 522          * these unmasked interrupts fail to be detected. We workaround the
 523          * hardware bugs here by ACKing all the possible interrupts so that
 524          * interrupt coalescing can still be achieved.
 525          */
 526         iwl_write32(priv(trans), CSR_INT,
 527                 trans_pcie->inta | ~trans_pcie->inta_mask);
 528
 529         inta = trans_pcie->inta;
 530
 531 #ifdef CONFIG_IWLWIFI_DEBUG
 532         if (iwl_get_debug_level(trans->shrd) & IWL_DL_ISR) {
 533                 /* just for debug */
 534                 inta_mask = iwl_read32(priv(trans), CSR_INT_MASK);
 535                 IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n ",
 536                                 inta, inta_mask);
 537         }
 538 #endif
 539
 540         spin_unlock_irqrestore(&trans->shrd->lock, flags);
 541
 542         /* saved interrupt in inta variable now we can reset trans_pcie->inta */
 543         trans_pcie->inta = 0;
 544
 545         /* Now service all interrupt bits discovered above. */
 546         if (inta & CSR_INT_BIT_HW_ERR) {
 547                 IWL_ERR(trans, "Hardware error detected.  Restarting.\n");
 548
 549                 /* Tell the device to stop sending interrupts */
 550                 iwl_disable_interrupts(trans);
 551
 552                 priv(trans)->isr_stats.hw++;
 553                 iwl_irq_handle_error(priv(trans));
 554
 555                 handled |= CSR_INT_BIT_HW_ERR;
 556
 557                 return;
 558         }
 559
 560 #ifdef CONFIG_IWLWIFI_DEBUG
 561         if (iwl_get_debug_level(trans->shrd) & (IWL_DL_ISR)) {
 562                 /* NIC fires this, but we don't use it, redundant with WAKEUP */
 563                 if (inta & CSR_INT_BIT_SCD) {
 564                         IWL_DEBUG_ISR(trans, "Scheduler finished to transmit "
 565                                       "the frame/frames.\n");
 566                         priv(trans)->isr_stats.sch++;
 567                 }
 568
 569                 /* Alive notification via Rx interrupt will do the real work */
 570                 if (inta & CSR_INT_BIT_ALIVE) {
 571                         IWL_DEBUG_ISR(trans, "Alive interrupt\n");
 572                         priv(trans)->isr_stats.alive++;
 573                 }
 574         }
 575 #endif
 576         /* Safely ignore these bits for debug checks below */
 577         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
 578
 579         /* HW RF KILL switch toggled */
 580         if (inta & CSR_INT_BIT_RF_KILL) {
 581                 int hw_rf_kill = 0;
 582                 if (!(iwl_read32(priv(trans), CSR_GP_CNTRL) &
 583                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
 584                         hw_rf_kill = 1;
 585
 586                 IWL_WARN(trans, "RF_KILL bit toggled to %s.\n",
 587                                 hw_rf_kill ? "disable radio" : "enable radio");
 588
 589                 priv(trans)->isr_stats.rfkill++;
 590
 591                 /* driver only loads ucode once setting the interface up.
 592                  * the driver allows loading the ucode even if the radio
 593                  * is killed. Hence update the killswitch state here. The
 594                  * rfkill handler will care about restarting if needed.
 595                  */
 596                 if (!test_bit(STATUS_ALIVE, &trans->shrd->status)) {
 597                         if (hw_rf_kill)
 598                                 set_bit(STATUS_RF_KILL_HW,
 599                                         &trans->shrd->status);
 600                         else
 601                                 clear_bit(STATUS_RF_KILL_HW,
 602                                           &trans->shrd->status);
 603                         wiphy_rfkill_set_hw_state(priv(trans)->hw->wiphy,
 604                                                   hw_rf_kill);
 605                 }
 606
 607                 handled |= CSR_INT_BIT_RF_KILL;
 608         }
 609
 610         /* Chip got too hot and stopped itself */
 611         if (inta & CSR_INT_BIT_CT_KILL) {
 612                 IWL_ERR(trans, "Microcode CT kill error detected.\n");
 613                 priv(trans)->isr_stats.ctkill++;
 614                 handled |= CSR_INT_BIT_CT_KILL;
 615         }
 616
 617         /* Error detected by uCode */
 618         if (inta & CSR_INT_BIT_SW_ERR) {
 619                 IWL_ERR(trans, "Microcode SW error detected. "
 620                         " Restarting 0x%X.\n", inta);
 621                 priv(trans)->isr_stats.sw++;
 622                 iwl_irq_handle_error(priv(trans));
 623                 handled |= CSR_INT_BIT_SW_ERR;
 624         }
 625
 626         /* uCode wakes up after power-down sleep */
 627         if (inta & CSR_INT_BIT_WAKEUP) {
 628                 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n");
 629                 iwl_rx_queue_update_write_ptr(trans, &trans_pcie->rxq);
 630                 for (i = 0; i < hw_params(trans).max_txq_num; i++)
 631                         iwl_txq_update_write_ptr(priv(trans),
 632                                                  &priv(trans)->txq[i]);
 633
 634                 priv(trans)->isr_stats.wakeup++;
 635
 636                 handled |= CSR_INT_BIT_WAKEUP;
 637         }
 638
 639         /* All uCode command responses, including Tx command responses,
 640          * Rx "responses" (frame-received notification), and other
 641          * notifications from uCode come through here*/
 642         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
 643                         CSR_INT_BIT_RX_PERIODIC)) {
 644                 IWL_DEBUG_ISR(trans, "Rx interrupt\n");
 645                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
 646                         handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
 647                         iwl_write32(priv(trans), CSR_FH_INT_STATUS,
 648                                         CSR_FH_INT_RX_MASK);
 649                 }
 650                 if (inta & CSR_INT_BIT_RX_PERIODIC) {
 651                         handled |= CSR_INT_BIT_RX_PERIODIC;
 652                         iwl_write32(priv(trans),
 653                                 CSR_INT, CSR_INT_BIT_RX_PERIODIC);
 654                 }
 655                 /* Sending RX interrupt require many steps to be done in the
 656                  * the device:
 657                  * 1- write interrupt to current index in ICT table.
 658                  * 2- dma RX frame.
 659                  * 3- update RX shared data to indicate last write index.
 660                  * 4- send interrupt.
 661                  * This could lead to RX race, driver could receive RX interrupt
 662                  * but the shared data changes does not reflect this;
 663                  * periodic interrupt will detect any dangling Rx activity.
 664                  */
 665
 666                 /* Disable periodic interrupt; we use it as just a one-shot. */
 667                 iwl_write8(priv(trans), CSR_INT_PERIODIC_REG,
 668                             CSR_INT_PERIODIC_DIS);
 669                 iwl_rx_handle(trans);
 670
 671                 /*
 672                  * Enable periodic interrupt in 8 msec only if we received
 673                  * real RX interrupt (instead of just periodic int), to catch
 674                  * any dangling Rx interrupt.  If it was just the periodic
 675                  * interrupt, there was no dangling Rx activity, and no need
 676                  * to extend the periodic interrupt; one-shot is enough.
 677                  */
 678                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
 679                         iwl_write8(priv(trans), CSR_INT_PERIODIC_REG,
 680                                     CSR_INT_PERIODIC_ENA);
 681
 682                 priv(trans)->isr_stats.rx++;
 683         }
 684
 685         /* This "Tx" DMA channel is used only for loading uCode */
 686         if (inta & CSR_INT_BIT_FH_TX) {
 687                 iwl_write32(priv(trans), CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
 688                 IWL_DEBUG_ISR(trans, "uCode load interrupt\n");
 689                 priv(trans)->isr_stats.tx++;
 690                 handled |= CSR_INT_BIT_FH_TX;
 691                 /* Wake up uCode load routine, now that load is complete */
 692                 priv(trans)->ucode_write_complete = 1;
 693                 wake_up_interruptible(&priv(trans)->wait_command_queue);
 694         }
 695
 696         if (inta & ~handled) {
 697                 IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
 698                 priv(trans)->isr_stats.unhandled++;
 699         }
 700
 701         if (inta & ~(trans_pcie->inta_mask)) {
 702                 IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n",
 703                          inta & ~trans_pcie->inta_mask);
 704         }
 705
 706         /* Re-enable all interrupts */
 707         /* only Re-enable if disabled by irq */
 708         if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status))
 709                 iwl_enable_interrupts(trans);
 710         /* Re-enable RF_KILL if it occurred */
 711         else if (handled & CSR_INT_BIT_RF_KILL)
 712                 iwl_enable_rfkill_int(priv(trans));
 713 }
 714
 715 /******************************************************************************
 716  *
 717  * ICT functions
 718  *
 719  ******************************************************************************/
 720 #define ICT_COUNT (PAGE_SIZE/sizeof(u32))
 721
 722 /* Free dram table */
 723 void iwl_free_isr_ict(struct iwl_trans *trans)
 724 {
 725         struct iwl_trans_pcie *trans_pcie =
 726                 IWL_TRANS_GET_PCIE_TRANS(trans);
 727
 728         if (trans_pcie->ict_tbl_vir) {
 729                 dma_free_coherent(bus(trans)->dev,
 730                                   (sizeof(u32) * ICT_COUNT) + PAGE_SIZE,
 731                                   trans_pcie->ict_tbl_vir,
 732                                   trans_pcie->ict_tbl_dma);
 733                 trans_pcie->ict_tbl_vir = NULL;
 734                 memset(&trans_pcie->ict_tbl_dma, 0,
 735                         sizeof(trans_pcie->ict_tbl_dma));
 736                 memset(&trans_pcie->aligned_ict_tbl_dma, 0,
 737                         sizeof(trans_pcie->aligned_ict_tbl_dma));
 738         }
 739 }
 740
 741
 742 /* allocate dram shared table it is a PAGE_SIZE aligned
 743  * also reset all data related to ICT table interrupt.
 744  */
 745 int iwl_alloc_isr_ict(struct iwl_trans *trans)
 746 {
 747         struct iwl_trans_pcie *trans_pcie =
 748                 IWL_TRANS_GET_PCIE_TRANS(trans);
 749
 750         /* allocate shrared data table */
 751         trans_pcie->ict_tbl_vir =
 752                 dma_alloc_coherent(bus(trans)->dev,
 753                                    (sizeof(u32) * ICT_COUNT) + PAGE_SIZE,
 754                                    &trans_pcie->ict_tbl_dma, GFP_KERNEL);
 755         if (!trans_pcie->ict_tbl_vir)
 756                 return -ENOMEM;
 757
 758         /* align table to PAGE_SIZE boundary */
 759         trans_pcie->aligned_ict_tbl_dma =
 760                 ALIGN(trans_pcie->ict_tbl_dma, PAGE_SIZE);
 761
 762         IWL_DEBUG_ISR(trans, "ict dma addr %Lx dma aligned %Lx diff %d\n",
 763                            (unsigned long long)trans_pcie->ict_tbl_dma,
 764                            (unsigned long long)trans_pcie->aligned_ict_tbl_dma,
 765                            (int)(trans_pcie->aligned_ict_tbl_dma -
 766                            trans_pcie->ict_tbl_dma));
 767
 768         trans_pcie->ict_tbl =  trans_pcie->ict_tbl_vir +
 769                           (trans_pcie->aligned_ict_tbl_dma -
 770                           trans_pcie->ict_tbl_dma);
 771
 772         IWL_DEBUG_ISR(trans, "ict vir addr %p vir aligned %p diff %d\n",
 773                              trans_pcie->ict_tbl, trans_pcie->ict_tbl_vir,
 774                         (int)(trans_pcie->aligned_ict_tbl_dma -
 775                             trans_pcie->ict_tbl_dma));
 776
 777         /* reset table and index to all 0 */
 778         memset(trans_pcie->ict_tbl_vir, 0,
 779                 (sizeof(u32) * ICT_COUNT) + PAGE_SIZE);
 780         trans_pcie->ict_index = 0;
 781
 782         /* add periodic RX interrupt */
 783         trans_pcie->inta_mask |= CSR_INT_BIT_RX_PERIODIC;
 784         return 0;
 785 }
 786
 787 /* Device is going up inform it about using ICT interrupt table,
 788  * also we need to tell the driver to start using ICT interrupt.
 789  */
 790 int iwl_reset_ict(struct iwl_priv *priv)
 791 {
 792         u32 val;
 793         unsigned long flags;
 794         struct iwl_trans *trans = trans(priv);
 795         struct iwl_trans_pcie *trans_pcie =
 796                 IWL_TRANS_GET_PCIE_TRANS(trans);
 797
 798         if (!trans_pcie->ict_tbl_vir)
 799                 return 0;
 800
 801         spin_lock_irqsave(&trans->shrd->lock, flags);
 802         iwl_disable_interrupts(trans);
 803
 804         memset(&trans_pcie->ict_tbl[0], 0, sizeof(u32) * ICT_COUNT);
 805
 806         val = trans_pcie->aligned_ict_tbl_dma >> PAGE_SHIFT;
 807
 808         val |= CSR_DRAM_INT_TBL_ENABLE;
 809         val |= CSR_DRAM_INIT_TBL_WRAP_CHECK;
 810
 811         IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%X "
 812                         "aligned dma address %Lx\n",
 813                         val,
 814                         (unsigned long long)trans_pcie->aligned_ict_tbl_dma);
 815
 816         iwl_write32(priv(trans), CSR_DRAM_INT_TBL_REG, val);
 817         trans_pcie->use_ict = true;
 818         trans_pcie->ict_index = 0;
 819         iwl_write32(priv(trans), CSR_INT, trans_pcie->inta_mask);
 820         iwl_enable_interrupts(trans);
 821         spin_unlock_irqrestore(&trans->shrd->lock, flags);
 822
 823         return 0;
 824 }
 825
 826 /* Device is going down disable ict interrupt usage */
 827 void iwl_disable_ict(struct iwl_trans *trans)
 828 {
 829         struct iwl_trans_pcie *trans_pcie =
 830                 IWL_TRANS_GET_PCIE_TRANS(trans);
 831
 832         unsigned long flags;
 833
 834         spin_lock_irqsave(&trans->shrd->lock, flags);
 835         trans_pcie->use_ict = false;
 836         spin_unlock_irqrestore(&trans->shrd->lock, flags);
 837 }
 838
 839 static irqreturn_t iwl_isr(int irq, void *data)
 840 {
 841         struct iwl_trans *trans = data;
 842         struct iwl_trans_pcie *trans_pcie;
 843         u32 inta, inta_mask;
 844         unsigned long flags;
 845 #ifdef CONFIG_IWLWIFI_DEBUG
 846         u32 inta_fh;
 847 #endif
 848         if (!trans)
 849                 return IRQ_NONE;
 850
 851         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 852
 853         spin_lock_irqsave(&trans->shrd->lock, flags);
 854
 855         /* Disable (but don't clear!) interrupts here to avoid
 856          *    back-to-back ISRs and sporadic interrupts from our NIC.
 857          * If we have something to service, the tasklet will re-enable ints.
 858          * If we *don't* have something, we'll re-enable before leaving here. */
 859         inta_mask = iwl_read32(priv(trans), CSR_INT_MASK);  /* just for debug */
 860         iwl_write32(priv(trans), CSR_INT_MASK, 0x00000000);
 861
 862         /* Discover which interrupts are active/pending */
 863         inta = iwl_read32(priv(trans), CSR_INT);
 864
 865         /* Ignore interrupt if there's nothing in NIC to service.
 866          * This may be due to IRQ shared with another device,
 867          * or due to sporadic interrupts thrown from our NIC. */
 868         if (!inta) {
 869                 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
 870                 goto none;
 871         }
 872
 873         if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
 874                 /* Hardware disappeared. It might have already raised
 875                  * an interrupt */
 876                 IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
 877                 goto unplugged;
 878         }
 879
 880 #ifdef CONFIG_IWLWIFI_DEBUG
 881         if (iwl_get_debug_level(trans->shrd) & (IWL_DL_ISR)) {
 882                 inta_fh = iwl_read32(priv(trans), CSR_FH_INT_STATUS);
 883                 IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled 0x%08x, "
 884                               "fh 0x%08x\n", inta, inta_mask, inta_fh);
 885         }
 886 #endif
 887
 888         trans_pcie->inta |= inta;
 889         /* iwl_irq_tasklet() will service interrupts and re-enable them */
 890         if (likely(inta))
 891                 tasklet_schedule(&trans_pcie->irq_tasklet);
 892         else if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status) &&
 893                         !trans_pcie->inta)
 894                 iwl_enable_interrupts(trans);
 895
 896  unplugged:
 897         spin_unlock_irqrestore(&trans->shrd->lock, flags);
 898         return IRQ_HANDLED;
 899
 900  none:
 901         /* re-enable interrupts here since we don't have anything to service. */
 902         /* only Re-enable if disabled by irq  and no schedules tasklet. */
 903         if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status) &&
 904                 !trans_pcie->inta)
 905                 iwl_enable_interrupts(trans);
 906
 907         spin_unlock_irqrestore(&trans->shrd->lock, flags);
 908         return IRQ_NONE;
 909 }
 910
 911 /* interrupt handler using ict table, with this interrupt driver will
 912  * stop using INTA register to get device's interrupt, reading this register
 913  * is expensive, device will write interrupts in ICT dram table, increment
 914  * index then will fire interrupt to driver, driver will OR all ICT table
 915  * entries from current index up to table entry with 0 value. the result is
 916  * the interrupt we need to service, driver will set the entries back to 0 and
 917  * set index.
 918  */
 919 irqreturn_t iwl_isr_ict(int irq, void *data)
 920 {
 921         struct iwl_trans *trans = data;
 922         struct iwl_trans_pcie *trans_pcie;
 923         u32 inta, inta_mask;
 924         u32 val = 0;
 925         unsigned long flags;
 926
 927         if (!trans)
 928                 return IRQ_NONE;
 929
 930         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 931
 932         /* dram interrupt table not set yet,
 933          * use legacy interrupt.
 934          */
 935         if (!trans_pcie->use_ict)
 936                 return iwl_isr(irq, data);
 937
 938         spin_lock_irqsave(&trans->shrd->lock, flags);
 939
 940         /* Disable (but don't clear!) interrupts here to avoid
 941          * back-to-back ISRs and sporadic interrupts from our NIC.
 942          * If we have something to service, the tasklet will re-enable ints.
 943          * If we *don't* have something, we'll re-enable before leaving here.
 944          */
 945         inta_mask = iwl_read32(priv(trans), CSR_INT_MASK);  /* just for debug */
 946         iwl_write32(priv(trans), CSR_INT_MASK, 0x00000000);
 947
 948
 949         /* Ignore interrupt if there's nothing in NIC to service.
 950          * This may be due to IRQ shared with another device,
 951          * or due to sporadic interrupts thrown from our NIC. */
 952         if (!trans_pcie->ict_tbl[trans_pcie->ict_index]) {
 953                 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
 954                 goto none;
 955         }
 956
 957         /* read all entries that not 0 start with ict_index */
 958         while (trans_pcie->ict_tbl[trans_pcie->ict_index]) {
 959
 960                 val |= le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
 961                 IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n",
 962                                 trans_pcie->ict_index,
 963                                 le32_to_cpu(
 964                                   trans_pcie->ict_tbl[trans_pcie->ict_index]));
 965                 trans_pcie->ict_tbl[trans_pcie->ict_index] = 0;
 966                 trans_pcie->ict_index =
 967                         iwl_queue_inc_wrap(trans_pcie->ict_index, ICT_COUNT);
 968
 969         }
 970
 971         /* We should not get this value, just ignore it. */
 972         if (val == 0xffffffff)
 973                 val = 0;
 974
 975         /*
 976          * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit
 977          * (bit 15 before shifting it to 31) to clear when using interrupt
 978          * coalescing. fortunately, bits 18 and 19 stay set when this happens
 979          * so we use them to decide on the real state of the Rx bit.
 980          * In order words, bit 15 is set if bit 18 or bit 19 are set.
 981          */
 982         if (val & 0xC0000)
 983                 val |= 0x8000;
 984
 985         inta = (0xff & val) | ((0xff00 & val) << 16);
 986         IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n",
 987                         inta, inta_mask, val);
 988
 989         inta &= trans_pcie->inta_mask;
 990         trans_pcie->inta |= inta;
 991
 992         /* iwl_irq_tasklet() will service interrupts and re-enable them */
 993         if (likely(inta))
 994                 tasklet_schedule(&trans_pcie->irq_tasklet);
 995         else if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status) &&
 996                         !trans_pcie->inta) {
 997                 /* Allow interrupt if was disabled by this handler and
 998                  * no tasklet was schedules, We should not enable interrupt,
 999                  * tasklet will enable it.
1000                  */
1001                 iwl_enable_interrupts(trans);
1002         }
1003
1004         spin_unlock_irqrestore(&trans->shrd->lock, flags);
1005         return IRQ_HANDLED;
1006
1007  none:
1008         /* re-enable interrupts here since we don't have anything to service.
1009          * only Re-enable if disabled by irq.
1010          */
1011         if (test_bit(STATUS_INT_ENABLED, &trans->shrd->status) &&
1012                 !trans_pcie->inta)
1013                 iwl_enable_interrupts(trans);
1014
1015         spin_unlock_irqrestore(&trans->shrd->lock, flags);
1016         return IRQ_NONE;
1017 }