drivers/net/wireless/iwlwifi/iwl-trans-pcie.c

   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of version 2 of the GNU General Public License as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
  15  * WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * General Public License for more details.
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  20  * along with this program; if not, write to the Free Software
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  22  * USA
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  25  * in the file called LICENSE.GPL.
  26  *
  27  * Contact Information:
  28  *  Intel Linux Wireless <ilw@linux.intel.com>
  29  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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  32  *
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  37  * modification, are permitted provided that the following conditions
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  41  *    notice, this list of conditions and the following disclaimer.
  42  *  * Redistributions in binary form must reproduce the above copyright
  43  *    notice, this list of conditions and the following disclaimer in
  44  *    the documentation and/or other materials provided with the
  45  *    distribution.
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  47  *    contributors may be used to endorse or promote products derived
  48  *    from this software without specific prior written permission.
  49  *
  50  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  51  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  52  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  53  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  54  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  55  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  56  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  57  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  58  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  59  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  60  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  61  *
  62  *****************************************************************************/
  63 #include <linux/pci.h>
  64 #include <linux/pci-aspm.h>
  65 #include <linux/interrupt.h>
  66 #include <linux/debugfs.h>
  67 #include <linux/sched.h>
  68 #include <linux/bitops.h>
  69 #include <linux/gfp.h>
  70
  71 #include "iwl-trans.h"
  72 #include "iwl-trans-pcie-int.h"
  73 #include "iwl-csr.h"
  74 #include "iwl-prph.h"
  75 #include "iwl-shared.h"
  76 #include "iwl-eeprom.h"
  77 #include "iwl-agn-hw.h"
  78
  79 #define IWL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo))))
  80
  81 static int iwl_trans_rx_alloc(struct iwl_trans *trans)
  82 {
  83         struct iwl_trans_pcie *trans_pcie =
  84                 IWL_TRANS_GET_PCIE_TRANS(trans);
  85         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
  86         struct device *dev = trans->dev;
  87
  88         memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq));
  89
  90         spin_lock_init(&rxq->lock);
  91
  92         if (WARN_ON(rxq->bd || rxq->rb_stts))
  93                 return -EINVAL;
  94
  95         /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
  96         rxq->bd = dma_zalloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
  97                                       &rxq->bd_dma, GFP_KERNEL);
  98         if (!rxq->bd)
  99                 goto err_bd;
 100
 101         /*Allocate the driver's pointer to receive buffer status */
 102         rxq->rb_stts = dma_zalloc_coherent(dev, sizeof(*rxq->rb_stts),
 103                                            &rxq->rb_stts_dma, GFP_KERNEL);
 104         if (!rxq->rb_stts)
 105                 goto err_rb_stts;
 106
 107         return 0;
 108
 109 err_rb_stts:
 110         dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
 111                         rxq->bd, rxq->bd_dma);
 112         memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
 113         rxq->bd = NULL;
 114 err_bd:
 115         return -ENOMEM;
 116 }
 117
 118 static void iwl_trans_rxq_free_rx_bufs(struct iwl_trans *trans)
 119 {
 120         struct iwl_trans_pcie *trans_pcie =
 121                 IWL_TRANS_GET_PCIE_TRANS(trans);
 122         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 123         int i;
 124
 125         /* Fill the rx_used queue with _all_ of the Rx buffers */
 126         for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
 127                 /* In the reset function, these buffers may have been allocated
 128                  * to an SKB, so we need to unmap and free potential storage */
 129                 if (rxq->pool[i].page != NULL) {
 130                         dma_unmap_page(trans->dev, rxq->pool[i].page_dma,
 131                                 PAGE_SIZE << hw_params(trans).rx_page_order,
 132                                 DMA_FROM_DEVICE);
 133                         __free_pages(rxq->pool[i].page,
 134                                      hw_params(trans).rx_page_order);
 135                         rxq->pool[i].page = NULL;
 136                 }
 137                 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
 138         }
 139 }
 140
 141 static void iwl_trans_rx_hw_init(struct iwl_trans *trans,
 142                                  struct iwl_rx_queue *rxq)
 143 {
 144         u32 rb_size;
 145         const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
 146         u32 rb_timeout = RX_RB_TIMEOUT; /* FIXME: RX_RB_TIMEOUT for all devices? */
 147
 148         if (iwlagn_mod_params.amsdu_size_8K)
 149                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
 150         else
 151                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
 152
 153         /* Stop Rx DMA */
 154         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 155
 156         /* Reset driver's Rx queue write index */
 157         iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
 158
 159         /* Tell device where to find RBD circular buffer in DRAM */
 160         iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
 161                            (u32)(rxq->bd_dma >> 8));
 162
 163         /* Tell device where in DRAM to update its Rx status */
 164         iwl_write_direct32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,
 165                            rxq->rb_stts_dma >> 4);
 166
 167         /* Enable Rx DMA
 168          * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
 169          *      the credit mechanism in 5000 HW RX FIFO
 170          * Direct rx interrupts to hosts
 171          * Rx buffer size 4 or 8k
 172          * RB timeout 0x10
 173          * 256 RBDs
 174          */
 175         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,
 176                            FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
 177                            FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
 178                            FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
 179                            FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
 180                            rb_size|
 181                            (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
 182                            (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
 183
 184         /* Set interrupt coalescing timer to default (2048 usecs) */
 185         iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
 186 }
 187
 188 static int iwl_rx_init(struct iwl_trans *trans)
 189 {
 190         struct iwl_trans_pcie *trans_pcie =
 191                 IWL_TRANS_GET_PCIE_TRANS(trans);
 192         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 193
 194         int i, err;
 195         unsigned long flags;
 196
 197         if (!rxq->bd) {
 198                 err = iwl_trans_rx_alloc(trans);
 199                 if (err)
 200                         return err;
 201         }
 202
 203         spin_lock_irqsave(&rxq->lock, flags);
 204         INIT_LIST_HEAD(&rxq->rx_free);
 205         INIT_LIST_HEAD(&rxq->rx_used);
 206
 207         iwl_trans_rxq_free_rx_bufs(trans);
 208
 209         for (i = 0; i < RX_QUEUE_SIZE; i++)
 210                 rxq->queue[i] = NULL;
 211
 212         /* Set us so that we have processed and used all buffers, but have
 213          * not restocked the Rx queue with fresh buffers */
 214         rxq->read = rxq->write = 0;
 215         rxq->write_actual = 0;
 216         rxq->free_count = 0;
 217         spin_unlock_irqrestore(&rxq->lock, flags);
 218
 219         iwlagn_rx_replenish(trans);
 220
 221         iwl_trans_rx_hw_init(trans, rxq);
 222
 223         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 224         rxq->need_update = 1;
 225         iwl_rx_queue_update_write_ptr(trans, rxq);
 226         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 227
 228         return 0;
 229 }
 230
 231 static void iwl_trans_pcie_rx_free(struct iwl_trans *trans)
 232 {
 233         struct iwl_trans_pcie *trans_pcie =
 234                 IWL_TRANS_GET_PCIE_TRANS(trans);
 235         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 236
 237         unsigned long flags;
 238
 239         /*if rxq->bd is NULL, it means that nothing has been allocated,
 240          * exit now */
 241         if (!rxq->bd) {
 242                 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
 243                 return;
 244         }
 245
 246         spin_lock_irqsave(&rxq->lock, flags);
 247         iwl_trans_rxq_free_rx_bufs(trans);
 248         spin_unlock_irqrestore(&rxq->lock, flags);
 249
 250         dma_free_coherent(trans->dev, sizeof(__le32) * RX_QUEUE_SIZE,
 251                           rxq->bd, rxq->bd_dma);
 252         memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
 253         rxq->bd = NULL;
 254
 255         if (rxq->rb_stts)
 256                 dma_free_coherent(trans->dev,
 257                                   sizeof(struct iwl_rb_status),
 258                                   rxq->rb_stts, rxq->rb_stts_dma);
 259         else
 260                 IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n");
 261         memset(&rxq->rb_stts_dma, 0, sizeof(rxq->rb_stts_dma));
 262         rxq->rb_stts = NULL;
 263 }
 264
 265 static int iwl_trans_rx_stop(struct iwl_trans *trans)
 266 {
 267
 268         /* stop Rx DMA */
 269         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 270         return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG,
 271                             FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
 272 }
 273
 274 static inline int iwlagn_alloc_dma_ptr(struct iwl_trans *trans,
 275                                     struct iwl_dma_ptr *ptr, size_t size)
 276 {
 277         if (WARN_ON(ptr->addr))
 278                 return -EINVAL;
 279
 280         ptr->addr = dma_alloc_coherent(trans->dev, size,
 281                                        &ptr->dma, GFP_KERNEL);
 282         if (!ptr->addr)
 283                 return -ENOMEM;
 284         ptr->size = size;
 285         return 0;
 286 }
 287
 288 static inline void iwlagn_free_dma_ptr(struct iwl_trans *trans,
 289                                     struct iwl_dma_ptr *ptr)
 290 {
 291         if (unlikely(!ptr->addr))
 292                 return;
 293
 294         dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
 295         memset(ptr, 0, sizeof(*ptr));
 296 }
 297
 298 static int iwl_trans_txq_alloc(struct iwl_trans *trans,
 299                                 struct iwl_tx_queue *txq, int slots_num,
 300                                 u32 txq_id)
 301 {
 302         size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
 303         int i;
 304
 305         if (WARN_ON(txq->meta || txq->cmd || txq->skbs || txq->tfds))
 306                 return -EINVAL;
 307
 308         txq->q.n_window = slots_num;
 309
 310         txq->meta = kcalloc(slots_num, sizeof(txq->meta[0]), GFP_KERNEL);
 311         txq->cmd = kcalloc(slots_num, sizeof(txq->cmd[0]), GFP_KERNEL);
 312
 313         if (!txq->meta || !txq->cmd)
 314                 goto error;
 315
 316         if (txq_id == trans->shrd->cmd_queue)
 317                 for (i = 0; i < slots_num; i++) {
 318                         txq->cmd[i] = kmalloc(sizeof(struct iwl_device_cmd),
 319                                                 GFP_KERNEL);
 320                         if (!txq->cmd[i])
 321                                 goto error;
 322                 }
 323
 324         /* Alloc driver data array and TFD circular buffer */
 325         /* Driver private data, only for Tx (not command) queues,
 326          * not shared with device. */
 327         if (txq_id != trans->shrd->cmd_queue) {
 328                 txq->skbs = kcalloc(TFD_QUEUE_SIZE_MAX, sizeof(txq->skbs[0]),
 329                                     GFP_KERNEL);
 330                 if (!txq->skbs) {
 331                         IWL_ERR(trans, "kmalloc for auxiliary BD "
 332                                   "structures failed\n");
 333                         goto error;
 334                 }
 335         } else {
 336                 txq->skbs = NULL;
 337         }
 338
 339         /* Circular buffer of transmit frame descriptors (TFDs),
 340          * shared with device */
 341         txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
 342                                        &txq->q.dma_addr, GFP_KERNEL);
 343         if (!txq->tfds) {
 344                 IWL_ERR(trans, "dma_alloc_coherent(%zd) failed\n", tfd_sz);
 345                 goto error;
 346         }
 347         txq->q.id = txq_id;
 348
 349         return 0;
 350 error:
 351         kfree(txq->skbs);
 352         txq->skbs = NULL;
 353         /* since txq->cmd has been zeroed,
 354          * all non allocated cmd[i] will be NULL */
 355         if (txq->cmd && txq_id == trans->shrd->cmd_queue)
 356                 for (i = 0; i < slots_num; i++)
 357                         kfree(txq->cmd[i]);
 358         kfree(txq->meta);
 359         kfree(txq->cmd);
 360         txq->meta = NULL;
 361         txq->cmd = NULL;
 362
 363         return -ENOMEM;
 364
 365 }
 366
 367 static int iwl_trans_txq_init(struct iwl_trans *trans, struct iwl_tx_queue *txq,
 368                       int slots_num, u32 txq_id)
 369 {
 370         int ret;
 371
 372         txq->need_update = 0;
 373         memset(txq->meta, 0, sizeof(txq->meta[0]) * slots_num);
 374
 375         /*
 376          * For the default queues 0-3, set up the swq_id
 377          * already -- all others need to get one later
 378          * (if they need one at all).
 379          */
 380         if (txq_id < 4)
 381                 iwl_set_swq_id(txq, txq_id, txq_id);
 382
 383         /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
 384          * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
 385         BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
 386
 387         /* Initialize queue's high/low-water marks, and head/tail indexes */
 388         ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num,
 389                         txq_id);
 390         if (ret)
 391                 return ret;
 392
 393         spin_lock_init(&txq->lock);
 394
 395         /*
 396          * Tell nic where to find circular buffer of Tx Frame Descriptors for
 397          * given Tx queue, and enable the DMA channel used for that queue.
 398          * Circular buffer (TFD queue in DRAM) physical base address */
 399         iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
 400                              txq->q.dma_addr >> 8);
 401
 402         return 0;
 403 }
 404
 405 /**
 406  * iwl_tx_queue_unmap -  Unmap any remaining DMA mappings and free skb's
 407  */
 408 static void iwl_tx_queue_unmap(struct iwl_trans *trans, int txq_id)
 409 {
 410         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 411         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
 412         struct iwl_queue *q = &txq->q;
 413         enum dma_data_direction dma_dir;
 414
 415         if (!q->n_bd)
 416                 return;
 417
 418         /* In the command queue, all the TBs are mapped as BIDI
 419          * so unmap them as such.
 420          */
 421         if (txq_id == trans->shrd->cmd_queue)
 422                 dma_dir = DMA_BIDIRECTIONAL;
 423         else
 424                 dma_dir = DMA_TO_DEVICE;
 425
 426         spin_lock_bh(&txq->lock);
 427         while (q->write_ptr != q->read_ptr) {
 428                 /* The read_ptr needs to bound by q->n_window */
 429                 iwlagn_txq_free_tfd(trans, txq, get_cmd_index(q, q->read_ptr),
 430                                     dma_dir);
 431                 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
 432         }
 433         spin_unlock_bh(&txq->lock);
 434 }
 435
 436 /**
 437  * iwl_tx_queue_free - Deallocate DMA queue.
 438  * @txq: Transmit queue to deallocate.
 439  *
 440  * Empty queue by removing and destroying all BD's.
 441  * Free all buffers.
 442  * 0-fill, but do not free "txq" descriptor structure.
 443  */
 444 static void iwl_tx_queue_free(struct iwl_trans *trans, int txq_id)
 445 {
 446         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 447         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
 448         struct device *dev = trans->dev;
 449         int i;
 450         if (WARN_ON(!txq))
 451                 return;
 452
 453         iwl_tx_queue_unmap(trans, txq_id);
 454
 455         /* De-alloc array of command/tx buffers */
 456
 457         if (txq_id == trans->shrd->cmd_queue)
 458                 for (i = 0; i < txq->q.n_window; i++)
 459                         kfree(txq->cmd[i]);
 460
 461         /* De-alloc circular buffer of TFDs */
 462         if (txq->q.n_bd) {
 463                 dma_free_coherent(dev, sizeof(struct iwl_tfd) *
 464                                   txq->q.n_bd, txq->tfds, txq->q.dma_addr);
 465                 memset(&txq->q.dma_addr, 0, sizeof(txq->q.dma_addr));
 466         }
 467
 468         /* De-alloc array of per-TFD driver data */
 469         kfree(txq->skbs);
 470         txq->skbs = NULL;
 471
 472         /* deallocate arrays */
 473         kfree(txq->cmd);
 474         kfree(txq->meta);
 475         txq->cmd = NULL;
 476         txq->meta = NULL;
 477
 478         /* 0-fill queue descriptor structure */
 479         memset(txq, 0, sizeof(*txq));
 480 }
 481
 482 /**
 483  * iwl_trans_tx_free - Free TXQ Context
 484  *
 485  * Destroy all TX DMA queues and structures
 486  */
 487 static void iwl_trans_pcie_tx_free(struct iwl_trans *trans)
 488 {
 489         int txq_id;
 490         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 491
 492         /* Tx queues */
 493         if (trans_pcie->txq) {
 494                 for (txq_id = 0;
 495                      txq_id < hw_params(trans).max_txq_num; txq_id++)
 496                         iwl_tx_queue_free(trans, txq_id);
 497         }
 498
 499         kfree(trans_pcie->txq);
 500         trans_pcie->txq = NULL;
 501
 502         iwlagn_free_dma_ptr(trans, &trans_pcie->kw);
 503
 504         iwlagn_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
 505 }
 506
 507 /**
 508  * iwl_trans_tx_alloc - allocate TX context
 509  * Allocate all Tx DMA structures and initialize them
 510  *
 511  * @param priv
 512  * @return error code
 513  */
 514 static int iwl_trans_tx_alloc(struct iwl_trans *trans)
 515 {
 516         int ret;
 517         int txq_id, slots_num;
 518         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 519
 520         u16 scd_bc_tbls_size = hw_params(trans).max_txq_num *
 521                         sizeof(struct iwlagn_scd_bc_tbl);
 522
 523         /*It is not allowed to alloc twice, so warn when this happens.
 524          * We cannot rely on the previous allocation, so free and fail */
 525         if (WARN_ON(trans_pcie->txq)) {
 526                 ret = -EINVAL;
 527                 goto error;
 528         }
 529
 530         ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
 531                                    scd_bc_tbls_size);
 532         if (ret) {
 533                 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
 534                 goto error;
 535         }
 536
 537         /* Alloc keep-warm buffer */
 538         ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
 539         if (ret) {
 540                 IWL_ERR(trans, "Keep Warm allocation failed\n");
 541                 goto error;
 542         }
 543
 544         trans_pcie->txq = kcalloc(hw_params(trans).max_txq_num,
 545                                   sizeof(struct iwl_tx_queue), GFP_KERNEL);
 546         if (!trans_pcie->txq) {
 547                 IWL_ERR(trans, "Not enough memory for txq\n");
 548                 ret = ENOMEM;
 549                 goto error;
 550         }
 551
 552         /* Alloc and init all Tx queues, including the command queue (#4/#9) */
 553         for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) {
 554                 slots_num = (txq_id == trans->shrd->cmd_queue) ?
 555                                         TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
 556                 ret = iwl_trans_txq_alloc(trans, &trans_pcie->txq[txq_id],
 557                                           slots_num, txq_id);
 558                 if (ret) {
 559                         IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
 560                         goto error;
 561                 }
 562         }
 563
 564         return 0;
 565
 566 error:
 567         iwl_trans_pcie_tx_free(trans);
 568
 569         return ret;
 570 }
 571 static int iwl_tx_init(struct iwl_trans *trans)
 572 {
 573         int ret;
 574         int txq_id, slots_num;
 575         unsigned long flags;
 576         bool alloc = false;
 577         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 578
 579         if (!trans_pcie->txq) {
 580                 ret = iwl_trans_tx_alloc(trans);
 581                 if (ret)
 582                         goto error;
 583                 alloc = true;
 584         }
 585
 586         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 587
 588         /* Turn off all Tx DMA fifos */
 589         iwl_write_prph(trans, SCD_TXFACT, 0);
 590
 591         /* Tell NIC where to find the "keep warm" buffer */
 592         iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
 593                            trans_pcie->kw.dma >> 4);
 594
 595         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 596
 597         /* Alloc and init all Tx queues, including the command queue (#4/#9) */
 598         for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) {
 599                 slots_num = (txq_id == trans->shrd->cmd_queue) ?
 600                                         TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
 601                 ret = iwl_trans_txq_init(trans, &trans_pcie->txq[txq_id],
 602                                          slots_num, txq_id);
 603                 if (ret) {
 604                         IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
 605                         goto error;
 606                 }
 607         }
 608
 609         return 0;
 610 error:
 611         /*Upon error, free only if we allocated something */
 612         if (alloc)
 613                 iwl_trans_pcie_tx_free(trans);
 614         return ret;
 615 }
 616
 617 static void iwl_set_pwr_vmain(struct iwl_trans *trans)
 618 {
 619 /*
 620  * (for documentation purposes)
 621  * to set power to V_AUX, do:
 622
 623                 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
 624                         iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 625                                                APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 626                                                ~APMG_PS_CTRL_MSK_PWR_SRC);
 627  */
 628
 629         iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 630                                APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 631                                ~APMG_PS_CTRL_MSK_PWR_SRC);
 632 }
 633
 634 /* PCI registers */
 635 #define PCI_CFG_RETRY_TIMEOUT   0x041
 636 #define PCI_CFG_LINK_CTRL_VAL_L0S_EN    0x01
 637 #define PCI_CFG_LINK_CTRL_VAL_L1_EN     0x02
 638
 639 static u16 iwl_pciexp_link_ctrl(struct iwl_trans *trans)
 640 {
 641         int pos;
 642         u16 pci_lnk_ctl;
 643         struct iwl_trans_pcie *trans_pcie =
 644                 IWL_TRANS_GET_PCIE_TRANS(trans);
 645
 646         struct pci_dev *pci_dev = trans_pcie->pci_dev;
 647
 648         pos = pci_pcie_cap(pci_dev);
 649         pci_read_config_word(pci_dev, pos + PCI_EXP_LNKCTL, &pci_lnk_ctl);
 650         return pci_lnk_ctl;
 651 }
 652
 653 static void iwl_apm_config(struct iwl_trans *trans)
 654 {
 655         /*
 656          * HW bug W/A for instability in PCIe bus L0S->L1 transition.
 657          * Check if BIOS (or OS) enabled L1-ASPM on this device.
 658          * If so (likely), disable L0S, so device moves directly L0->L1;
 659          *    costs negligible amount of power savings.
 660          * If not (unlikely), enable L0S, so there is at least some
 661          *    power savings, even without L1.
 662          */
 663         u16 lctl = iwl_pciexp_link_ctrl(trans);
 664
 665         if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
 666                                 PCI_CFG_LINK_CTRL_VAL_L1_EN) {
 667                 /* L1-ASPM enabled; disable(!) L0S */
 668                 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 669                 dev_printk(KERN_INFO, trans->dev,
 670                            "L1 Enabled; Disabling L0S\n");
 671         } else {
 672                 /* L1-ASPM disabled; enable(!) L0S */
 673                 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 674                 dev_printk(KERN_INFO, trans->dev,
 675                            "L1 Disabled; Enabling L0S\n");
 676         }
 677         trans->pm_support = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN);
 678 }
 679
 680 /*
 681  * Start up NIC's basic functionality after it has been reset
 682  * (e.g. after platform boot, or shutdown via iwl_apm_stop())
 683  * NOTE:  This does not load uCode nor start the embedded processor
 684  */
 685 static int iwl_apm_init(struct iwl_trans *trans)
 686 {
 687         int ret = 0;
 688         IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
 689
 690         /*
 691          * Use "set_bit" below rather than "write", to preserve any hardware
 692          * bits already set by default after reset.
 693          */
 694
 695         /* Disable L0S exit timer (platform NMI Work/Around) */
 696         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 697                           CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 698
 699         /*
 700          * Disable L0s without affecting L1;
 701          *  don't wait for ICH L0s (ICH bug W/A)
 702          */
 703         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 704                           CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 705
 706         /* Set FH wait threshold to maximum (HW error during stress W/A) */
 707         iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 708
 709         /*
 710          * Enable HAP INTA (interrupt from management bus) to
 711          * wake device's PCI Express link L1a -> L0s
 712          */
 713         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 714                                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 715
 716         iwl_apm_config(trans);
 717
 718         /* Configure analog phase-lock-loop before activating to D0A */
 719         if (cfg(trans)->base_params->pll_cfg_val)
 720                 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
 721                             cfg(trans)->base_params->pll_cfg_val);
 722
 723         /*
 724          * Set "initialization complete" bit to move adapter from
 725          * D0U* --> D0A* (powered-up active) state.
 726          */
 727         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 728
 729         /*
 730          * Wait for clock stabilization; once stabilized, access to
 731          * device-internal resources is supported, e.g. iwl_write_prph()
 732          * and accesses to uCode SRAM.
 733          */
 734         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 735                         CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 736                         CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 737         if (ret < 0) {
 738                 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
 739                 goto out;
 740         }
 741
 742         /*
 743          * Enable DMA clock and wait for it to stabilize.
 744          *
 745          * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
 746          * do not disable clocks.  This preserves any hardware bits already
 747          * set by default in "CLK_CTRL_REG" after reset.
 748          */
 749         iwl_write_prph(trans, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
 750         udelay(20);
 751
 752         /* Disable L1-Active */
 753         iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 754                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 755
 756         set_bit(STATUS_DEVICE_ENABLED, &trans->shrd->status);
 757
 758 out:
 759         return ret;
 760 }
 761
 762 static int iwl_apm_stop_master(struct iwl_trans *trans)
 763 {
 764         int ret = 0;
 765
 766         /* stop device's busmaster DMA activity */
 767         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
 768
 769         ret = iwl_poll_bit(trans, CSR_RESET,
 770                         CSR_RESET_REG_FLAG_MASTER_DISABLED,
 771                         CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
 772         if (ret)
 773                 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
 774
 775         IWL_DEBUG_INFO(trans, "stop master\n");
 776
 777         return ret;
 778 }
 779
 780 static void iwl_apm_stop(struct iwl_trans *trans)
 781 {
 782         IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
 783
 784         clear_bit(STATUS_DEVICE_ENABLED, &trans->shrd->status);
 785
 786         /* Stop device's DMA activity */
 787         iwl_apm_stop_master(trans);
 788
 789         /* Reset the entire device */
 790         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 791
 792         udelay(10);
 793
 794         /*
 795          * Clear "initialization complete" bit to move adapter from
 796          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 797          */
 798         iwl_clear_bit(trans, CSR_GP_CNTRL,
 799                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 800 }
 801
 802 static int iwl_nic_init(struct iwl_trans *trans)
 803 {
 804         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 805         unsigned long flags;
 806
 807         /* nic_init */
 808         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 809         iwl_apm_init(trans);
 810
 811         /* Set interrupt coalescing calibration timer to default (512 usecs) */
 812         iwl_write8(trans, CSR_INT_COALESCING,
 813                 IWL_HOST_INT_CALIB_TIMEOUT_DEF);
 814
 815         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 816
 817         iwl_set_pwr_vmain(trans);
 818
 819         iwl_op_mode_nic_config(trans->op_mode);
 820
 821 #ifndef CONFIG_IWLWIFI_IDI
 822         /* Allocate the RX queue, or reset if it is already allocated */
 823         iwl_rx_init(trans);
 824 #endif
 825
 826         /* Allocate or reset and init all Tx and Command queues */
 827         if (iwl_tx_init(trans))
 828                 return -ENOMEM;
 829
 830         if (cfg(trans)->base_params->shadow_reg_enable) {
 831                 /* enable shadow regs in HW */
 832                 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL,
 833                         0x800FFFFF);
 834         }
 835
 836         return 0;
 837 }
 838
 839 #define HW_READY_TIMEOUT (50)
 840
 841 /* Note: returns poll_bit return value, which is >= 0 if success */
 842 static int iwl_set_hw_ready(struct iwl_trans *trans)
 843 {
 844         int ret;
 845
 846         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 847                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
 848
 849         /* See if we got it */
 850         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 851                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 852                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 853                                 HW_READY_TIMEOUT);
 854
 855         IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
 856         return ret;
 857 }
 858
 859 /* Note: returns standard 0/-ERROR code */
 860 static int iwl_prepare_card_hw(struct iwl_trans *trans)
 861 {
 862         int ret;
 863
 864         IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
 865
 866         ret = iwl_set_hw_ready(trans);
 867         /* If the card is ready, exit 0 */
 868         if (ret >= 0)
 869                 return 0;
 870
 871         /* If HW is not ready, prepare the conditions to check again */
 872         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 873                         CSR_HW_IF_CONFIG_REG_PREPARE);
 874
 875         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 876                         ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
 877                         CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
 878
 879         if (ret < 0)
 880                 return ret;
 881
 882         /* HW should be ready by now, check again. */
 883         ret = iwl_set_hw_ready(trans);
 884         if (ret >= 0)
 885                 return 0;
 886         return ret;
 887 }
 888
 889 #define IWL_AC_UNSET -1
 890
 891 struct queue_to_fifo_ac {
 892         s8 fifo, ac;
 893 };
 894
 895 static const struct queue_to_fifo_ac iwlagn_default_queue_to_tx_fifo[] = {
 896         { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
 897         { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
 898         { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
 899         { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
 900         { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
 901         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 902         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 903         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 904         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 905         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 906         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 907 };
 908
 909 static const struct queue_to_fifo_ac iwlagn_ipan_queue_to_tx_fifo[] = {
 910         { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
 911         { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
 912         { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
 913         { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
 914         { IWL_TX_FIFO_BK_IPAN, IEEE80211_AC_BK, },
 915         { IWL_TX_FIFO_BE_IPAN, IEEE80211_AC_BE, },
 916         { IWL_TX_FIFO_VI_IPAN, IEEE80211_AC_VI, },
 917         { IWL_TX_FIFO_VO_IPAN, IEEE80211_AC_VO, },
 918         { IWL_TX_FIFO_BE_IPAN, 2, },
 919         { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
 920         { IWL_TX_FIFO_AUX, IWL_AC_UNSET, },
 921 };
 922
 923 static const u8 iwlagn_bss_ac_to_fifo[] = {
 924         IWL_TX_FIFO_VO,
 925         IWL_TX_FIFO_VI,
 926         IWL_TX_FIFO_BE,
 927         IWL_TX_FIFO_BK,
 928 };
 929 static const u8 iwlagn_bss_ac_to_queue[] = {
 930         0, 1, 2, 3,
 931 };
 932 static const u8 iwlagn_pan_ac_to_fifo[] = {
 933         IWL_TX_FIFO_VO_IPAN,
 934         IWL_TX_FIFO_VI_IPAN,
 935         IWL_TX_FIFO_BE_IPAN,
 936         IWL_TX_FIFO_BK_IPAN,
 937 };
 938 static const u8 iwlagn_pan_ac_to_queue[] = {
 939         7, 6, 5, 4,
 940 };
 941
 942 /*
 943  * ucode
 944  */
 945 static int iwl_load_section(struct iwl_trans *trans, const char *name,
 946                             const struct fw_desc *image, u32 dst_addr)
 947 {
 948         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 949         dma_addr_t phy_addr = image->p_addr;
 950         u32 byte_cnt = image->len;
 951         int ret;
 952
 953         trans_pcie->ucode_write_complete = false;
 954
 955         iwl_write_direct32(trans,
 956                 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 957                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 958
 959         iwl_write_direct32(trans,
 960                 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
 961
 962         iwl_write_direct32(trans,
 963                 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 964                 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 965
 966         iwl_write_direct32(trans,
 967                 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 968                 (iwl_get_dma_hi_addr(phy_addr)
 969                         << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 970
 971         iwl_write_direct32(trans,
 972                 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 973                 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
 974                 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
 975                 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 976
 977         iwl_write_direct32(trans,
 978                 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 979                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE       |
 980                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE    |
 981                 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 982
 983         IWL_DEBUG_FW(trans, "%s uCode section being loaded...\n", name);
 984         ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
 985                                  trans_pcie->ucode_write_complete, 5 * HZ);
 986         if (!ret) {
 987                 IWL_ERR(trans, "Could not load the %s uCode section\n",
 988                         name);
 989                 return -ETIMEDOUT;
 990         }
 991
 992         return 0;
 993 }
 994
 995 static int iwl_load_given_ucode(struct iwl_trans *trans,
 996                                 const struct fw_img *image)
 997 {
 998         int ret = 0;
 999
1000         ret = iwl_load_section(trans, "INST", &image->code,
1001                                    IWLAGN_RTC_INST_LOWER_BOUND);
1002         if (ret)
1003                 return ret;
1004
1005         ret = iwl_load_section(trans, "DATA", &image->data,
1006                                     IWLAGN_RTC_DATA_LOWER_BOUND);
1007         if (ret)
1008                 return ret;
1009
1010         /* Remove all resets to allow NIC to operate */
1011         iwl_write32(trans, CSR_RESET, 0);
1012
1013         return 0;
1014 }
1015
1016 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1017                                    const struct fw_img *fw)
1018 {
1019         int ret;
1020         struct iwl_trans_pcie *trans_pcie =
1021                 IWL_TRANS_GET_PCIE_TRANS(trans);
1022         bool hw_rfkill;
1023
1024         trans_pcie->ac_to_queue[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_queue;
1025         trans_pcie->ac_to_queue[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_queue;
1026
1027         trans_pcie->ac_to_fifo[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_fifo;
1028         trans_pcie->ac_to_fifo[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_fifo;
1029
1030         trans_pcie->mcast_queue[IWL_RXON_CTX_BSS] = 0;
1031         trans_pcie->mcast_queue[IWL_RXON_CTX_PAN] = IWL_IPAN_MCAST_QUEUE;
1032
1033         /* This may fail if AMT took ownership of the device */
1034         if (iwl_prepare_card_hw(trans)) {
1035                 IWL_WARN(trans, "Exit HW not ready\n");
1036                 return -EIO;
1037         }
1038
1039         /* If platform's RF_KILL switch is NOT set to KILL */
1040         hw_rfkill = !(iwl_read32(trans, CSR_GP_CNTRL) &
1041                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
1042         iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1043
1044         if (hw_rfkill) {
1045                 iwl_enable_rfkill_int(trans);
1046                 return -ERFKILL;
1047         }
1048
1049         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1050
1051         ret = iwl_nic_init(trans);
1052         if (ret) {
1053                 IWL_ERR(trans, "Unable to init nic\n");
1054                 return ret;
1055         }
1056
1057         /* make sure rfkill handshake bits are cleared */
1058         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1059         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1060                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1061
1062         /* clear (again), then enable host interrupts */
1063         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1064         iwl_enable_interrupts(trans);
1065
1066         /* really make sure rfkill handshake bits are cleared */
1067         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1068         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1069
1070         /* Load the given image to the HW */
1071         return iwl_load_given_ucode(trans, fw);
1072 }
1073
1074 /*
1075  * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
1076  * must be called under the irq lock and with MAC access
1077  */
1078 static void iwl_trans_txq_set_sched(struct iwl_trans *trans, u32 mask)
1079 {
1080         struct iwl_trans_pcie __maybe_unused *trans_pcie =
1081                 IWL_TRANS_GET_PCIE_TRANS(trans);
1082
1083         lockdep_assert_held(&trans_pcie->irq_lock);
1084
1085         iwl_write_prph(trans, SCD_TXFACT, mask);
1086 }
1087
1088 static void iwl_tx_start(struct iwl_trans *trans)
1089 {
1090         const struct queue_to_fifo_ac *queue_to_fifo;
1091         struct iwl_trans_pcie *trans_pcie =
1092                 IWL_TRANS_GET_PCIE_TRANS(trans);
1093         u32 a;
1094         unsigned long flags;
1095         int i, chan;
1096         u32 reg_val;
1097
1098         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1099
1100         trans_pcie->scd_base_addr =
1101                 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
1102         a = trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND;
1103         /* reset conext data memory */
1104         for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND;
1105                 a += 4)
1106                 iwl_write_targ_mem(trans, a, 0);
1107         /* reset tx status memory */
1108         for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND;
1109                 a += 4)
1110                 iwl_write_targ_mem(trans, a, 0);
1111         for (; a < trans_pcie->scd_base_addr +
1112                SCD_TRANS_TBL_OFFSET_QUEUE(hw_params(trans).max_txq_num);
1113                a += 4)
1114                 iwl_write_targ_mem(trans, a, 0);
1115
1116         iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
1117                        trans_pcie->scd_bc_tbls.dma >> 10);
1118
1119         /* Enable DMA channel */
1120         for (chan = 0; chan < FH_TCSR_CHNL_NUM ; chan++)
1121                 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
1122                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
1123                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
1124
1125         /* Update FH chicken bits */
1126         reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
1127         iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
1128                            reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
1129
1130         iwl_write_prph(trans, SCD_QUEUECHAIN_SEL,
1131                 SCD_QUEUECHAIN_SEL_ALL(trans));
1132         iwl_write_prph(trans, SCD_AGGR_SEL, 0);
1133
1134         /* initiate the queues */
1135         for (i = 0; i < hw_params(trans).max_txq_num; i++) {
1136                 iwl_write_prph(trans, SCD_QUEUE_RDPTR(i), 0);
1137                 iwl_write_direct32(trans, HBUS_TARG_WRPTR, 0 | (i << 8));
1138                 iwl_write_targ_mem(trans, trans_pcie->scd_base_addr +
1139                                 SCD_CONTEXT_QUEUE_OFFSET(i), 0);
1140                 iwl_write_targ_mem(trans, trans_pcie->scd_base_addr +
1141                                 SCD_CONTEXT_QUEUE_OFFSET(i) +
1142                                 sizeof(u32),
1143                                 ((SCD_WIN_SIZE <<
1144                                 SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1145                                 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1146                                 ((SCD_FRAME_LIMIT <<
1147                                 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1148                                 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1149         }
1150
1151         iwl_write_prph(trans, SCD_INTERRUPT_MASK,
1152                         IWL_MASK(0, hw_params(trans).max_txq_num));
1153
1154         /* Activate all Tx DMA/FIFO channels */
1155         iwl_trans_txq_set_sched(trans, IWL_MASK(0, 7));
1156
1157         /* map queues to FIFOs */
1158         if (trans->shrd->valid_contexts != BIT(IWL_RXON_CTX_BSS))
1159                 queue_to_fifo = iwlagn_ipan_queue_to_tx_fifo;
1160         else
1161                 queue_to_fifo = iwlagn_default_queue_to_tx_fifo;
1162
1163         iwl_trans_set_wr_ptrs(trans, trans->shrd->cmd_queue, 0);
1164
1165         /* make sure all queue are not stopped */
1166         memset(&trans_pcie->queue_stopped[0], 0,
1167                 sizeof(trans_pcie->queue_stopped));
1168         for (i = 0; i < 4; i++)
1169                 atomic_set(&trans_pcie->queue_stop_count[i], 0);
1170
1171         /* reset to 0 to enable all the queue first */
1172         trans_pcie->txq_ctx_active_msk = 0;
1173
1174         BUILD_BUG_ON(ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo) <
1175                                                 IWLAGN_FIRST_AMPDU_QUEUE);
1176         BUILD_BUG_ON(ARRAY_SIZE(iwlagn_ipan_queue_to_tx_fifo) <
1177                                                 IWLAGN_FIRST_AMPDU_QUEUE);
1178
1179         for (i = 0; i < IWLAGN_FIRST_AMPDU_QUEUE; i++) {
1180                 int fifo = queue_to_fifo[i].fifo;
1181                 int ac = queue_to_fifo[i].ac;
1182
1183                 iwl_txq_ctx_activate(trans_pcie, i);
1184
1185                 if (fifo == IWL_TX_FIFO_UNUSED)
1186                         continue;
1187
1188                 if (ac != IWL_AC_UNSET)
1189                         iwl_set_swq_id(&trans_pcie->txq[i], ac, i);
1190                 iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[i],
1191                                               fifo, 0);
1192         }
1193
1194         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1195
1196         /* Enable L1-Active */
1197         iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
1198                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1199 }
1200
1201 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans)
1202 {
1203         iwl_reset_ict(trans);
1204         iwl_tx_start(trans);
1205 }
1206
1207 /**
1208  * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
1209  */
1210 static int iwl_trans_tx_stop(struct iwl_trans *trans)
1211 {
1212         int ch, txq_id, ret;
1213         unsigned long flags;
1214         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1215
1216         /* Turn off all Tx DMA fifos */
1217         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1218
1219         iwl_trans_txq_set_sched(trans, 0);
1220
1221         /* Stop each Tx DMA channel, and wait for it to be idle */
1222         for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
1223                 iwl_write_direct32(trans,
1224                                    FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
1225                 ret = iwl_poll_direct_bit(trans, FH_TSSR_TX_STATUS_REG,
1226                                     FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
1227                                     1000);
1228                 if (ret < 0)
1229                         IWL_ERR(trans, "Failing on timeout while stopping"
1230                             " DMA channel %d [0x%08x]", ch,
1231                             iwl_read_direct32(trans,
1232                                               FH_TSSR_TX_STATUS_REG));
1233         }
1234         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1235
1236         if (!trans_pcie->txq) {
1237                 IWL_WARN(trans, "Stopping tx queues that aren't allocated...");
1238                 return 0;
1239         }
1240
1241         /* Unmap DMA from host system and free skb's */
1242         for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++)
1243                 iwl_tx_queue_unmap(trans, txq_id);
1244
1245         return 0;
1246 }
1247
1248 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
1249 {
1250         unsigned long flags;
1251         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1252
1253         /* tell the device to stop sending interrupts */
1254         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1255         iwl_disable_interrupts(trans);
1256         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1257
1258         /* device going down, Stop using ICT table */
1259         iwl_disable_ict(trans);
1260
1261         /*
1262          * If a HW restart happens during firmware loading,
1263          * then the firmware loading might call this function
1264          * and later it might be called again due to the
1265          * restart. So don't process again if the device is
1266          * already dead.
1267          */
1268         if (test_bit(STATUS_DEVICE_ENABLED, &trans->shrd->status)) {
1269                 iwl_trans_tx_stop(trans);
1270 #ifndef CONFIG_IWLWIFI_IDI
1271                 iwl_trans_rx_stop(trans);
1272 #endif
1273                 /* Power-down device's busmaster DMA clocks */
1274                 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1275                                APMG_CLK_VAL_DMA_CLK_RQT);
1276                 udelay(5);
1277         }
1278
1279         /* Make sure (redundant) we've released our request to stay awake */
1280         iwl_clear_bit(trans, CSR_GP_CNTRL,
1281                         CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1282
1283         /* Stop the device, and put it in low power state */
1284         iwl_apm_stop(trans);
1285
1286         /* Upon stop, the APM issues an interrupt if HW RF kill is set.
1287          * Clean again the interrupt here
1288          */
1289         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1290         iwl_disable_interrupts(trans);
1291         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1292
1293         /* wait to make sure we flush pending tasklet*/
1294         synchronize_irq(trans_pcie->irq);
1295         tasklet_kill(&trans_pcie->irq_tasklet);
1296
1297         cancel_work_sync(&trans_pcie->rx_replenish);
1298
1299         /* stop and reset the on-board processor */
1300         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
1301 }
1302
1303 static void iwl_trans_pcie_wowlan_suspend(struct iwl_trans *trans)
1304 {
1305         /* let the ucode operate on its own */
1306         iwl_write32(trans, CSR_UCODE_DRV_GP1_SET,
1307                     CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);
1308
1309         iwl_disable_interrupts(trans);
1310         iwl_clear_bit(trans, CSR_GP_CNTRL,
1311                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1312 }
1313
1314 static int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
1315                 struct iwl_device_cmd *dev_cmd, enum iwl_rxon_context_id ctx,
1316                 u8 sta_id, u8 tid)
1317 {
1318         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1319         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1320         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1321         struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *) dev_cmd->payload;
1322         struct iwl_cmd_meta *out_meta;
1323         struct iwl_tx_queue *txq;
1324         struct iwl_queue *q;
1325
1326         dma_addr_t phys_addr = 0;
1327         dma_addr_t txcmd_phys;
1328         dma_addr_t scratch_phys;
1329         u16 len, firstlen, secondlen;
1330         u8 wait_write_ptr = 0;
1331         u8 txq_id;
1332         bool is_agg = false;
1333         __le16 fc = hdr->frame_control;
1334         u8 hdr_len = ieee80211_hdrlen(fc);
1335         u16 __maybe_unused wifi_seq;
1336
1337         /*
1338          * Send this frame after DTIM -- there's a special queue
1339          * reserved for this for contexts that support AP mode.
1340          */
1341         if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
1342                 txq_id = trans_pcie->mcast_queue[ctx];
1343
1344                 /*
1345                  * The microcode will clear the more data
1346                  * bit in the last frame it transmits.
1347                  */
1348                 hdr->frame_control |=
1349                         cpu_to_le16(IEEE80211_FCTL_MOREDATA);
1350         } else if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN)
1351                 txq_id = IWL_AUX_QUEUE;
1352         else
1353                 txq_id =
1354                     trans_pcie->ac_to_queue[ctx][skb_get_queue_mapping(skb)];
1355
1356         /* aggregation is on for this <sta,tid> */
1357         if (info->flags & IEEE80211_TX_CTL_AMPDU) {
1358                 WARN_ON(tid >= IWL_MAX_TID_COUNT);
1359                 txq_id = trans_pcie->agg_txq[sta_id][tid];
1360                 is_agg = true;
1361         }
1362
1363         txq = &trans_pcie->txq[txq_id];
1364         q = &txq->q;
1365
1366         spin_lock(&txq->lock);
1367
1368         /* In AGG mode, the index in the ring must correspond to the WiFi
1369          * sequence number. This is a HW requirements to help the SCD to parse
1370          * the BA.
1371          * Check here that the packets are in the right place on the ring.
1372          */
1373 #ifdef CONFIG_IWLWIFI_DEBUG
1374         wifi_seq = SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
1375         WARN_ONCE(is_agg && ((wifi_seq & 0xff) != q->write_ptr),
1376                   "Q: %d WiFi Seq %d tfdNum %d",
1377                   txq_id, wifi_seq, q->write_ptr);
1378 #endif
1379
1380         /* Set up driver data for this TFD */
1381         txq->skbs[q->write_ptr] = skb;
1382         txq->cmd[q->write_ptr] = dev_cmd;
1383
1384         dev_cmd->hdr.cmd = REPLY_TX;
1385         dev_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
1386                                 INDEX_TO_SEQ(q->write_ptr)));
1387
1388         /* Set up first empty entry in queue's array of Tx/cmd buffers */
1389         out_meta = &txq->meta[q->write_ptr];
1390
1391         /*
1392          * Use the first empty entry in this queue's command buffer array
1393          * to contain the Tx command and MAC header concatenated together
1394          * (payload data will be in another buffer).
1395          * Size of this varies, due to varying MAC header length.
1396          * If end is not dword aligned, we'll have 2 extra bytes at the end
1397          * of the MAC header (device reads on dword boundaries).
1398          * We'll tell device about this padding later.
1399          */
1400         len = sizeof(struct iwl_tx_cmd) +
1401                 sizeof(struct iwl_cmd_header) + hdr_len;
1402         firstlen = (len + 3) & ~3;
1403
1404         /* Tell NIC about any 2-byte padding after MAC header */
1405         if (firstlen != len)
1406                 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1407
1408         /* Physical address of this Tx command's header (not MAC header!),
1409          * within command buffer array. */
1410         txcmd_phys = dma_map_single(trans->dev,
1411                                     &dev_cmd->hdr, firstlen,
1412                                     DMA_BIDIRECTIONAL);
1413         if (unlikely(dma_mapping_error(trans->dev, txcmd_phys)))
1414                 goto out_err;
1415         dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
1416         dma_unmap_len_set(out_meta, len, firstlen);
1417
1418         if (!ieee80211_has_morefrags(fc)) {
1419                 txq->need_update = 1;
1420         } else {
1421                 wait_write_ptr = 1;
1422                 txq->need_update = 0;
1423         }
1424
1425         /* Set up TFD's 2nd entry to point directly to remainder of skb,
1426          * if any (802.11 null frames have no payload). */
1427         secondlen = skb->len - hdr_len;
1428         if (secondlen > 0) {
1429                 phys_addr = dma_map_single(trans->dev, skb->data + hdr_len,
1430                                            secondlen, DMA_TO_DEVICE);
1431                 if (unlikely(dma_mapping_error(trans->dev, phys_addr))) {
1432                         dma_unmap_single(trans->dev,
1433                                          dma_unmap_addr(out_meta, mapping),
1434                                          dma_unmap_len(out_meta, len),
1435                                          DMA_BIDIRECTIONAL);
1436                         goto out_err;
1437                 }
1438         }
1439
1440         /* Attach buffers to TFD */
1441         iwlagn_txq_attach_buf_to_tfd(trans, txq, txcmd_phys, firstlen, 1);
1442         if (secondlen > 0)
1443                 iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr,
1444                                              secondlen, 0);
1445
1446         scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
1447                                 offsetof(struct iwl_tx_cmd, scratch);
1448
1449         /* take back ownership of DMA buffer to enable update */
1450         dma_sync_single_for_cpu(trans->dev, txcmd_phys, firstlen,
1451                         DMA_BIDIRECTIONAL);
1452         tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1453         tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1454
1455         IWL_DEBUG_TX(trans, "sequence nr = 0X%x\n",
1456                      le16_to_cpu(dev_cmd->hdr.sequence));
1457         IWL_DEBUG_TX(trans, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
1458         iwl_print_hex_dump(trans, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
1459         iwl_print_hex_dump(trans, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
1460
1461         /* Set up entry for this TFD in Tx byte-count array */
1462         iwl_trans_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len));
1463
1464         dma_sync_single_for_device(trans->dev, txcmd_phys, firstlen,
1465                         DMA_BIDIRECTIONAL);
1466
1467         trace_iwlwifi_dev_tx(trans->dev,
1468                              &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr],
1469                              sizeof(struct iwl_tfd),
1470                              &dev_cmd->hdr, firstlen,
1471                              skb->data + hdr_len, secondlen);
1472
1473         /* Tell device the write index *just past* this latest filled TFD */
1474         q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1475         iwl_txq_update_write_ptr(trans, txq);
1476
1477         /*
1478          * At this point the frame is "transmitted" successfully
1479          * and we will get a TX status notification eventually,
1480          * regardless of the value of ret. "ret" only indicates
1481          * whether or not we should update the write pointer.
1482          */
1483         if (iwl_queue_space(q) < q->high_mark) {
1484                 if (wait_write_ptr) {
1485                         txq->need_update = 1;
1486                         iwl_txq_update_write_ptr(trans, txq);
1487                 } else {
1488                         iwl_stop_queue(trans, txq, "Queue is full");
1489                 }
1490         }
1491         spin_unlock(&txq->lock);
1492         return 0;
1493  out_err:
1494         spin_unlock(&txq->lock);
1495         return -1;
1496 }
1497
1498 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1499 {
1500         struct iwl_trans_pcie *trans_pcie =
1501                 IWL_TRANS_GET_PCIE_TRANS(trans);
1502         int err;
1503         bool hw_rfkill;
1504
1505         trans_pcie->inta_mask = CSR_INI_SET_MASK;
1506
1507         if (!trans_pcie->irq_requested) {
1508                 tasklet_init(&trans_pcie->irq_tasklet, (void (*)(unsigned long))
1509                         iwl_irq_tasklet, (unsigned long)trans);
1510
1511                 iwl_alloc_isr_ict(trans);
1512
1513                 err = request_irq(trans_pcie->irq, iwl_isr_ict, IRQF_SHARED,
1514                         DRV_NAME, trans);
1515                 if (err) {
1516                         IWL_ERR(trans, "Error allocating IRQ %d\n",
1517                                 trans_pcie->irq);
1518                         goto error;
1519                 }
1520
1521                 INIT_WORK(&trans_pcie->rx_replenish, iwl_bg_rx_replenish);
1522                 trans_pcie->irq_requested = true;
1523         }
1524
1525         err = iwl_prepare_card_hw(trans);
1526         if (err) {
1527                 IWL_ERR(trans, "Error while preparing HW: %d", err);
1528                 goto err_free_irq;
1529         }
1530
1531         iwl_apm_init(trans);
1532
1533         hw_rfkill = !(iwl_read32(trans, CSR_GP_CNTRL) &
1534                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
1535         iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1536
1537         return err;
1538
1539 err_free_irq:
1540         free_irq(trans_pcie->irq, trans);
1541 error:
1542         iwl_free_isr_ict(trans);
1543         tasklet_kill(&trans_pcie->irq_tasklet);
1544         return err;
1545 }
1546
1547 static void iwl_trans_pcie_stop_hw(struct iwl_trans *trans)
1548 {
1549         iwl_apm_stop(trans);
1550
1551         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1552
1553         /* Even if we stop the HW, we still want the RF kill interrupt */
1554         iwl_enable_rfkill_int(trans);
1555 }
1556
1557 static int iwl_trans_pcie_reclaim(struct iwl_trans *trans, int sta_id, int tid,
1558                       int txq_id, int ssn, struct sk_buff_head *skbs)
1559 {
1560         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1561         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
1562         /* n_bd is usually 256 => n_bd - 1 = 0xff */
1563         int tfd_num = ssn & (txq->q.n_bd - 1);
1564         int freed = 0;
1565
1566         spin_lock(&txq->lock);
1567
1568         txq->time_stamp = jiffies;
1569
1570         if (unlikely(txq_id >= IWLAGN_FIRST_AMPDU_QUEUE &&
1571                      tid != IWL_TID_NON_QOS &&
1572                      txq_id != trans_pcie->agg_txq[sta_id][tid])) {
1573                 /*
1574                  * FIXME: this is a uCode bug which need to be addressed,
1575                  * log the information and return for now.
1576                  * Since it is can possibly happen very often and in order
1577                  * not to fill the syslog, don't use IWL_ERR or IWL_WARN
1578                  */
1579                 IWL_DEBUG_TX_QUEUES(trans, "Bad queue mapping txq_id %d, "
1580                         "agg_txq[sta_id[tid] %d", txq_id,
1581                         trans_pcie->agg_txq[sta_id][tid]);
1582                 spin_unlock(&txq->lock);
1583                 return 1;
1584         }
1585
1586         if (txq->q.read_ptr != tfd_num) {
1587                 IWL_DEBUG_TX_REPLY(trans, "[Q %d | AC %d] %d -> %d (%d)\n",
1588                                 txq_id, iwl_get_queue_ac(txq), txq->q.read_ptr,
1589                                 tfd_num, ssn);
1590                 freed = iwl_tx_queue_reclaim(trans, txq_id, tfd_num, skbs);
1591                 if (iwl_queue_space(&txq->q) > txq->q.low_mark)
1592                         iwl_wake_queue(trans, txq, "Packets reclaimed");
1593         }
1594
1595         spin_unlock(&txq->lock);
1596         return 0;
1597 }
1598
1599 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1600 {
1601         writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1602 }
1603
1604 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1605 {
1606         writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1607 }
1608
1609 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1610 {
1611         return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1612 }
1613
1614 static void iwl_trans_pcie_free(struct iwl_trans *trans)
1615 {
1616         struct iwl_trans_pcie *trans_pcie =
1617                 IWL_TRANS_GET_PCIE_TRANS(trans);
1618
1619         iwl_trans_pcie_tx_free(trans);
1620 #ifndef CONFIG_IWLWIFI_IDI
1621         iwl_trans_pcie_rx_free(trans);
1622 #endif
1623         if (trans_pcie->irq_requested == true) {
1624                 free_irq(trans_pcie->irq, trans);
1625                 iwl_free_isr_ict(trans);
1626         }
1627
1628         pci_disable_msi(trans_pcie->pci_dev);
1629         iounmap(trans_pcie->hw_base);
1630         pci_release_regions(trans_pcie->pci_dev);
1631         pci_disable_device(trans_pcie->pci_dev);
1632
1633         trans->shrd->trans = NULL;
1634         kfree(trans);
1635 }
1636
1637 #ifdef CONFIG_PM_SLEEP
1638 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
1639 {
1640         return 0;
1641 }
1642
1643 static int iwl_trans_pcie_resume(struct iwl_trans *trans)
1644 {
1645         bool hw_rfkill;
1646
1647         hw_rfkill = !(iwl_read32(trans, CSR_GP_CNTRL) &
1648                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
1649
1650         if (hw_rfkill)
1651                 iwl_enable_rfkill_int(trans);
1652         else
1653                 iwl_enable_interrupts(trans);
1654
1655         iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1656
1657         return 0;
1658 }
1659 #endif /* CONFIG_PM_SLEEP */
1660
1661 #define IWL_FLUSH_WAIT_MS       2000
1662
1663 static int iwl_trans_pcie_wait_tx_queue_empty(struct iwl_trans *trans)
1664 {
1665         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1666         struct iwl_tx_queue *txq;
1667         struct iwl_queue *q;
1668         int cnt;
1669         unsigned long now = jiffies;
1670         int ret = 0;
1671
1672         /* waiting for all the tx frames complete might take a while */
1673         for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) {
1674                 if (cnt == trans->shrd->cmd_queue)
1675                         continue;
1676                 txq = &trans_pcie->txq[cnt];
1677                 q = &txq->q;
1678                 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1679                        now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1680                         msleep(1);
1681
1682                 if (q->read_ptr != q->write_ptr) {
1683                         IWL_ERR(trans, "fail to flush all tx fifo queues\n");
1684                         ret = -ETIMEDOUT;
1685                         break;
1686                 }
1687         }
1688         return ret;
1689 }
1690
1691 /*
1692  * On every watchdog tick we check (latest) time stamp. If it does not
1693  * change during timeout period and queue is not empty we reset firmware.
1694  */
1695 static int iwl_trans_pcie_check_stuck_queue(struct iwl_trans *trans, int cnt)
1696 {
1697         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1698         struct iwl_tx_queue *txq = &trans_pcie->txq[cnt];
1699         struct iwl_queue *q = &txq->q;
1700         unsigned long timeout;
1701
1702         if (q->read_ptr == q->write_ptr) {
1703                 txq->time_stamp = jiffies;
1704                 return 0;
1705         }
1706
1707         timeout = txq->time_stamp +
1708                   msecs_to_jiffies(hw_params(trans).wd_timeout);
1709
1710         if (time_after(jiffies, timeout)) {
1711                 IWL_ERR(trans, "Queue %d stuck for %u ms.\n", q->id,
1712                         hw_params(trans).wd_timeout);
1713                 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1714                         q->read_ptr, q->write_ptr);
1715                 IWL_ERR(trans, "Current HW read_ptr %d write_ptr %d\n",
1716                         iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt))
1717                                 & (TFD_QUEUE_SIZE_MAX - 1),
1718                         iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1719                 return 1;
1720         }
1721
1722         return 0;
1723 }
1724
1725 static const char *get_fh_string(int cmd)
1726 {
1727         switch (cmd) {
1728         IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
1729         IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
1730         IWL_CMD(FH_RSCSR_CHNL0_WPTR);
1731         IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
1732         IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
1733         IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
1734         IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
1735         IWL_CMD(FH_TSSR_TX_STATUS_REG);
1736         IWL_CMD(FH_TSSR_TX_ERROR_REG);
1737         default:
1738                 return "UNKNOWN";
1739         }
1740 }
1741
1742 int iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display)
1743 {
1744         int i;
1745 #ifdef CONFIG_IWLWIFI_DEBUG
1746         int pos = 0;
1747         size_t bufsz = 0;
1748 #endif
1749         static const u32 fh_tbl[] = {
1750                 FH_RSCSR_CHNL0_STTS_WPTR_REG,
1751                 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
1752                 FH_RSCSR_CHNL0_WPTR,
1753                 FH_MEM_RCSR_CHNL0_CONFIG_REG,
1754                 FH_MEM_RSSR_SHARED_CTRL_REG,
1755                 FH_MEM_RSSR_RX_STATUS_REG,
1756                 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
1757                 FH_TSSR_TX_STATUS_REG,
1758                 FH_TSSR_TX_ERROR_REG
1759         };
1760 #ifdef CONFIG_IWLWIFI_DEBUG
1761         if (display) {
1762                 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
1763                 *buf = kmalloc(bufsz, GFP_KERNEL);
1764                 if (!*buf)
1765                         return -ENOMEM;
1766                 pos += scnprintf(*buf + pos, bufsz - pos,
1767                                 "FH register values:\n");
1768                 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1769                         pos += scnprintf(*buf + pos, bufsz - pos,
1770                                 "  %34s: 0X%08x\n",
1771                                 get_fh_string(fh_tbl[i]),
1772                                 iwl_read_direct32(trans, fh_tbl[i]));
1773                 }
1774                 return pos;
1775         }
1776 #endif
1777         IWL_ERR(trans, "FH register values:\n");
1778         for (i = 0; i <  ARRAY_SIZE(fh_tbl); i++) {
1779                 IWL_ERR(trans, "  %34s: 0X%08x\n",
1780                         get_fh_string(fh_tbl[i]),
1781                         iwl_read_direct32(trans, fh_tbl[i]));
1782         }
1783         return 0;
1784 }
1785
1786 static const char *get_csr_string(int cmd)
1787 {
1788         switch (cmd) {
1789         IWL_CMD(CSR_HW_IF_CONFIG_REG);
1790         IWL_CMD(CSR_INT_COALESCING);
1791         IWL_CMD(CSR_INT);
1792         IWL_CMD(CSR_INT_MASK);
1793         IWL_CMD(CSR_FH_INT_STATUS);
1794         IWL_CMD(CSR_GPIO_IN);
1795         IWL_CMD(CSR_RESET);
1796         IWL_CMD(CSR_GP_CNTRL);
1797         IWL_CMD(CSR_HW_REV);
1798         IWL_CMD(CSR_EEPROM_REG);
1799         IWL_CMD(CSR_EEPROM_GP);
1800         IWL_CMD(CSR_OTP_GP_REG);
1801         IWL_CMD(CSR_GIO_REG);
1802         IWL_CMD(CSR_GP_UCODE_REG);
1803         IWL_CMD(CSR_GP_DRIVER_REG);
1804         IWL_CMD(CSR_UCODE_DRV_GP1);
1805         IWL_CMD(CSR_UCODE_DRV_GP2);
1806         IWL_CMD(CSR_LED_REG);
1807         IWL_CMD(CSR_DRAM_INT_TBL_REG);
1808         IWL_CMD(CSR_GIO_CHICKEN_BITS);
1809         IWL_CMD(CSR_ANA_PLL_CFG);
1810         IWL_CMD(CSR_HW_REV_WA_REG);
1811         IWL_CMD(CSR_DBG_HPET_MEM_REG);
1812         default:
1813                 return "UNKNOWN";
1814         }
1815 }
1816
1817 void iwl_dump_csr(struct iwl_trans *trans)
1818 {
1819         int i;
1820         static const u32 csr_tbl[] = {
1821                 CSR_HW_IF_CONFIG_REG,
1822                 CSR_INT_COALESCING,
1823                 CSR_INT,
1824                 CSR_INT_MASK,
1825                 CSR_FH_INT_STATUS,
1826                 CSR_GPIO_IN,
1827                 CSR_RESET,
1828                 CSR_GP_CNTRL,
1829                 CSR_HW_REV,
1830                 CSR_EEPROM_REG,
1831                 CSR_EEPROM_GP,
1832                 CSR_OTP_GP_REG,
1833                 CSR_GIO_REG,
1834                 CSR_GP_UCODE_REG,
1835                 CSR_GP_DRIVER_REG,
1836                 CSR_UCODE_DRV_GP1,
1837                 CSR_UCODE_DRV_GP2,
1838                 CSR_LED_REG,
1839                 CSR_DRAM_INT_TBL_REG,
1840                 CSR_GIO_CHICKEN_BITS,
1841                 CSR_ANA_PLL_CFG,
1842                 CSR_HW_REV_WA_REG,
1843                 CSR_DBG_HPET_MEM_REG
1844         };
1845         IWL_ERR(trans, "CSR values:\n");
1846         IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1847                 "CSR_INT_PERIODIC_REG)\n");
1848         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
1849                 IWL_ERR(trans, "  %25s: 0X%08x\n",
1850                         get_csr_string(csr_tbl[i]),
1851                         iwl_read32(trans, csr_tbl[i]));
1852         }
1853 }
1854
1855 #ifdef CONFIG_IWLWIFI_DEBUGFS
1856 /* create and remove of files */
1857 #define DEBUGFS_ADD_FILE(name, parent, mode) do {                       \
1858         if (!debugfs_create_file(#name, mode, parent, trans,            \
1859                                  &iwl_dbgfs_##name##_ops))              \
1860                 return -ENOMEM;                                         \
1861 } while (0)
1862
1863 /* file operation */
1864 #define DEBUGFS_READ_FUNC(name)                                         \
1865 static ssize_t iwl_dbgfs_##name##_read(struct file *file,               \
1866                                         char __user *user_buf,          \
1867                                         size_t count, loff_t *ppos);
1868
1869 #define DEBUGFS_WRITE_FUNC(name)                                        \
1870 static ssize_t iwl_dbgfs_##name##_write(struct file *file,              \
1871                                         const char __user *user_buf,    \
1872                                         size_t count, loff_t *ppos);
1873
1874
1875 static int iwl_dbgfs_open_file_generic(struct inode *inode, struct file *file)
1876 {
1877         file->private_data = inode->i_private;
1878         return 0;
1879 }
1880
1881 #define DEBUGFS_READ_FILE_OPS(name)                                     \
1882         DEBUGFS_READ_FUNC(name);                                        \
1883 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1884         .read = iwl_dbgfs_##name##_read,                                \
1885         .open = iwl_dbgfs_open_file_generic,                            \
1886         .llseek = generic_file_llseek,                                  \
1887 };
1888
1889 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
1890         DEBUGFS_WRITE_FUNC(name);                                       \
1891 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1892         .write = iwl_dbgfs_##name##_write,                              \
1893         .open = iwl_dbgfs_open_file_generic,                            \
1894         .llseek = generic_file_llseek,                                  \
1895 };
1896
1897 #define DEBUGFS_READ_WRITE_FILE_OPS(name)                               \
1898         DEBUGFS_READ_FUNC(name);                                        \
1899         DEBUGFS_WRITE_FUNC(name);                                       \
1900 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1901         .write = iwl_dbgfs_##name##_write,                              \
1902         .read = iwl_dbgfs_##name##_read,                                \
1903         .open = iwl_dbgfs_open_file_generic,                            \
1904         .llseek = generic_file_llseek,                                  \
1905 };
1906
1907 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1908                                                 char __user *user_buf,
1909                                                 size_t count, loff_t *ppos)
1910 {
1911         struct iwl_trans *trans = file->private_data;
1912         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1913         struct iwl_tx_queue *txq;
1914         struct iwl_queue *q;
1915         char *buf;
1916         int pos = 0;
1917         int cnt;
1918         int ret;
1919         const size_t bufsz = sizeof(char) * 64 * hw_params(trans).max_txq_num;
1920
1921         if (!trans_pcie->txq) {
1922                 IWL_ERR(trans, "txq not ready\n");
1923                 return -EAGAIN;
1924         }
1925         buf = kzalloc(bufsz, GFP_KERNEL);
1926         if (!buf)
1927                 return -ENOMEM;
1928
1929         for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) {
1930                 txq = &trans_pcie->txq[cnt];
1931                 q = &txq->q;
1932                 pos += scnprintf(buf + pos, bufsz - pos,
1933                                 "hwq %.2d: read=%u write=%u stop=%d"
1934                                 " swq_id=%#.2x (ac %d/hwq %d)\n",
1935                                 cnt, q->read_ptr, q->write_ptr,
1936                                 !!test_bit(cnt, trans_pcie->queue_stopped),
1937                                 txq->swq_id, txq->swq_id & 3,
1938                                 (txq->swq_id >> 2) & 0x1f);
1939                 if (cnt >= 4)
1940                         continue;
1941                 /* for the ACs, display the stop count too */
1942                 pos += scnprintf(buf + pos, bufsz - pos,
1943                         "        stop-count: %d\n",
1944                         atomic_read(&trans_pcie->queue_stop_count[cnt]));
1945         }
1946         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1947         kfree(buf);
1948         return ret;
1949 }
1950
1951 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1952                                                 char __user *user_buf,
1953                                                 size_t count, loff_t *ppos) {
1954         struct iwl_trans *trans = file->private_data;
1955         struct iwl_trans_pcie *trans_pcie =
1956                 IWL_TRANS_GET_PCIE_TRANS(trans);
1957         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
1958         char buf[256];
1959         int pos = 0;
1960         const size_t bufsz = sizeof(buf);
1961
1962         pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1963                                                 rxq->read);
1964         pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1965                                                 rxq->write);
1966         pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1967                                                 rxq->free_count);
1968         if (rxq->rb_stts) {
1969                 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1970                          le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF);
1971         } else {
1972                 pos += scnprintf(buf + pos, bufsz - pos,
1973                                         "closed_rb_num: Not Allocated\n");
1974         }
1975         return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1976 }
1977
1978 static ssize_t iwl_dbgfs_log_event_read(struct file *file,
1979                                          char __user *user_buf,
1980                                          size_t count, loff_t *ppos)
1981 {
1982         struct iwl_trans *trans = file->private_data;
1983         char *buf;
1984         int pos = 0;
1985         ssize_t ret = -ENOMEM;
1986
1987         ret = pos = iwl_dump_nic_event_log(trans, true, &buf, true);
1988         if (buf) {
1989                 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1990                 kfree(buf);
1991         }
1992         return ret;
1993 }
1994
1995 static ssize_t iwl_dbgfs_log_event_write(struct file *file,
1996                                         const char __user *user_buf,
1997                                         size_t count, loff_t *ppos)
1998 {
1999         struct iwl_trans *trans = file->private_data;
2000         u32 event_log_flag;
2001         char buf[8];
2002         int buf_size;
2003
2004         memset(buf, 0, sizeof(buf));
2005         buf_size = min(count, sizeof(buf) -  1);
2006         if (copy_from_user(buf, user_buf, buf_size))
2007                 return -EFAULT;
2008         if (sscanf(buf, "%d", &event_log_flag) != 1)
2009                 return -EFAULT;
2010         if (event_log_flag == 1)
2011                 iwl_dump_nic_event_log(trans, true, NULL, false);
2012
2013         return count;
2014 }
2015
2016 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
2017                                         char __user *user_buf,
2018                                         size_t count, loff_t *ppos) {
2019
2020         struct iwl_trans *trans = file->private_data;
2021         struct iwl_trans_pcie *trans_pcie =
2022                 IWL_TRANS_GET_PCIE_TRANS(trans);
2023         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2024
2025         int pos = 0;
2026         char *buf;
2027         int bufsz = 24 * 64; /* 24 items * 64 char per item */
2028         ssize_t ret;
2029
2030         buf = kzalloc(bufsz, GFP_KERNEL);
2031         if (!buf) {
2032                 IWL_ERR(trans, "Can not allocate Buffer\n");
2033                 return -ENOMEM;
2034         }
2035
2036         pos += scnprintf(buf + pos, bufsz - pos,
2037                         "Interrupt Statistics Report:\n");
2038
2039         pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2040                 isr_stats->hw);
2041         pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2042                 isr_stats->sw);
2043         if (isr_stats->sw || isr_stats->hw) {
2044                 pos += scnprintf(buf + pos, bufsz - pos,
2045                         "\tLast Restarting Code:  0x%X\n",
2046                         isr_stats->err_code);
2047         }
2048 #ifdef CONFIG_IWLWIFI_DEBUG
2049         pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2050                 isr_stats->sch);
2051         pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2052                 isr_stats->alive);
2053 #endif
2054         pos += scnprintf(buf + pos, bufsz - pos,
2055                 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2056
2057         pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2058                 isr_stats->ctkill);
2059
2060         pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2061                 isr_stats->wakeup);
2062
2063         pos += scnprintf(buf + pos, bufsz - pos,
2064                 "Rx command responses:\t\t %u\n", isr_stats->rx);
2065
2066         pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2067                 isr_stats->tx);
2068
2069         pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2070                 isr_stats->unhandled);
2071
2072         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2073         kfree(buf);
2074         return ret;
2075 }
2076
2077 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2078                                          const char __user *user_buf,
2079                                          size_t count, loff_t *ppos)
2080 {
2081         struct iwl_trans *trans = file->private_data;
2082         struct iwl_trans_pcie *trans_pcie =
2083                 IWL_TRANS_GET_PCIE_TRANS(trans);
2084         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2085
2086         char buf[8];
2087         int buf_size;
2088         u32 reset_flag;
2089
2090         memset(buf, 0, sizeof(buf));
2091         buf_size = min(count, sizeof(buf) -  1);
2092         if (copy_from_user(buf, user_buf, buf_size))
2093                 return -EFAULT;
2094         if (sscanf(buf, "%x", &reset_flag) != 1)
2095                 return -EFAULT;
2096         if (reset_flag == 0)
2097                 memset(isr_stats, 0, sizeof(*isr_stats));
2098
2099         return count;
2100 }
2101
2102 static ssize_t iwl_dbgfs_csr_write(struct file *file,
2103                                          const char __user *user_buf,
2104                                          size_t count, loff_t *ppos)
2105 {
2106         struct iwl_trans *trans = file->private_data;
2107         char buf[8];
2108         int buf_size;
2109         int csr;
2110
2111         memset(buf, 0, sizeof(buf));
2112         buf_size = min(count, sizeof(buf) -  1);
2113         if (copy_from_user(buf, user_buf, buf_size))
2114                 return -EFAULT;
2115         if (sscanf(buf, "%d", &csr) != 1)
2116                 return -EFAULT;
2117
2118         iwl_dump_csr(trans);
2119
2120         return count;
2121 }
2122
2123 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
2124                                          char __user *user_buf,
2125                                          size_t count, loff_t *ppos)
2126 {
2127         struct iwl_trans *trans = file->private_data;
2128         char *buf;
2129         int pos = 0;
2130         ssize_t ret = -EFAULT;
2131
2132         ret = pos = iwl_dump_fh(trans, &buf, true);
2133         if (buf) {
2134                 ret = simple_read_from_buffer(user_buf,
2135                                               count, ppos, buf, pos);
2136                 kfree(buf);
2137         }
2138
2139         return ret;
2140 }
2141
2142 DEBUGFS_READ_WRITE_FILE_OPS(log_event);
2143 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
2144 DEBUGFS_READ_FILE_OPS(fh_reg);
2145 DEBUGFS_READ_FILE_OPS(rx_queue);
2146 DEBUGFS_READ_FILE_OPS(tx_queue);
2147 DEBUGFS_WRITE_FILE_OPS(csr);
2148
2149 /*
2150  * Create the debugfs files and directories
2151  *
2152  */
2153 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2154                                         struct dentry *dir)
2155 {
2156         DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2157         DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
2158         DEBUGFS_ADD_FILE(log_event, dir, S_IWUSR | S_IRUSR);
2159         DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
2160         DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2161         DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
2162         return 0;
2163 }
2164 #else
2165 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2166                                         struct dentry *dir)
2167 { return 0; }
2168
2169 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2170
2171 const struct iwl_trans_ops trans_ops_pcie = {
2172         .start_hw = iwl_trans_pcie_start_hw,
2173         .stop_hw = iwl_trans_pcie_stop_hw,
2174         .fw_alive = iwl_trans_pcie_fw_alive,
2175         .start_fw = iwl_trans_pcie_start_fw,
2176         .stop_device = iwl_trans_pcie_stop_device,
2177
2178         .wowlan_suspend = iwl_trans_pcie_wowlan_suspend,
2179
2180         .send_cmd = iwl_trans_pcie_send_cmd,
2181
2182         .tx = iwl_trans_pcie_tx,
2183         .reclaim = iwl_trans_pcie_reclaim,
2184
2185         .tx_agg_disable = iwl_trans_pcie_tx_agg_disable,
2186         .tx_agg_alloc = iwl_trans_pcie_tx_agg_alloc,
2187         .tx_agg_setup = iwl_trans_pcie_tx_agg_setup,
2188
2189         .free = iwl_trans_pcie_free,
2190
2191         .dbgfs_register = iwl_trans_pcie_dbgfs_register,
2192
2193         .wait_tx_queue_empty = iwl_trans_pcie_wait_tx_queue_empty,
2194         .check_stuck_queue = iwl_trans_pcie_check_stuck_queue,
2195
2196 #ifdef CONFIG_PM_SLEEP
2197         .suspend = iwl_trans_pcie_suspend,
2198         .resume = iwl_trans_pcie_resume,
2199 #endif
2200         .write8 = iwl_trans_pcie_write8,
2201         .write32 = iwl_trans_pcie_write32,
2202         .read32 = iwl_trans_pcie_read32,
2203 };
2204
2205 struct iwl_trans *iwl_trans_pcie_alloc(struct iwl_shared *shrd,
2206                                        struct pci_dev *pdev,
2207                                        const struct pci_device_id *ent)
2208 {
2209         struct iwl_trans_pcie *trans_pcie;
2210         struct iwl_trans *trans;
2211         u16 pci_cmd;
2212         int err;
2213
2214         trans = kzalloc(sizeof(struct iwl_trans) +
2215                              sizeof(struct iwl_trans_pcie), GFP_KERNEL);
2216
2217         if (WARN_ON(!trans))
2218                 return NULL;
2219
2220         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2221
2222         trans->ops = &trans_ops_pcie;
2223         trans->shrd = shrd;
2224         trans_pcie->trans = trans;
2225         spin_lock_init(&trans_pcie->irq_lock);
2226         init_waitqueue_head(&trans_pcie->ucode_write_waitq);
2227
2228         /* W/A - seems to solve weird behavior. We need to remove this if we
2229          * don't want to stay in L1 all the time. This wastes a lot of power */
2230         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
2231                                 PCIE_LINK_STATE_CLKPM);
2232
2233         if (pci_enable_device(pdev)) {
2234                 err = -ENODEV;
2235                 goto out_no_pci;
2236         }
2237
2238         pci_set_master(pdev);
2239
2240         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2241         if (!err)
2242                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2243         if (err) {
2244                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2245                 if (!err)
2246                         err = pci_set_consistent_dma_mask(pdev,
2247                                                         DMA_BIT_MASK(32));
2248                 /* both attempts failed: */
2249                 if (err) {
2250                         dev_printk(KERN_ERR, &pdev->dev,
2251                                    "No suitable DMA available.\n");
2252                         goto out_pci_disable_device;
2253                 }
2254         }
2255
2256         err = pci_request_regions(pdev, DRV_NAME);
2257         if (err) {
2258                 dev_printk(KERN_ERR, &pdev->dev, "pci_request_regions failed");
2259                 goto out_pci_disable_device;
2260         }
2261
2262         trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
2263         if (!trans_pcie->hw_base) {
2264                 dev_printk(KERN_ERR, &pdev->dev, "pci_ioremap_bar failed");
2265                 err = -ENODEV;
2266                 goto out_pci_release_regions;
2267         }
2268
2269         dev_printk(KERN_INFO, &pdev->dev,
2270                 "pci_resource_len = 0x%08llx\n",
2271                 (unsigned long long) pci_resource_len(pdev, 0));
2272         dev_printk(KERN_INFO, &pdev->dev,
2273                 "pci_resource_base = %p\n", trans_pcie->hw_base);
2274
2275         dev_printk(KERN_INFO, &pdev->dev,
2276                 "HW Revision ID = 0x%X\n", pdev->revision);
2277
2278         /* We disable the RETRY_TIMEOUT register (0x41) to keep
2279          * PCI Tx retries from interfering with C3 CPU state */
2280         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2281
2282         err = pci_enable_msi(pdev);
2283         if (err)
2284                 dev_printk(KERN_ERR, &pdev->dev,
2285                         "pci_enable_msi failed(0X%x)", err);
2286
2287         trans->dev = &pdev->dev;
2288         trans_pcie->irq = pdev->irq;
2289         trans_pcie->pci_dev = pdev;
2290         trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
2291         trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
2292         snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2293                  "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
2294
2295         /* TODO: Move this away, not needed if not MSI */
2296         /* enable rfkill interrupt: hw bug w/a */
2297         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2298         if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2299                 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2300                 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2301         }
2302
2303         return trans;
2304
2305 out_pci_release_regions:
2306         pci_release_regions(pdev);
2307 out_pci_disable_device:
2308         pci_disable_device(pdev);
2309 out_no_pci:
2310         kfree(trans);
2311         return NULL;
2312 }
2313