drivers/net/wireless/iwlwifi/iwl-trans-pcie.c

   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of version 2 of the GNU General Public License as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
  15  * WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * General Public License for more details.
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  20  * along with this program; if not, write to the Free Software
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  22  * USA
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  25  * in the file called LICENSE.GPL.
  26  *
  27  * Contact Information:
  28  *  Intel Linux Wireless <ilw@linux.intel.com>
  29  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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  32  *
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  37  * modification, are permitted provided that the following conditions
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  41  *    notice, this list of conditions and the following disclaimer.
  42  *  * Redistributions in binary form must reproduce the above copyright
  43  *    notice, this list of conditions and the following disclaimer in
  44  *    the documentation and/or other materials provided with the
  45  *    distribution.
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  47  *    contributors may be used to endorse or promote products derived
  48  *    from this software without specific prior written permission.
  49  *
  50  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  51  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  52  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  53  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  54  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  55  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  56  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  57  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  58  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  59  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  60  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  61  *
  62  *****************************************************************************/
  63 #include <linux/pci.h>
  64 #include <linux/pci-aspm.h>
  65 #include <linux/interrupt.h>
  66 #include <linux/debugfs.h>
  67 #include <linux/sched.h>
  68 #include <linux/bitops.h>
  69 #include <linux/gfp.h>
  70
  71 #include "iwl-trans.h"
  72 #include "iwl-trans-pcie-int.h"
  73 #include "iwl-csr.h"
  74 #include "iwl-prph.h"
  75 #include "iwl-shared.h"
  76 #include "iwl-eeprom.h"
  77 #include "iwl-agn-hw.h"
  78
  79 #define IWL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo))))
  80
  81 static int iwl_trans_rx_alloc(struct iwl_trans *trans)
  82 {
  83         struct iwl_trans_pcie *trans_pcie =
  84                 IWL_TRANS_GET_PCIE_TRANS(trans);
  85         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
  86         struct device *dev = trans->dev;
  87
  88         memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq));
  89
  90         spin_lock_init(&rxq->lock);
  91
  92         if (WARN_ON(rxq->bd || rxq->rb_stts))
  93                 return -EINVAL;
  94
  95         /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
  96         rxq->bd = dma_zalloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
  97                                       &rxq->bd_dma, GFP_KERNEL);
  98         if (!rxq->bd)
  99                 goto err_bd;
 100
 101         /*Allocate the driver's pointer to receive buffer status */
 102         rxq->rb_stts = dma_zalloc_coherent(dev, sizeof(*rxq->rb_stts),
 103                                            &rxq->rb_stts_dma, GFP_KERNEL);
 104         if (!rxq->rb_stts)
 105                 goto err_rb_stts;
 106
 107         return 0;
 108
 109 err_rb_stts:
 110         dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
 111                         rxq->bd, rxq->bd_dma);
 112         memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
 113         rxq->bd = NULL;
 114 err_bd:
 115         return -ENOMEM;
 116 }
 117
 118 static void iwl_trans_rxq_free_rx_bufs(struct iwl_trans *trans)
 119 {
 120         struct iwl_trans_pcie *trans_pcie =
 121                 IWL_TRANS_GET_PCIE_TRANS(trans);
 122         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 123         int i;
 124
 125         /* Fill the rx_used queue with _all_ of the Rx buffers */
 126         for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
 127                 /* In the reset function, these buffers may have been allocated
 128                  * to an SKB, so we need to unmap and free potential storage */
 129                 if (rxq->pool[i].page != NULL) {
 130                         dma_unmap_page(trans->dev, rxq->pool[i].page_dma,
 131                                 PAGE_SIZE << hw_params(trans).rx_page_order,
 132                                 DMA_FROM_DEVICE);
 133                         __free_pages(rxq->pool[i].page,
 134                                      hw_params(trans).rx_page_order);
 135                         rxq->pool[i].page = NULL;
 136                 }
 137                 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
 138         }
 139 }
 140
 141 static void iwl_trans_rx_hw_init(struct iwl_trans *trans,
 142                                  struct iwl_rx_queue *rxq)
 143 {
 144         u32 rb_size;
 145         const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
 146         u32 rb_timeout = RX_RB_TIMEOUT; /* FIXME: RX_RB_TIMEOUT for all devices? */
 147
 148         if (iwlagn_mod_params.amsdu_size_8K)
 149                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
 150         else
 151                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
 152
 153         /* Stop Rx DMA */
 154         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 155
 156         /* Reset driver's Rx queue write index */
 157         iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
 158
 159         /* Tell device where to find RBD circular buffer in DRAM */
 160         iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
 161                            (u32)(rxq->bd_dma >> 8));
 162
 163         /* Tell device where in DRAM to update its Rx status */
 164         iwl_write_direct32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,
 165                            rxq->rb_stts_dma >> 4);
 166
 167         /* Enable Rx DMA
 168          * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
 169          *      the credit mechanism in 5000 HW RX FIFO
 170          * Direct rx interrupts to hosts
 171          * Rx buffer size 4 or 8k
 172          * RB timeout 0x10
 173          * 256 RBDs
 174          */
 175         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,
 176                            FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
 177                            FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
 178                            FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
 179                            FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
 180                            rb_size|
 181                            (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
 182                            (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
 183
 184         /* Set interrupt coalescing timer to default (2048 usecs) */
 185         iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
 186 }
 187
 188 static int iwl_rx_init(struct iwl_trans *trans)
 189 {
 190         struct iwl_trans_pcie *trans_pcie =
 191                 IWL_TRANS_GET_PCIE_TRANS(trans);
 192         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 193
 194         int i, err;
 195         unsigned long flags;
 196
 197         if (!rxq->bd) {
 198                 err = iwl_trans_rx_alloc(trans);
 199                 if (err)
 200                         return err;
 201         }
 202
 203         spin_lock_irqsave(&rxq->lock, flags);
 204         INIT_LIST_HEAD(&rxq->rx_free);
 205         INIT_LIST_HEAD(&rxq->rx_used);
 206
 207         iwl_trans_rxq_free_rx_bufs(trans);
 208
 209         for (i = 0; i < RX_QUEUE_SIZE; i++)
 210                 rxq->queue[i] = NULL;
 211
 212         /* Set us so that we have processed and used all buffers, but have
 213          * not restocked the Rx queue with fresh buffers */
 214         rxq->read = rxq->write = 0;
 215         rxq->write_actual = 0;
 216         rxq->free_count = 0;
 217         spin_unlock_irqrestore(&rxq->lock, flags);
 218
 219         iwlagn_rx_replenish(trans);
 220
 221         iwl_trans_rx_hw_init(trans, rxq);
 222
 223         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 224         rxq->need_update = 1;
 225         iwl_rx_queue_update_write_ptr(trans, rxq);
 226         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 227
 228         return 0;
 229 }
 230
 231 static void iwl_trans_pcie_rx_free(struct iwl_trans *trans)
 232 {
 233         struct iwl_trans_pcie *trans_pcie =
 234                 IWL_TRANS_GET_PCIE_TRANS(trans);
 235         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 236
 237         unsigned long flags;
 238
 239         /*if rxq->bd is NULL, it means that nothing has been allocated,
 240          * exit now */
 241         if (!rxq->bd) {
 242                 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
 243                 return;
 244         }
 245
 246         spin_lock_irqsave(&rxq->lock, flags);
 247         iwl_trans_rxq_free_rx_bufs(trans);
 248         spin_unlock_irqrestore(&rxq->lock, flags);
 249
 250         dma_free_coherent(trans->dev, sizeof(__le32) * RX_QUEUE_SIZE,
 251                           rxq->bd, rxq->bd_dma);
 252         memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
 253         rxq->bd = NULL;
 254
 255         if (rxq->rb_stts)
 256                 dma_free_coherent(trans->dev,
 257                                   sizeof(struct iwl_rb_status),
 258                                   rxq->rb_stts, rxq->rb_stts_dma);
 259         else
 260                 IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n");
 261         memset(&rxq->rb_stts_dma, 0, sizeof(rxq->rb_stts_dma));
 262         rxq->rb_stts = NULL;
 263 }
 264
 265 static int iwl_trans_rx_stop(struct iwl_trans *trans)
 266 {
 267
 268         /* stop Rx DMA */
 269         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 270         return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG,
 271                             FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
 272 }
 273
 274 static inline int iwlagn_alloc_dma_ptr(struct iwl_trans *trans,
 275                                     struct iwl_dma_ptr *ptr, size_t size)
 276 {
 277         if (WARN_ON(ptr->addr))
 278                 return -EINVAL;
 279
 280         ptr->addr = dma_alloc_coherent(trans->dev, size,
 281                                        &ptr->dma, GFP_KERNEL);
 282         if (!ptr->addr)
 283                 return -ENOMEM;
 284         ptr->size = size;
 285         return 0;
 286 }
 287
 288 static inline void iwlagn_free_dma_ptr(struct iwl_trans *trans,
 289                                     struct iwl_dma_ptr *ptr)
 290 {
 291         if (unlikely(!ptr->addr))
 292                 return;
 293
 294         dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
 295         memset(ptr, 0, sizeof(*ptr));
 296 }
 297
 298 static int iwl_trans_txq_alloc(struct iwl_trans *trans,
 299                                 struct iwl_tx_queue *txq, int slots_num,
 300                                 u32 txq_id)
 301 {
 302         size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
 303         int i;
 304
 305         if (WARN_ON(txq->meta || txq->cmd || txq->skbs || txq->tfds))
 306                 return -EINVAL;
 307
 308         txq->q.n_window = slots_num;
 309
 310         txq->meta = kcalloc(slots_num, sizeof(txq->meta[0]), GFP_KERNEL);
 311         txq->cmd = kcalloc(slots_num, sizeof(txq->cmd[0]), GFP_KERNEL);
 312
 313         if (!txq->meta || !txq->cmd)
 314                 goto error;
 315
 316         if (txq_id == trans->shrd->cmd_queue)
 317                 for (i = 0; i < slots_num; i++) {
 318                         txq->cmd[i] = kmalloc(sizeof(struct iwl_device_cmd),
 319                                                 GFP_KERNEL);
 320                         if (!txq->cmd[i])
 321                                 goto error;
 322                 }
 323
 324         /* Alloc driver data array and TFD circular buffer */
 325         /* Driver private data, only for Tx (not command) queues,
 326          * not shared with device. */
 327         if (txq_id != trans->shrd->cmd_queue) {
 328                 txq->skbs = kcalloc(TFD_QUEUE_SIZE_MAX, sizeof(txq->skbs[0]),
 329                                     GFP_KERNEL);
 330                 if (!txq->skbs) {
 331                         IWL_ERR(trans, "kmalloc for auxiliary BD "
 332                                   "structures failed\n");
 333                         goto error;
 334                 }
 335         } else {
 336                 txq->skbs = NULL;
 337         }
 338
 339         /* Circular buffer of transmit frame descriptors (TFDs),
 340          * shared with device */
 341         txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
 342                                        &txq->q.dma_addr, GFP_KERNEL);
 343         if (!txq->tfds) {
 344                 IWL_ERR(trans, "dma_alloc_coherent(%zd) failed\n", tfd_sz);
 345                 goto error;
 346         }
 347         txq->q.id = txq_id;
 348
 349         return 0;
 350 error:
 351         kfree(txq->skbs);
 352         txq->skbs = NULL;
 353         /* since txq->cmd has been zeroed,
 354          * all non allocated cmd[i] will be NULL */
 355         if (txq->cmd && txq_id == trans->shrd->cmd_queue)
 356                 for (i = 0; i < slots_num; i++)
 357                         kfree(txq->cmd[i]);
 358         kfree(txq->meta);
 359         kfree(txq->cmd);
 360         txq->meta = NULL;
 361         txq->cmd = NULL;
 362
 363         return -ENOMEM;
 364
 365 }
 366
 367 static int iwl_trans_txq_init(struct iwl_trans *trans, struct iwl_tx_queue *txq,
 368                       int slots_num, u32 txq_id)
 369 {
 370         int ret;
 371
 372         txq->need_update = 0;
 373         memset(txq->meta, 0, sizeof(txq->meta[0]) * slots_num);
 374
 375         /*
 376          * For the default queues 0-3, set up the swq_id
 377          * already -- all others need to get one later
 378          * (if they need one at all).
 379          */
 380         if (txq_id < 4)
 381                 iwl_set_swq_id(txq, txq_id, txq_id);
 382
 383         /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
 384          * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
 385         BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
 386
 387         /* Initialize queue's high/low-water marks, and head/tail indexes */
 388         ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num,
 389                         txq_id);
 390         if (ret)
 391                 return ret;
 392
 393         spin_lock_init(&txq->lock);
 394
 395         /*
 396          * Tell nic where to find circular buffer of Tx Frame Descriptors for
 397          * given Tx queue, and enable the DMA channel used for that queue.
 398          * Circular buffer (TFD queue in DRAM) physical base address */
 399         iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
 400                              txq->q.dma_addr >> 8);
 401
 402         return 0;
 403 }
 404
 405 /**
 406  * iwl_tx_queue_unmap -  Unmap any remaining DMA mappings and free skb's
 407  */
 408 static void iwl_tx_queue_unmap(struct iwl_trans *trans, int txq_id)
 409 {
 410         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 411         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
 412         struct iwl_queue *q = &txq->q;
 413         enum dma_data_direction dma_dir;
 414
 415         if (!q->n_bd)
 416                 return;
 417
 418         /* In the command queue, all the TBs are mapped as BIDI
 419          * so unmap them as such.
 420          */
 421         if (txq_id == trans->shrd->cmd_queue)
 422                 dma_dir = DMA_BIDIRECTIONAL;
 423         else
 424                 dma_dir = DMA_TO_DEVICE;
 425
 426         spin_lock_bh(&txq->lock);
 427         while (q->write_ptr != q->read_ptr) {
 428                 /* The read_ptr needs to bound by q->n_window */
 429                 iwlagn_txq_free_tfd(trans, txq, get_cmd_index(q, q->read_ptr),
 430                                     dma_dir);
 431                 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
 432         }
 433         spin_unlock_bh(&txq->lock);
 434 }
 435
 436 /**
 437  * iwl_tx_queue_free - Deallocate DMA queue.
 438  * @txq: Transmit queue to deallocate.
 439  *
 440  * Empty queue by removing and destroying all BD's.
 441  * Free all buffers.
 442  * 0-fill, but do not free "txq" descriptor structure.
 443  */
 444 static void iwl_tx_queue_free(struct iwl_trans *trans, int txq_id)
 445 {
 446         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 447         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
 448         struct device *dev = trans->dev;
 449         int i;
 450         if (WARN_ON(!txq))
 451                 return;
 452
 453         iwl_tx_queue_unmap(trans, txq_id);
 454
 455         /* De-alloc array of command/tx buffers */
 456
 457         if (txq_id == trans->shrd->cmd_queue)
 458                 for (i = 0; i < txq->q.n_window; i++)
 459                         kfree(txq->cmd[i]);
 460
 461         /* De-alloc circular buffer of TFDs */
 462         if (txq->q.n_bd) {
 463                 dma_free_coherent(dev, sizeof(struct iwl_tfd) *
 464                                   txq->q.n_bd, txq->tfds, txq->q.dma_addr);
 465                 memset(&txq->q.dma_addr, 0, sizeof(txq->q.dma_addr));
 466         }
 467
 468         /* De-alloc array of per-TFD driver data */
 469         kfree(txq->skbs);
 470         txq->skbs = NULL;
 471
 472         /* deallocate arrays */
 473         kfree(txq->cmd);
 474         kfree(txq->meta);
 475         txq->cmd = NULL;
 476         txq->meta = NULL;
 477
 478         /* 0-fill queue descriptor structure */
 479         memset(txq, 0, sizeof(*txq));
 480 }
 481
 482 /**
 483  * iwl_trans_tx_free - Free TXQ Context
 484  *
 485  * Destroy all TX DMA queues and structures
 486  */
 487 static void iwl_trans_pcie_tx_free(struct iwl_trans *trans)
 488 {
 489         int txq_id;
 490         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 491
 492         /* Tx queues */
 493         if (trans_pcie->txq) {
 494                 for (txq_id = 0;
 495                      txq_id < hw_params(trans).max_txq_num; txq_id++)
 496                         iwl_tx_queue_free(trans, txq_id);
 497         }
 498
 499         kfree(trans_pcie->txq);
 500         trans_pcie->txq = NULL;
 501
 502         iwlagn_free_dma_ptr(trans, &trans_pcie->kw);
 503
 504         iwlagn_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
 505 }
 506
 507 /**
 508  * iwl_trans_tx_alloc - allocate TX context
 509  * Allocate all Tx DMA structures and initialize them
 510  *
 511  * @param priv
 512  * @return error code
 513  */
 514 static int iwl_trans_tx_alloc(struct iwl_trans *trans)
 515 {
 516         int ret;
 517         int txq_id, slots_num;
 518         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 519
 520         u16 scd_bc_tbls_size = hw_params(trans).max_txq_num *
 521                         sizeof(struct iwlagn_scd_bc_tbl);
 522
 523         /*It is not allowed to alloc twice, so warn when this happens.
 524          * We cannot rely on the previous allocation, so free and fail */
 525         if (WARN_ON(trans_pcie->txq)) {
 526                 ret = -EINVAL;
 527                 goto error;
 528         }
 529
 530         ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
 531                                    scd_bc_tbls_size);
 532         if (ret) {
 533                 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
 534                 goto error;
 535         }
 536
 537         /* Alloc keep-warm buffer */
 538         ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
 539         if (ret) {
 540                 IWL_ERR(trans, "Keep Warm allocation failed\n");
 541                 goto error;
 542         }
 543
 544         trans_pcie->txq = kcalloc(hw_params(trans).max_txq_num,
 545                                   sizeof(struct iwl_tx_queue), GFP_KERNEL);
 546         if (!trans_pcie->txq) {
 547                 IWL_ERR(trans, "Not enough memory for txq\n");
 548                 ret = ENOMEM;
 549                 goto error;
 550         }
 551
 552         /* Alloc and init all Tx queues, including the command queue (#4/#9) */
 553         for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) {
 554                 slots_num = (txq_id == trans->shrd->cmd_queue) ?
 555                                         TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
 556                 ret = iwl_trans_txq_alloc(trans, &trans_pcie->txq[txq_id],
 557                                           slots_num, txq_id);
 558                 if (ret) {
 559                         IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
 560                         goto error;
 561                 }
 562         }
 563
 564         return 0;
 565
 566 error:
 567         iwl_trans_pcie_tx_free(trans);
 568
 569         return ret;
 570 }
 571 static int iwl_tx_init(struct iwl_trans *trans)
 572 {
 573         int ret;
 574         int txq_id, slots_num;
 575         unsigned long flags;
 576         bool alloc = false;
 577         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 578
 579         if (!trans_pcie->txq) {
 580                 ret = iwl_trans_tx_alloc(trans);
 581                 if (ret)
 582                         goto error;
 583                 alloc = true;
 584         }
 585
 586         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 587
 588         /* Turn off all Tx DMA fifos */
 589         iwl_write_prph(trans, SCD_TXFACT, 0);
 590
 591         /* Tell NIC where to find the "keep warm" buffer */
 592         iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
 593                            trans_pcie->kw.dma >> 4);
 594
 595         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 596
 597         /* Alloc and init all Tx queues, including the command queue (#4/#9) */
 598         for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) {
 599                 slots_num = (txq_id == trans->shrd->cmd_queue) ?
 600                                         TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
 601                 ret = iwl_trans_txq_init(trans, &trans_pcie->txq[txq_id],
 602                                          slots_num, txq_id);
 603                 if (ret) {
 604                         IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
 605                         goto error;
 606                 }
 607         }
 608
 609         return 0;
 610 error:
 611         /*Upon error, free only if we allocated something */
 612         if (alloc)
 613                 iwl_trans_pcie_tx_free(trans);
 614         return ret;
 615 }
 616
 617 static void iwl_set_pwr_vmain(struct iwl_trans *trans)
 618 {
 619 /*
 620  * (for documentation purposes)
 621  * to set power to V_AUX, do:
 622
 623                 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
 624                         iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 625                                                APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 626                                                ~APMG_PS_CTRL_MSK_PWR_SRC);
 627  */
 628
 629         iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 630                                APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 631                                ~APMG_PS_CTRL_MSK_PWR_SRC);
 632 }
 633
 634 /* PCI registers */
 635 #define PCI_CFG_RETRY_TIMEOUT   0x041
 636 #define PCI_CFG_LINK_CTRL_VAL_L0S_EN    0x01
 637 #define PCI_CFG_LINK_CTRL_VAL_L1_EN     0x02
 638
 639 static u16 iwl_pciexp_link_ctrl(struct iwl_trans *trans)
 640 {
 641         int pos;
 642         u16 pci_lnk_ctl;
 643         struct iwl_trans_pcie *trans_pcie =
 644                 IWL_TRANS_GET_PCIE_TRANS(trans);
 645
 646         struct pci_dev *pci_dev = trans_pcie->pci_dev;
 647
 648         pos = pci_pcie_cap(pci_dev);
 649         pci_read_config_word(pci_dev, pos + PCI_EXP_LNKCTL, &pci_lnk_ctl);
 650         return pci_lnk_ctl;
 651 }
 652
 653 static void iwl_apm_config(struct iwl_trans *trans)
 654 {
 655         /*
 656          * HW bug W/A for instability in PCIe bus L0S->L1 transition.
 657          * Check if BIOS (or OS) enabled L1-ASPM on this device.
 658          * If so (likely), disable L0S, so device moves directly L0->L1;
 659          *    costs negligible amount of power savings.
 660          * If not (unlikely), enable L0S, so there is at least some
 661          *    power savings, even without L1.
 662          */
 663         u16 lctl = iwl_pciexp_link_ctrl(trans);
 664
 665         if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
 666                                 PCI_CFG_LINK_CTRL_VAL_L1_EN) {
 667                 /* L1-ASPM enabled; disable(!) L0S */
 668                 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 669                 dev_printk(KERN_INFO, trans->dev,
 670                            "L1 Enabled; Disabling L0S\n");
 671         } else {
 672                 /* L1-ASPM disabled; enable(!) L0S */
 673                 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 674                 dev_printk(KERN_INFO, trans->dev,
 675                            "L1 Disabled; Enabling L0S\n");
 676         }
 677         trans->pm_support = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN);
 678 }
 679
 680 /*
 681  * Start up NIC's basic functionality after it has been reset
 682  * (e.g. after platform boot, or shutdown via iwl_apm_stop())
 683  * NOTE:  This does not load uCode nor start the embedded processor
 684  */
 685 static int iwl_apm_init(struct iwl_trans *trans)
 686 {
 687         int ret = 0;
 688         IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
 689
 690         /*
 691          * Use "set_bit" below rather than "write", to preserve any hardware
 692          * bits already set by default after reset.
 693          */
 694
 695         /* Disable L0S exit timer (platform NMI Work/Around) */
 696         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 697                           CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 698
 699         /*
 700          * Disable L0s without affecting L1;
 701          *  don't wait for ICH L0s (ICH bug W/A)
 702          */
 703         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 704                           CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 705
 706         /* Set FH wait threshold to maximum (HW error during stress W/A) */
 707         iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 708
 709         /*
 710          * Enable HAP INTA (interrupt from management bus) to
 711          * wake device's PCI Express link L1a -> L0s
 712          */
 713         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 714                                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 715
 716         iwl_apm_config(trans);
 717
 718         /* Configure analog phase-lock-loop before activating to D0A */
 719         if (cfg(trans)->base_params->pll_cfg_val)
 720                 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
 721                             cfg(trans)->base_params->pll_cfg_val);
 722
 723         /*
 724          * Set "initialization complete" bit to move adapter from
 725          * D0U* --> D0A* (powered-up active) state.
 726          */
 727         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 728
 729         /*
 730          * Wait for clock stabilization; once stabilized, access to
 731          * device-internal resources is supported, e.g. iwl_write_prph()
 732          * and accesses to uCode SRAM.
 733          */
 734         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 735                         CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 736                         CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 737         if (ret < 0) {
 738                 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
 739                 goto out;
 740         }
 741
 742         /*
 743          * Enable DMA clock and wait for it to stabilize.
 744          *
 745          * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
 746          * do not disable clocks.  This preserves any hardware bits already
 747          * set by default in "CLK_CTRL_REG" after reset.
 748          */
 749         iwl_write_prph(trans, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
 750         udelay(20);
 751
 752         /* Disable L1-Active */
 753         iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 754                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 755
 756         set_bit(STATUS_DEVICE_ENABLED, &trans->shrd->status);
 757
 758 out:
 759         return ret;
 760 }
 761
 762 static int iwl_apm_stop_master(struct iwl_trans *trans)
 763 {
 764         int ret = 0;
 765
 766         /* stop device's busmaster DMA activity */
 767         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
 768
 769         ret = iwl_poll_bit(trans, CSR_RESET,
 770                         CSR_RESET_REG_FLAG_MASTER_DISABLED,
 771                         CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
 772         if (ret)
 773                 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
 774
 775         IWL_DEBUG_INFO(trans, "stop master\n");
 776
 777         return ret;
 778 }
 779
 780 static void iwl_apm_stop(struct iwl_trans *trans)
 781 {
 782         IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
 783
 784         clear_bit(STATUS_DEVICE_ENABLED, &trans->shrd->status);
 785
 786         /* Stop device's DMA activity */
 787         iwl_apm_stop_master(trans);
 788
 789         /* Reset the entire device */
 790         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 791
 792         udelay(10);
 793
 794         /*
 795          * Clear "initialization complete" bit to move adapter from
 796          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 797          */
 798         iwl_clear_bit(trans, CSR_GP_CNTRL,
 799                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 800 }
 801
 802 static int iwl_nic_init(struct iwl_trans *trans)
 803 {
 804         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 805         unsigned long flags;
 806
 807         /* nic_init */
 808         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 809         iwl_apm_init(trans);
 810
 811         /* Set interrupt coalescing calibration timer to default (512 usecs) */
 812         iwl_write8(trans, CSR_INT_COALESCING,
 813                 IWL_HOST_INT_CALIB_TIMEOUT_DEF);
 814
 815         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 816
 817         iwl_set_pwr_vmain(trans);
 818
 819         iwl_op_mode_nic_config(trans->op_mode);
 820
 821 #ifndef CONFIG_IWLWIFI_IDI
 822         /* Allocate the RX queue, or reset if it is already allocated */
 823         iwl_rx_init(trans);
 824 #endif
 825
 826         /* Allocate or reset and init all Tx and Command queues */
 827         if (iwl_tx_init(trans))
 828                 return -ENOMEM;
 829
 830         if (cfg(trans)->base_params->shadow_reg_enable) {
 831                 /* enable shadow regs in HW */
 832                 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL,
 833                         0x800FFFFF);
 834         }
 835
 836         set_bit(STATUS_INIT, &trans->shrd->status);
 837
 838         return 0;
 839 }
 840
 841 #define HW_READY_TIMEOUT (50)
 842
 843 /* Note: returns poll_bit return value, which is >= 0 if success */
 844 static int iwl_set_hw_ready(struct iwl_trans *trans)
 845 {
 846         int ret;
 847
 848         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 849                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
 850
 851         /* See if we got it */
 852         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 853                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 854                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 855                                 HW_READY_TIMEOUT);
 856
 857         IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
 858         return ret;
 859 }
 860
 861 /* Note: returns standard 0/-ERROR code */
 862 static int iwl_prepare_card_hw(struct iwl_trans *trans)
 863 {
 864         int ret;
 865
 866         IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
 867
 868         ret = iwl_set_hw_ready(trans);
 869         /* If the card is ready, exit 0 */
 870         if (ret >= 0)
 871                 return 0;
 872
 873         /* If HW is not ready, prepare the conditions to check again */
 874         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 875                         CSR_HW_IF_CONFIG_REG_PREPARE);
 876
 877         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 878                         ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
 879                         CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
 880
 881         if (ret < 0)
 882                 return ret;
 883
 884         /* HW should be ready by now, check again. */
 885         ret = iwl_set_hw_ready(trans);
 886         if (ret >= 0)
 887                 return 0;
 888         return ret;
 889 }
 890
 891 #define IWL_AC_UNSET -1
 892
 893 struct queue_to_fifo_ac {
 894         s8 fifo, ac;
 895 };
 896
 897 static const struct queue_to_fifo_ac iwlagn_default_queue_to_tx_fifo[] = {
 898         { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
 899         { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
 900         { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
 901         { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
 902         { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
 903         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 904         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 905         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 906         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 907         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 908         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 909 };
 910
 911 static const struct queue_to_fifo_ac iwlagn_ipan_queue_to_tx_fifo[] = {
 912         { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
 913         { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
 914         { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
 915         { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
 916         { IWL_TX_FIFO_BK_IPAN, IEEE80211_AC_BK, },
 917         { IWL_TX_FIFO_BE_IPAN, IEEE80211_AC_BE, },
 918         { IWL_TX_FIFO_VI_IPAN, IEEE80211_AC_VI, },
 919         { IWL_TX_FIFO_VO_IPAN, IEEE80211_AC_VO, },
 920         { IWL_TX_FIFO_BE_IPAN, 2, },
 921         { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
 922         { IWL_TX_FIFO_AUX, IWL_AC_UNSET, },
 923 };
 924
 925 static const u8 iwlagn_bss_ac_to_fifo[] = {
 926         IWL_TX_FIFO_VO,
 927         IWL_TX_FIFO_VI,
 928         IWL_TX_FIFO_BE,
 929         IWL_TX_FIFO_BK,
 930 };
 931 static const u8 iwlagn_bss_ac_to_queue[] = {
 932         0, 1, 2, 3,
 933 };
 934 static const u8 iwlagn_pan_ac_to_fifo[] = {
 935         IWL_TX_FIFO_VO_IPAN,
 936         IWL_TX_FIFO_VI_IPAN,
 937         IWL_TX_FIFO_BE_IPAN,
 938         IWL_TX_FIFO_BK_IPAN,
 939 };
 940 static const u8 iwlagn_pan_ac_to_queue[] = {
 941         7, 6, 5, 4,
 942 };
 943
 944 /*
 945  * ucode
 946  */
 947 static int iwl_load_section(struct iwl_trans *trans, const char *name,
 948                             const struct fw_desc *image, u32 dst_addr)
 949 {
 950         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 951         dma_addr_t phy_addr = image->p_addr;
 952         u32 byte_cnt = image->len;
 953         int ret;
 954
 955         trans_pcie->ucode_write_complete = false;
 956
 957         iwl_write_direct32(trans,
 958                 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 959                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 960
 961         iwl_write_direct32(trans,
 962                 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
 963
 964         iwl_write_direct32(trans,
 965                 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 966                 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 967
 968         iwl_write_direct32(trans,
 969                 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 970                 (iwl_get_dma_hi_addr(phy_addr)
 971                         << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 972
 973         iwl_write_direct32(trans,
 974                 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 975                 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
 976                 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
 977                 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 978
 979         iwl_write_direct32(trans,
 980                 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 981                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE       |
 982                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE    |
 983                 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 984
 985         IWL_DEBUG_FW(trans, "%s uCode section being loaded...\n", name);
 986         ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
 987                                  trans_pcie->ucode_write_complete, 5 * HZ);
 988         if (!ret) {
 989                 IWL_ERR(trans, "Could not load the %s uCode section\n",
 990                         name);
 991                 return -ETIMEDOUT;
 992         }
 993
 994         return 0;
 995 }
 996
 997 static int iwl_load_given_ucode(struct iwl_trans *trans,
 998                                 const struct fw_img *image)
 999 {
1000         int ret = 0;
1001
1002         ret = iwl_load_section(trans, "INST", &image->code,
1003                                    IWLAGN_RTC_INST_LOWER_BOUND);
1004         if (ret)
1005                 return ret;
1006
1007         ret = iwl_load_section(trans, "DATA", &image->data,
1008                                     IWLAGN_RTC_DATA_LOWER_BOUND);
1009         if (ret)
1010                 return ret;
1011
1012         /* Remove all resets to allow NIC to operate */
1013         iwl_write32(trans, CSR_RESET, 0);
1014
1015         return 0;
1016 }
1017
1018 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1019                                    const struct fw_img *fw)
1020 {
1021         int ret;
1022         struct iwl_trans_pcie *trans_pcie =
1023                 IWL_TRANS_GET_PCIE_TRANS(trans);
1024         bool hw_rfkill;
1025
1026         trans_pcie->ac_to_queue[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_queue;
1027         trans_pcie->ac_to_queue[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_queue;
1028
1029         trans_pcie->ac_to_fifo[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_fifo;
1030         trans_pcie->ac_to_fifo[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_fifo;
1031
1032         trans_pcie->mcast_queue[IWL_RXON_CTX_BSS] = 0;
1033         trans_pcie->mcast_queue[IWL_RXON_CTX_PAN] = IWL_IPAN_MCAST_QUEUE;
1034
1035         /* This may fail if AMT took ownership of the device */
1036         if (iwl_prepare_card_hw(trans)) {
1037                 IWL_WARN(trans, "Exit HW not ready\n");
1038                 return -EIO;
1039         }
1040
1041         /* If platform's RF_KILL switch is NOT set to KILL */
1042         hw_rfkill = !(iwl_read32(trans, CSR_GP_CNTRL) &
1043                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
1044         iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1045
1046         if (hw_rfkill) {
1047                 iwl_enable_rfkill_int(trans);
1048                 return -ERFKILL;
1049         }
1050
1051         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1052
1053         ret = iwl_nic_init(trans);
1054         if (ret) {
1055                 IWL_ERR(trans, "Unable to init nic\n");
1056                 return ret;
1057         }
1058
1059         /* make sure rfkill handshake bits are cleared */
1060         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1061         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1062                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1063
1064         /* clear (again), then enable host interrupts */
1065         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1066         iwl_enable_interrupts(trans);
1067
1068         /* really make sure rfkill handshake bits are cleared */
1069         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1070         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1071
1072         /* Load the given image to the HW */
1073         return iwl_load_given_ucode(trans, fw);
1074 }
1075
1076 /*
1077  * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
1078  * must be called under the irq lock and with MAC access
1079  */
1080 static void iwl_trans_txq_set_sched(struct iwl_trans *trans, u32 mask)
1081 {
1082         struct iwl_trans_pcie __maybe_unused *trans_pcie =
1083                 IWL_TRANS_GET_PCIE_TRANS(trans);
1084
1085         lockdep_assert_held(&trans_pcie->irq_lock);
1086
1087         iwl_write_prph(trans, SCD_TXFACT, mask);
1088 }
1089
1090 static void iwl_tx_start(struct iwl_trans *trans)
1091 {
1092         const struct queue_to_fifo_ac *queue_to_fifo;
1093         struct iwl_trans_pcie *trans_pcie =
1094                 IWL_TRANS_GET_PCIE_TRANS(trans);
1095         u32 a;
1096         unsigned long flags;
1097         int i, chan;
1098         u32 reg_val;
1099
1100         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1101
1102         trans_pcie->scd_base_addr =
1103                 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
1104         a = trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND;
1105         /* reset conext data memory */
1106         for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND;
1107                 a += 4)
1108                 iwl_write_targ_mem(trans, a, 0);
1109         /* reset tx status memory */
1110         for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND;
1111                 a += 4)
1112                 iwl_write_targ_mem(trans, a, 0);
1113         for (; a < trans_pcie->scd_base_addr +
1114                SCD_TRANS_TBL_OFFSET_QUEUE(hw_params(trans).max_txq_num);
1115                a += 4)
1116                 iwl_write_targ_mem(trans, a, 0);
1117
1118         iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
1119                        trans_pcie->scd_bc_tbls.dma >> 10);
1120
1121         /* Enable DMA channel */
1122         for (chan = 0; chan < FH_TCSR_CHNL_NUM ; chan++)
1123                 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
1124                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
1125                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
1126
1127         /* Update FH chicken bits */
1128         reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
1129         iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
1130                            reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
1131
1132         iwl_write_prph(trans, SCD_QUEUECHAIN_SEL,
1133                 SCD_QUEUECHAIN_SEL_ALL(trans));
1134         iwl_write_prph(trans, SCD_AGGR_SEL, 0);
1135
1136         /* initiate the queues */
1137         for (i = 0; i < hw_params(trans).max_txq_num; i++) {
1138                 iwl_write_prph(trans, SCD_QUEUE_RDPTR(i), 0);
1139                 iwl_write_direct32(trans, HBUS_TARG_WRPTR, 0 | (i << 8));
1140                 iwl_write_targ_mem(trans, trans_pcie->scd_base_addr +
1141                                 SCD_CONTEXT_QUEUE_OFFSET(i), 0);
1142                 iwl_write_targ_mem(trans, trans_pcie->scd_base_addr +
1143                                 SCD_CONTEXT_QUEUE_OFFSET(i) +
1144                                 sizeof(u32),
1145                                 ((SCD_WIN_SIZE <<
1146                                 SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1147                                 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1148                                 ((SCD_FRAME_LIMIT <<
1149                                 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1150                                 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1151         }
1152
1153         iwl_write_prph(trans, SCD_INTERRUPT_MASK,
1154                         IWL_MASK(0, hw_params(trans).max_txq_num));
1155
1156         /* Activate all Tx DMA/FIFO channels */
1157         iwl_trans_txq_set_sched(trans, IWL_MASK(0, 7));
1158
1159         /* map queues to FIFOs */
1160         if (trans->shrd->valid_contexts != BIT(IWL_RXON_CTX_BSS))
1161                 queue_to_fifo = iwlagn_ipan_queue_to_tx_fifo;
1162         else
1163                 queue_to_fifo = iwlagn_default_queue_to_tx_fifo;
1164
1165         iwl_trans_set_wr_ptrs(trans, trans->shrd->cmd_queue, 0);
1166
1167         /* make sure all queue are not stopped */
1168         memset(&trans_pcie->queue_stopped[0], 0,
1169                 sizeof(trans_pcie->queue_stopped));
1170         for (i = 0; i < 4; i++)
1171                 atomic_set(&trans_pcie->queue_stop_count[i], 0);
1172
1173         /* reset to 0 to enable all the queue first */
1174         trans_pcie->txq_ctx_active_msk = 0;
1175
1176         BUILD_BUG_ON(ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo) <
1177                                                 IWLAGN_FIRST_AMPDU_QUEUE);
1178         BUILD_BUG_ON(ARRAY_SIZE(iwlagn_ipan_queue_to_tx_fifo) <
1179                                                 IWLAGN_FIRST_AMPDU_QUEUE);
1180
1181         for (i = 0; i < IWLAGN_FIRST_AMPDU_QUEUE; i++) {
1182                 int fifo = queue_to_fifo[i].fifo;
1183                 int ac = queue_to_fifo[i].ac;
1184
1185                 iwl_txq_ctx_activate(trans_pcie, i);
1186
1187                 if (fifo == IWL_TX_FIFO_UNUSED)
1188                         continue;
1189
1190                 if (ac != IWL_AC_UNSET)
1191                         iwl_set_swq_id(&trans_pcie->txq[i], ac, i);
1192                 iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[i],
1193                                               fifo, 0);
1194         }
1195
1196         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1197
1198         /* Enable L1-Active */
1199         iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
1200                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1201 }
1202
1203 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans)
1204 {
1205         iwl_reset_ict(trans);
1206         iwl_tx_start(trans);
1207 }
1208
1209 /**
1210  * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
1211  */
1212 static int iwl_trans_tx_stop(struct iwl_trans *trans)
1213 {
1214         int ch, txq_id, ret;
1215         unsigned long flags;
1216         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1217
1218         /* Turn off all Tx DMA fifos */
1219         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1220
1221         iwl_trans_txq_set_sched(trans, 0);
1222
1223         /* Stop each Tx DMA channel, and wait for it to be idle */
1224         for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
1225                 iwl_write_direct32(trans,
1226                                    FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
1227                 ret = iwl_poll_direct_bit(trans, FH_TSSR_TX_STATUS_REG,
1228                                     FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
1229                                     1000);
1230                 if (ret < 0)
1231                         IWL_ERR(trans, "Failing on timeout while stopping"
1232                             " DMA channel %d [0x%08x]", ch,
1233                             iwl_read_direct32(trans,
1234                                               FH_TSSR_TX_STATUS_REG));
1235         }
1236         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1237
1238         if (!trans_pcie->txq) {
1239                 IWL_WARN(trans, "Stopping tx queues that aren't allocated...");
1240                 return 0;
1241         }
1242
1243         /* Unmap DMA from host system and free skb's */
1244         for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++)
1245                 iwl_tx_queue_unmap(trans, txq_id);
1246
1247         return 0;
1248 }
1249
1250 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
1251 {
1252         unsigned long flags;
1253         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1254
1255         /* tell the device to stop sending interrupts */
1256         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1257         iwl_disable_interrupts(trans);
1258         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1259
1260         /* device going down, Stop using ICT table */
1261         iwl_disable_ict(trans);
1262
1263         /*
1264          * If a HW restart happens during firmware loading,
1265          * then the firmware loading might call this function
1266          * and later it might be called again due to the
1267          * restart. So don't process again if the device is
1268          * already dead.
1269          */
1270         if (test_bit(STATUS_DEVICE_ENABLED, &trans->shrd->status)) {
1271                 iwl_trans_tx_stop(trans);
1272 #ifndef CONFIG_IWLWIFI_IDI
1273                 iwl_trans_rx_stop(trans);
1274 #endif
1275                 /* Power-down device's busmaster DMA clocks */
1276                 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1277                                APMG_CLK_VAL_DMA_CLK_RQT);
1278                 udelay(5);
1279         }
1280
1281         /* Make sure (redundant) we've released our request to stay awake */
1282         iwl_clear_bit(trans, CSR_GP_CNTRL,
1283                         CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1284
1285         /* Stop the device, and put it in low power state */
1286         iwl_apm_stop(trans);
1287
1288         /* Upon stop, the APM issues an interrupt if HW RF kill is set.
1289          * Clean again the interrupt here
1290          */
1291         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1292         iwl_disable_interrupts(trans);
1293         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1294
1295         /* wait to make sure we flush pending tasklet*/
1296         synchronize_irq(trans_pcie->irq);
1297         tasklet_kill(&trans_pcie->irq_tasklet);
1298
1299         cancel_work_sync(&trans_pcie->rx_replenish);
1300
1301         /* stop and reset the on-board processor */
1302         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
1303 }
1304
1305 static void iwl_trans_pcie_wowlan_suspend(struct iwl_trans *trans)
1306 {
1307         /* let the ucode operate on its own */
1308         iwl_write32(trans, CSR_UCODE_DRV_GP1_SET,
1309                     CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);
1310
1311         iwl_disable_interrupts(trans);
1312         iwl_clear_bit(trans, CSR_GP_CNTRL,
1313                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1314 }
1315
1316 static int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
1317                 struct iwl_device_cmd *dev_cmd, enum iwl_rxon_context_id ctx,
1318                 u8 sta_id, u8 tid)
1319 {
1320         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1321         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1322         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1323         struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *) dev_cmd->payload;
1324         struct iwl_cmd_meta *out_meta;
1325         struct iwl_tx_queue *txq;
1326         struct iwl_queue *q;
1327
1328         dma_addr_t phys_addr = 0;
1329         dma_addr_t txcmd_phys;
1330         dma_addr_t scratch_phys;
1331         u16 len, firstlen, secondlen;
1332         u8 wait_write_ptr = 0;
1333         u8 txq_id;
1334         bool is_agg = false;
1335         __le16 fc = hdr->frame_control;
1336         u8 hdr_len = ieee80211_hdrlen(fc);
1337         u16 __maybe_unused wifi_seq;
1338
1339         /*
1340          * Send this frame after DTIM -- there's a special queue
1341          * reserved for this for contexts that support AP mode.
1342          */
1343         if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
1344                 txq_id = trans_pcie->mcast_queue[ctx];
1345
1346                 /*
1347                  * The microcode will clear the more data
1348                  * bit in the last frame it transmits.
1349                  */
1350                 hdr->frame_control |=
1351                         cpu_to_le16(IEEE80211_FCTL_MOREDATA);
1352         } else if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN)
1353                 txq_id = IWL_AUX_QUEUE;
1354         else
1355                 txq_id =
1356                     trans_pcie->ac_to_queue[ctx][skb_get_queue_mapping(skb)];
1357
1358         /* aggregation is on for this <sta,tid> */
1359         if (info->flags & IEEE80211_TX_CTL_AMPDU) {
1360                 WARN_ON(tid >= IWL_MAX_TID_COUNT);
1361                 txq_id = trans_pcie->agg_txq[sta_id][tid];
1362                 is_agg = true;
1363         }
1364
1365         txq = &trans_pcie->txq[txq_id];
1366         q = &txq->q;
1367
1368         spin_lock(&txq->lock);
1369
1370         /* In AGG mode, the index in the ring must correspond to the WiFi
1371          * sequence number. This is a HW requirements to help the SCD to parse
1372          * the BA.
1373          * Check here that the packets are in the right place on the ring.
1374          */
1375 #ifdef CONFIG_IWLWIFI_DEBUG
1376         wifi_seq = SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
1377         WARN_ONCE(is_agg && ((wifi_seq & 0xff) != q->write_ptr),
1378                   "Q: %d WiFi Seq %d tfdNum %d",
1379                   txq_id, wifi_seq, q->write_ptr);
1380 #endif
1381
1382         /* Set up driver data for this TFD */
1383         txq->skbs[q->write_ptr] = skb;
1384         txq->cmd[q->write_ptr] = dev_cmd;
1385
1386         dev_cmd->hdr.cmd = REPLY_TX;
1387         dev_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
1388                                 INDEX_TO_SEQ(q->write_ptr)));
1389
1390         /* Set up first empty entry in queue's array of Tx/cmd buffers */
1391         out_meta = &txq->meta[q->write_ptr];
1392
1393         /*
1394          * Use the first empty entry in this queue's command buffer array
1395          * to contain the Tx command and MAC header concatenated together
1396          * (payload data will be in another buffer).
1397          * Size of this varies, due to varying MAC header length.
1398          * If end is not dword aligned, we'll have 2 extra bytes at the end
1399          * of the MAC header (device reads on dword boundaries).
1400          * We'll tell device about this padding later.
1401          */
1402         len = sizeof(struct iwl_tx_cmd) +
1403                 sizeof(struct iwl_cmd_header) + hdr_len;
1404         firstlen = (len + 3) & ~3;
1405
1406         /* Tell NIC about any 2-byte padding after MAC header */
1407         if (firstlen != len)
1408                 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1409
1410         /* Physical address of this Tx command's header (not MAC header!),
1411          * within command buffer array. */
1412         txcmd_phys = dma_map_single(trans->dev,
1413                                     &dev_cmd->hdr, firstlen,
1414                                     DMA_BIDIRECTIONAL);
1415         if (unlikely(dma_mapping_error(trans->dev, txcmd_phys)))
1416                 goto out_err;
1417         dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
1418         dma_unmap_len_set(out_meta, len, firstlen);
1419
1420         if (!ieee80211_has_morefrags(fc)) {
1421                 txq->need_update = 1;
1422         } else {
1423                 wait_write_ptr = 1;
1424                 txq->need_update = 0;
1425         }
1426
1427         /* Set up TFD's 2nd entry to point directly to remainder of skb,
1428          * if any (802.11 null frames have no payload). */
1429         secondlen = skb->len - hdr_len;
1430         if (secondlen > 0) {
1431                 phys_addr = dma_map_single(trans->dev, skb->data + hdr_len,
1432                                            secondlen, DMA_TO_DEVICE);
1433                 if (unlikely(dma_mapping_error(trans->dev, phys_addr))) {
1434                         dma_unmap_single(trans->dev,
1435                                          dma_unmap_addr(out_meta, mapping),
1436                                          dma_unmap_len(out_meta, len),
1437                                          DMA_BIDIRECTIONAL);
1438                         goto out_err;
1439                 }
1440         }
1441
1442         /* Attach buffers to TFD */
1443         iwlagn_txq_attach_buf_to_tfd(trans, txq, txcmd_phys, firstlen, 1);
1444         if (secondlen > 0)
1445                 iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr,
1446                                              secondlen, 0);
1447
1448         scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
1449                                 offsetof(struct iwl_tx_cmd, scratch);
1450
1451         /* take back ownership of DMA buffer to enable update */
1452         dma_sync_single_for_cpu(trans->dev, txcmd_phys, firstlen,
1453                         DMA_BIDIRECTIONAL);
1454         tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1455         tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1456
1457         IWL_DEBUG_TX(trans, "sequence nr = 0X%x\n",
1458                      le16_to_cpu(dev_cmd->hdr.sequence));
1459         IWL_DEBUG_TX(trans, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
1460         iwl_print_hex_dump(trans, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
1461         iwl_print_hex_dump(trans, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
1462
1463         /* Set up entry for this TFD in Tx byte-count array */
1464         iwl_trans_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len));
1465
1466         dma_sync_single_for_device(trans->dev, txcmd_phys, firstlen,
1467                         DMA_BIDIRECTIONAL);
1468
1469         trace_iwlwifi_dev_tx(trans->dev,
1470                              &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr],
1471                              sizeof(struct iwl_tfd),
1472                              &dev_cmd->hdr, firstlen,
1473                              skb->data + hdr_len, secondlen);
1474
1475         /* Tell device the write index *just past* this latest filled TFD */
1476         q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1477         iwl_txq_update_write_ptr(trans, txq);
1478
1479         /*
1480          * At this point the frame is "transmitted" successfully
1481          * and we will get a TX status notification eventually,
1482          * regardless of the value of ret. "ret" only indicates
1483          * whether or not we should update the write pointer.
1484          */
1485         if (iwl_queue_space(q) < q->high_mark) {
1486                 if (wait_write_ptr) {
1487                         txq->need_update = 1;
1488                         iwl_txq_update_write_ptr(trans, txq);
1489                 } else {
1490                         iwl_stop_queue(trans, txq, "Queue is full");
1491                 }
1492         }
1493         spin_unlock(&txq->lock);
1494         return 0;
1495  out_err:
1496         spin_unlock(&txq->lock);
1497         return -1;
1498 }
1499
1500 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1501 {
1502         struct iwl_trans_pcie *trans_pcie =
1503                 IWL_TRANS_GET_PCIE_TRANS(trans);
1504         int err;
1505         bool hw_rfkill;
1506
1507         trans_pcie->inta_mask = CSR_INI_SET_MASK;
1508
1509         if (!trans_pcie->irq_requested) {
1510                 tasklet_init(&trans_pcie->irq_tasklet, (void (*)(unsigned long))
1511                         iwl_irq_tasklet, (unsigned long)trans);
1512
1513                 iwl_alloc_isr_ict(trans);
1514
1515                 err = request_irq(trans_pcie->irq, iwl_isr_ict, IRQF_SHARED,
1516                         DRV_NAME, trans);
1517                 if (err) {
1518                         IWL_ERR(trans, "Error allocating IRQ %d\n",
1519                                 trans_pcie->irq);
1520                         goto error;
1521                 }
1522
1523                 INIT_WORK(&trans_pcie->rx_replenish, iwl_bg_rx_replenish);
1524                 trans_pcie->irq_requested = true;
1525         }
1526
1527         err = iwl_prepare_card_hw(trans);
1528         if (err) {
1529                 IWL_ERR(trans, "Error while preparing HW: %d", err);
1530                 goto err_free_irq;
1531         }
1532
1533         iwl_apm_init(trans);
1534
1535         hw_rfkill = !(iwl_read32(trans, CSR_GP_CNTRL) &
1536                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
1537         iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1538
1539         return err;
1540
1541 err_free_irq:
1542         free_irq(trans_pcie->irq, trans);
1543 error:
1544         iwl_free_isr_ict(trans);
1545         tasklet_kill(&trans_pcie->irq_tasklet);
1546         return err;
1547 }
1548
1549 static void iwl_trans_pcie_stop_hw(struct iwl_trans *trans)
1550 {
1551         iwl_apm_stop(trans);
1552
1553         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1554
1555         /* Even if we stop the HW, we still want the RF kill interrupt */
1556         iwl_enable_rfkill_int(trans);
1557 }
1558
1559 static int iwl_trans_pcie_reclaim(struct iwl_trans *trans, int sta_id, int tid,
1560                       int txq_id, int ssn, struct sk_buff_head *skbs)
1561 {
1562         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1563         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
1564         /* n_bd is usually 256 => n_bd - 1 = 0xff */
1565         int tfd_num = ssn & (txq->q.n_bd - 1);
1566         int freed = 0;
1567
1568         spin_lock(&txq->lock);
1569
1570         txq->time_stamp = jiffies;
1571
1572         if (unlikely(txq_id >= IWLAGN_FIRST_AMPDU_QUEUE &&
1573                      tid != IWL_TID_NON_QOS &&
1574                      txq_id != trans_pcie->agg_txq[sta_id][tid])) {
1575                 /*
1576                  * FIXME: this is a uCode bug which need to be addressed,
1577                  * log the information and return for now.
1578                  * Since it is can possibly happen very often and in order
1579                  * not to fill the syslog, don't use IWL_ERR or IWL_WARN
1580                  */
1581                 IWL_DEBUG_TX_QUEUES(trans, "Bad queue mapping txq_id %d, "
1582                         "agg_txq[sta_id[tid] %d", txq_id,
1583                         trans_pcie->agg_txq[sta_id][tid]);
1584                 spin_unlock(&txq->lock);
1585                 return 1;
1586         }
1587
1588         if (txq->q.read_ptr != tfd_num) {
1589                 IWL_DEBUG_TX_REPLY(trans, "[Q %d | AC %d] %d -> %d (%d)\n",
1590                                 txq_id, iwl_get_queue_ac(txq), txq->q.read_ptr,
1591                                 tfd_num, ssn);
1592                 freed = iwl_tx_queue_reclaim(trans, txq_id, tfd_num, skbs);
1593                 if (iwl_queue_space(&txq->q) > txq->q.low_mark)
1594                         iwl_wake_queue(trans, txq, "Packets reclaimed");
1595         }
1596
1597         spin_unlock(&txq->lock);
1598         return 0;
1599 }
1600
1601 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1602 {
1603         writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1604 }
1605
1606 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1607 {
1608         writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1609 }
1610
1611 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1612 {
1613         return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1614 }
1615
1616 static void iwl_trans_pcie_free(struct iwl_trans *trans)
1617 {
1618         struct iwl_trans_pcie *trans_pcie =
1619                 IWL_TRANS_GET_PCIE_TRANS(trans);
1620
1621         iwl_trans_pcie_tx_free(trans);
1622 #ifndef CONFIG_IWLWIFI_IDI
1623         iwl_trans_pcie_rx_free(trans);
1624 #endif
1625         if (trans_pcie->irq_requested == true) {
1626                 free_irq(trans_pcie->irq, trans);
1627                 iwl_free_isr_ict(trans);
1628         }
1629
1630         pci_disable_msi(trans_pcie->pci_dev);
1631         iounmap(trans_pcie->hw_base);
1632         pci_release_regions(trans_pcie->pci_dev);
1633         pci_disable_device(trans_pcie->pci_dev);
1634
1635         trans->shrd->trans = NULL;
1636         kfree(trans);
1637 }
1638
1639 #ifdef CONFIG_PM_SLEEP
1640 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
1641 {
1642         return 0;
1643 }
1644
1645 static int iwl_trans_pcie_resume(struct iwl_trans *trans)
1646 {
1647         bool hw_rfkill;
1648
1649         hw_rfkill = !(iwl_read32(trans, CSR_GP_CNTRL) &
1650                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
1651
1652         if (hw_rfkill)
1653                 iwl_enable_rfkill_int(trans);
1654         else
1655                 iwl_enable_interrupts(trans);
1656
1657         iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1658
1659         return 0;
1660 }
1661 #endif /* CONFIG_PM_SLEEP */
1662
1663 #define IWL_FLUSH_WAIT_MS       2000
1664
1665 static int iwl_trans_pcie_wait_tx_queue_empty(struct iwl_trans *trans)
1666 {
1667         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1668         struct iwl_tx_queue *txq;
1669         struct iwl_queue *q;
1670         int cnt;
1671         unsigned long now = jiffies;
1672         int ret = 0;
1673
1674         /* waiting for all the tx frames complete might take a while */
1675         for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) {
1676                 if (cnt == trans->shrd->cmd_queue)
1677                         continue;
1678                 txq = &trans_pcie->txq[cnt];
1679                 q = &txq->q;
1680                 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1681                        now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1682                         msleep(1);
1683
1684                 if (q->read_ptr != q->write_ptr) {
1685                         IWL_ERR(trans, "fail to flush all tx fifo queues\n");
1686                         ret = -ETIMEDOUT;
1687                         break;
1688                 }
1689         }
1690         return ret;
1691 }
1692
1693 /*
1694  * On every watchdog tick we check (latest) time stamp. If it does not
1695  * change during timeout period and queue is not empty we reset firmware.
1696  */
1697 static int iwl_trans_pcie_check_stuck_queue(struct iwl_trans *trans, int cnt)
1698 {
1699         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1700         struct iwl_tx_queue *txq = &trans_pcie->txq[cnt];
1701         struct iwl_queue *q = &txq->q;
1702         unsigned long timeout;
1703
1704         if (q->read_ptr == q->write_ptr) {
1705                 txq->time_stamp = jiffies;
1706                 return 0;
1707         }
1708
1709         timeout = txq->time_stamp +
1710                   msecs_to_jiffies(hw_params(trans).wd_timeout);
1711
1712         if (time_after(jiffies, timeout)) {
1713                 IWL_ERR(trans, "Queue %d stuck for %u ms.\n", q->id,
1714                         hw_params(trans).wd_timeout);
1715                 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1716                         q->read_ptr, q->write_ptr);
1717                 IWL_ERR(trans, "Current HW read_ptr %d write_ptr %d\n",
1718                         iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt))
1719                                 & (TFD_QUEUE_SIZE_MAX - 1),
1720                         iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1721                 return 1;
1722         }
1723
1724         return 0;
1725 }
1726
1727 static const char *get_fh_string(int cmd)
1728 {
1729         switch (cmd) {
1730         IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
1731         IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
1732         IWL_CMD(FH_RSCSR_CHNL0_WPTR);
1733         IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
1734         IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
1735         IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
1736         IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
1737         IWL_CMD(FH_TSSR_TX_STATUS_REG);
1738         IWL_CMD(FH_TSSR_TX_ERROR_REG);
1739         default:
1740                 return "UNKNOWN";
1741         }
1742 }
1743
1744 int iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display)
1745 {
1746         int i;
1747 #ifdef CONFIG_IWLWIFI_DEBUG
1748         int pos = 0;
1749         size_t bufsz = 0;
1750 #endif
1751         static const u32 fh_tbl[] = {
1752                 FH_RSCSR_CHNL0_STTS_WPTR_REG,
1753                 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
1754                 FH_RSCSR_CHNL0_WPTR,
1755                 FH_MEM_RCSR_CHNL0_CONFIG_REG,
1756                 FH_MEM_RSSR_SHARED_CTRL_REG,
1757                 FH_MEM_RSSR_RX_STATUS_REG,
1758                 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
1759                 FH_TSSR_TX_STATUS_REG,
1760                 FH_TSSR_TX_ERROR_REG
1761         };
1762 #ifdef CONFIG_IWLWIFI_DEBUG
1763         if (display) {
1764                 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
1765                 *buf = kmalloc(bufsz, GFP_KERNEL);
1766                 if (!*buf)
1767                         return -ENOMEM;
1768                 pos += scnprintf(*buf + pos, bufsz - pos,
1769                                 "FH register values:\n");
1770                 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1771                         pos += scnprintf(*buf + pos, bufsz - pos,
1772                                 "  %34s: 0X%08x\n",
1773                                 get_fh_string(fh_tbl[i]),
1774                                 iwl_read_direct32(trans, fh_tbl[i]));
1775                 }
1776                 return pos;
1777         }
1778 #endif
1779         IWL_ERR(trans, "FH register values:\n");
1780         for (i = 0; i <  ARRAY_SIZE(fh_tbl); i++) {
1781                 IWL_ERR(trans, "  %34s: 0X%08x\n",
1782                         get_fh_string(fh_tbl[i]),
1783                         iwl_read_direct32(trans, fh_tbl[i]));
1784         }
1785         return 0;
1786 }
1787
1788 static const char *get_csr_string(int cmd)
1789 {
1790         switch (cmd) {
1791         IWL_CMD(CSR_HW_IF_CONFIG_REG);
1792         IWL_CMD(CSR_INT_COALESCING);
1793         IWL_CMD(CSR_INT);
1794         IWL_CMD(CSR_INT_MASK);
1795         IWL_CMD(CSR_FH_INT_STATUS);
1796         IWL_CMD(CSR_GPIO_IN);
1797         IWL_CMD(CSR_RESET);
1798         IWL_CMD(CSR_GP_CNTRL);
1799         IWL_CMD(CSR_HW_REV);
1800         IWL_CMD(CSR_EEPROM_REG);
1801         IWL_CMD(CSR_EEPROM_GP);
1802         IWL_CMD(CSR_OTP_GP_REG);
1803         IWL_CMD(CSR_GIO_REG);
1804         IWL_CMD(CSR_GP_UCODE_REG);
1805         IWL_CMD(CSR_GP_DRIVER_REG);
1806         IWL_CMD(CSR_UCODE_DRV_GP1);
1807         IWL_CMD(CSR_UCODE_DRV_GP2);
1808         IWL_CMD(CSR_LED_REG);
1809         IWL_CMD(CSR_DRAM_INT_TBL_REG);
1810         IWL_CMD(CSR_GIO_CHICKEN_BITS);
1811         IWL_CMD(CSR_ANA_PLL_CFG);
1812         IWL_CMD(CSR_HW_REV_WA_REG);
1813         IWL_CMD(CSR_DBG_HPET_MEM_REG);
1814         default:
1815                 return "UNKNOWN";
1816         }
1817 }
1818
1819 void iwl_dump_csr(struct iwl_trans *trans)
1820 {
1821         int i;
1822         static const u32 csr_tbl[] = {
1823                 CSR_HW_IF_CONFIG_REG,
1824                 CSR_INT_COALESCING,
1825                 CSR_INT,
1826                 CSR_INT_MASK,
1827                 CSR_FH_INT_STATUS,
1828                 CSR_GPIO_IN,
1829                 CSR_RESET,
1830                 CSR_GP_CNTRL,
1831                 CSR_HW_REV,
1832                 CSR_EEPROM_REG,
1833                 CSR_EEPROM_GP,
1834                 CSR_OTP_GP_REG,
1835                 CSR_GIO_REG,
1836                 CSR_GP_UCODE_REG,
1837                 CSR_GP_DRIVER_REG,
1838                 CSR_UCODE_DRV_GP1,
1839                 CSR_UCODE_DRV_GP2,
1840                 CSR_LED_REG,
1841                 CSR_DRAM_INT_TBL_REG,
1842                 CSR_GIO_CHICKEN_BITS,
1843                 CSR_ANA_PLL_CFG,
1844                 CSR_HW_REV_WA_REG,
1845                 CSR_DBG_HPET_MEM_REG
1846         };
1847         IWL_ERR(trans, "CSR values:\n");
1848         IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1849                 "CSR_INT_PERIODIC_REG)\n");
1850         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
1851                 IWL_ERR(trans, "  %25s: 0X%08x\n",
1852                         get_csr_string(csr_tbl[i]),
1853                         iwl_read32(trans, csr_tbl[i]));
1854         }
1855 }
1856
1857 #ifdef CONFIG_IWLWIFI_DEBUGFS
1858 /* create and remove of files */
1859 #define DEBUGFS_ADD_FILE(name, parent, mode) do {                       \
1860         if (!debugfs_create_file(#name, mode, parent, trans,            \
1861                                  &iwl_dbgfs_##name##_ops))              \
1862                 return -ENOMEM;                                         \
1863 } while (0)
1864
1865 /* file operation */
1866 #define DEBUGFS_READ_FUNC(name)                                         \
1867 static ssize_t iwl_dbgfs_##name##_read(struct file *file,               \
1868                                         char __user *user_buf,          \
1869                                         size_t count, loff_t *ppos);
1870
1871 #define DEBUGFS_WRITE_FUNC(name)                                        \
1872 static ssize_t iwl_dbgfs_##name##_write(struct file *file,              \
1873                                         const char __user *user_buf,    \
1874                                         size_t count, loff_t *ppos);
1875
1876
1877 static int iwl_dbgfs_open_file_generic(struct inode *inode, struct file *file)
1878 {
1879         file->private_data = inode->i_private;
1880         return 0;
1881 }
1882
1883 #define DEBUGFS_READ_FILE_OPS(name)                                     \
1884         DEBUGFS_READ_FUNC(name);                                        \
1885 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1886         .read = iwl_dbgfs_##name##_read,                                \
1887         .open = iwl_dbgfs_open_file_generic,                            \
1888         .llseek = generic_file_llseek,                                  \
1889 };
1890
1891 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
1892         DEBUGFS_WRITE_FUNC(name);                                       \
1893 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1894         .write = iwl_dbgfs_##name##_write,                              \
1895         .open = iwl_dbgfs_open_file_generic,                            \
1896         .llseek = generic_file_llseek,                                  \
1897 };
1898
1899 #define DEBUGFS_READ_WRITE_FILE_OPS(name)                               \
1900         DEBUGFS_READ_FUNC(name);                                        \
1901         DEBUGFS_WRITE_FUNC(name);                                       \
1902 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1903         .write = iwl_dbgfs_##name##_write,                              \
1904         .read = iwl_dbgfs_##name##_read,                                \
1905         .open = iwl_dbgfs_open_file_generic,                            \
1906         .llseek = generic_file_llseek,                                  \
1907 };
1908
1909 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1910                                                 char __user *user_buf,
1911                                                 size_t count, loff_t *ppos)
1912 {
1913         struct iwl_trans *trans = file->private_data;
1914         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1915         struct iwl_tx_queue *txq;
1916         struct iwl_queue *q;
1917         char *buf;
1918         int pos = 0;
1919         int cnt;
1920         int ret;
1921         const size_t bufsz = sizeof(char) * 64 * hw_params(trans).max_txq_num;
1922
1923         if (!trans_pcie->txq) {
1924                 IWL_ERR(trans, "txq not ready\n");
1925                 return -EAGAIN;
1926         }
1927         buf = kzalloc(bufsz, GFP_KERNEL);
1928         if (!buf)
1929                 return -ENOMEM;
1930
1931         for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) {
1932                 txq = &trans_pcie->txq[cnt];
1933                 q = &txq->q;
1934                 pos += scnprintf(buf + pos, bufsz - pos,
1935                                 "hwq %.2d: read=%u write=%u stop=%d"
1936                                 " swq_id=%#.2x (ac %d/hwq %d)\n",
1937                                 cnt, q->read_ptr, q->write_ptr,
1938                                 !!test_bit(cnt, trans_pcie->queue_stopped),
1939                                 txq->swq_id, txq->swq_id & 3,
1940                                 (txq->swq_id >> 2) & 0x1f);
1941                 if (cnt >= 4)
1942                         continue;
1943                 /* for the ACs, display the stop count too */
1944                 pos += scnprintf(buf + pos, bufsz - pos,
1945                         "        stop-count: %d\n",
1946                         atomic_read(&trans_pcie->queue_stop_count[cnt]));
1947         }
1948         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1949         kfree(buf);
1950         return ret;
1951 }
1952
1953 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1954                                                 char __user *user_buf,
1955                                                 size_t count, loff_t *ppos) {
1956         struct iwl_trans *trans = file->private_data;
1957         struct iwl_trans_pcie *trans_pcie =
1958                 IWL_TRANS_GET_PCIE_TRANS(trans);
1959         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
1960         char buf[256];
1961         int pos = 0;
1962         const size_t bufsz = sizeof(buf);
1963
1964         pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1965                                                 rxq->read);
1966         pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1967                                                 rxq->write);
1968         pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1969                                                 rxq->free_count);
1970         if (rxq->rb_stts) {
1971                 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1972                          le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF);
1973         } else {
1974                 pos += scnprintf(buf + pos, bufsz - pos,
1975                                         "closed_rb_num: Not Allocated\n");
1976         }
1977         return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1978 }
1979
1980 static ssize_t iwl_dbgfs_log_event_read(struct file *file,
1981                                          char __user *user_buf,
1982                                          size_t count, loff_t *ppos)
1983 {
1984         struct iwl_trans *trans = file->private_data;
1985         char *buf;
1986         int pos = 0;
1987         ssize_t ret = -ENOMEM;
1988
1989         ret = pos = iwl_dump_nic_event_log(trans, true, &buf, true);
1990         if (buf) {
1991                 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1992                 kfree(buf);
1993         }
1994         return ret;
1995 }
1996
1997 static ssize_t iwl_dbgfs_log_event_write(struct file *file,
1998                                         const char __user *user_buf,
1999                                         size_t count, loff_t *ppos)
2000 {
2001         struct iwl_trans *trans = file->private_data;
2002         u32 event_log_flag;
2003         char buf[8];
2004         int buf_size;
2005
2006         memset(buf, 0, sizeof(buf));
2007         buf_size = min(count, sizeof(buf) -  1);
2008         if (copy_from_user(buf, user_buf, buf_size))
2009                 return -EFAULT;
2010         if (sscanf(buf, "%d", &event_log_flag) != 1)
2011                 return -EFAULT;
2012         if (event_log_flag == 1)
2013                 iwl_dump_nic_event_log(trans, true, NULL, false);
2014
2015         return count;
2016 }
2017
2018 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
2019                                         char __user *user_buf,
2020                                         size_t count, loff_t *ppos) {
2021
2022         struct iwl_trans *trans = file->private_data;
2023         struct iwl_trans_pcie *trans_pcie =
2024                 IWL_TRANS_GET_PCIE_TRANS(trans);
2025         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2026
2027         int pos = 0;
2028         char *buf;
2029         int bufsz = 24 * 64; /* 24 items * 64 char per item */
2030         ssize_t ret;
2031
2032         buf = kzalloc(bufsz, GFP_KERNEL);
2033         if (!buf) {
2034                 IWL_ERR(trans, "Can not allocate Buffer\n");
2035                 return -ENOMEM;
2036         }
2037
2038         pos += scnprintf(buf + pos, bufsz - pos,
2039                         "Interrupt Statistics Report:\n");
2040
2041         pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2042                 isr_stats->hw);
2043         pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2044                 isr_stats->sw);
2045         if (isr_stats->sw || isr_stats->hw) {
2046                 pos += scnprintf(buf + pos, bufsz - pos,
2047                         "\tLast Restarting Code:  0x%X\n",
2048                         isr_stats->err_code);
2049         }
2050 #ifdef CONFIG_IWLWIFI_DEBUG
2051         pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2052                 isr_stats->sch);
2053         pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2054                 isr_stats->alive);
2055 #endif
2056         pos += scnprintf(buf + pos, bufsz - pos,
2057                 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2058
2059         pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2060                 isr_stats->ctkill);
2061
2062         pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2063                 isr_stats->wakeup);
2064
2065         pos += scnprintf(buf + pos, bufsz - pos,
2066                 "Rx command responses:\t\t %u\n", isr_stats->rx);
2067
2068         pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2069                 isr_stats->tx);
2070
2071         pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2072                 isr_stats->unhandled);
2073
2074         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2075         kfree(buf);
2076         return ret;
2077 }
2078
2079 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2080                                          const char __user *user_buf,
2081                                          size_t count, loff_t *ppos)
2082 {
2083         struct iwl_trans *trans = file->private_data;
2084         struct iwl_trans_pcie *trans_pcie =
2085                 IWL_TRANS_GET_PCIE_TRANS(trans);
2086         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2087
2088         char buf[8];
2089         int buf_size;
2090         u32 reset_flag;
2091
2092         memset(buf, 0, sizeof(buf));
2093         buf_size = min(count, sizeof(buf) -  1);
2094         if (copy_from_user(buf, user_buf, buf_size))
2095                 return -EFAULT;
2096         if (sscanf(buf, "%x", &reset_flag) != 1)
2097                 return -EFAULT;
2098         if (reset_flag == 0)
2099                 memset(isr_stats, 0, sizeof(*isr_stats));
2100
2101         return count;
2102 }
2103
2104 static ssize_t iwl_dbgfs_csr_write(struct file *file,
2105                                          const char __user *user_buf,
2106                                          size_t count, loff_t *ppos)
2107 {
2108         struct iwl_trans *trans = file->private_data;
2109         char buf[8];
2110         int buf_size;
2111         int csr;
2112
2113         memset(buf, 0, sizeof(buf));
2114         buf_size = min(count, sizeof(buf) -  1);
2115         if (copy_from_user(buf, user_buf, buf_size))
2116                 return -EFAULT;
2117         if (sscanf(buf, "%d", &csr) != 1)
2118                 return -EFAULT;
2119
2120         iwl_dump_csr(trans);
2121
2122         return count;
2123 }
2124
2125 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
2126                                          char __user *user_buf,
2127                                          size_t count, loff_t *ppos)
2128 {
2129         struct iwl_trans *trans = file->private_data;
2130         char *buf;
2131         int pos = 0;
2132         ssize_t ret = -EFAULT;
2133
2134         ret = pos = iwl_dump_fh(trans, &buf, true);
2135         if (buf) {
2136                 ret = simple_read_from_buffer(user_buf,
2137                                               count, ppos, buf, pos);
2138                 kfree(buf);
2139         }
2140
2141         return ret;
2142 }
2143
2144 DEBUGFS_READ_WRITE_FILE_OPS(log_event);
2145 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
2146 DEBUGFS_READ_FILE_OPS(fh_reg);
2147 DEBUGFS_READ_FILE_OPS(rx_queue);
2148 DEBUGFS_READ_FILE_OPS(tx_queue);
2149 DEBUGFS_WRITE_FILE_OPS(csr);
2150
2151 /*
2152  * Create the debugfs files and directories
2153  *
2154  */
2155 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2156                                         struct dentry *dir)
2157 {
2158         DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2159         DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
2160         DEBUGFS_ADD_FILE(log_event, dir, S_IWUSR | S_IRUSR);
2161         DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
2162         DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2163         DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
2164         return 0;
2165 }
2166 #else
2167 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2168                                         struct dentry *dir)
2169 { return 0; }
2170
2171 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2172
2173 const struct iwl_trans_ops trans_ops_pcie = {
2174         .start_hw = iwl_trans_pcie_start_hw,
2175         .stop_hw = iwl_trans_pcie_stop_hw,
2176         .fw_alive = iwl_trans_pcie_fw_alive,
2177         .start_fw = iwl_trans_pcie_start_fw,
2178         .stop_device = iwl_trans_pcie_stop_device,
2179
2180         .wowlan_suspend = iwl_trans_pcie_wowlan_suspend,
2181
2182         .send_cmd = iwl_trans_pcie_send_cmd,
2183
2184         .tx = iwl_trans_pcie_tx,
2185         .reclaim = iwl_trans_pcie_reclaim,
2186
2187         .tx_agg_disable = iwl_trans_pcie_tx_agg_disable,
2188         .tx_agg_alloc = iwl_trans_pcie_tx_agg_alloc,
2189         .tx_agg_setup = iwl_trans_pcie_tx_agg_setup,
2190
2191         .free = iwl_trans_pcie_free,
2192
2193         .dbgfs_register = iwl_trans_pcie_dbgfs_register,
2194
2195         .wait_tx_queue_empty = iwl_trans_pcie_wait_tx_queue_empty,
2196         .check_stuck_queue = iwl_trans_pcie_check_stuck_queue,
2197
2198 #ifdef CONFIG_PM_SLEEP
2199         .suspend = iwl_trans_pcie_suspend,
2200         .resume = iwl_trans_pcie_resume,
2201 #endif
2202         .write8 = iwl_trans_pcie_write8,
2203         .write32 = iwl_trans_pcie_write32,
2204         .read32 = iwl_trans_pcie_read32,
2205 };
2206
2207 struct iwl_trans *iwl_trans_pcie_alloc(struct iwl_shared *shrd,
2208                                        struct pci_dev *pdev,
2209                                        const struct pci_device_id *ent)
2210 {
2211         struct iwl_trans_pcie *trans_pcie;
2212         struct iwl_trans *trans;
2213         u16 pci_cmd;
2214         int err;
2215
2216         trans = kzalloc(sizeof(struct iwl_trans) +
2217                              sizeof(struct iwl_trans_pcie), GFP_KERNEL);
2218
2219         if (WARN_ON(!trans))
2220                 return NULL;
2221
2222         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2223
2224         trans->ops = &trans_ops_pcie;
2225         trans->shrd = shrd;
2226         trans_pcie->trans = trans;
2227         spin_lock_init(&trans_pcie->irq_lock);
2228         init_waitqueue_head(&trans_pcie->ucode_write_waitq);
2229
2230         /* W/A - seems to solve weird behavior. We need to remove this if we
2231          * don't want to stay in L1 all the time. This wastes a lot of power */
2232         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
2233                                 PCIE_LINK_STATE_CLKPM);
2234
2235         if (pci_enable_device(pdev)) {
2236                 err = -ENODEV;
2237                 goto out_no_pci;
2238         }
2239
2240         pci_set_master(pdev);
2241
2242         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2243         if (!err)
2244                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2245         if (err) {
2246                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2247                 if (!err)
2248                         err = pci_set_consistent_dma_mask(pdev,
2249                                                         DMA_BIT_MASK(32));
2250                 /* both attempts failed: */
2251                 if (err) {
2252                         dev_printk(KERN_ERR, &pdev->dev,
2253                                    "No suitable DMA available.\n");
2254                         goto out_pci_disable_device;
2255                 }
2256         }
2257
2258         err = pci_request_regions(pdev, DRV_NAME);
2259         if (err) {
2260                 dev_printk(KERN_ERR, &pdev->dev, "pci_request_regions failed");
2261                 goto out_pci_disable_device;
2262         }
2263
2264         trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
2265         if (!trans_pcie->hw_base) {
2266                 dev_printk(KERN_ERR, &pdev->dev, "pci_ioremap_bar failed");
2267                 err = -ENODEV;
2268                 goto out_pci_release_regions;
2269         }
2270
2271         dev_printk(KERN_INFO, &pdev->dev,
2272                 "pci_resource_len = 0x%08llx\n",
2273                 (unsigned long long) pci_resource_len(pdev, 0));
2274         dev_printk(KERN_INFO, &pdev->dev,
2275                 "pci_resource_base = %p\n", trans_pcie->hw_base);
2276
2277         dev_printk(KERN_INFO, &pdev->dev,
2278                 "HW Revision ID = 0x%X\n", pdev->revision);
2279
2280         /* We disable the RETRY_TIMEOUT register (0x41) to keep
2281          * PCI Tx retries from interfering with C3 CPU state */
2282         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2283
2284         err = pci_enable_msi(pdev);
2285         if (err)
2286                 dev_printk(KERN_ERR, &pdev->dev,
2287                         "pci_enable_msi failed(0X%x)", err);
2288
2289         trans->dev = &pdev->dev;
2290         trans_pcie->irq = pdev->irq;
2291         trans_pcie->pci_dev = pdev;
2292         trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
2293         trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
2294         snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2295                  "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
2296
2297         /* TODO: Move this away, not needed if not MSI */
2298         /* enable rfkill interrupt: hw bug w/a */
2299         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2300         if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2301                 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2302                 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2303         }
2304
2305         return trans;
2306
2307 out_pci_release_regions:
2308         pci_release_regions(pdev);
2309 out_pci_disable_device:
2310         pci_disable_device(pdev);
2311 out_no_pci:
2312         kfree(trans);
2313         return NULL;
2314 }
2315