drivers/net/wireless/iwlwifi/iwl-trans-pcie.c

   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of version 2 of the GNU General Public License as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
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  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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  20  * along with this program; if not, write to the Free Software
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  25  * in the file called LICENSE.GPL.
  26  *
  27  * Contact Information:
  28  *  Intel Linux Wireless <ilw@linux.intel.com>
  29  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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  32  *
  33  * Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
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  41  *    notice, this list of conditions and the following disclaimer.
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  43  *    notice, this list of conditions and the following disclaimer in
  44  *    the documentation and/or other materials provided with the
  45  *    distribution.
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  47  *    contributors may be used to endorse or promote products derived
  48  *    from this software without specific prior written permission.
  49  *
  50  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  51  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  52  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  53  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  54  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  55  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  56  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  57  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  58  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  59  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  60  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  61  *
  62  *****************************************************************************/
  63 #include <linux/pci.h>
  64 #include <linux/pci-aspm.h>
  65 #include <linux/interrupt.h>
  66 #include <linux/debugfs.h>
  67 #include <linux/sched.h>
  68 #include <linux/bitops.h>
  69 #include <linux/gfp.h>
  70
  71 #include "iwl-trans.h"
  72 #include "iwl-trans-pcie-int.h"
  73 #include "iwl-csr.h"
  74 #include "iwl-prph.h"
  75 #include "iwl-shared.h"
  76 #include "iwl-eeprom.h"
  77 #include "iwl-agn-hw.h"
  78 #include "iwl-core.h"
  79
  80 static int iwl_trans_rx_alloc(struct iwl_trans *trans)
  81 {
  82         struct iwl_trans_pcie *trans_pcie =
  83                 IWL_TRANS_GET_PCIE_TRANS(trans);
  84         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
  85         struct device *dev = trans->dev;
  86
  87         memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq));
  88
  89         spin_lock_init(&rxq->lock);
  90
  91         if (WARN_ON(rxq->bd || rxq->rb_stts))
  92                 return -EINVAL;
  93
  94         /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
  95         rxq->bd = dma_zalloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
  96                                       &rxq->bd_dma, GFP_KERNEL);
  97         if (!rxq->bd)
  98                 goto err_bd;
  99
 100         /*Allocate the driver's pointer to receive buffer status */
 101         rxq->rb_stts = dma_zalloc_coherent(dev, sizeof(*rxq->rb_stts),
 102                                            &rxq->rb_stts_dma, GFP_KERNEL);
 103         if (!rxq->rb_stts)
 104                 goto err_rb_stts;
 105
 106         return 0;
 107
 108 err_rb_stts:
 109         dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
 110                         rxq->bd, rxq->bd_dma);
 111         memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
 112         rxq->bd = NULL;
 113 err_bd:
 114         return -ENOMEM;
 115 }
 116
 117 static void iwl_trans_rxq_free_rx_bufs(struct iwl_trans *trans)
 118 {
 119         struct iwl_trans_pcie *trans_pcie =
 120                 IWL_TRANS_GET_PCIE_TRANS(trans);
 121         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 122         int i;
 123
 124         /* Fill the rx_used queue with _all_ of the Rx buffers */
 125         for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
 126                 /* In the reset function, these buffers may have been allocated
 127                  * to an SKB, so we need to unmap and free potential storage */
 128                 if (rxq->pool[i].page != NULL) {
 129                         dma_unmap_page(trans->dev, rxq->pool[i].page_dma,
 130                                 PAGE_SIZE << hw_params(trans).rx_page_order,
 131                                 DMA_FROM_DEVICE);
 132                         __free_pages(rxq->pool[i].page,
 133                                      hw_params(trans).rx_page_order);
 134                         rxq->pool[i].page = NULL;
 135                 }
 136                 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
 137         }
 138 }
 139
 140 static void iwl_trans_rx_hw_init(struct iwl_trans *trans,
 141                                  struct iwl_rx_queue *rxq)
 142 {
 143         u32 rb_size;
 144         const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
 145         u32 rb_timeout = RX_RB_TIMEOUT; /* FIXME: RX_RB_TIMEOUT for all devices? */
 146
 147         if (iwlagn_mod_params.amsdu_size_8K)
 148                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
 149         else
 150                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
 151
 152         /* Stop Rx DMA */
 153         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 154
 155         /* Reset driver's Rx queue write index */
 156         iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
 157
 158         /* Tell device where to find RBD circular buffer in DRAM */
 159         iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
 160                            (u32)(rxq->bd_dma >> 8));
 161
 162         /* Tell device where in DRAM to update its Rx status */
 163         iwl_write_direct32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,
 164                            rxq->rb_stts_dma >> 4);
 165
 166         /* Enable Rx DMA
 167          * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
 168          *      the credit mechanism in 5000 HW RX FIFO
 169          * Direct rx interrupts to hosts
 170          * Rx buffer size 4 or 8k
 171          * RB timeout 0x10
 172          * 256 RBDs
 173          */
 174         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,
 175                            FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
 176                            FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
 177                            FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
 178                            FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
 179                            rb_size|
 180                            (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
 181                            (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
 182
 183         /* Set interrupt coalescing timer to default (2048 usecs) */
 184         iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
 185 }
 186
 187 static int iwl_rx_init(struct iwl_trans *trans)
 188 {
 189         struct iwl_trans_pcie *trans_pcie =
 190                 IWL_TRANS_GET_PCIE_TRANS(trans);
 191         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 192
 193         int i, err;
 194         unsigned long flags;
 195
 196         if (!rxq->bd) {
 197                 err = iwl_trans_rx_alloc(trans);
 198                 if (err)
 199                         return err;
 200         }
 201
 202         spin_lock_irqsave(&rxq->lock, flags);
 203         INIT_LIST_HEAD(&rxq->rx_free);
 204         INIT_LIST_HEAD(&rxq->rx_used);
 205
 206         iwl_trans_rxq_free_rx_bufs(trans);
 207
 208         for (i = 0; i < RX_QUEUE_SIZE; i++)
 209                 rxq->queue[i] = NULL;
 210
 211         /* Set us so that we have processed and used all buffers, but have
 212          * not restocked the Rx queue with fresh buffers */
 213         rxq->read = rxq->write = 0;
 214         rxq->write_actual = 0;
 215         rxq->free_count = 0;
 216         spin_unlock_irqrestore(&rxq->lock, flags);
 217
 218         iwlagn_rx_replenish(trans);
 219
 220         iwl_trans_rx_hw_init(trans, rxq);
 221
 222         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 223         rxq->need_update = 1;
 224         iwl_rx_queue_update_write_ptr(trans, rxq);
 225         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 226
 227         return 0;
 228 }
 229
 230 static void iwl_trans_pcie_rx_free(struct iwl_trans *trans)
 231 {
 232         struct iwl_trans_pcie *trans_pcie =
 233                 IWL_TRANS_GET_PCIE_TRANS(trans);
 234         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 235
 236         unsigned long flags;
 237
 238         /*if rxq->bd is NULL, it means that nothing has been allocated,
 239          * exit now */
 240         if (!rxq->bd) {
 241                 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
 242                 return;
 243         }
 244
 245         spin_lock_irqsave(&rxq->lock, flags);
 246         iwl_trans_rxq_free_rx_bufs(trans);
 247         spin_unlock_irqrestore(&rxq->lock, flags);
 248
 249         dma_free_coherent(trans->dev, sizeof(__le32) * RX_QUEUE_SIZE,
 250                           rxq->bd, rxq->bd_dma);
 251         memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
 252         rxq->bd = NULL;
 253
 254         if (rxq->rb_stts)
 255                 dma_free_coherent(trans->dev,
 256                                   sizeof(struct iwl_rb_status),
 257                                   rxq->rb_stts, rxq->rb_stts_dma);
 258         else
 259                 IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n");
 260         memset(&rxq->rb_stts_dma, 0, sizeof(rxq->rb_stts_dma));
 261         rxq->rb_stts = NULL;
 262 }
 263
 264 static int iwl_trans_rx_stop(struct iwl_trans *trans)
 265 {
 266
 267         /* stop Rx DMA */
 268         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 269         return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG,
 270                             FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
 271 }
 272
 273 static inline int iwlagn_alloc_dma_ptr(struct iwl_trans *trans,
 274                                     struct iwl_dma_ptr *ptr, size_t size)
 275 {
 276         if (WARN_ON(ptr->addr))
 277                 return -EINVAL;
 278
 279         ptr->addr = dma_alloc_coherent(trans->dev, size,
 280                                        &ptr->dma, GFP_KERNEL);
 281         if (!ptr->addr)
 282                 return -ENOMEM;
 283         ptr->size = size;
 284         return 0;
 285 }
 286
 287 static inline void iwlagn_free_dma_ptr(struct iwl_trans *trans,
 288                                     struct iwl_dma_ptr *ptr)
 289 {
 290         if (unlikely(!ptr->addr))
 291                 return;
 292
 293         dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
 294         memset(ptr, 0, sizeof(*ptr));
 295 }
 296
 297 static int iwl_trans_txq_alloc(struct iwl_trans *trans,
 298                                 struct iwl_tx_queue *txq, int slots_num,
 299                                 u32 txq_id)
 300 {
 301         size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
 302         int i;
 303
 304         if (WARN_ON(txq->meta || txq->cmd || txq->skbs || txq->tfds))
 305                 return -EINVAL;
 306
 307         txq->q.n_window = slots_num;
 308
 309         txq->meta = kcalloc(slots_num, sizeof(txq->meta[0]), GFP_KERNEL);
 310         txq->cmd = kcalloc(slots_num, sizeof(txq->cmd[0]), GFP_KERNEL);
 311
 312         if (!txq->meta || !txq->cmd)
 313                 goto error;
 314
 315         if (txq_id == trans->shrd->cmd_queue)
 316                 for (i = 0; i < slots_num; i++) {
 317                         txq->cmd[i] = kmalloc(sizeof(struct iwl_device_cmd),
 318                                                 GFP_KERNEL);
 319                         if (!txq->cmd[i])
 320                                 goto error;
 321                 }
 322
 323         /* Alloc driver data array and TFD circular buffer */
 324         /* Driver private data, only for Tx (not command) queues,
 325          * not shared with device. */
 326         if (txq_id != trans->shrd->cmd_queue) {
 327                 txq->skbs = kcalloc(TFD_QUEUE_SIZE_MAX, sizeof(txq->skbs[0]),
 328                                     GFP_KERNEL);
 329                 if (!txq->skbs) {
 330                         IWL_ERR(trans, "kmalloc for auxiliary BD "
 331                                   "structures failed\n");
 332                         goto error;
 333                 }
 334         } else {
 335                 txq->skbs = NULL;
 336         }
 337
 338         /* Circular buffer of transmit frame descriptors (TFDs),
 339          * shared with device */
 340         txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
 341                                        &txq->q.dma_addr, GFP_KERNEL);
 342         if (!txq->tfds) {
 343                 IWL_ERR(trans, "dma_alloc_coherent(%zd) failed\n", tfd_sz);
 344                 goto error;
 345         }
 346         txq->q.id = txq_id;
 347
 348         return 0;
 349 error:
 350         kfree(txq->skbs);
 351         txq->skbs = NULL;
 352         /* since txq->cmd has been zeroed,
 353          * all non allocated cmd[i] will be NULL */
 354         if (txq->cmd && txq_id == trans->shrd->cmd_queue)
 355                 for (i = 0; i < slots_num; i++)
 356                         kfree(txq->cmd[i]);
 357         kfree(txq->meta);
 358         kfree(txq->cmd);
 359         txq->meta = NULL;
 360         txq->cmd = NULL;
 361
 362         return -ENOMEM;
 363
 364 }
 365
 366 static int iwl_trans_txq_init(struct iwl_trans *trans, struct iwl_tx_queue *txq,
 367                       int slots_num, u32 txq_id)
 368 {
 369         int ret;
 370
 371         txq->need_update = 0;
 372         memset(txq->meta, 0, sizeof(txq->meta[0]) * slots_num);
 373
 374         /*
 375          * For the default queues 0-3, set up the swq_id
 376          * already -- all others need to get one later
 377          * (if they need one at all).
 378          */
 379         if (txq_id < 4)
 380                 iwl_set_swq_id(txq, txq_id, txq_id);
 381
 382         /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
 383          * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
 384         BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
 385
 386         /* Initialize queue's high/low-water marks, and head/tail indexes */
 387         ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num,
 388                         txq_id);
 389         if (ret)
 390                 return ret;
 391
 392         /*
 393          * Tell nic where to find circular buffer of Tx Frame Descriptors for
 394          * given Tx queue, and enable the DMA channel used for that queue.
 395          * Circular buffer (TFD queue in DRAM) physical base address */
 396         iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
 397                              txq->q.dma_addr >> 8);
 398
 399         return 0;
 400 }
 401
 402 /**
 403  * iwl_tx_queue_unmap -  Unmap any remaining DMA mappings and free skb's
 404  */
 405 static void iwl_tx_queue_unmap(struct iwl_trans *trans, int txq_id)
 406 {
 407         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 408         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
 409         struct iwl_queue *q = &txq->q;
 410         enum dma_data_direction dma_dir;
 411         unsigned long flags;
 412         spinlock_t *lock;
 413
 414         if (!q->n_bd)
 415                 return;
 416
 417         /* In the command queue, all the TBs are mapped as BIDI
 418          * so unmap them as such.
 419          */
 420         if (txq_id == trans->shrd->cmd_queue) {
 421                 dma_dir = DMA_BIDIRECTIONAL;
 422                 lock = &trans->hcmd_lock;
 423         } else {
 424                 dma_dir = DMA_TO_DEVICE;
 425                 lock = &trans->shrd->sta_lock;
 426         }
 427
 428         spin_lock_irqsave(lock, flags);
 429         while (q->write_ptr != q->read_ptr) {
 430                 /* The read_ptr needs to bound by q->n_window */
 431                 iwlagn_txq_free_tfd(trans, txq, get_cmd_index(q, q->read_ptr),
 432                                     dma_dir);
 433                 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
 434         }
 435         spin_unlock_irqrestore(lock, flags);
 436 }
 437
 438 /**
 439  * iwl_tx_queue_free - Deallocate DMA queue.
 440  * @txq: Transmit queue to deallocate.
 441  *
 442  * Empty queue by removing and destroying all BD's.
 443  * Free all buffers.
 444  * 0-fill, but do not free "txq" descriptor structure.
 445  */
 446 static void iwl_tx_queue_free(struct iwl_trans *trans, int txq_id)
 447 {
 448         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 449         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
 450         struct device *dev = trans->dev;
 451         int i;
 452         if (WARN_ON(!txq))
 453                 return;
 454
 455         iwl_tx_queue_unmap(trans, txq_id);
 456
 457         /* De-alloc array of command/tx buffers */
 458
 459         if (txq_id == trans->shrd->cmd_queue)
 460                 for (i = 0; i < txq->q.n_window; i++)
 461                         kfree(txq->cmd[i]);
 462
 463         /* De-alloc circular buffer of TFDs */
 464         if (txq->q.n_bd) {
 465                 dma_free_coherent(dev, sizeof(struct iwl_tfd) *
 466                                   txq->q.n_bd, txq->tfds, txq->q.dma_addr);
 467                 memset(&txq->q.dma_addr, 0, sizeof(txq->q.dma_addr));
 468         }
 469
 470         /* De-alloc array of per-TFD driver data */
 471         kfree(txq->skbs);
 472         txq->skbs = NULL;
 473
 474         /* deallocate arrays */
 475         kfree(txq->cmd);
 476         kfree(txq->meta);
 477         txq->cmd = NULL;
 478         txq->meta = NULL;
 479
 480         /* 0-fill queue descriptor structure */
 481         memset(txq, 0, sizeof(*txq));
 482 }
 483
 484 /**
 485  * iwl_trans_tx_free - Free TXQ Context
 486  *
 487  * Destroy all TX DMA queues and structures
 488  */
 489 static void iwl_trans_pcie_tx_free(struct iwl_trans *trans)
 490 {
 491         int txq_id;
 492         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 493
 494         /* Tx queues */
 495         if (trans_pcie->txq) {
 496                 for (txq_id = 0;
 497                      txq_id < hw_params(trans).max_txq_num; txq_id++)
 498                         iwl_tx_queue_free(trans, txq_id);
 499         }
 500
 501         kfree(trans_pcie->txq);
 502         trans_pcie->txq = NULL;
 503
 504         iwlagn_free_dma_ptr(trans, &trans_pcie->kw);
 505
 506         iwlagn_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
 507 }
 508
 509 /**
 510  * iwl_trans_tx_alloc - allocate TX context
 511  * Allocate all Tx DMA structures and initialize them
 512  *
 513  * @param priv
 514  * @return error code
 515  */
 516 static int iwl_trans_tx_alloc(struct iwl_trans *trans)
 517 {
 518         int ret;
 519         int txq_id, slots_num;
 520         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 521
 522         u16 scd_bc_tbls_size = hw_params(trans).max_txq_num *
 523                         sizeof(struct iwlagn_scd_bc_tbl);
 524
 525         /*It is not allowed to alloc twice, so warn when this happens.
 526          * We cannot rely on the previous allocation, so free and fail */
 527         if (WARN_ON(trans_pcie->txq)) {
 528                 ret = -EINVAL;
 529                 goto error;
 530         }
 531
 532         ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
 533                                    scd_bc_tbls_size);
 534         if (ret) {
 535                 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
 536                 goto error;
 537         }
 538
 539         /* Alloc keep-warm buffer */
 540         ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
 541         if (ret) {
 542                 IWL_ERR(trans, "Keep Warm allocation failed\n");
 543                 goto error;
 544         }
 545
 546         trans_pcie->txq = kcalloc(hw_params(trans).max_txq_num,
 547                                   sizeof(struct iwl_tx_queue), GFP_KERNEL);
 548         if (!trans_pcie->txq) {
 549                 IWL_ERR(trans, "Not enough memory for txq\n");
 550                 ret = ENOMEM;
 551                 goto error;
 552         }
 553
 554         /* Alloc and init all Tx queues, including the command queue (#4/#9) */
 555         for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) {
 556                 slots_num = (txq_id == trans->shrd->cmd_queue) ?
 557                                         TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
 558                 ret = iwl_trans_txq_alloc(trans, &trans_pcie->txq[txq_id],
 559                                           slots_num, txq_id);
 560                 if (ret) {
 561                         IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
 562                         goto error;
 563                 }
 564         }
 565
 566         return 0;
 567
 568 error:
 569         iwl_trans_pcie_tx_free(trans);
 570
 571         return ret;
 572 }
 573 static int iwl_tx_init(struct iwl_trans *trans)
 574 {
 575         int ret;
 576         int txq_id, slots_num;
 577         unsigned long flags;
 578         bool alloc = false;
 579         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 580
 581         if (!trans_pcie->txq) {
 582                 ret = iwl_trans_tx_alloc(trans);
 583                 if (ret)
 584                         goto error;
 585                 alloc = true;
 586         }
 587
 588         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 589
 590         /* Turn off all Tx DMA fifos */
 591         iwl_write_prph(trans, SCD_TXFACT, 0);
 592
 593         /* Tell NIC where to find the "keep warm" buffer */
 594         iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
 595                            trans_pcie->kw.dma >> 4);
 596
 597         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 598
 599         /* Alloc and init all Tx queues, including the command queue (#4/#9) */
 600         for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) {
 601                 slots_num = (txq_id == trans->shrd->cmd_queue) ?
 602                                         TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
 603                 ret = iwl_trans_txq_init(trans, &trans_pcie->txq[txq_id],
 604                                          slots_num, txq_id);
 605                 if (ret) {
 606                         IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
 607                         goto error;
 608                 }
 609         }
 610
 611         return 0;
 612 error:
 613         /*Upon error, free only if we allocated something */
 614         if (alloc)
 615                 iwl_trans_pcie_tx_free(trans);
 616         return ret;
 617 }
 618
 619 static void iwl_set_pwr_vmain(struct iwl_trans *trans)
 620 {
 621 /*
 622  * (for documentation purposes)
 623  * to set power to V_AUX, do:
 624
 625                 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
 626                         iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 627                                                APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 628                                                ~APMG_PS_CTRL_MSK_PWR_SRC);
 629  */
 630
 631         iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 632                                APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 633                                ~APMG_PS_CTRL_MSK_PWR_SRC);
 634 }
 635
 636 /* PCI registers */
 637 #define PCI_CFG_RETRY_TIMEOUT   0x041
 638 #define PCI_CFG_LINK_CTRL_VAL_L0S_EN    0x01
 639 #define PCI_CFG_LINK_CTRL_VAL_L1_EN     0x02
 640
 641 static u16 iwl_pciexp_link_ctrl(struct iwl_trans *trans)
 642 {
 643         int pos;
 644         u16 pci_lnk_ctl;
 645         struct iwl_trans_pcie *trans_pcie =
 646                 IWL_TRANS_GET_PCIE_TRANS(trans);
 647
 648         struct pci_dev *pci_dev = trans_pcie->pci_dev;
 649
 650         pos = pci_pcie_cap(pci_dev);
 651         pci_read_config_word(pci_dev, pos + PCI_EXP_LNKCTL, &pci_lnk_ctl);
 652         return pci_lnk_ctl;
 653 }
 654
 655 static void iwl_apm_config(struct iwl_trans *trans)
 656 {
 657         /*
 658          * HW bug W/A for instability in PCIe bus L0S->L1 transition.
 659          * Check if BIOS (or OS) enabled L1-ASPM on this device.
 660          * If so (likely), disable L0S, so device moves directly L0->L1;
 661          *    costs negligible amount of power savings.
 662          * If not (unlikely), enable L0S, so there is at least some
 663          *    power savings, even without L1.
 664          */
 665         u16 lctl = iwl_pciexp_link_ctrl(trans);
 666
 667         if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
 668                                 PCI_CFG_LINK_CTRL_VAL_L1_EN) {
 669                 /* L1-ASPM enabled; disable(!) L0S */
 670                 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 671                 dev_printk(KERN_INFO, trans->dev,
 672                            "L1 Enabled; Disabling L0S\n");
 673         } else {
 674                 /* L1-ASPM disabled; enable(!) L0S */
 675                 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 676                 dev_printk(KERN_INFO, trans->dev,
 677                            "L1 Disabled; Enabling L0S\n");
 678         }
 679         trans->pm_support = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN);
 680 }
 681
 682 /*
 683  * Start up NIC's basic functionality after it has been reset
 684  * (e.g. after platform boot, or shutdown via iwl_apm_stop())
 685  * NOTE:  This does not load uCode nor start the embedded processor
 686  */
 687 static int iwl_apm_init(struct iwl_trans *trans)
 688 {
 689         int ret = 0;
 690         IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
 691
 692         /*
 693          * Use "set_bit" below rather than "write", to preserve any hardware
 694          * bits already set by default after reset.
 695          */
 696
 697         /* Disable L0S exit timer (platform NMI Work/Around) */
 698         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 699                           CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 700
 701         /*
 702          * Disable L0s without affecting L1;
 703          *  don't wait for ICH L0s (ICH bug W/A)
 704          */
 705         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 706                           CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 707
 708         /* Set FH wait threshold to maximum (HW error during stress W/A) */
 709         iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 710
 711         /*
 712          * Enable HAP INTA (interrupt from management bus) to
 713          * wake device's PCI Express link L1a -> L0s
 714          */
 715         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 716                                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 717
 718         iwl_apm_config(trans);
 719
 720         /* Configure analog phase-lock-loop before activating to D0A */
 721         if (cfg(trans)->base_params->pll_cfg_val)
 722                 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
 723                             cfg(trans)->base_params->pll_cfg_val);
 724
 725         /*
 726          * Set "initialization complete" bit to move adapter from
 727          * D0U* --> D0A* (powered-up active) state.
 728          */
 729         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 730
 731         /*
 732          * Wait for clock stabilization; once stabilized, access to
 733          * device-internal resources is supported, e.g. iwl_write_prph()
 734          * and accesses to uCode SRAM.
 735          */
 736         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 737                         CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 738                         CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 739         if (ret < 0) {
 740                 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
 741                 goto out;
 742         }
 743
 744         /*
 745          * Enable DMA clock and wait for it to stabilize.
 746          *
 747          * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
 748          * do not disable clocks.  This preserves any hardware bits already
 749          * set by default in "CLK_CTRL_REG" after reset.
 750          */
 751         iwl_write_prph(trans, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
 752         udelay(20);
 753
 754         /* Disable L1-Active */
 755         iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 756                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 757
 758         set_bit(STATUS_DEVICE_ENABLED, &trans->shrd->status);
 759
 760 out:
 761         return ret;
 762 }
 763
 764 static int iwl_apm_stop_master(struct iwl_trans *trans)
 765 {
 766         int ret = 0;
 767
 768         /* stop device's busmaster DMA activity */
 769         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
 770
 771         ret = iwl_poll_bit(trans, CSR_RESET,
 772                         CSR_RESET_REG_FLAG_MASTER_DISABLED,
 773                         CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
 774         if (ret)
 775                 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
 776
 777         IWL_DEBUG_INFO(trans, "stop master\n");
 778
 779         return ret;
 780 }
 781
 782 static void iwl_apm_stop(struct iwl_trans *trans)
 783 {
 784         IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
 785
 786         clear_bit(STATUS_DEVICE_ENABLED, &trans->shrd->status);
 787
 788         /* Stop device's DMA activity */
 789         iwl_apm_stop_master(trans);
 790
 791         /* Reset the entire device */
 792         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 793
 794         udelay(10);
 795
 796         /*
 797          * Clear "initialization complete" bit to move adapter from
 798          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 799          */
 800         iwl_clear_bit(trans, CSR_GP_CNTRL,
 801                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 802 }
 803
 804 static int iwl_nic_init(struct iwl_trans *trans)
 805 {
 806         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 807         unsigned long flags;
 808
 809         /* nic_init */
 810         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 811         iwl_apm_init(trans);
 812
 813         /* Set interrupt coalescing calibration timer to default (512 usecs) */
 814         iwl_write8(trans, CSR_INT_COALESCING,
 815                 IWL_HOST_INT_CALIB_TIMEOUT_DEF);
 816
 817         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 818
 819         iwl_set_pwr_vmain(trans);
 820
 821         iwl_nic_config(priv(trans));
 822
 823 #ifndef CONFIG_IWLWIFI_IDI
 824         /* Allocate the RX queue, or reset if it is already allocated */
 825         iwl_rx_init(trans);
 826 #endif
 827
 828         /* Allocate or reset and init all Tx and Command queues */
 829         if (iwl_tx_init(trans))
 830                 return -ENOMEM;
 831
 832         if (hw_params(trans).shadow_reg_enable) {
 833                 /* enable shadow regs in HW */
 834                 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL,
 835                         0x800FFFFF);
 836         }
 837
 838         set_bit(STATUS_INIT, &trans->shrd->status);
 839
 840         return 0;
 841 }
 842
 843 #define HW_READY_TIMEOUT (50)
 844
 845 /* Note: returns poll_bit return value, which is >= 0 if success */
 846 static int iwl_set_hw_ready(struct iwl_trans *trans)
 847 {
 848         int ret;
 849
 850         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 851                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
 852
 853         /* See if we got it */
 854         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 855                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 856                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 857                                 HW_READY_TIMEOUT);
 858
 859         IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
 860         return ret;
 861 }
 862
 863 /* Note: returns standard 0/-ERROR code */
 864 static int iwl_prepare_card_hw(struct iwl_trans *trans)
 865 {
 866         int ret;
 867
 868         IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
 869
 870         ret = iwl_set_hw_ready(trans);
 871         /* If the card is ready, exit 0 */
 872         if (ret >= 0)
 873                 return 0;
 874
 875         /* If HW is not ready, prepare the conditions to check again */
 876         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 877                         CSR_HW_IF_CONFIG_REG_PREPARE);
 878
 879         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 880                         ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
 881                         CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
 882
 883         if (ret < 0)
 884                 return ret;
 885
 886         /* HW should be ready by now, check again. */
 887         ret = iwl_set_hw_ready(trans);
 888         if (ret >= 0)
 889                 return 0;
 890         return ret;
 891 }
 892
 893 #define IWL_AC_UNSET -1
 894
 895 struct queue_to_fifo_ac {
 896         s8 fifo, ac;
 897 };
 898
 899 static const struct queue_to_fifo_ac iwlagn_default_queue_to_tx_fifo[] = {
 900         { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
 901         { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
 902         { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
 903         { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
 904         { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
 905         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 906         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 907         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 908         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 909         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 910         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 911 };
 912
 913 static const struct queue_to_fifo_ac iwlagn_ipan_queue_to_tx_fifo[] = {
 914         { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
 915         { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
 916         { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
 917         { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
 918         { IWL_TX_FIFO_BK_IPAN, IEEE80211_AC_BK, },
 919         { IWL_TX_FIFO_BE_IPAN, IEEE80211_AC_BE, },
 920         { IWL_TX_FIFO_VI_IPAN, IEEE80211_AC_VI, },
 921         { IWL_TX_FIFO_VO_IPAN, IEEE80211_AC_VO, },
 922         { IWL_TX_FIFO_BE_IPAN, 2, },
 923         { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
 924         { IWL_TX_FIFO_AUX, IWL_AC_UNSET, },
 925 };
 926
 927 static const u8 iwlagn_bss_ac_to_fifo[] = {
 928         IWL_TX_FIFO_VO,
 929         IWL_TX_FIFO_VI,
 930         IWL_TX_FIFO_BE,
 931         IWL_TX_FIFO_BK,
 932 };
 933 static const u8 iwlagn_bss_ac_to_queue[] = {
 934         0, 1, 2, 3,
 935 };
 936 static const u8 iwlagn_pan_ac_to_fifo[] = {
 937         IWL_TX_FIFO_VO_IPAN,
 938         IWL_TX_FIFO_VI_IPAN,
 939         IWL_TX_FIFO_BE_IPAN,
 940         IWL_TX_FIFO_BK_IPAN,
 941 };
 942 static const u8 iwlagn_pan_ac_to_queue[] = {
 943         7, 6, 5, 4,
 944 };
 945
 946 /*
 947  * ucode
 948  */
 949 static int iwl_load_section(struct iwl_trans *trans, const char *name,
 950                                 struct fw_desc *image, u32 dst_addr)
 951 {
 952         dma_addr_t phy_addr = image->p_addr;
 953         u32 byte_cnt = image->len;
 954         int ret;
 955
 956         trans->ucode_write_complete = 0;
 957
 958         iwl_write_direct32(trans,
 959                 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 960                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 961
 962         iwl_write_direct32(trans,
 963                 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
 964
 965         iwl_write_direct32(trans,
 966                 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 967                 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 968
 969         iwl_write_direct32(trans,
 970                 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 971                 (iwl_get_dma_hi_addr(phy_addr)
 972                         << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 973
 974         iwl_write_direct32(trans,
 975                 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 976                 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
 977                 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
 978                 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 979
 980         iwl_write_direct32(trans,
 981                 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 982                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE       |
 983                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE    |
 984                 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 985
 986         IWL_DEBUG_FW(trans, "%s uCode section being loaded...\n", name);
 987         ret = wait_event_timeout(trans->shrd->wait_command_queue,
 988                                  trans->ucode_write_complete, 5 * HZ);
 989         if (!ret) {
 990                 IWL_ERR(trans, "Could not load the %s uCode section\n",
 991                         name);
 992                 return -ETIMEDOUT;
 993         }
 994
 995         return 0;
 996 }
 997
 998 static int iwl_load_given_ucode(struct iwl_trans *trans, struct fw_img *image)
 999 {
1000         int ret = 0;
1001
1002         ret = iwl_load_section(trans, "INST", &image->code,
1003                                    IWLAGN_RTC_INST_LOWER_BOUND);
1004         if (ret)
1005                 return ret;
1006
1007         ret = iwl_load_section(trans, "DATA", &image->data,
1008                                     IWLAGN_RTC_DATA_LOWER_BOUND);
1009         if (ret)
1010                 return ret;
1011
1012         /* Remove all resets to allow NIC to operate */
1013         iwl_write32(trans, CSR_RESET, 0);
1014
1015         return 0;
1016 }
1017
1018 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, struct fw_img *fw)
1019 {
1020         int ret;
1021         struct iwl_trans_pcie *trans_pcie =
1022                 IWL_TRANS_GET_PCIE_TRANS(trans);
1023
1024         trans->shrd->ucode_owner = IWL_OWNERSHIP_DRIVER;
1025         trans_pcie->ac_to_queue[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_queue;
1026         trans_pcie->ac_to_queue[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_queue;
1027
1028         trans_pcie->ac_to_fifo[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_fifo;
1029         trans_pcie->ac_to_fifo[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_fifo;
1030
1031         trans_pcie->mcast_queue[IWL_RXON_CTX_BSS] = 0;
1032         trans_pcie->mcast_queue[IWL_RXON_CTX_PAN] = IWL_IPAN_MCAST_QUEUE;
1033
1034         if ((hw_params(trans).sku & EEPROM_SKU_CAP_AMT_ENABLE) &&
1035              iwl_prepare_card_hw(trans)) {
1036                 IWL_WARN(trans, "Exit HW not ready\n");
1037                 return -EIO;
1038         }
1039
1040         /* If platform's RF_KILL switch is NOT set to KILL */
1041         if (iwl_read32(trans, CSR_GP_CNTRL) &
1042                         CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
1043                 clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1044         else
1045                 set_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1046
1047         if (iwl_is_rfkill(trans->shrd)) {
1048                 iwl_set_hw_rfkill_state(priv(trans), true);
1049                 iwl_enable_interrupts(trans);
1050                 return -ERFKILL;
1051         }
1052
1053         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1054
1055         ret = iwl_nic_init(trans);
1056         if (ret) {
1057                 IWL_ERR(trans, "Unable to init nic\n");
1058                 return ret;
1059         }
1060
1061         /* make sure rfkill handshake bits are cleared */
1062         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1063         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1064                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1065
1066         /* clear (again), then enable host interrupts */
1067         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1068         iwl_enable_interrupts(trans);
1069
1070         /* really make sure rfkill handshake bits are cleared */
1071         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1072         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1073
1074         /* Load the given image to the HW */
1075         iwl_load_given_ucode(trans, fw);
1076
1077         return 0;
1078 }
1079
1080 /*
1081  * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
1082  * must be called under the irq lock and with MAC access
1083  */
1084 static void iwl_trans_txq_set_sched(struct iwl_trans *trans, u32 mask)
1085 {
1086         struct iwl_trans_pcie __maybe_unused *trans_pcie =
1087                 IWL_TRANS_GET_PCIE_TRANS(trans);
1088
1089         lockdep_assert_held(&trans_pcie->irq_lock);
1090
1091         iwl_write_prph(trans, SCD_TXFACT, mask);
1092 }
1093
1094 static void iwl_tx_start(struct iwl_trans *trans)
1095 {
1096         const struct queue_to_fifo_ac *queue_to_fifo;
1097         struct iwl_trans_pcie *trans_pcie =
1098                 IWL_TRANS_GET_PCIE_TRANS(trans);
1099         u32 a;
1100         unsigned long flags;
1101         int i, chan;
1102         u32 reg_val;
1103
1104         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1105
1106         trans_pcie->scd_base_addr =
1107                 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
1108         a = trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND;
1109         /* reset conext data memory */
1110         for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND;
1111                 a += 4)
1112                 iwl_write_targ_mem(trans, a, 0);
1113         /* reset tx status memory */
1114         for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND;
1115                 a += 4)
1116                 iwl_write_targ_mem(trans, a, 0);
1117         for (; a < trans_pcie->scd_base_addr +
1118                SCD_TRANS_TBL_OFFSET_QUEUE(hw_params(trans).max_txq_num);
1119                a += 4)
1120                 iwl_write_targ_mem(trans, a, 0);
1121
1122         iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
1123                        trans_pcie->scd_bc_tbls.dma >> 10);
1124
1125         /* Enable DMA channel */
1126         for (chan = 0; chan < FH_TCSR_CHNL_NUM ; chan++)
1127                 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
1128                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
1129                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
1130
1131         /* Update FH chicken bits */
1132         reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
1133         iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
1134                            reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
1135
1136         iwl_write_prph(trans, SCD_QUEUECHAIN_SEL,
1137                 SCD_QUEUECHAIN_SEL_ALL(trans));
1138         iwl_write_prph(trans, SCD_AGGR_SEL, 0);
1139
1140         /* initiate the queues */
1141         for (i = 0; i < hw_params(trans).max_txq_num; i++) {
1142                 iwl_write_prph(trans, SCD_QUEUE_RDPTR(i), 0);
1143                 iwl_write_direct32(trans, HBUS_TARG_WRPTR, 0 | (i << 8));
1144                 iwl_write_targ_mem(trans, trans_pcie->scd_base_addr +
1145                                 SCD_CONTEXT_QUEUE_OFFSET(i), 0);
1146                 iwl_write_targ_mem(trans, trans_pcie->scd_base_addr +
1147                                 SCD_CONTEXT_QUEUE_OFFSET(i) +
1148                                 sizeof(u32),
1149                                 ((SCD_WIN_SIZE <<
1150                                 SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1151                                 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1152                                 ((SCD_FRAME_LIMIT <<
1153                                 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1154                                 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1155         }
1156
1157         iwl_write_prph(trans, SCD_INTERRUPT_MASK,
1158                         IWL_MASK(0, hw_params(trans).max_txq_num));
1159
1160         /* Activate all Tx DMA/FIFO channels */
1161         iwl_trans_txq_set_sched(trans, IWL_MASK(0, 7));
1162
1163         /* map queues to FIFOs */
1164         if (trans->shrd->valid_contexts != BIT(IWL_RXON_CTX_BSS))
1165                 queue_to_fifo = iwlagn_ipan_queue_to_tx_fifo;
1166         else
1167                 queue_to_fifo = iwlagn_default_queue_to_tx_fifo;
1168
1169         iwl_trans_set_wr_ptrs(trans, trans->shrd->cmd_queue, 0);
1170
1171         /* make sure all queue are not stopped */
1172         memset(&trans_pcie->queue_stopped[0], 0,
1173                 sizeof(trans_pcie->queue_stopped));
1174         for (i = 0; i < 4; i++)
1175                 atomic_set(&trans_pcie->queue_stop_count[i], 0);
1176
1177         /* reset to 0 to enable all the queue first */
1178         trans_pcie->txq_ctx_active_msk = 0;
1179
1180         BUILD_BUG_ON(ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo) <
1181                                                 IWLAGN_FIRST_AMPDU_QUEUE);
1182         BUILD_BUG_ON(ARRAY_SIZE(iwlagn_ipan_queue_to_tx_fifo) <
1183                                                 IWLAGN_FIRST_AMPDU_QUEUE);
1184
1185         for (i = 0; i < IWLAGN_FIRST_AMPDU_QUEUE; i++) {
1186                 int fifo = queue_to_fifo[i].fifo;
1187                 int ac = queue_to_fifo[i].ac;
1188
1189                 iwl_txq_ctx_activate(trans_pcie, i);
1190
1191                 if (fifo == IWL_TX_FIFO_UNUSED)
1192                         continue;
1193
1194                 if (ac != IWL_AC_UNSET)
1195                         iwl_set_swq_id(&trans_pcie->txq[i], ac, i);
1196                 iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[i],
1197                                               fifo, 0);
1198         }
1199
1200         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1201
1202         /* Enable L1-Active */
1203         iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
1204                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1205 }
1206
1207 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans)
1208 {
1209         iwl_reset_ict(trans);
1210         iwl_tx_start(trans);
1211 }
1212
1213 /**
1214  * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
1215  */
1216 static int iwl_trans_tx_stop(struct iwl_trans *trans)
1217 {
1218         int ch, txq_id;
1219         unsigned long flags;
1220         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1221
1222         /* Turn off all Tx DMA fifos */
1223         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1224
1225         iwl_trans_txq_set_sched(trans, 0);
1226
1227         /* Stop each Tx DMA channel, and wait for it to be idle */
1228         for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
1229                 iwl_write_direct32(trans,
1230                                    FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
1231                 if (iwl_poll_direct_bit(trans, FH_TSSR_TX_STATUS_REG,
1232                                     FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
1233                                     1000))
1234                         IWL_ERR(trans, "Failing on timeout while stopping"
1235                             " DMA channel %d [0x%08x]", ch,
1236                             iwl_read_direct32(trans,
1237                                               FH_TSSR_TX_STATUS_REG));
1238         }
1239         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1240
1241         if (!trans_pcie->txq) {
1242                 IWL_WARN(trans, "Stopping tx queues that aren't allocated...");
1243                 return 0;
1244         }
1245
1246         /* Unmap DMA from host system and free skb's */
1247         for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++)
1248                 iwl_tx_queue_unmap(trans, txq_id);
1249
1250         return 0;
1251 }
1252
1253 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
1254 {
1255         unsigned long flags;
1256         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1257
1258         /* tell the device to stop sending interrupts */
1259         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1260         iwl_disable_interrupts(trans);
1261         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1262
1263         /* device going down, Stop using ICT table */
1264         iwl_disable_ict(trans);
1265
1266         /*
1267          * If a HW restart happens during firmware loading,
1268          * then the firmware loading might call this function
1269          * and later it might be called again due to the
1270          * restart. So don't process again if the device is
1271          * already dead.
1272          */
1273         if (test_bit(STATUS_DEVICE_ENABLED, &trans->shrd->status)) {
1274                 iwl_trans_tx_stop(trans);
1275 #ifndef CONFIG_IWLWIFI_IDI
1276                 iwl_trans_rx_stop(trans);
1277 #endif
1278                 /* Power-down device's busmaster DMA clocks */
1279                 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1280                                APMG_CLK_VAL_DMA_CLK_RQT);
1281                 udelay(5);
1282         }
1283
1284         /* Make sure (redundant) we've released our request to stay awake */
1285         iwl_clear_bit(trans, CSR_GP_CNTRL,
1286                         CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1287
1288         /* Stop the device, and put it in low power state */
1289         iwl_apm_stop(trans);
1290
1291         /* Upon stop, the APM issues an interrupt if HW RF kill is set.
1292          * Clean again the interrupt here
1293          */
1294         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1295         iwl_disable_interrupts(trans);
1296         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1297
1298         /* wait to make sure we flush pending tasklet*/
1299         synchronize_irq(trans->irq);
1300         tasklet_kill(&trans_pcie->irq_tasklet);
1301
1302         cancel_work_sync(&trans_pcie->rx_replenish);
1303
1304         /* stop and reset the on-board processor */
1305         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
1306 }
1307
1308 static int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
1309                 struct iwl_device_cmd *dev_cmd, enum iwl_rxon_context_id ctx,
1310                 u8 sta_id, u8 tid)
1311 {
1312         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1313         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1314         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1315         struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *) dev_cmd->payload;
1316         struct iwl_cmd_meta *out_meta;
1317         struct iwl_tx_queue *txq;
1318         struct iwl_queue *q;
1319
1320         dma_addr_t phys_addr = 0;
1321         dma_addr_t txcmd_phys;
1322         dma_addr_t scratch_phys;
1323         u16 len, firstlen, secondlen;
1324         u8 wait_write_ptr = 0;
1325         u8 txq_id;
1326         bool is_agg = false;
1327         __le16 fc = hdr->frame_control;
1328         u8 hdr_len = ieee80211_hdrlen(fc);
1329         u16 __maybe_unused wifi_seq;
1330
1331         /*
1332          * Send this frame after DTIM -- there's a special queue
1333          * reserved for this for contexts that support AP mode.
1334          */
1335         if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
1336                 txq_id = trans_pcie->mcast_queue[ctx];
1337
1338                 /*
1339                  * The microcode will clear the more data
1340                  * bit in the last frame it transmits.
1341                  */
1342                 hdr->frame_control |=
1343                         cpu_to_le16(IEEE80211_FCTL_MOREDATA);
1344         } else if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN)
1345                 txq_id = IWL_AUX_QUEUE;
1346         else
1347                 txq_id =
1348                     trans_pcie->ac_to_queue[ctx][skb_get_queue_mapping(skb)];
1349
1350         /* aggregation is on for this <sta,tid> */
1351         if (info->flags & IEEE80211_TX_CTL_AMPDU) {
1352                 WARN_ON(tid >= IWL_MAX_TID_COUNT);
1353                 txq_id = trans_pcie->agg_txq[sta_id][tid];
1354                 is_agg = true;
1355         }
1356
1357         txq = &trans_pcie->txq[txq_id];
1358         q = &txq->q;
1359
1360         /* In AGG mode, the index in the ring must correspond to the WiFi
1361          * sequence number. This is a HW requirements to help the SCD to parse
1362          * the BA.
1363          * Check here that the packets are in the right place on the ring.
1364          */
1365 #ifdef CONFIG_IWLWIFI_DEBUG
1366         wifi_seq = SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
1367         WARN_ONCE(is_agg && ((wifi_seq & 0xff) != q->write_ptr),
1368                   "Q: %d WiFi Seq %d tfdNum %d",
1369                   txq_id, wifi_seq, q->write_ptr);
1370 #endif
1371
1372         /* Set up driver data for this TFD */
1373         txq->skbs[q->write_ptr] = skb;
1374         txq->cmd[q->write_ptr] = dev_cmd;
1375
1376         dev_cmd->hdr.cmd = REPLY_TX;
1377         dev_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
1378                                 INDEX_TO_SEQ(q->write_ptr)));
1379
1380         /* Set up first empty entry in queue's array of Tx/cmd buffers */
1381         out_meta = &txq->meta[q->write_ptr];
1382
1383         /*
1384          * Use the first empty entry in this queue's command buffer array
1385          * to contain the Tx command and MAC header concatenated together
1386          * (payload data will be in another buffer).
1387          * Size of this varies, due to varying MAC header length.
1388          * If end is not dword aligned, we'll have 2 extra bytes at the end
1389          * of the MAC header (device reads on dword boundaries).
1390          * We'll tell device about this padding later.
1391          */
1392         len = sizeof(struct iwl_tx_cmd) +
1393                 sizeof(struct iwl_cmd_header) + hdr_len;
1394         firstlen = (len + 3) & ~3;
1395
1396         /* Tell NIC about any 2-byte padding after MAC header */
1397         if (firstlen != len)
1398                 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1399
1400         /* Physical address of this Tx command's header (not MAC header!),
1401          * within command buffer array. */
1402         txcmd_phys = dma_map_single(trans->dev,
1403                                     &dev_cmd->hdr, firstlen,
1404                                     DMA_BIDIRECTIONAL);
1405         if (unlikely(dma_mapping_error(trans->dev, txcmd_phys)))
1406                 return -1;
1407         dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
1408         dma_unmap_len_set(out_meta, len, firstlen);
1409
1410         if (!ieee80211_has_morefrags(fc)) {
1411                 txq->need_update = 1;
1412         } else {
1413                 wait_write_ptr = 1;
1414                 txq->need_update = 0;
1415         }
1416
1417         /* Set up TFD's 2nd entry to point directly to remainder of skb,
1418          * if any (802.11 null frames have no payload). */
1419         secondlen = skb->len - hdr_len;
1420         if (secondlen > 0) {
1421                 phys_addr = dma_map_single(trans->dev, skb->data + hdr_len,
1422                                            secondlen, DMA_TO_DEVICE);
1423                 if (unlikely(dma_mapping_error(trans->dev, phys_addr))) {
1424                         dma_unmap_single(trans->dev,
1425                                          dma_unmap_addr(out_meta, mapping),
1426                                          dma_unmap_len(out_meta, len),
1427                                          DMA_BIDIRECTIONAL);
1428                         return -1;
1429                 }
1430         }
1431
1432         /* Attach buffers to TFD */
1433         iwlagn_txq_attach_buf_to_tfd(trans, txq, txcmd_phys, firstlen, 1);
1434         if (secondlen > 0)
1435                 iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr,
1436                                              secondlen, 0);
1437
1438         scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
1439                                 offsetof(struct iwl_tx_cmd, scratch);
1440
1441         /* take back ownership of DMA buffer to enable update */
1442         dma_sync_single_for_cpu(trans->dev, txcmd_phys, firstlen,
1443                         DMA_BIDIRECTIONAL);
1444         tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1445         tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1446
1447         IWL_DEBUG_TX(trans, "sequence nr = 0X%x\n",
1448                      le16_to_cpu(dev_cmd->hdr.sequence));
1449         IWL_DEBUG_TX(trans, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
1450         iwl_print_hex_dump(trans, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
1451         iwl_print_hex_dump(trans, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
1452
1453         /* Set up entry for this TFD in Tx byte-count array */
1454         iwl_trans_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len));
1455
1456         dma_sync_single_for_device(trans->dev, txcmd_phys, firstlen,
1457                         DMA_BIDIRECTIONAL);
1458
1459         trace_iwlwifi_dev_tx(priv(trans),
1460                              &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr],
1461                              sizeof(struct iwl_tfd),
1462                              &dev_cmd->hdr, firstlen,
1463                              skb->data + hdr_len, secondlen);
1464
1465         /* Tell device the write index *just past* this latest filled TFD */
1466         q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1467         iwl_txq_update_write_ptr(trans, txq);
1468
1469         /*
1470          * At this point the frame is "transmitted" successfully
1471          * and we will get a TX status notification eventually,
1472          * regardless of the value of ret. "ret" only indicates
1473          * whether or not we should update the write pointer.
1474          */
1475         if (iwl_queue_space(q) < q->high_mark) {
1476                 if (wait_write_ptr) {
1477                         txq->need_update = 1;
1478                         iwl_txq_update_write_ptr(trans, txq);
1479                 } else {
1480                         iwl_stop_queue(trans, txq, "Queue is full");
1481                 }
1482         }
1483         return 0;
1484 }
1485
1486 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1487 {
1488         struct iwl_trans_pcie *trans_pcie =
1489                 IWL_TRANS_GET_PCIE_TRANS(trans);
1490         int err;
1491
1492         trans_pcie->inta_mask = CSR_INI_SET_MASK;
1493
1494         if (!trans_pcie->irq_requested) {
1495                 tasklet_init(&trans_pcie->irq_tasklet, (void (*)(unsigned long))
1496                         iwl_irq_tasklet, (unsigned long)trans);
1497
1498                 iwl_alloc_isr_ict(trans);
1499
1500                 err = request_irq(trans->irq, iwl_isr_ict, IRQF_SHARED,
1501                         DRV_NAME, trans);
1502                 if (err) {
1503                         IWL_ERR(trans, "Error allocating IRQ %d\n",
1504                                 trans->irq);
1505                         goto error;
1506                 }
1507
1508                 INIT_WORK(&trans_pcie->rx_replenish, iwl_bg_rx_replenish);
1509                 trans_pcie->irq_requested = true;
1510         }
1511
1512         err = iwl_prepare_card_hw(trans);
1513         if (err) {
1514                 IWL_ERR(trans, "Error while preparing HW: %d", err);
1515                 goto err_free_irq;
1516         }
1517
1518         iwl_apm_init(trans);
1519
1520         /* If platform's RF_KILL switch is NOT set to KILL */
1521         if (iwl_read32(trans,
1522                         CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
1523                 clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1524         else
1525                 set_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1526
1527         iwl_set_hw_rfkill_state(priv(trans),
1528                                 test_bit(STATUS_RF_KILL_HW,
1529                                          &trans->shrd->status));
1530
1531         return err;
1532
1533 err_free_irq:
1534         free_irq(trans->irq, trans);
1535 error:
1536         iwl_free_isr_ict(trans);
1537         tasklet_kill(&trans_pcie->irq_tasklet);
1538         return err;
1539 }
1540
1541 static void iwl_trans_pcie_stop_hw(struct iwl_trans *trans)
1542 {
1543         iwl_apm_stop(trans);
1544
1545         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1546
1547         /* Even if we stop the HW, we still want the RF kill interrupt */
1548         IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n");
1549         iwl_write32(trans, CSR_INT_MASK, CSR_INT_BIT_RF_KILL);
1550 }
1551
1552 static int iwl_trans_pcie_reclaim(struct iwl_trans *trans, int sta_id, int tid,
1553                       int txq_id, int ssn, u32 status,
1554                       struct sk_buff_head *skbs)
1555 {
1556         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1557         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
1558         /* n_bd is usually 256 => n_bd - 1 = 0xff */
1559         int tfd_num = ssn & (txq->q.n_bd - 1);
1560         int freed = 0;
1561
1562         txq->time_stamp = jiffies;
1563
1564         if (unlikely(txq_id >= IWLAGN_FIRST_AMPDU_QUEUE &&
1565                      tid != IWL_TID_NON_QOS &&
1566                      txq_id != trans_pcie->agg_txq[sta_id][tid])) {
1567                 /*
1568                  * FIXME: this is a uCode bug which need to be addressed,
1569                  * log the information and return for now.
1570                  * Since it is can possibly happen very often and in order
1571                  * not to fill the syslog, don't use IWL_ERR or IWL_WARN
1572                  */
1573                 IWL_DEBUG_TX_QUEUES(trans, "Bad queue mapping txq_id %d, "
1574                         "agg_txq[sta_id[tid] %d", txq_id,
1575                         trans_pcie->agg_txq[sta_id][tid]);
1576                 return 1;
1577         }
1578
1579         if (txq->q.read_ptr != tfd_num) {
1580                 IWL_DEBUG_TX_REPLY(trans, "[Q %d | AC %d] %d -> %d (%d)\n",
1581                                 txq_id, iwl_get_queue_ac(txq), txq->q.read_ptr,
1582                                 tfd_num, ssn);
1583                 freed = iwl_tx_queue_reclaim(trans, txq_id, tfd_num, skbs);
1584                 if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
1585                    (!txq->sched_retry ||
1586                    status != TX_STATUS_FAIL_PASSIVE_NO_RX))
1587                         iwl_wake_queue(trans, txq, "Packets reclaimed");
1588         }
1589         return 0;
1590 }
1591
1592 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1593 {
1594         iowrite8(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1595 }
1596
1597 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1598 {
1599         iowrite32(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1600 }
1601
1602 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1603 {
1604         u32 val = ioread32(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1605         return val;
1606 }
1607
1608 static void iwl_trans_pcie_free(struct iwl_trans *trans)
1609 {
1610         struct iwl_trans_pcie *trans_pcie =
1611                 IWL_TRANS_GET_PCIE_TRANS(trans);
1612
1613         iwl_calib_free_results(trans);
1614         iwl_trans_pcie_tx_free(trans);
1615 #ifndef CONFIG_IWLWIFI_IDI
1616         iwl_trans_pcie_rx_free(trans);
1617 #endif
1618         if (trans_pcie->irq_requested == true) {
1619                 free_irq(trans->irq, trans);
1620                 iwl_free_isr_ict(trans);
1621         }
1622
1623         pci_disable_msi(trans_pcie->pci_dev);
1624         pci_iounmap(trans_pcie->pci_dev, trans_pcie->hw_base);
1625         pci_release_regions(trans_pcie->pci_dev);
1626         pci_disable_device(trans_pcie->pci_dev);
1627
1628         trans->shrd->trans = NULL;
1629         kfree(trans);
1630 }
1631
1632 #ifdef CONFIG_PM_SLEEP
1633 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
1634 {
1635         /*
1636          * This function is called when system goes into suspend state
1637          * mac80211 will call iwlagn_mac_stop() from the mac80211 suspend
1638          * function first but since iwlagn_mac_stop() has no knowledge of
1639          * who the caller is,
1640          * it will not call apm_ops.stop() to stop the DMA operation.
1641          * Calling apm_ops.stop here to make sure we stop the DMA.
1642          *
1643          * But of course ... if we have configured WoWLAN then we did other
1644          * things already :-)
1645          */
1646         if (!trans->shrd->wowlan) {
1647                 iwl_apm_stop(trans);
1648         } else {
1649                 iwl_disable_interrupts(trans);
1650                 iwl_clear_bit(trans, CSR_GP_CNTRL,
1651                               CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1652         }
1653
1654         return 0;
1655 }
1656
1657 static int iwl_trans_pcie_resume(struct iwl_trans *trans)
1658 {
1659         bool hw_rfkill = false;
1660
1661         iwl_enable_interrupts(trans);
1662
1663         if (!(iwl_read32(trans, CSR_GP_CNTRL) &
1664                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1665                 hw_rfkill = true;
1666
1667         if (hw_rfkill)
1668                 set_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1669         else
1670                 clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
1671
1672         iwl_set_hw_rfkill_state(priv(trans), hw_rfkill);
1673
1674         return 0;
1675 }
1676 #endif /* CONFIG_PM_SLEEP */
1677
1678 static void iwl_trans_pcie_wake_any_queue(struct iwl_trans *trans,
1679                                           enum iwl_rxon_context_id ctx,
1680                                           const char *msg)
1681 {
1682         u8 ac, txq_id;
1683         struct iwl_trans_pcie *trans_pcie =
1684                 IWL_TRANS_GET_PCIE_TRANS(trans);
1685
1686         for (ac = 0; ac < AC_NUM; ac++) {
1687                 txq_id = trans_pcie->ac_to_queue[ctx][ac];
1688                 IWL_DEBUG_TX_QUEUES(trans, "Queue Status: Q[%d] %s\n",
1689                         ac,
1690                         (atomic_read(&trans_pcie->queue_stop_count[ac]) > 0)
1691                               ? "stopped" : "awake");
1692                 iwl_wake_queue(trans, &trans_pcie->txq[txq_id], msg);
1693         }
1694 }
1695
1696 static void iwl_trans_pcie_stop_queue(struct iwl_trans *trans, int txq_id,
1697                                       const char *msg)
1698 {
1699         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1700
1701         iwl_stop_queue(trans, &trans_pcie->txq[txq_id], msg);
1702 }
1703
1704 #define IWL_FLUSH_WAIT_MS       2000
1705
1706 static int iwl_trans_pcie_wait_tx_queue_empty(struct iwl_trans *trans)
1707 {
1708         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1709         struct iwl_tx_queue *txq;
1710         struct iwl_queue *q;
1711         int cnt;
1712         unsigned long now = jiffies;
1713         int ret = 0;
1714
1715         /* waiting for all the tx frames complete might take a while */
1716         for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) {
1717                 if (cnt == trans->shrd->cmd_queue)
1718                         continue;
1719                 txq = &trans_pcie->txq[cnt];
1720                 q = &txq->q;
1721                 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1722                        now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1723                         msleep(1);
1724
1725                 if (q->read_ptr != q->write_ptr) {
1726                         IWL_ERR(trans, "fail to flush all tx fifo queues\n");
1727                         ret = -ETIMEDOUT;
1728                         break;
1729                 }
1730         }
1731         return ret;
1732 }
1733
1734 /*
1735  * On every watchdog tick we check (latest) time stamp. If it does not
1736  * change during timeout period and queue is not empty we reset firmware.
1737  */
1738 static int iwl_trans_pcie_check_stuck_queue(struct iwl_trans *trans, int cnt)
1739 {
1740         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1741         struct iwl_tx_queue *txq = &trans_pcie->txq[cnt];
1742         struct iwl_queue *q = &txq->q;
1743         unsigned long timeout;
1744
1745         if (q->read_ptr == q->write_ptr) {
1746                 txq->time_stamp = jiffies;
1747                 return 0;
1748         }
1749
1750         timeout = txq->time_stamp +
1751                   msecs_to_jiffies(hw_params(trans).wd_timeout);
1752
1753         if (time_after(jiffies, timeout)) {
1754                 IWL_ERR(trans, "Queue %d stuck for %u ms.\n", q->id,
1755                         hw_params(trans).wd_timeout);
1756                 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1757                         q->read_ptr, q->write_ptr);
1758                 IWL_ERR(trans, "Current HW read_ptr %d write_ptr %d\n",
1759                         iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt))
1760                                 & (TFD_QUEUE_SIZE_MAX - 1),
1761                         iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1762                 return 1;
1763         }
1764
1765         return 0;
1766 }
1767
1768 static const char *get_fh_string(int cmd)
1769 {
1770         switch (cmd) {
1771         IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
1772         IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
1773         IWL_CMD(FH_RSCSR_CHNL0_WPTR);
1774         IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
1775         IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
1776         IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
1777         IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
1778         IWL_CMD(FH_TSSR_TX_STATUS_REG);
1779         IWL_CMD(FH_TSSR_TX_ERROR_REG);
1780         default:
1781                 return "UNKNOWN";
1782         }
1783 }
1784
1785 int iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display)
1786 {
1787         int i;
1788 #ifdef CONFIG_IWLWIFI_DEBUG
1789         int pos = 0;
1790         size_t bufsz = 0;
1791 #endif
1792         static const u32 fh_tbl[] = {
1793                 FH_RSCSR_CHNL0_STTS_WPTR_REG,
1794                 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
1795                 FH_RSCSR_CHNL0_WPTR,
1796                 FH_MEM_RCSR_CHNL0_CONFIG_REG,
1797                 FH_MEM_RSSR_SHARED_CTRL_REG,
1798                 FH_MEM_RSSR_RX_STATUS_REG,
1799                 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
1800                 FH_TSSR_TX_STATUS_REG,
1801                 FH_TSSR_TX_ERROR_REG
1802         };
1803 #ifdef CONFIG_IWLWIFI_DEBUG
1804         if (display) {
1805                 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
1806                 *buf = kmalloc(bufsz, GFP_KERNEL);
1807                 if (!*buf)
1808                         return -ENOMEM;
1809                 pos += scnprintf(*buf + pos, bufsz - pos,
1810                                 "FH register values:\n");
1811                 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1812                         pos += scnprintf(*buf + pos, bufsz - pos,
1813                                 "  %34s: 0X%08x\n",
1814                                 get_fh_string(fh_tbl[i]),
1815                                 iwl_read_direct32(trans, fh_tbl[i]));
1816                 }
1817                 return pos;
1818         }
1819 #endif
1820         IWL_ERR(trans, "FH register values:\n");
1821         for (i = 0; i <  ARRAY_SIZE(fh_tbl); i++) {
1822                 IWL_ERR(trans, "  %34s: 0X%08x\n",
1823                         get_fh_string(fh_tbl[i]),
1824                         iwl_read_direct32(trans, fh_tbl[i]));
1825         }
1826         return 0;
1827 }
1828
1829 static const char *get_csr_string(int cmd)
1830 {
1831         switch (cmd) {
1832         IWL_CMD(CSR_HW_IF_CONFIG_REG);
1833         IWL_CMD(CSR_INT_COALESCING);
1834         IWL_CMD(CSR_INT);
1835         IWL_CMD(CSR_INT_MASK);
1836         IWL_CMD(CSR_FH_INT_STATUS);
1837         IWL_CMD(CSR_GPIO_IN);
1838         IWL_CMD(CSR_RESET);
1839         IWL_CMD(CSR_GP_CNTRL);
1840         IWL_CMD(CSR_HW_REV);
1841         IWL_CMD(CSR_EEPROM_REG);
1842         IWL_CMD(CSR_EEPROM_GP);
1843         IWL_CMD(CSR_OTP_GP_REG);
1844         IWL_CMD(CSR_GIO_REG);
1845         IWL_CMD(CSR_GP_UCODE_REG);
1846         IWL_CMD(CSR_GP_DRIVER_REG);
1847         IWL_CMD(CSR_UCODE_DRV_GP1);
1848         IWL_CMD(CSR_UCODE_DRV_GP2);
1849         IWL_CMD(CSR_LED_REG);
1850         IWL_CMD(CSR_DRAM_INT_TBL_REG);
1851         IWL_CMD(CSR_GIO_CHICKEN_BITS);
1852         IWL_CMD(CSR_ANA_PLL_CFG);
1853         IWL_CMD(CSR_HW_REV_WA_REG);
1854         IWL_CMD(CSR_DBG_HPET_MEM_REG);
1855         default:
1856                 return "UNKNOWN";
1857         }
1858 }
1859
1860 void iwl_dump_csr(struct iwl_trans *trans)
1861 {
1862         int i;
1863         static const u32 csr_tbl[] = {
1864                 CSR_HW_IF_CONFIG_REG,
1865                 CSR_INT_COALESCING,
1866                 CSR_INT,
1867                 CSR_INT_MASK,
1868                 CSR_FH_INT_STATUS,
1869                 CSR_GPIO_IN,
1870                 CSR_RESET,
1871                 CSR_GP_CNTRL,
1872                 CSR_HW_REV,
1873                 CSR_EEPROM_REG,
1874                 CSR_EEPROM_GP,
1875                 CSR_OTP_GP_REG,
1876                 CSR_GIO_REG,
1877                 CSR_GP_UCODE_REG,
1878                 CSR_GP_DRIVER_REG,
1879                 CSR_UCODE_DRV_GP1,
1880                 CSR_UCODE_DRV_GP2,
1881                 CSR_LED_REG,
1882                 CSR_DRAM_INT_TBL_REG,
1883                 CSR_GIO_CHICKEN_BITS,
1884                 CSR_ANA_PLL_CFG,
1885                 CSR_HW_REV_WA_REG,
1886                 CSR_DBG_HPET_MEM_REG
1887         };
1888         IWL_ERR(trans, "CSR values:\n");
1889         IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1890                 "CSR_INT_PERIODIC_REG)\n");
1891         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
1892                 IWL_ERR(trans, "  %25s: 0X%08x\n",
1893                         get_csr_string(csr_tbl[i]),
1894                         iwl_read32(trans, csr_tbl[i]));
1895         }
1896 }
1897
1898 #ifdef CONFIG_IWLWIFI_DEBUGFS
1899 /* create and remove of files */
1900 #define DEBUGFS_ADD_FILE(name, parent, mode) do {                       \
1901         if (!debugfs_create_file(#name, mode, parent, trans,            \
1902                                  &iwl_dbgfs_##name##_ops))              \
1903                 return -ENOMEM;                                         \
1904 } while (0)
1905
1906 /* file operation */
1907 #define DEBUGFS_READ_FUNC(name)                                         \
1908 static ssize_t iwl_dbgfs_##name##_read(struct file *file,               \
1909                                         char __user *user_buf,          \
1910                                         size_t count, loff_t *ppos);
1911
1912 #define DEBUGFS_WRITE_FUNC(name)                                        \
1913 static ssize_t iwl_dbgfs_##name##_write(struct file *file,              \
1914                                         const char __user *user_buf,    \
1915                                         size_t count, loff_t *ppos);
1916
1917
1918 static int iwl_dbgfs_open_file_generic(struct inode *inode, struct file *file)
1919 {
1920         file->private_data = inode->i_private;
1921         return 0;
1922 }
1923
1924 #define DEBUGFS_READ_FILE_OPS(name)                                     \
1925         DEBUGFS_READ_FUNC(name);                                        \
1926 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1927         .read = iwl_dbgfs_##name##_read,                                \
1928         .open = iwl_dbgfs_open_file_generic,                            \
1929         .llseek = generic_file_llseek,                                  \
1930 };
1931
1932 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
1933         DEBUGFS_WRITE_FUNC(name);                                       \
1934 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1935         .write = iwl_dbgfs_##name##_write,                              \
1936         .open = iwl_dbgfs_open_file_generic,                            \
1937         .llseek = generic_file_llseek,                                  \
1938 };
1939
1940 #define DEBUGFS_READ_WRITE_FILE_OPS(name)                               \
1941         DEBUGFS_READ_FUNC(name);                                        \
1942         DEBUGFS_WRITE_FUNC(name);                                       \
1943 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1944         .write = iwl_dbgfs_##name##_write,                              \
1945         .read = iwl_dbgfs_##name##_read,                                \
1946         .open = iwl_dbgfs_open_file_generic,                            \
1947         .llseek = generic_file_llseek,                                  \
1948 };
1949
1950 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1951                                                 char __user *user_buf,
1952                                                 size_t count, loff_t *ppos)
1953 {
1954         struct iwl_trans *trans = file->private_data;
1955         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1956         struct iwl_tx_queue *txq;
1957         struct iwl_queue *q;
1958         char *buf;
1959         int pos = 0;
1960         int cnt;
1961         int ret;
1962         const size_t bufsz = sizeof(char) * 64 * hw_params(trans).max_txq_num;
1963
1964         if (!trans_pcie->txq) {
1965                 IWL_ERR(trans, "txq not ready\n");
1966                 return -EAGAIN;
1967         }
1968         buf = kzalloc(bufsz, GFP_KERNEL);
1969         if (!buf)
1970                 return -ENOMEM;
1971
1972         for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) {
1973                 txq = &trans_pcie->txq[cnt];
1974                 q = &txq->q;
1975                 pos += scnprintf(buf + pos, bufsz - pos,
1976                                 "hwq %.2d: read=%u write=%u stop=%d"
1977                                 " swq_id=%#.2x (ac %d/hwq %d)\n",
1978                                 cnt, q->read_ptr, q->write_ptr,
1979                                 !!test_bit(cnt, trans_pcie->queue_stopped),
1980                                 txq->swq_id, txq->swq_id & 3,
1981                                 (txq->swq_id >> 2) & 0x1f);
1982                 if (cnt >= 4)
1983                         continue;
1984                 /* for the ACs, display the stop count too */
1985                 pos += scnprintf(buf + pos, bufsz - pos,
1986                         "        stop-count: %d\n",
1987                         atomic_read(&trans_pcie->queue_stop_count[cnt]));
1988         }
1989         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1990         kfree(buf);
1991         return ret;
1992 }
1993
1994 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1995                                                 char __user *user_buf,
1996                                                 size_t count, loff_t *ppos) {
1997         struct iwl_trans *trans = file->private_data;
1998         struct iwl_trans_pcie *trans_pcie =
1999                 IWL_TRANS_GET_PCIE_TRANS(trans);
2000         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
2001         char buf[256];
2002         int pos = 0;
2003         const size_t bufsz = sizeof(buf);
2004
2005         pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
2006                                                 rxq->read);
2007         pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
2008                                                 rxq->write);
2009         pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
2010                                                 rxq->free_count);
2011         if (rxq->rb_stts) {
2012                 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
2013                          le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF);
2014         } else {
2015                 pos += scnprintf(buf + pos, bufsz - pos,
2016                                         "closed_rb_num: Not Allocated\n");
2017         }
2018         return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2019 }
2020
2021 static ssize_t iwl_dbgfs_log_event_read(struct file *file,
2022                                          char __user *user_buf,
2023                                          size_t count, loff_t *ppos)
2024 {
2025         struct iwl_trans *trans = file->private_data;
2026         char *buf;
2027         int pos = 0;
2028         ssize_t ret = -ENOMEM;
2029
2030         ret = pos = iwl_dump_nic_event_log(trans, true, &buf, true);
2031         if (buf) {
2032                 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2033                 kfree(buf);
2034         }
2035         return ret;
2036 }
2037
2038 static ssize_t iwl_dbgfs_log_event_write(struct file *file,
2039                                         const char __user *user_buf,
2040                                         size_t count, loff_t *ppos)
2041 {
2042         struct iwl_trans *trans = file->private_data;
2043         u32 event_log_flag;
2044         char buf[8];
2045         int buf_size;
2046
2047         memset(buf, 0, sizeof(buf));
2048         buf_size = min(count, sizeof(buf) -  1);
2049         if (copy_from_user(buf, user_buf, buf_size))
2050                 return -EFAULT;
2051         if (sscanf(buf, "%d", &event_log_flag) != 1)
2052                 return -EFAULT;
2053         if (event_log_flag == 1)
2054                 iwl_dump_nic_event_log(trans, true, NULL, false);
2055
2056         return count;
2057 }
2058
2059 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
2060                                         char __user *user_buf,
2061                                         size_t count, loff_t *ppos) {
2062
2063         struct iwl_trans *trans = file->private_data;
2064         struct iwl_trans_pcie *trans_pcie =
2065                 IWL_TRANS_GET_PCIE_TRANS(trans);
2066         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2067
2068         int pos = 0;
2069         char *buf;
2070         int bufsz = 24 * 64; /* 24 items * 64 char per item */
2071         ssize_t ret;
2072
2073         buf = kzalloc(bufsz, GFP_KERNEL);
2074         if (!buf) {
2075                 IWL_ERR(trans, "Can not allocate Buffer\n");
2076                 return -ENOMEM;
2077         }
2078
2079         pos += scnprintf(buf + pos, bufsz - pos,
2080                         "Interrupt Statistics Report:\n");
2081
2082         pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2083                 isr_stats->hw);
2084         pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2085                 isr_stats->sw);
2086         if (isr_stats->sw || isr_stats->hw) {
2087                 pos += scnprintf(buf + pos, bufsz - pos,
2088                         "\tLast Restarting Code:  0x%X\n",
2089                         isr_stats->err_code);
2090         }
2091 #ifdef CONFIG_IWLWIFI_DEBUG
2092         pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2093                 isr_stats->sch);
2094         pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2095                 isr_stats->alive);
2096 #endif
2097         pos += scnprintf(buf + pos, bufsz - pos,
2098                 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2099
2100         pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2101                 isr_stats->ctkill);
2102
2103         pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2104                 isr_stats->wakeup);
2105
2106         pos += scnprintf(buf + pos, bufsz - pos,
2107                 "Rx command responses:\t\t %u\n", isr_stats->rx);
2108
2109         pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2110                 isr_stats->tx);
2111
2112         pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2113                 isr_stats->unhandled);
2114
2115         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2116         kfree(buf);
2117         return ret;
2118 }
2119
2120 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2121                                          const char __user *user_buf,
2122                                          size_t count, loff_t *ppos)
2123 {
2124         struct iwl_trans *trans = file->private_data;
2125         struct iwl_trans_pcie *trans_pcie =
2126                 IWL_TRANS_GET_PCIE_TRANS(trans);
2127         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2128
2129         char buf[8];
2130         int buf_size;
2131         u32 reset_flag;
2132
2133         memset(buf, 0, sizeof(buf));
2134         buf_size = min(count, sizeof(buf) -  1);
2135         if (copy_from_user(buf, user_buf, buf_size))
2136                 return -EFAULT;
2137         if (sscanf(buf, "%x", &reset_flag) != 1)
2138                 return -EFAULT;
2139         if (reset_flag == 0)
2140                 memset(isr_stats, 0, sizeof(*isr_stats));
2141
2142         return count;
2143 }
2144
2145 static ssize_t iwl_dbgfs_csr_write(struct file *file,
2146                                          const char __user *user_buf,
2147                                          size_t count, loff_t *ppos)
2148 {
2149         struct iwl_trans *trans = file->private_data;
2150         char buf[8];
2151         int buf_size;
2152         int csr;
2153
2154         memset(buf, 0, sizeof(buf));
2155         buf_size = min(count, sizeof(buf) -  1);
2156         if (copy_from_user(buf, user_buf, buf_size))
2157                 return -EFAULT;
2158         if (sscanf(buf, "%d", &csr) != 1)
2159                 return -EFAULT;
2160
2161         iwl_dump_csr(trans);
2162
2163         return count;
2164 }
2165
2166 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
2167                                          char __user *user_buf,
2168                                          size_t count, loff_t *ppos)
2169 {
2170         struct iwl_trans *trans = file->private_data;
2171         char *buf;
2172         int pos = 0;
2173         ssize_t ret = -EFAULT;
2174
2175         ret = pos = iwl_dump_fh(trans, &buf, true);
2176         if (buf) {
2177                 ret = simple_read_from_buffer(user_buf,
2178                                               count, ppos, buf, pos);
2179                 kfree(buf);
2180         }
2181
2182         return ret;
2183 }
2184
2185 DEBUGFS_READ_WRITE_FILE_OPS(log_event);
2186 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
2187 DEBUGFS_READ_FILE_OPS(fh_reg);
2188 DEBUGFS_READ_FILE_OPS(rx_queue);
2189 DEBUGFS_READ_FILE_OPS(tx_queue);
2190 DEBUGFS_WRITE_FILE_OPS(csr);
2191
2192 /*
2193  * Create the debugfs files and directories
2194  *
2195  */
2196 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2197                                         struct dentry *dir)
2198 {
2199         DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2200         DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
2201         DEBUGFS_ADD_FILE(log_event, dir, S_IWUSR | S_IRUSR);
2202         DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
2203         DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2204         DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
2205         return 0;
2206 }
2207 #else
2208 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2209                                         struct dentry *dir)
2210 { return 0; }
2211
2212 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2213
2214 const struct iwl_trans_ops trans_ops_pcie = {
2215         .start_hw = iwl_trans_pcie_start_hw,
2216         .stop_hw = iwl_trans_pcie_stop_hw,
2217         .fw_alive = iwl_trans_pcie_fw_alive,
2218         .start_fw = iwl_trans_pcie_start_fw,
2219         .stop_device = iwl_trans_pcie_stop_device,
2220
2221         .wake_any_queue = iwl_trans_pcie_wake_any_queue,
2222
2223         .send_cmd = iwl_trans_pcie_send_cmd,
2224
2225         .tx = iwl_trans_pcie_tx,
2226         .reclaim = iwl_trans_pcie_reclaim,
2227
2228         .tx_agg_disable = iwl_trans_pcie_tx_agg_disable,
2229         .tx_agg_alloc = iwl_trans_pcie_tx_agg_alloc,
2230         .tx_agg_setup = iwl_trans_pcie_tx_agg_setup,
2231
2232         .free = iwl_trans_pcie_free,
2233         .stop_queue = iwl_trans_pcie_stop_queue,
2234
2235         .dbgfs_register = iwl_trans_pcie_dbgfs_register,
2236
2237         .wait_tx_queue_empty = iwl_trans_pcie_wait_tx_queue_empty,
2238         .check_stuck_queue = iwl_trans_pcie_check_stuck_queue,
2239
2240 #ifdef CONFIG_PM_SLEEP
2241         .suspend = iwl_trans_pcie_suspend,
2242         .resume = iwl_trans_pcie_resume,
2243 #endif
2244         .write8 = iwl_trans_pcie_write8,
2245         .write32 = iwl_trans_pcie_write32,
2246         .read32 = iwl_trans_pcie_read32,
2247 };
2248
2249 struct iwl_trans *iwl_trans_pcie_alloc(struct iwl_shared *shrd,
2250                                        struct pci_dev *pdev,
2251                                        const struct pci_device_id *ent)
2252 {
2253         struct iwl_trans_pcie *trans_pcie;
2254         struct iwl_trans *trans;
2255         u16 pci_cmd;
2256         int err;
2257
2258         trans = kzalloc(sizeof(struct iwl_trans) +
2259                              sizeof(struct iwl_trans_pcie), GFP_KERNEL);
2260
2261         if (WARN_ON(!trans))
2262                 return NULL;
2263
2264         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2265
2266         trans->ops = &trans_ops_pcie;
2267         trans->shrd = shrd;
2268         trans_pcie->trans = trans;
2269         spin_lock_init(&trans->hcmd_lock);
2270         spin_lock_init(&trans_pcie->irq_lock);
2271
2272         /* W/A - seems to solve weird behavior. We need to remove this if we
2273          * don't want to stay in L1 all the time. This wastes a lot of power */
2274         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
2275                                 PCIE_LINK_STATE_CLKPM);
2276
2277         if (pci_enable_device(pdev)) {
2278                 err = -ENODEV;
2279                 goto out_no_pci;
2280         }
2281
2282         pci_set_master(pdev);
2283
2284         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2285         if (!err)
2286                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2287         if (err) {
2288                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2289                 if (!err)
2290                         err = pci_set_consistent_dma_mask(pdev,
2291                                                         DMA_BIT_MASK(32));
2292                 /* both attempts failed: */
2293                 if (err) {
2294                         dev_printk(KERN_ERR, &pdev->dev,
2295                                    "No suitable DMA available.\n");
2296                         goto out_pci_disable_device;
2297                 }
2298         }
2299
2300         err = pci_request_regions(pdev, DRV_NAME);
2301         if (err) {
2302                 dev_printk(KERN_ERR, &pdev->dev, "pci_request_regions failed");
2303                 goto out_pci_disable_device;
2304         }
2305
2306         trans_pcie->hw_base = pci_iomap(pdev, 0, 0);
2307         if (!trans_pcie->hw_base) {
2308                 dev_printk(KERN_ERR, &pdev->dev, "pci_iomap failed");
2309                 err = -ENODEV;
2310                 goto out_pci_release_regions;
2311         }
2312
2313         dev_printk(KERN_INFO, &pdev->dev,
2314                 "pci_resource_len = 0x%08llx\n",
2315                 (unsigned long long) pci_resource_len(pdev, 0));
2316         dev_printk(KERN_INFO, &pdev->dev,
2317                 "pci_resource_base = %p\n", trans_pcie->hw_base);
2318
2319         dev_printk(KERN_INFO, &pdev->dev,
2320                 "HW Revision ID = 0x%X\n", pdev->revision);
2321
2322         /* We disable the RETRY_TIMEOUT register (0x41) to keep
2323          * PCI Tx retries from interfering with C3 CPU state */
2324         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2325
2326         err = pci_enable_msi(pdev);
2327         if (err)
2328                 dev_printk(KERN_ERR, &pdev->dev,
2329                         "pci_enable_msi failed(0X%x)", err);
2330
2331         trans->dev = &pdev->dev;
2332         trans->irq = pdev->irq;
2333         trans_pcie->pci_dev = pdev;
2334         trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
2335         trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
2336         snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2337                  "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
2338
2339         /* TODO: Move this away, not needed if not MSI */
2340         /* enable rfkill interrupt: hw bug w/a */
2341         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2342         if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2343                 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2344                 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2345         }
2346
2347         return trans;
2348
2349 out_pci_release_regions:
2350         pci_release_regions(pdev);
2351 out_pci_disable_device:
2352         pci_disable_device(pdev);
2353 out_no_pci:
2354         kfree(trans);
2355         return NULL;
2356 }
2357