1 /******************************************************************************
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
8 * Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
27 * Contact Information:
28 * Intel Linux Wireless <ilw@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
33 * Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
34 * All rights reserved.
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
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43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
62 *****************************************************************************/
63 #include <linux/pci.h>
64 #include <linux/pci-aspm.h>
65 #include <linux/interrupt.h>
66 #include <linux/debugfs.h>
67 #include <linux/sched.h>
68 #include <linux/bitops.h>
69 #include <linux/gfp.h>
71 #include "iwl-trans.h"
72 #include "iwl-trans-pcie-int.h"
75 #include "iwl-shared.h"
76 #include "iwl-eeprom.h"
77 #include "iwl-agn-hw.h"
79 #define IWL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo))))
81 static int iwl_trans_rx_alloc(struct iwl_trans *trans)
83 struct iwl_trans_pcie *trans_pcie =
84 IWL_TRANS_GET_PCIE_TRANS(trans);
85 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
86 struct device *dev = trans->dev;
88 memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq));
90 spin_lock_init(&rxq->lock);
92 if (WARN_ON(rxq->bd || rxq->rb_stts))
95 /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
96 rxq->bd = dma_zalloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
97 &rxq->bd_dma, GFP_KERNEL);
101 /*Allocate the driver's pointer to receive buffer status */
102 rxq->rb_stts = dma_zalloc_coherent(dev, sizeof(*rxq->rb_stts),
103 &rxq->rb_stts_dma, GFP_KERNEL);
110 dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
111 rxq->bd, rxq->bd_dma);
112 memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
118 static void iwl_trans_rxq_free_rx_bufs(struct iwl_trans *trans)
120 struct iwl_trans_pcie *trans_pcie =
121 IWL_TRANS_GET_PCIE_TRANS(trans);
122 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
125 /* Fill the rx_used queue with _all_ of the Rx buffers */
126 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
127 /* In the reset function, these buffers may have been allocated
128 * to an SKB, so we need to unmap and free potential storage */
129 if (rxq->pool[i].page != NULL) {
130 dma_unmap_page(trans->dev, rxq->pool[i].page_dma,
131 PAGE_SIZE << hw_params(trans).rx_page_order,
133 __free_pages(rxq->pool[i].page,
134 hw_params(trans).rx_page_order);
135 rxq->pool[i].page = NULL;
137 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
141 static void iwl_trans_rx_hw_init(struct iwl_trans *trans,
142 struct iwl_rx_queue *rxq)
145 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
146 u32 rb_timeout = RX_RB_TIMEOUT; /* FIXME: RX_RB_TIMEOUT for all devices? */
148 if (iwlagn_mod_params.amsdu_size_8K)
149 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
151 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
154 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
156 /* Reset driver's Rx queue write index */
157 iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
159 /* Tell device where to find RBD circular buffer in DRAM */
160 iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
161 (u32)(rxq->bd_dma >> 8));
163 /* Tell device where in DRAM to update its Rx status */
164 iwl_write_direct32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,
165 rxq->rb_stts_dma >> 4);
168 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
169 * the credit mechanism in 5000 HW RX FIFO
170 * Direct rx interrupts to hosts
171 * Rx buffer size 4 or 8k
175 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,
176 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
177 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
178 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
179 FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
181 (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
182 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
184 /* Set interrupt coalescing timer to default (2048 usecs) */
185 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
188 static int iwl_rx_init(struct iwl_trans *trans)
190 struct iwl_trans_pcie *trans_pcie =
191 IWL_TRANS_GET_PCIE_TRANS(trans);
192 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
198 err = iwl_trans_rx_alloc(trans);
203 spin_lock_irqsave(&rxq->lock, flags);
204 INIT_LIST_HEAD(&rxq->rx_free);
205 INIT_LIST_HEAD(&rxq->rx_used);
207 iwl_trans_rxq_free_rx_bufs(trans);
209 for (i = 0; i < RX_QUEUE_SIZE; i++)
210 rxq->queue[i] = NULL;
212 /* Set us so that we have processed and used all buffers, but have
213 * not restocked the Rx queue with fresh buffers */
214 rxq->read = rxq->write = 0;
215 rxq->write_actual = 0;
217 spin_unlock_irqrestore(&rxq->lock, flags);
219 iwlagn_rx_replenish(trans);
221 iwl_trans_rx_hw_init(trans, rxq);
223 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
224 rxq->need_update = 1;
225 iwl_rx_queue_update_write_ptr(trans, rxq);
226 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
231 static void iwl_trans_pcie_rx_free(struct iwl_trans *trans)
233 struct iwl_trans_pcie *trans_pcie =
234 IWL_TRANS_GET_PCIE_TRANS(trans);
235 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
239 /*if rxq->bd is NULL, it means that nothing has been allocated,
242 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
246 spin_lock_irqsave(&rxq->lock, flags);
247 iwl_trans_rxq_free_rx_bufs(trans);
248 spin_unlock_irqrestore(&rxq->lock, flags);
250 dma_free_coherent(trans->dev, sizeof(__le32) * RX_QUEUE_SIZE,
251 rxq->bd, rxq->bd_dma);
252 memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
256 dma_free_coherent(trans->dev,
257 sizeof(struct iwl_rb_status),
258 rxq->rb_stts, rxq->rb_stts_dma);
260 IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n");
261 memset(&rxq->rb_stts_dma, 0, sizeof(rxq->rb_stts_dma));
265 static int iwl_trans_rx_stop(struct iwl_trans *trans)
269 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
270 return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG,
271 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
274 static inline int iwlagn_alloc_dma_ptr(struct iwl_trans *trans,
275 struct iwl_dma_ptr *ptr, size_t size)
277 if (WARN_ON(ptr->addr))
280 ptr->addr = dma_alloc_coherent(trans->dev, size,
281 &ptr->dma, GFP_KERNEL);
288 static inline void iwlagn_free_dma_ptr(struct iwl_trans *trans,
289 struct iwl_dma_ptr *ptr)
291 if (unlikely(!ptr->addr))
294 dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
295 memset(ptr, 0, sizeof(*ptr));
298 static int iwl_trans_txq_alloc(struct iwl_trans *trans,
299 struct iwl_tx_queue *txq, int slots_num,
302 size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
305 if (WARN_ON(txq->meta || txq->cmd || txq->skbs || txq->tfds))
308 txq->q.n_window = slots_num;
310 txq->meta = kcalloc(slots_num, sizeof(txq->meta[0]), GFP_KERNEL);
311 txq->cmd = kcalloc(slots_num, sizeof(txq->cmd[0]), GFP_KERNEL);
313 if (!txq->meta || !txq->cmd)
316 if (txq_id == trans->shrd->cmd_queue)
317 for (i = 0; i < slots_num; i++) {
318 txq->cmd[i] = kmalloc(sizeof(struct iwl_device_cmd),
324 /* Alloc driver data array and TFD circular buffer */
325 /* Driver private data, only for Tx (not command) queues,
326 * not shared with device. */
327 if (txq_id != trans->shrd->cmd_queue) {
328 txq->skbs = kcalloc(TFD_QUEUE_SIZE_MAX, sizeof(txq->skbs[0]),
331 IWL_ERR(trans, "kmalloc for auxiliary BD "
332 "structures failed\n");
339 /* Circular buffer of transmit frame descriptors (TFDs),
340 * shared with device */
341 txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
342 &txq->q.dma_addr, GFP_KERNEL);
344 IWL_ERR(trans, "dma_alloc_coherent(%zd) failed\n", tfd_sz);
353 /* since txq->cmd has been zeroed,
354 * all non allocated cmd[i] will be NULL */
355 if (txq->cmd && txq_id == trans->shrd->cmd_queue)
356 for (i = 0; i < slots_num; i++)
367 static int iwl_trans_txq_init(struct iwl_trans *trans, struct iwl_tx_queue *txq,
368 int slots_num, u32 txq_id)
372 txq->need_update = 0;
373 memset(txq->meta, 0, sizeof(txq->meta[0]) * slots_num);
376 * For the default queues 0-3, set up the swq_id
377 * already -- all others need to get one later
378 * (if they need one at all).
381 iwl_set_swq_id(txq, txq_id, txq_id);
383 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
384 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
385 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
387 /* Initialize queue's high/low-water marks, and head/tail indexes */
388 ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num,
393 spin_lock_init(&txq->lock);
396 * Tell nic where to find circular buffer of Tx Frame Descriptors for
397 * given Tx queue, and enable the DMA channel used for that queue.
398 * Circular buffer (TFD queue in DRAM) physical base address */
399 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
400 txq->q.dma_addr >> 8);
406 * iwl_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
408 static void iwl_tx_queue_unmap(struct iwl_trans *trans, int txq_id)
410 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
411 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
412 struct iwl_queue *q = &txq->q;
413 enum dma_data_direction dma_dir;
418 /* In the command queue, all the TBs are mapped as BIDI
419 * so unmap them as such.
421 if (txq_id == trans->shrd->cmd_queue)
422 dma_dir = DMA_BIDIRECTIONAL;
424 dma_dir = DMA_TO_DEVICE;
426 spin_lock_bh(&txq->lock);
427 while (q->write_ptr != q->read_ptr) {
428 /* The read_ptr needs to bound by q->n_window */
429 iwlagn_txq_free_tfd(trans, txq, get_cmd_index(q, q->read_ptr),
431 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
433 spin_unlock_bh(&txq->lock);
437 * iwl_tx_queue_free - Deallocate DMA queue.
438 * @txq: Transmit queue to deallocate.
440 * Empty queue by removing and destroying all BD's.
442 * 0-fill, but do not free "txq" descriptor structure.
444 static void iwl_tx_queue_free(struct iwl_trans *trans, int txq_id)
446 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
447 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
448 struct device *dev = trans->dev;
453 iwl_tx_queue_unmap(trans, txq_id);
455 /* De-alloc array of command/tx buffers */
457 if (txq_id == trans->shrd->cmd_queue)
458 for (i = 0; i < txq->q.n_window; i++)
461 /* De-alloc circular buffer of TFDs */
463 dma_free_coherent(dev, sizeof(struct iwl_tfd) *
464 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
465 memset(&txq->q.dma_addr, 0, sizeof(txq->q.dma_addr));
468 /* De-alloc array of per-TFD driver data */
472 /* deallocate arrays */
478 /* 0-fill queue descriptor structure */
479 memset(txq, 0, sizeof(*txq));
483 * iwl_trans_tx_free - Free TXQ Context
485 * Destroy all TX DMA queues and structures
487 static void iwl_trans_pcie_tx_free(struct iwl_trans *trans)
490 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
493 if (trans_pcie->txq) {
495 txq_id < hw_params(trans).max_txq_num; txq_id++)
496 iwl_tx_queue_free(trans, txq_id);
499 kfree(trans_pcie->txq);
500 trans_pcie->txq = NULL;
502 iwlagn_free_dma_ptr(trans, &trans_pcie->kw);
504 iwlagn_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
508 * iwl_trans_tx_alloc - allocate TX context
509 * Allocate all Tx DMA structures and initialize them
514 static int iwl_trans_tx_alloc(struct iwl_trans *trans)
517 int txq_id, slots_num;
518 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
520 u16 scd_bc_tbls_size = hw_params(trans).max_txq_num *
521 sizeof(struct iwlagn_scd_bc_tbl);
523 /*It is not allowed to alloc twice, so warn when this happens.
524 * We cannot rely on the previous allocation, so free and fail */
525 if (WARN_ON(trans_pcie->txq)) {
530 ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
533 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
537 /* Alloc keep-warm buffer */
538 ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
540 IWL_ERR(trans, "Keep Warm allocation failed\n");
544 trans_pcie->txq = kcalloc(hw_params(trans).max_txq_num,
545 sizeof(struct iwl_tx_queue), GFP_KERNEL);
546 if (!trans_pcie->txq) {
547 IWL_ERR(trans, "Not enough memory for txq\n");
552 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
553 for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) {
554 slots_num = (txq_id == trans->shrd->cmd_queue) ?
555 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
556 ret = iwl_trans_txq_alloc(trans, &trans_pcie->txq[txq_id],
559 IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
567 iwl_trans_pcie_tx_free(trans);
571 static int iwl_tx_init(struct iwl_trans *trans)
574 int txq_id, slots_num;
577 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
579 if (!trans_pcie->txq) {
580 ret = iwl_trans_tx_alloc(trans);
586 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
588 /* Turn off all Tx DMA fifos */
589 iwl_write_prph(trans, SCD_TXFACT, 0);
591 /* Tell NIC where to find the "keep warm" buffer */
592 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
593 trans_pcie->kw.dma >> 4);
595 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
597 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
598 for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) {
599 slots_num = (txq_id == trans->shrd->cmd_queue) ?
600 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
601 ret = iwl_trans_txq_init(trans, &trans_pcie->txq[txq_id],
604 IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
611 /*Upon error, free only if we allocated something */
613 iwl_trans_pcie_tx_free(trans);
617 static void iwl_set_pwr_vmain(struct iwl_trans *trans)
620 * (for documentation purposes)
621 * to set power to V_AUX, do:
623 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
624 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
625 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
626 ~APMG_PS_CTRL_MSK_PWR_SRC);
629 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
630 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
631 ~APMG_PS_CTRL_MSK_PWR_SRC);
635 #define PCI_CFG_RETRY_TIMEOUT 0x041
636 #define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01
637 #define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02
639 static u16 iwl_pciexp_link_ctrl(struct iwl_trans *trans)
643 struct iwl_trans_pcie *trans_pcie =
644 IWL_TRANS_GET_PCIE_TRANS(trans);
646 struct pci_dev *pci_dev = trans_pcie->pci_dev;
648 pos = pci_pcie_cap(pci_dev);
649 pci_read_config_word(pci_dev, pos + PCI_EXP_LNKCTL, &pci_lnk_ctl);
653 static void iwl_apm_config(struct iwl_trans *trans)
656 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
657 * Check if BIOS (or OS) enabled L1-ASPM on this device.
658 * If so (likely), disable L0S, so device moves directly L0->L1;
659 * costs negligible amount of power savings.
660 * If not (unlikely), enable L0S, so there is at least some
661 * power savings, even without L1.
663 u16 lctl = iwl_pciexp_link_ctrl(trans);
665 if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
666 PCI_CFG_LINK_CTRL_VAL_L1_EN) {
667 /* L1-ASPM enabled; disable(!) L0S */
668 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
669 dev_printk(KERN_INFO, trans->dev,
670 "L1 Enabled; Disabling L0S\n");
672 /* L1-ASPM disabled; enable(!) L0S */
673 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
674 dev_printk(KERN_INFO, trans->dev,
675 "L1 Disabled; Enabling L0S\n");
677 trans->pm_support = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN);
681 * Start up NIC's basic functionality after it has been reset
682 * (e.g. after platform boot, or shutdown via iwl_apm_stop())
683 * NOTE: This does not load uCode nor start the embedded processor
685 static int iwl_apm_init(struct iwl_trans *trans)
688 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
691 * Use "set_bit" below rather than "write", to preserve any hardware
692 * bits already set by default after reset.
695 /* Disable L0S exit timer (platform NMI Work/Around) */
696 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
697 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
700 * Disable L0s without affecting L1;
701 * don't wait for ICH L0s (ICH bug W/A)
703 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
704 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
706 /* Set FH wait threshold to maximum (HW error during stress W/A) */
707 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
710 * Enable HAP INTA (interrupt from management bus) to
711 * wake device's PCI Express link L1a -> L0s
713 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
714 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
716 iwl_apm_config(trans);
718 /* Configure analog phase-lock-loop before activating to D0A */
719 if (cfg(trans)->base_params->pll_cfg_val)
720 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
721 cfg(trans)->base_params->pll_cfg_val);
724 * Set "initialization complete" bit to move adapter from
725 * D0U* --> D0A* (powered-up active) state.
727 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
730 * Wait for clock stabilization; once stabilized, access to
731 * device-internal resources is supported, e.g. iwl_write_prph()
732 * and accesses to uCode SRAM.
734 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
735 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
736 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
738 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
743 * Enable DMA clock and wait for it to stabilize.
745 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
746 * do not disable clocks. This preserves any hardware bits already
747 * set by default in "CLK_CTRL_REG" after reset.
749 iwl_write_prph(trans, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
752 /* Disable L1-Active */
753 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
754 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
756 set_bit(STATUS_DEVICE_ENABLED, &trans->shrd->status);
762 static int iwl_apm_stop_master(struct iwl_trans *trans)
766 /* stop device's busmaster DMA activity */
767 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
769 ret = iwl_poll_bit(trans, CSR_RESET,
770 CSR_RESET_REG_FLAG_MASTER_DISABLED,
771 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
773 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
775 IWL_DEBUG_INFO(trans, "stop master\n");
780 static void iwl_apm_stop(struct iwl_trans *trans)
782 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
784 clear_bit(STATUS_DEVICE_ENABLED, &trans->shrd->status);
786 /* Stop device's DMA activity */
787 iwl_apm_stop_master(trans);
789 /* Reset the entire device */
790 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
795 * Clear "initialization complete" bit to move adapter from
796 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
798 iwl_clear_bit(trans, CSR_GP_CNTRL,
799 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
802 static int iwl_nic_init(struct iwl_trans *trans)
804 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
808 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
811 /* Set interrupt coalescing calibration timer to default (512 usecs) */
812 iwl_write8(trans, CSR_INT_COALESCING,
813 IWL_HOST_INT_CALIB_TIMEOUT_DEF);
815 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
817 iwl_set_pwr_vmain(trans);
819 iwl_op_mode_nic_config(trans->op_mode);
821 #ifndef CONFIG_IWLWIFI_IDI
822 /* Allocate the RX queue, or reset if it is already allocated */
826 /* Allocate or reset and init all Tx and Command queues */
827 if (iwl_tx_init(trans))
830 if (cfg(trans)->base_params->shadow_reg_enable) {
831 /* enable shadow regs in HW */
832 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL,
836 set_bit(STATUS_INIT, &trans->shrd->status);
841 #define HW_READY_TIMEOUT (50)
843 /* Note: returns poll_bit return value, which is >= 0 if success */
844 static int iwl_set_hw_ready(struct iwl_trans *trans)
848 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
849 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
851 /* See if we got it */
852 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
853 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
854 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
857 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
861 /* Note: returns standard 0/-ERROR code */
862 static int iwl_prepare_card_hw(struct iwl_trans *trans)
866 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
868 ret = iwl_set_hw_ready(trans);
869 /* If the card is ready, exit 0 */
873 /* If HW is not ready, prepare the conditions to check again */
874 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
875 CSR_HW_IF_CONFIG_REG_PREPARE);
877 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
878 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
879 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
884 /* HW should be ready by now, check again. */
885 ret = iwl_set_hw_ready(trans);
891 #define IWL_AC_UNSET -1
893 struct queue_to_fifo_ac {
897 static const struct queue_to_fifo_ac iwlagn_default_queue_to_tx_fifo[] = {
898 { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
899 { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
900 { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
901 { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
902 { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
903 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
904 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
905 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
906 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
907 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
908 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
911 static const struct queue_to_fifo_ac iwlagn_ipan_queue_to_tx_fifo[] = {
912 { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
913 { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
914 { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
915 { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
916 { IWL_TX_FIFO_BK_IPAN, IEEE80211_AC_BK, },
917 { IWL_TX_FIFO_BE_IPAN, IEEE80211_AC_BE, },
918 { IWL_TX_FIFO_VI_IPAN, IEEE80211_AC_VI, },
919 { IWL_TX_FIFO_VO_IPAN, IEEE80211_AC_VO, },
920 { IWL_TX_FIFO_BE_IPAN, 2, },
921 { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
922 { IWL_TX_FIFO_AUX, IWL_AC_UNSET, },
925 static const u8 iwlagn_bss_ac_to_fifo[] = {
931 static const u8 iwlagn_bss_ac_to_queue[] = {
934 static const u8 iwlagn_pan_ac_to_fifo[] = {
940 static const u8 iwlagn_pan_ac_to_queue[] = {
947 static int iwl_load_section(struct iwl_trans *trans, const char *name,
948 const struct fw_desc *image, u32 dst_addr)
950 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
951 dma_addr_t phy_addr = image->p_addr;
952 u32 byte_cnt = image->len;
955 trans_pcie->ucode_write_complete = false;
957 iwl_write_direct32(trans,
958 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
959 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
961 iwl_write_direct32(trans,
962 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
964 iwl_write_direct32(trans,
965 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
966 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
968 iwl_write_direct32(trans,
969 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
970 (iwl_get_dma_hi_addr(phy_addr)
971 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
973 iwl_write_direct32(trans,
974 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
975 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
976 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
977 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
979 iwl_write_direct32(trans,
980 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
981 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
982 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
983 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
985 IWL_DEBUG_FW(trans, "%s uCode section being loaded...\n", name);
986 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
987 trans_pcie->ucode_write_complete, 5 * HZ);
989 IWL_ERR(trans, "Could not load the %s uCode section\n",
997 static int iwl_load_given_ucode(struct iwl_trans *trans,
998 const struct fw_img *image)
1002 ret = iwl_load_section(trans, "INST", &image->code,
1003 IWLAGN_RTC_INST_LOWER_BOUND);
1007 ret = iwl_load_section(trans, "DATA", &image->data,
1008 IWLAGN_RTC_DATA_LOWER_BOUND);
1012 /* Remove all resets to allow NIC to operate */
1013 iwl_write32(trans, CSR_RESET, 0);
1018 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1019 const struct fw_img *fw)
1022 struct iwl_trans_pcie *trans_pcie =
1023 IWL_TRANS_GET_PCIE_TRANS(trans);
1026 trans_pcie->ac_to_queue[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_queue;
1027 trans_pcie->ac_to_queue[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_queue;
1029 trans_pcie->ac_to_fifo[IWL_RXON_CTX_BSS] = iwlagn_bss_ac_to_fifo;
1030 trans_pcie->ac_to_fifo[IWL_RXON_CTX_PAN] = iwlagn_pan_ac_to_fifo;
1032 trans_pcie->mcast_queue[IWL_RXON_CTX_BSS] = 0;
1033 trans_pcie->mcast_queue[IWL_RXON_CTX_PAN] = IWL_IPAN_MCAST_QUEUE;
1035 /* This may fail if AMT took ownership of the device */
1036 if (iwl_prepare_card_hw(trans)) {
1037 IWL_WARN(trans, "Exit HW not ready\n");
1041 /* If platform's RF_KILL switch is NOT set to KILL */
1042 hw_rfkill = !(iwl_read32(trans, CSR_GP_CNTRL) &
1043 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
1044 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1047 iwl_enable_interrupts(trans);
1051 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1053 ret = iwl_nic_init(trans);
1055 IWL_ERR(trans, "Unable to init nic\n");
1059 /* make sure rfkill handshake bits are cleared */
1060 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1061 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1062 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1064 /* clear (again), then enable host interrupts */
1065 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1066 iwl_enable_interrupts(trans);
1068 /* really make sure rfkill handshake bits are cleared */
1069 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1070 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1072 /* Load the given image to the HW */
1073 return iwl_load_given_ucode(trans, fw);
1077 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
1078 * must be called under the irq lock and with MAC access
1080 static void iwl_trans_txq_set_sched(struct iwl_trans *trans, u32 mask)
1082 struct iwl_trans_pcie __maybe_unused *trans_pcie =
1083 IWL_TRANS_GET_PCIE_TRANS(trans);
1085 lockdep_assert_held(&trans_pcie->irq_lock);
1087 iwl_write_prph(trans, SCD_TXFACT, mask);
1090 static void iwl_tx_start(struct iwl_trans *trans)
1092 const struct queue_to_fifo_ac *queue_to_fifo;
1093 struct iwl_trans_pcie *trans_pcie =
1094 IWL_TRANS_GET_PCIE_TRANS(trans);
1096 unsigned long flags;
1100 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1102 trans_pcie->scd_base_addr =
1103 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
1104 a = trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND;
1105 /* reset conext data memory */
1106 for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND;
1108 iwl_write_targ_mem(trans, a, 0);
1109 /* reset tx status memory */
1110 for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND;
1112 iwl_write_targ_mem(trans, a, 0);
1113 for (; a < trans_pcie->scd_base_addr +
1114 SCD_TRANS_TBL_OFFSET_QUEUE(hw_params(trans).max_txq_num);
1116 iwl_write_targ_mem(trans, a, 0);
1118 iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
1119 trans_pcie->scd_bc_tbls.dma >> 10);
1121 /* Enable DMA channel */
1122 for (chan = 0; chan < FH_TCSR_CHNL_NUM ; chan++)
1123 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
1124 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
1125 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
1127 /* Update FH chicken bits */
1128 reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
1129 iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
1130 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
1132 iwl_write_prph(trans, SCD_QUEUECHAIN_SEL,
1133 SCD_QUEUECHAIN_SEL_ALL(trans));
1134 iwl_write_prph(trans, SCD_AGGR_SEL, 0);
1136 /* initiate the queues */
1137 for (i = 0; i < hw_params(trans).max_txq_num; i++) {
1138 iwl_write_prph(trans, SCD_QUEUE_RDPTR(i), 0);
1139 iwl_write_direct32(trans, HBUS_TARG_WRPTR, 0 | (i << 8));
1140 iwl_write_targ_mem(trans, trans_pcie->scd_base_addr +
1141 SCD_CONTEXT_QUEUE_OFFSET(i), 0);
1142 iwl_write_targ_mem(trans, trans_pcie->scd_base_addr +
1143 SCD_CONTEXT_QUEUE_OFFSET(i) +
1146 SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1147 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1148 ((SCD_FRAME_LIMIT <<
1149 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1150 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1153 iwl_write_prph(trans, SCD_INTERRUPT_MASK,
1154 IWL_MASK(0, hw_params(trans).max_txq_num));
1156 /* Activate all Tx DMA/FIFO channels */
1157 iwl_trans_txq_set_sched(trans, IWL_MASK(0, 7));
1159 /* map queues to FIFOs */
1160 if (trans->shrd->valid_contexts != BIT(IWL_RXON_CTX_BSS))
1161 queue_to_fifo = iwlagn_ipan_queue_to_tx_fifo;
1163 queue_to_fifo = iwlagn_default_queue_to_tx_fifo;
1165 iwl_trans_set_wr_ptrs(trans, trans->shrd->cmd_queue, 0);
1167 /* make sure all queue are not stopped */
1168 memset(&trans_pcie->queue_stopped[0], 0,
1169 sizeof(trans_pcie->queue_stopped));
1170 for (i = 0; i < 4; i++)
1171 atomic_set(&trans_pcie->queue_stop_count[i], 0);
1173 /* reset to 0 to enable all the queue first */
1174 trans_pcie->txq_ctx_active_msk = 0;
1176 BUILD_BUG_ON(ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo) <
1177 IWLAGN_FIRST_AMPDU_QUEUE);
1178 BUILD_BUG_ON(ARRAY_SIZE(iwlagn_ipan_queue_to_tx_fifo) <
1179 IWLAGN_FIRST_AMPDU_QUEUE);
1181 for (i = 0; i < IWLAGN_FIRST_AMPDU_QUEUE; i++) {
1182 int fifo = queue_to_fifo[i].fifo;
1183 int ac = queue_to_fifo[i].ac;
1185 iwl_txq_ctx_activate(trans_pcie, i);
1187 if (fifo == IWL_TX_FIFO_UNUSED)
1190 if (ac != IWL_AC_UNSET)
1191 iwl_set_swq_id(&trans_pcie->txq[i], ac, i);
1192 iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[i],
1196 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1198 /* Enable L1-Active */
1199 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
1200 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1203 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans)
1205 iwl_reset_ict(trans);
1206 iwl_tx_start(trans);
1210 * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
1212 static int iwl_trans_tx_stop(struct iwl_trans *trans)
1215 unsigned long flags;
1216 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1218 /* Turn off all Tx DMA fifos */
1219 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1221 iwl_trans_txq_set_sched(trans, 0);
1223 /* Stop each Tx DMA channel, and wait for it to be idle */
1224 for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
1225 iwl_write_direct32(trans,
1226 FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
1227 if (iwl_poll_direct_bit(trans, FH_TSSR_TX_STATUS_REG,
1228 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
1230 IWL_ERR(trans, "Failing on timeout while stopping"
1231 " DMA channel %d [0x%08x]", ch,
1232 iwl_read_direct32(trans,
1233 FH_TSSR_TX_STATUS_REG));
1235 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1237 if (!trans_pcie->txq) {
1238 IWL_WARN(trans, "Stopping tx queues that aren't allocated...");
1242 /* Unmap DMA from host system and free skb's */
1243 for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++)
1244 iwl_tx_queue_unmap(trans, txq_id);
1249 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
1251 unsigned long flags;
1252 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1254 /* tell the device to stop sending interrupts */
1255 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1256 iwl_disable_interrupts(trans);
1257 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1259 /* device going down, Stop using ICT table */
1260 iwl_disable_ict(trans);
1263 * If a HW restart happens during firmware loading,
1264 * then the firmware loading might call this function
1265 * and later it might be called again due to the
1266 * restart. So don't process again if the device is
1269 if (test_bit(STATUS_DEVICE_ENABLED, &trans->shrd->status)) {
1270 iwl_trans_tx_stop(trans);
1271 #ifndef CONFIG_IWLWIFI_IDI
1272 iwl_trans_rx_stop(trans);
1274 /* Power-down device's busmaster DMA clocks */
1275 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1276 APMG_CLK_VAL_DMA_CLK_RQT);
1280 /* Make sure (redundant) we've released our request to stay awake */
1281 iwl_clear_bit(trans, CSR_GP_CNTRL,
1282 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1284 /* Stop the device, and put it in low power state */
1285 iwl_apm_stop(trans);
1287 /* Upon stop, the APM issues an interrupt if HW RF kill is set.
1288 * Clean again the interrupt here
1290 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1291 iwl_disable_interrupts(trans);
1292 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1294 /* wait to make sure we flush pending tasklet*/
1295 synchronize_irq(trans_pcie->irq);
1296 tasklet_kill(&trans_pcie->irq_tasklet);
1298 cancel_work_sync(&trans_pcie->rx_replenish);
1300 /* stop and reset the on-board processor */
1301 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
1304 static void iwl_trans_pcie_wowlan_suspend(struct iwl_trans *trans)
1306 /* let the ucode operate on its own */
1307 iwl_write32(trans, CSR_UCODE_DRV_GP1_SET,
1308 CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);
1310 iwl_disable_interrupts(trans);
1311 iwl_clear_bit(trans, CSR_GP_CNTRL,
1312 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1315 static int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
1316 struct iwl_device_cmd *dev_cmd, enum iwl_rxon_context_id ctx,
1319 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1320 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1321 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1322 struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *) dev_cmd->payload;
1323 struct iwl_cmd_meta *out_meta;
1324 struct iwl_tx_queue *txq;
1325 struct iwl_queue *q;
1327 dma_addr_t phys_addr = 0;
1328 dma_addr_t txcmd_phys;
1329 dma_addr_t scratch_phys;
1330 u16 len, firstlen, secondlen;
1331 u8 wait_write_ptr = 0;
1333 bool is_agg = false;
1334 __le16 fc = hdr->frame_control;
1335 u8 hdr_len = ieee80211_hdrlen(fc);
1336 u16 __maybe_unused wifi_seq;
1339 * Send this frame after DTIM -- there's a special queue
1340 * reserved for this for contexts that support AP mode.
1342 if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
1343 txq_id = trans_pcie->mcast_queue[ctx];
1346 * The microcode will clear the more data
1347 * bit in the last frame it transmits.
1349 hdr->frame_control |=
1350 cpu_to_le16(IEEE80211_FCTL_MOREDATA);
1351 } else if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN)
1352 txq_id = IWL_AUX_QUEUE;
1355 trans_pcie->ac_to_queue[ctx][skb_get_queue_mapping(skb)];
1357 /* aggregation is on for this <sta,tid> */
1358 if (info->flags & IEEE80211_TX_CTL_AMPDU) {
1359 WARN_ON(tid >= IWL_MAX_TID_COUNT);
1360 txq_id = trans_pcie->agg_txq[sta_id][tid];
1364 txq = &trans_pcie->txq[txq_id];
1367 spin_lock(&txq->lock);
1369 /* In AGG mode, the index in the ring must correspond to the WiFi
1370 * sequence number. This is a HW requirements to help the SCD to parse
1372 * Check here that the packets are in the right place on the ring.
1374 #ifdef CONFIG_IWLWIFI_DEBUG
1375 wifi_seq = SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
1376 WARN_ONCE(is_agg && ((wifi_seq & 0xff) != q->write_ptr),
1377 "Q: %d WiFi Seq %d tfdNum %d",
1378 txq_id, wifi_seq, q->write_ptr);
1381 /* Set up driver data for this TFD */
1382 txq->skbs[q->write_ptr] = skb;
1383 txq->cmd[q->write_ptr] = dev_cmd;
1385 dev_cmd->hdr.cmd = REPLY_TX;
1386 dev_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
1387 INDEX_TO_SEQ(q->write_ptr)));
1389 /* Set up first empty entry in queue's array of Tx/cmd buffers */
1390 out_meta = &txq->meta[q->write_ptr];
1393 * Use the first empty entry in this queue's command buffer array
1394 * to contain the Tx command and MAC header concatenated together
1395 * (payload data will be in another buffer).
1396 * Size of this varies, due to varying MAC header length.
1397 * If end is not dword aligned, we'll have 2 extra bytes at the end
1398 * of the MAC header (device reads on dword boundaries).
1399 * We'll tell device about this padding later.
1401 len = sizeof(struct iwl_tx_cmd) +
1402 sizeof(struct iwl_cmd_header) + hdr_len;
1403 firstlen = (len + 3) & ~3;
1405 /* Tell NIC about any 2-byte padding after MAC header */
1406 if (firstlen != len)
1407 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1409 /* Physical address of this Tx command's header (not MAC header!),
1410 * within command buffer array. */
1411 txcmd_phys = dma_map_single(trans->dev,
1412 &dev_cmd->hdr, firstlen,
1414 if (unlikely(dma_mapping_error(trans->dev, txcmd_phys)))
1416 dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
1417 dma_unmap_len_set(out_meta, len, firstlen);
1419 if (!ieee80211_has_morefrags(fc)) {
1420 txq->need_update = 1;
1423 txq->need_update = 0;
1426 /* Set up TFD's 2nd entry to point directly to remainder of skb,
1427 * if any (802.11 null frames have no payload). */
1428 secondlen = skb->len - hdr_len;
1429 if (secondlen > 0) {
1430 phys_addr = dma_map_single(trans->dev, skb->data + hdr_len,
1431 secondlen, DMA_TO_DEVICE);
1432 if (unlikely(dma_mapping_error(trans->dev, phys_addr))) {
1433 dma_unmap_single(trans->dev,
1434 dma_unmap_addr(out_meta, mapping),
1435 dma_unmap_len(out_meta, len),
1441 /* Attach buffers to TFD */
1442 iwlagn_txq_attach_buf_to_tfd(trans, txq, txcmd_phys, firstlen, 1);
1444 iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr,
1447 scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
1448 offsetof(struct iwl_tx_cmd, scratch);
1450 /* take back ownership of DMA buffer to enable update */
1451 dma_sync_single_for_cpu(trans->dev, txcmd_phys, firstlen,
1453 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1454 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1456 IWL_DEBUG_TX(trans, "sequence nr = 0X%x\n",
1457 le16_to_cpu(dev_cmd->hdr.sequence));
1458 IWL_DEBUG_TX(trans, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
1459 iwl_print_hex_dump(trans, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
1460 iwl_print_hex_dump(trans, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
1462 /* Set up entry for this TFD in Tx byte-count array */
1463 iwl_trans_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len));
1465 dma_sync_single_for_device(trans->dev, txcmd_phys, firstlen,
1468 trace_iwlwifi_dev_tx(trans->dev,
1469 &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr],
1470 sizeof(struct iwl_tfd),
1471 &dev_cmd->hdr, firstlen,
1472 skb->data + hdr_len, secondlen);
1474 /* Tell device the write index *just past* this latest filled TFD */
1475 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1476 iwl_txq_update_write_ptr(trans, txq);
1479 * At this point the frame is "transmitted" successfully
1480 * and we will get a TX status notification eventually,
1481 * regardless of the value of ret. "ret" only indicates
1482 * whether or not we should update the write pointer.
1484 if (iwl_queue_space(q) < q->high_mark) {
1485 if (wait_write_ptr) {
1486 txq->need_update = 1;
1487 iwl_txq_update_write_ptr(trans, txq);
1489 iwl_stop_queue(trans, txq, "Queue is full");
1492 spin_unlock(&txq->lock);
1495 spin_unlock(&txq->lock);
1499 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1501 struct iwl_trans_pcie *trans_pcie =
1502 IWL_TRANS_GET_PCIE_TRANS(trans);
1506 trans_pcie->inta_mask = CSR_INI_SET_MASK;
1508 if (!trans_pcie->irq_requested) {
1509 tasklet_init(&trans_pcie->irq_tasklet, (void (*)(unsigned long))
1510 iwl_irq_tasklet, (unsigned long)trans);
1512 iwl_alloc_isr_ict(trans);
1514 err = request_irq(trans_pcie->irq, iwl_isr_ict, IRQF_SHARED,
1517 IWL_ERR(trans, "Error allocating IRQ %d\n",
1522 INIT_WORK(&trans_pcie->rx_replenish, iwl_bg_rx_replenish);
1523 trans_pcie->irq_requested = true;
1526 err = iwl_prepare_card_hw(trans);
1528 IWL_ERR(trans, "Error while preparing HW: %d", err);
1532 iwl_apm_init(trans);
1534 hw_rfkill = !(iwl_read32(trans, CSR_GP_CNTRL) &
1535 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
1536 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1541 free_irq(trans_pcie->irq, trans);
1543 iwl_free_isr_ict(trans);
1544 tasklet_kill(&trans_pcie->irq_tasklet);
1548 static void iwl_trans_pcie_stop_hw(struct iwl_trans *trans)
1550 iwl_apm_stop(trans);
1552 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1554 /* Even if we stop the HW, we still want the RF kill interrupt */
1555 IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n");
1556 iwl_write32(trans, CSR_INT_MASK, CSR_INT_BIT_RF_KILL);
1559 static int iwl_trans_pcie_reclaim(struct iwl_trans *trans, int sta_id, int tid,
1560 int txq_id, int ssn, struct sk_buff_head *skbs)
1562 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1563 struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
1564 /* n_bd is usually 256 => n_bd - 1 = 0xff */
1565 int tfd_num = ssn & (txq->q.n_bd - 1);
1568 spin_lock(&txq->lock);
1570 txq->time_stamp = jiffies;
1572 if (unlikely(txq_id >= IWLAGN_FIRST_AMPDU_QUEUE &&
1573 tid != IWL_TID_NON_QOS &&
1574 txq_id != trans_pcie->agg_txq[sta_id][tid])) {
1576 * FIXME: this is a uCode bug which need to be addressed,
1577 * log the information and return for now.
1578 * Since it is can possibly happen very often and in order
1579 * not to fill the syslog, don't use IWL_ERR or IWL_WARN
1581 IWL_DEBUG_TX_QUEUES(trans, "Bad queue mapping txq_id %d, "
1582 "agg_txq[sta_id[tid] %d", txq_id,
1583 trans_pcie->agg_txq[sta_id][tid]);
1584 spin_unlock(&txq->lock);
1588 if (txq->q.read_ptr != tfd_num) {
1589 IWL_DEBUG_TX_REPLY(trans, "[Q %d | AC %d] %d -> %d (%d)\n",
1590 txq_id, iwl_get_queue_ac(txq), txq->q.read_ptr,
1592 freed = iwl_tx_queue_reclaim(trans, txq_id, tfd_num, skbs);
1593 if (iwl_queue_space(&txq->q) > txq->q.low_mark)
1594 iwl_wake_queue(trans, txq, "Packets reclaimed");
1597 spin_unlock(&txq->lock);
1601 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1603 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1606 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1608 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1611 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1613 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1616 static void iwl_trans_pcie_free(struct iwl_trans *trans)
1618 struct iwl_trans_pcie *trans_pcie =
1619 IWL_TRANS_GET_PCIE_TRANS(trans);
1621 iwl_trans_pcie_tx_free(trans);
1622 #ifndef CONFIG_IWLWIFI_IDI
1623 iwl_trans_pcie_rx_free(trans);
1625 if (trans_pcie->irq_requested == true) {
1626 free_irq(trans_pcie->irq, trans);
1627 iwl_free_isr_ict(trans);
1630 pci_disable_msi(trans_pcie->pci_dev);
1631 iounmap(trans_pcie->hw_base);
1632 pci_release_regions(trans_pcie->pci_dev);
1633 pci_disable_device(trans_pcie->pci_dev);
1635 trans->shrd->trans = NULL;
1639 #ifdef CONFIG_PM_SLEEP
1640 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
1645 static int iwl_trans_pcie_resume(struct iwl_trans *trans)
1649 iwl_enable_interrupts(trans);
1651 hw_rfkill = !(iwl_read32(trans, CSR_GP_CNTRL) &
1652 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
1653 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1657 #endif /* CONFIG_PM_SLEEP */
1659 #define IWL_FLUSH_WAIT_MS 2000
1661 static int iwl_trans_pcie_wait_tx_queue_empty(struct iwl_trans *trans)
1663 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1664 struct iwl_tx_queue *txq;
1665 struct iwl_queue *q;
1667 unsigned long now = jiffies;
1670 /* waiting for all the tx frames complete might take a while */
1671 for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) {
1672 if (cnt == trans->shrd->cmd_queue)
1674 txq = &trans_pcie->txq[cnt];
1676 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1677 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1680 if (q->read_ptr != q->write_ptr) {
1681 IWL_ERR(trans, "fail to flush all tx fifo queues\n");
1690 * On every watchdog tick we check (latest) time stamp. If it does not
1691 * change during timeout period and queue is not empty we reset firmware.
1693 static int iwl_trans_pcie_check_stuck_queue(struct iwl_trans *trans, int cnt)
1695 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1696 struct iwl_tx_queue *txq = &trans_pcie->txq[cnt];
1697 struct iwl_queue *q = &txq->q;
1698 unsigned long timeout;
1700 if (q->read_ptr == q->write_ptr) {
1701 txq->time_stamp = jiffies;
1705 timeout = txq->time_stamp +
1706 msecs_to_jiffies(hw_params(trans).wd_timeout);
1708 if (time_after(jiffies, timeout)) {
1709 IWL_ERR(trans, "Queue %d stuck for %u ms.\n", q->id,
1710 hw_params(trans).wd_timeout);
1711 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1712 q->read_ptr, q->write_ptr);
1713 IWL_ERR(trans, "Current HW read_ptr %d write_ptr %d\n",
1714 iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt))
1715 & (TFD_QUEUE_SIZE_MAX - 1),
1716 iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1723 static const char *get_fh_string(int cmd)
1726 IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
1727 IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
1728 IWL_CMD(FH_RSCSR_CHNL0_WPTR);
1729 IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
1730 IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
1731 IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
1732 IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
1733 IWL_CMD(FH_TSSR_TX_STATUS_REG);
1734 IWL_CMD(FH_TSSR_TX_ERROR_REG);
1740 int iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display)
1743 #ifdef CONFIG_IWLWIFI_DEBUG
1747 static const u32 fh_tbl[] = {
1748 FH_RSCSR_CHNL0_STTS_WPTR_REG,
1749 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
1750 FH_RSCSR_CHNL0_WPTR,
1751 FH_MEM_RCSR_CHNL0_CONFIG_REG,
1752 FH_MEM_RSSR_SHARED_CTRL_REG,
1753 FH_MEM_RSSR_RX_STATUS_REG,
1754 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
1755 FH_TSSR_TX_STATUS_REG,
1756 FH_TSSR_TX_ERROR_REG
1758 #ifdef CONFIG_IWLWIFI_DEBUG
1760 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
1761 *buf = kmalloc(bufsz, GFP_KERNEL);
1764 pos += scnprintf(*buf + pos, bufsz - pos,
1765 "FH register values:\n");
1766 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1767 pos += scnprintf(*buf + pos, bufsz - pos,
1769 get_fh_string(fh_tbl[i]),
1770 iwl_read_direct32(trans, fh_tbl[i]));
1775 IWL_ERR(trans, "FH register values:\n");
1776 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
1777 IWL_ERR(trans, " %34s: 0X%08x\n",
1778 get_fh_string(fh_tbl[i]),
1779 iwl_read_direct32(trans, fh_tbl[i]));
1784 static const char *get_csr_string(int cmd)
1787 IWL_CMD(CSR_HW_IF_CONFIG_REG);
1788 IWL_CMD(CSR_INT_COALESCING);
1790 IWL_CMD(CSR_INT_MASK);
1791 IWL_CMD(CSR_FH_INT_STATUS);
1792 IWL_CMD(CSR_GPIO_IN);
1794 IWL_CMD(CSR_GP_CNTRL);
1795 IWL_CMD(CSR_HW_REV);
1796 IWL_CMD(CSR_EEPROM_REG);
1797 IWL_CMD(CSR_EEPROM_GP);
1798 IWL_CMD(CSR_OTP_GP_REG);
1799 IWL_CMD(CSR_GIO_REG);
1800 IWL_CMD(CSR_GP_UCODE_REG);
1801 IWL_CMD(CSR_GP_DRIVER_REG);
1802 IWL_CMD(CSR_UCODE_DRV_GP1);
1803 IWL_CMD(CSR_UCODE_DRV_GP2);
1804 IWL_CMD(CSR_LED_REG);
1805 IWL_CMD(CSR_DRAM_INT_TBL_REG);
1806 IWL_CMD(CSR_GIO_CHICKEN_BITS);
1807 IWL_CMD(CSR_ANA_PLL_CFG);
1808 IWL_CMD(CSR_HW_REV_WA_REG);
1809 IWL_CMD(CSR_DBG_HPET_MEM_REG);
1815 void iwl_dump_csr(struct iwl_trans *trans)
1818 static const u32 csr_tbl[] = {
1819 CSR_HW_IF_CONFIG_REG,
1837 CSR_DRAM_INT_TBL_REG,
1838 CSR_GIO_CHICKEN_BITS,
1841 CSR_DBG_HPET_MEM_REG
1843 IWL_ERR(trans, "CSR values:\n");
1844 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1845 "CSR_INT_PERIODIC_REG)\n");
1846 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
1847 IWL_ERR(trans, " %25s: 0X%08x\n",
1848 get_csr_string(csr_tbl[i]),
1849 iwl_read32(trans, csr_tbl[i]));
1853 #ifdef CONFIG_IWLWIFI_DEBUGFS
1854 /* create and remove of files */
1855 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \
1856 if (!debugfs_create_file(#name, mode, parent, trans, \
1857 &iwl_dbgfs_##name##_ops)) \
1861 /* file operation */
1862 #define DEBUGFS_READ_FUNC(name) \
1863 static ssize_t iwl_dbgfs_##name##_read(struct file *file, \
1864 char __user *user_buf, \
1865 size_t count, loff_t *ppos);
1867 #define DEBUGFS_WRITE_FUNC(name) \
1868 static ssize_t iwl_dbgfs_##name##_write(struct file *file, \
1869 const char __user *user_buf, \
1870 size_t count, loff_t *ppos);
1873 static int iwl_dbgfs_open_file_generic(struct inode *inode, struct file *file)
1875 file->private_data = inode->i_private;
1879 #define DEBUGFS_READ_FILE_OPS(name) \
1880 DEBUGFS_READ_FUNC(name); \
1881 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1882 .read = iwl_dbgfs_##name##_read, \
1883 .open = iwl_dbgfs_open_file_generic, \
1884 .llseek = generic_file_llseek, \
1887 #define DEBUGFS_WRITE_FILE_OPS(name) \
1888 DEBUGFS_WRITE_FUNC(name); \
1889 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1890 .write = iwl_dbgfs_##name##_write, \
1891 .open = iwl_dbgfs_open_file_generic, \
1892 .llseek = generic_file_llseek, \
1895 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \
1896 DEBUGFS_READ_FUNC(name); \
1897 DEBUGFS_WRITE_FUNC(name); \
1898 static const struct file_operations iwl_dbgfs_##name##_ops = { \
1899 .write = iwl_dbgfs_##name##_write, \
1900 .read = iwl_dbgfs_##name##_read, \
1901 .open = iwl_dbgfs_open_file_generic, \
1902 .llseek = generic_file_llseek, \
1905 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1906 char __user *user_buf,
1907 size_t count, loff_t *ppos)
1909 struct iwl_trans *trans = file->private_data;
1910 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1911 struct iwl_tx_queue *txq;
1912 struct iwl_queue *q;
1917 const size_t bufsz = sizeof(char) * 64 * hw_params(trans).max_txq_num;
1919 if (!trans_pcie->txq) {
1920 IWL_ERR(trans, "txq not ready\n");
1923 buf = kzalloc(bufsz, GFP_KERNEL);
1927 for (cnt = 0; cnt < hw_params(trans).max_txq_num; cnt++) {
1928 txq = &trans_pcie->txq[cnt];
1930 pos += scnprintf(buf + pos, bufsz - pos,
1931 "hwq %.2d: read=%u write=%u stop=%d"
1932 " swq_id=%#.2x (ac %d/hwq %d)\n",
1933 cnt, q->read_ptr, q->write_ptr,
1934 !!test_bit(cnt, trans_pcie->queue_stopped),
1935 txq->swq_id, txq->swq_id & 3,
1936 (txq->swq_id >> 2) & 0x1f);
1939 /* for the ACs, display the stop count too */
1940 pos += scnprintf(buf + pos, bufsz - pos,
1941 " stop-count: %d\n",
1942 atomic_read(&trans_pcie->queue_stop_count[cnt]));
1944 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1949 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1950 char __user *user_buf,
1951 size_t count, loff_t *ppos) {
1952 struct iwl_trans *trans = file->private_data;
1953 struct iwl_trans_pcie *trans_pcie =
1954 IWL_TRANS_GET_PCIE_TRANS(trans);
1955 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
1958 const size_t bufsz = sizeof(buf);
1960 pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1962 pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1964 pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1967 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1968 le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF);
1970 pos += scnprintf(buf + pos, bufsz - pos,
1971 "closed_rb_num: Not Allocated\n");
1973 return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1976 static ssize_t iwl_dbgfs_log_event_read(struct file *file,
1977 char __user *user_buf,
1978 size_t count, loff_t *ppos)
1980 struct iwl_trans *trans = file->private_data;
1983 ssize_t ret = -ENOMEM;
1985 ret = pos = iwl_dump_nic_event_log(trans, true, &buf, true);
1987 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1993 static ssize_t iwl_dbgfs_log_event_write(struct file *file,
1994 const char __user *user_buf,
1995 size_t count, loff_t *ppos)
1997 struct iwl_trans *trans = file->private_data;
2002 memset(buf, 0, sizeof(buf));
2003 buf_size = min(count, sizeof(buf) - 1);
2004 if (copy_from_user(buf, user_buf, buf_size))
2006 if (sscanf(buf, "%d", &event_log_flag) != 1)
2008 if (event_log_flag == 1)
2009 iwl_dump_nic_event_log(trans, true, NULL, false);
2014 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
2015 char __user *user_buf,
2016 size_t count, loff_t *ppos) {
2018 struct iwl_trans *trans = file->private_data;
2019 struct iwl_trans_pcie *trans_pcie =
2020 IWL_TRANS_GET_PCIE_TRANS(trans);
2021 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2025 int bufsz = 24 * 64; /* 24 items * 64 char per item */
2028 buf = kzalloc(bufsz, GFP_KERNEL);
2030 IWL_ERR(trans, "Can not allocate Buffer\n");
2034 pos += scnprintf(buf + pos, bufsz - pos,
2035 "Interrupt Statistics Report:\n");
2037 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2039 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2041 if (isr_stats->sw || isr_stats->hw) {
2042 pos += scnprintf(buf + pos, bufsz - pos,
2043 "\tLast Restarting Code: 0x%X\n",
2044 isr_stats->err_code);
2046 #ifdef CONFIG_IWLWIFI_DEBUG
2047 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2049 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2052 pos += scnprintf(buf + pos, bufsz - pos,
2053 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2055 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2058 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2061 pos += scnprintf(buf + pos, bufsz - pos,
2062 "Rx command responses:\t\t %u\n", isr_stats->rx);
2064 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2067 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2068 isr_stats->unhandled);
2070 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2075 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2076 const char __user *user_buf,
2077 size_t count, loff_t *ppos)
2079 struct iwl_trans *trans = file->private_data;
2080 struct iwl_trans_pcie *trans_pcie =
2081 IWL_TRANS_GET_PCIE_TRANS(trans);
2082 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2088 memset(buf, 0, sizeof(buf));
2089 buf_size = min(count, sizeof(buf) - 1);
2090 if (copy_from_user(buf, user_buf, buf_size))
2092 if (sscanf(buf, "%x", &reset_flag) != 1)
2094 if (reset_flag == 0)
2095 memset(isr_stats, 0, sizeof(*isr_stats));
2100 static ssize_t iwl_dbgfs_csr_write(struct file *file,
2101 const char __user *user_buf,
2102 size_t count, loff_t *ppos)
2104 struct iwl_trans *trans = file->private_data;
2109 memset(buf, 0, sizeof(buf));
2110 buf_size = min(count, sizeof(buf) - 1);
2111 if (copy_from_user(buf, user_buf, buf_size))
2113 if (sscanf(buf, "%d", &csr) != 1)
2116 iwl_dump_csr(trans);
2121 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
2122 char __user *user_buf,
2123 size_t count, loff_t *ppos)
2125 struct iwl_trans *trans = file->private_data;
2128 ssize_t ret = -EFAULT;
2130 ret = pos = iwl_dump_fh(trans, &buf, true);
2132 ret = simple_read_from_buffer(user_buf,
2133 count, ppos, buf, pos);
2140 DEBUGFS_READ_WRITE_FILE_OPS(log_event);
2141 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
2142 DEBUGFS_READ_FILE_OPS(fh_reg);
2143 DEBUGFS_READ_FILE_OPS(rx_queue);
2144 DEBUGFS_READ_FILE_OPS(tx_queue);
2145 DEBUGFS_WRITE_FILE_OPS(csr);
2148 * Create the debugfs files and directories
2151 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2154 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2155 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
2156 DEBUGFS_ADD_FILE(log_event, dir, S_IWUSR | S_IRUSR);
2157 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
2158 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2159 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
2163 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2167 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2169 const struct iwl_trans_ops trans_ops_pcie = {
2170 .start_hw = iwl_trans_pcie_start_hw,
2171 .stop_hw = iwl_trans_pcie_stop_hw,
2172 .fw_alive = iwl_trans_pcie_fw_alive,
2173 .start_fw = iwl_trans_pcie_start_fw,
2174 .stop_device = iwl_trans_pcie_stop_device,
2176 .wowlan_suspend = iwl_trans_pcie_wowlan_suspend,
2178 .send_cmd = iwl_trans_pcie_send_cmd,
2180 .tx = iwl_trans_pcie_tx,
2181 .reclaim = iwl_trans_pcie_reclaim,
2183 .tx_agg_disable = iwl_trans_pcie_tx_agg_disable,
2184 .tx_agg_alloc = iwl_trans_pcie_tx_agg_alloc,
2185 .tx_agg_setup = iwl_trans_pcie_tx_agg_setup,
2187 .free = iwl_trans_pcie_free,
2189 .dbgfs_register = iwl_trans_pcie_dbgfs_register,
2191 .wait_tx_queue_empty = iwl_trans_pcie_wait_tx_queue_empty,
2192 .check_stuck_queue = iwl_trans_pcie_check_stuck_queue,
2194 #ifdef CONFIG_PM_SLEEP
2195 .suspend = iwl_trans_pcie_suspend,
2196 .resume = iwl_trans_pcie_resume,
2198 .write8 = iwl_trans_pcie_write8,
2199 .write32 = iwl_trans_pcie_write32,
2200 .read32 = iwl_trans_pcie_read32,
2203 struct iwl_trans *iwl_trans_pcie_alloc(struct iwl_shared *shrd,
2204 struct pci_dev *pdev,
2205 const struct pci_device_id *ent)
2207 struct iwl_trans_pcie *trans_pcie;
2208 struct iwl_trans *trans;
2212 trans = kzalloc(sizeof(struct iwl_trans) +
2213 sizeof(struct iwl_trans_pcie), GFP_KERNEL);
2215 if (WARN_ON(!trans))
2218 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2220 trans->ops = &trans_ops_pcie;
2222 trans_pcie->trans = trans;
2223 spin_lock_init(&trans_pcie->irq_lock);
2224 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
2226 /* W/A - seems to solve weird behavior. We need to remove this if we
2227 * don't want to stay in L1 all the time. This wastes a lot of power */
2228 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
2229 PCIE_LINK_STATE_CLKPM);
2231 if (pci_enable_device(pdev)) {
2236 pci_set_master(pdev);
2238 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2240 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2242 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2244 err = pci_set_consistent_dma_mask(pdev,
2246 /* both attempts failed: */
2248 dev_printk(KERN_ERR, &pdev->dev,
2249 "No suitable DMA available.\n");
2250 goto out_pci_disable_device;
2254 err = pci_request_regions(pdev, DRV_NAME);
2256 dev_printk(KERN_ERR, &pdev->dev, "pci_request_regions failed");
2257 goto out_pci_disable_device;
2260 trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
2261 if (!trans_pcie->hw_base) {
2262 dev_printk(KERN_ERR, &pdev->dev, "pci_ioremap_bar failed");
2264 goto out_pci_release_regions;
2267 dev_printk(KERN_INFO, &pdev->dev,
2268 "pci_resource_len = 0x%08llx\n",
2269 (unsigned long long) pci_resource_len(pdev, 0));
2270 dev_printk(KERN_INFO, &pdev->dev,
2271 "pci_resource_base = %p\n", trans_pcie->hw_base);
2273 dev_printk(KERN_INFO, &pdev->dev,
2274 "HW Revision ID = 0x%X\n", pdev->revision);
2276 /* We disable the RETRY_TIMEOUT register (0x41) to keep
2277 * PCI Tx retries from interfering with C3 CPU state */
2278 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2280 err = pci_enable_msi(pdev);
2282 dev_printk(KERN_ERR, &pdev->dev,
2283 "pci_enable_msi failed(0X%x)", err);
2285 trans->dev = &pdev->dev;
2286 trans_pcie->irq = pdev->irq;
2287 trans_pcie->pci_dev = pdev;
2288 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
2289 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
2290 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2291 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
2293 /* TODO: Move this away, not needed if not MSI */
2294 /* enable rfkill interrupt: hw bug w/a */
2295 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2296 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2297 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2298 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2303 out_pci_release_regions:
2304 pci_release_regions(pdev);
2305 out_pci_disable_device:
2306 pci_disable_device(pdev);